WO2018014170A1

WO2018014170A1 - Tunnel field effect transistor, and manufacturing method thereof

Info

Publication number: WO2018014170A1
Application number: PCT/CN2016/090381
Authority: WO
Inventors: 徐慧龙; 李伟; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2016-07-19
Filing date: 2016-07-19
Publication date: 2018-01-25
Also published as: CN109417095B; CN109417095A

Abstract

A tunnel field effect transistor (TFET), and manufacturing method thereof. The tunnel field effect transistor employs thin-layer black phosphorus to fabricate a trench, such that the tunnel field effect transistor has a large on-state current, thus effectively solving the problem of silicon-based TFETs having a low on-state current.

Description

Tunneling field effect transistor and preparation method thereof

Technical field

Embodiments of the present invention relate to semiconductor technology, and in particular, to a tunneling field effect transistor and a method of fabricating the same.

Background technique

As the number of transistors per unit area increases, the power consumption problem of the chip becomes more and more prominent. Therefore, how to effectively reduce the power consumption of the chip is an issue of great concern in the industry. Generally, the power consumption of the chip can be approximated as proportional to the square of the operating voltage, so reducing the operating voltage is an effective means to reduce the power consumption of the chip. Among them, Tunnel Field-Effect Transistor (TFET) is a transistor technology with low voltage working potential. Unlike current transistors in Complementary Metal Oxide Semiconductor (CMOS) technology, the transition of the TFET between the on state and the off state is achieved by whether or not interband tunneling occurs. At room temperature, the subthreshold is The swing can theoretically be less than 60mV/dec, allowing normal opening and closing at very small voltages.

Currently, TFETs are primarily silicon-based TFETs, and one of the reasons is that the silicon process is very mature. However, silicon-based TFETs have a lower on-state current, currently about 1 microamperes per micron (μA/μm), which is 2-3 orders of magnitude smaller than the on-state current of transistors in CMOS technology. The small on-state current causes the TFET speed to drop, which corresponds to a decrease in the speed of the chip at the chip level, which is very disadvantageous for practical applications.

Summary of the invention

Embodiments of the present invention provide a tunneling field effect transistor and a method of fabricating the same to improve an on-state current of a TFET.

In a first aspect, an embodiment of the present invention provides a tunneling field effect transistor. The tunneling field effect transistor includes: a substrate; a channel disposed on the substrate, the length of the channel being less than a length of the substrate, and the material of the channel is a thin layer of black phosphorus, The thickness of the thin black phosphorus is greater than or equal to 2 nanometers, and the thickness of the thin black phosphorus is less than or equal to 30 nanometers; the source region and the drain region electrode, The source region electrode and the drain region electrode are respectively disposed at both ends of the substrate along a length direction of the substrate, and a portion of the source region electrode and the drain region electrode are disposed at the On the substrate, another portion is disposed on the channel; a gate dielectric layer covering the exposed portion of the substrate, the channel, the source region electrode and the drain region electrode; a first gate electrode, disposed On the gate dielectric layer, and seamlessly connected to the gate dielectric layer on the source region electrode side; a second gate electrode disposed on the gate dielectric layer and a gate dielectric layer on the drain region electrode side Seamlessly connected, a gap is formed between the second gate electrode and the first gate electrode.

In the embodiment of the invention, the channel of the tunneling field effect transistor is prepared by using the thin black phosphorus, so that the tunneling field effect transistor has a large on-state current, which can well solve the problem that the on-state current of the silicon-based TFET is small.

In a first possible implementation manner of the first aspect, the second gate electrode is a main gate electrode for controlling opening or closing of the channel, and the voltage of the second gate electrode is according to an applied switching instruction Changing in real time; the first gate electrode is a secondary gate electrode for controlling doping of a channel portion under the first gate electrode.

In a second possible implementation manner of the first aspect, when the material used in the source region electrode is a low work function metal, and the material used in the drain region electrode is a high work function metal, the first The material used for the gate electrode is a low work function metal, and a P-type tunneling field effect transistor is formed when a negative bias voltage is formed between the second gate electrode and the source region electrode; or, when the source region electrode is The material used is a high work function metal, and the material of the drain electrode is a low work function metal, the material used for the first gate electrode is a high work function metal, the second gate electrode and the When a positive bias is formed between the source region electrodes, an N-type tunneling field effect transistor is formed.

In a third possible implementation manner of the first aspect, the tunneling field effect transistor may further include: a first passivation layer covering the structure obtained after forming the first gate electrode and the second gate electrode.

In a fourth possible implementation manner of the first aspect, the tunneling field effect transistor may further include: a third gate electrode disposed on the gate dielectric layer at the source region electrode and the drain region electrode a region between the insulating layer and the exposed portion of the third gate electrode; wherein the first gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side, the second gate The electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side

In a fifth possible implementation manner of the first aspect, the third gate electrode is a main gate electrode for controlling opening or closing of the channel, and the voltage of the third gate electrode is according to an applied switching instruction Real The first gate electrode and the second gate electrode are both auxiliary gate electrodes for controlling the doping of the respective lower channel portions, and the respective voltage magnitudes and polarities remain fixed.

The embodiment of the invention combines the characteristics of black phosphorus to provide an electrostatic doping structure. The electrostatic doping structure can introduce doping in the form of an applied electric field to form a high-quality tunneling junction, which avoids ion implantation, ion activation, and the like. The process also solves the problem that the black phosphorus doping process is still immature, thereby improving the performance of the tunneling field effect transistor.

In a sixth possible implementation manner of the first aspect, the voltage magnitude of the first gate electrode and the voltage of the second gate electrode are both between -0.5 volts and 0.5 volts (if not specified, The default source electrode is the zero potential reference electrode).

In a seventh possible implementation manner of the first aspect, when the material used in the source region electrode is a low work function metal, and the material used in the drain region electrode is a high work function metal, the first a voltage polarity of a gate electrode is a positive electrode, a voltage polarity of the second gate electrode is a negative electrode, forming a P-type tunneling field effect transistor; or, when the material of the source region electrode is a high work function metal, When the material of the drain electrode is a low work function metal, the voltage polarity of the first gate electrode is a negative electrode, and the voltage polarity of the second gate electrode is a positive electrode, forming an N-type tunneling field effect. Transistor.

In an eighth possible implementation manner of the first aspect, in the P-type tunneling field effect transistor, a material used by the first gate electrode is a low work function metal, and the second gate electrode is used. The material is a high work function metal; or, in the N-type tunneling field effect transistor, the material used for the first gate electrode is a high work function metal, and the material used for the second gate electrode is low The work function metal further enhances the doping effect of the first gate electrode and the second gate electrode pair on the lower channel.

In a ninth possible implementation manner of the first aspect, in consideration of a practical effect of the fabrication process, the first metal block is further included on the gate dielectric layer of the source region electrode adjacent to the first gate electrode side, The third gate electrode further includes a second metal block on the insulating dielectric layer on a side of the first gate electrode, a material of the first metal block and the second metal block and the first gate electrode The material is the same; a third metal block is further disposed on the gate dielectric layer of the drain electrode adjacent to the second gate electrode, and the insulating dielectric layer is disposed on a side of the third gate electrode adjacent to the second gate electrode Further included is a fourth metal block, the material of the third metal block and the fourth metal block being the same as the material of the second gate electrode.

In a tenth possible implementation manner of the first aspect, the tunneling field effect transistor may further include: a second passivation layer covering the structure obtained after forming the insulating dielectric layer, so that the tunneling field The effect transistor is isolated from the air to prevent the tunneling field effect transistor from being oxidized.

In a second aspect, an embodiment of the present invention provides a method for fabricating a tunneling field effect transistor, including: forming a channel on a substrate, the length of the channel being less than a length of the substrate, and the channel adopting The material is a thin layer of black phosphorus, the thickness of the thin layer of black phosphorus is greater than or equal to 2 nanometers, and the thickness of the thin layer of black phosphorus is less than or equal to 30 nanometers; forming a source region electrode and a drain region electrode along the substrate a length direction, the source region electrode and the drain region electrode are respectively disposed at both ends of the substrate, and a part of the source region electrode and the drain region electrode are disposed on the substrate, and a portion is disposed on the channel; forming a gate dielectric layer covering the exposed portion of the substrate, the channel, the source region electrode and the drain region electrode; forming a first gate electrode And a second gate electrode, the first gate electrode is disposed on the gate dielectric layer, and the first gate electrode is seamlessly connected to the gate dielectric layer on the source region electrode side, and the second gate electrode is disposed On the gate dielectric layer, and the second gate electrode and the drain Electrode side of the gate dielectric layer seamless connection, a gap is formed between said second gate electrode and the first gate electrode.

The embodiment of the invention utilizes a thin layer of black phosphorus to prepare a channel of a tunneling field effect transistor, so that the tunneling field effect transistor has a large on-state current, which can well solve the problem that the on-state current of the silicon-based TFET is small; Combining the characteristics of black phosphorus, it provides an electrostatic doping structure. The electrostatic doping structure can introduce doping in the form of an applied electric field to form a high-quality tunneling junction, which avoids processes such as ion implantation and ion activation. At present, the black phosphorus doping process is still immature, which improves the performance of the tunneling field effect transistor.

In a first possible implementation manner of the second aspect, the forming the source region electrode and the drain region electrode include: a structure obtained after forming a channel on the substrate, except the source region electrode and the drain The position of the region electrode is spin-coated with a layer of photoresist and exposed; the source region electrode and the drain region electrode are formed by plating or sputtering, and the photoresist is removed.

In a second possible implementation manner of the second aspect, the forming the gate dielectric layer includes: forming the gate dielectric layer by atomic layer deposition on a structure obtained after forming the source region drain electrode and the drain region electrode.

In a third possible implementation manner of the second aspect, the forming the first gate electrode and the second gate electrode includes: a structure obtained after forming the insulating dielectric layer, except the first gate electrode and the Positioning the second gate electrode, spin coating a layer of photoresist, and exposing; forming the first gate electrode and the second gate electrode by plating and sputtering, and removing the photoresist.

In a fourth possible implementation manner of the second aspect, the method for fabricating the tunneling field effect transistor may further include: performing physical deposition or chemical deposition, after forming the first gate electrode and the second gate electrode The first passivation layer is structurally prepared.

In a fifth possible implementation manner of the second aspect, when the material used in the source region electrode is a low work function metal, and the material used in the drain region electrode is a high work function metal, the first The material used for the gate electrode is a low work function metal, and a P-type tunneling field effect transistor is formed when a negative bias voltage is formed between the second gate electrode and the source region electrode; or, when the source region electrode is The material used is a high work function metal, and the material of the drain electrode is a low work function metal, the material used for the first gate electrode is a high work function metal, the second gate electrode and the When a positive bias is formed between the source region electrodes, an N-type tunneling field effect transistor is formed.

In a sixth possible implementation manner of the second aspect, before the forming the first gate electrode and the second gate electrode, the method for preparing the tunneling field effect transistor may further include: forming a third gate electrode, wherein the a tri-gate electrode disposed on the gate dielectric layer at a region between the source region electrode and the drain region electrode; forming an insulating dielectric layer covering a bare portion of the third gate electrode; wherein The first gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side, and the second gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side.

In a seventh possible implementation manner of the second aspect, the forming the third gate electrode includes: coating a layer of light on the structure obtained after forming the gate dielectric layer except the position of the third gate electrode The glue is exposed and exposed; the third gate electrode is formed by plating and sputtering, and the photoresist is removed.

In an eighth possible implementation manner of the second aspect, the forming the insulating dielectric layer comprises: placing the structure obtained after forming the third gate electrode in air or ozone to form the insulating dielectric layer.

In a ninth possible implementation manner of the second aspect, after the forming the insulating dielectric layer, the preparing method may further include: preparing the structure obtained by forming the insulating dielectric layer by physical deposition or chemical deposition Two passivation layers to isolate the air.

In a tenth possible implementation manner of the second aspect, the material used for the source region electrode is a low work function metal, and the material of the drain region electrode is a high work function metal, when in the first a positive voltage is applied to the gate electrode, and a P-type tunneling field effect transistor is formed when the second gate electrode applies a negative voltage; or the material used for the source region electrode is a high work function metal, and the drain region electrode The material used is a low work function metal, when a negative voltage is applied to the first gate electrode, in the When a positive voltage is applied to the second gate electrode, an N-type tunneling field effect transistor is formed.

In an eleventh possible implementation manner of the second aspect, in the P-type tunneling field effect transistor, the material used in the first gate electrode is a low work function metal, and the second gate electrode The material used is a high work function metal; or, in the N-type tunneling field effect transistor, the material used for the first gate electrode is a high work function metal, and the material used for the second gate electrode is a low work function metal to further enhance the doping effect of the respective lower channel of the first gate electrode and the second gate electrode pair.

These and other aspects of the embodiments of the invention will be more apparent from the following description of the embodiments.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

1 is a schematic structural view of Embodiment 1 of a tunneling field effect transistor according to the present invention;

2 is a schematic view showing the arrangement of black phosphorus atoms;

3 is a schematic structural diagram of Embodiment 2 of a tunneling field effect transistor according to the present invention;

4 is a schematic structural diagram of Embodiment 3 of a tunneling field effect transistor according to the present invention;

FIG. 5 is a schematic structural diagram of Embodiment 4 of a tunneling field effect transistor according to the present invention; FIG.

6 is a flow chart of Embodiment 1 of a method for fabricating a tunneling field effect transistor according to the present invention;

7 is a flow chart of a second embodiment of a method for fabricating a tunneling field effect transistor according to the present invention;

8 to FIG. 12 are schematic structural views of a tunneling field effect transistor according to the present invention;

FIG. 13 is a schematic diagram of a simulation result of a tunneling field effect transistor and a silicon-based TFET according to the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, those of ordinary skill in the art are not doing All other embodiments obtained under the premise of creative labor are within the scope of the invention.

The terms "first", "second", "third" and the like in the specification and claims of the embodiments of the invention are used to distinguish similar objects, and are not necessarily used to describe a particular order or order. It is to be understood that the data so used may be interchanged as appropriate, such that the embodiments of the invention described herein can be implemented, for example, in a sequence other than those illustrated or described herein. In addition, the terms "comprises" and "comprises" and "the" and "the" are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to Those steps or units may include other steps or units not explicitly listed or inherent to such processes, methods, products or devices.

In a silicon-based TFET, when the gate voltage is zero, the valence band of the source region and the conduction band of the channel do not overlap, electrons cannot tunnel from the source region to the channel, and thus there is no current in the channel, and the silicon-based TFET is off. When the gate voltage is positive, the channel is gate-modulated, and the conduction band of the channel moves downward. When the conduction band of the channel and the valence band of the source region overlap, the source region electrons can tunnel into the trench. The conduction band of the track, thereby forming a current, that is, the silicon-based TFET is in an on state.

One amount directly related to the above-described electron tunneling process is the tunneling probability, the upper limit of the tunneling probability is 1, and the lower limit is zero. The higher the probability of tunneling, the greater the on-state current of the device; conversely, the smaller the tunneling probability, the smaller the on-state current of the device. The tunneling probability is usually inversely proportional to the band gap of the semiconductor and the effective mass of the carrier (ie, electron or hole), that is, the larger the band gap, the smaller the tunneling probability; the larger the effective mass of the carrier, the smaller the tunneling probability. In addition, the tunneling probability of the direct bandgap material is higher than the tunneling probability of the indirect bandgap material. For example, silicon is an indirect bandgap material with a band gap size of 1.1 eV.

In addition, in principle, the subthreshold swing of the silicon-based TFET can be less than 60mV/dec, but in practice, not much can be achieved below 60mV/dec. The ion implantation doping technique in the silicon process easily introduces defects into the crystal, and the defects near the tunnel junction reduce the quality of the tunnel junction; in addition, the implanted impurity ions require high temperature (above 900 degrees Celsius) to activate, which easily leads to tunneling. The ions near the junction are diffused, which affects the quality of the tunneling junction. Both of these tend to cause subthreshold swings to deteriorate, which results in poor performance of the silicon-based TFET.

Based on the above problems, an embodiment of the present invention provides a TFET having a channel material of black phosphorus, and a TFET prepared by using black phosphorus has a large on-state current, which can well solve a small on-state current of a silicon-based TFET. At the same time, the embodiment of the present invention combines the characteristics of black phosphorus to provide an electrostatic doping structure, and the electrostatic doping structure can introduce doping in the form of an applied electric field to form a high The mass tunneling junction avoids the processes of ion implantation and ion activation, and also solves the problem that the black phosphorus doping process is still immature.

1 is a schematic structural view of Embodiment 1 of a tunneling field effect transistor of the present invention. As shown in FIG. 1, the tunneling field effect transistor includes a substrate 10, a channel 11, a source region electrode 12, a drain region electrode 13, a gate dielectric layer 14, a first gate electrode 17, and a second gate electrode 18.

Specifically, the channel 11 is disposed over the substrate 10, and the length of the channel 11 is smaller than the length of the substrate 10. The material used for the channel 11 is black phosphorus. Along the length direction of the substrate 10, the source region electrode 12 and the drain region electrode 13 are respectively disposed at both ends of the substrate 10, and a part of the source region electrode 12 and the drain region electrode 13 are disposed on the substrate 10, and the other portion is disposed. On the channel 11. The gate dielectric layer 14 covers the exposed portions of the substrate 10, the channel 11, the source region electrode 12, and the drain region electrode 13. The first gate electrode 17 is disposed on the gate dielectric layer 14 and is seamlessly connected to the gate dielectric layer 14 on the source region electrode 12 side. The second gate electrode 18 is disposed on the gate dielectric layer 14 and is seamlessly connected to the gate dielectric layer 14 on the drain region electrode 13 side. A gap is formed between the second gate electrode 18 and the first gate electrode 17.

Among them, black phosphorus is formed by stacking layered phosphorus atoms. A single layer of phosphorus atoms is often referred to as a phosphonene or a single layer of phosphonene, and a few layers are stacked as a thin layer of black phosphorus. The thickness of the single layer of phosphene is about 0.5 nm, and the band gap is about 2 eV. The corresponding band gap will decrease correspondingly with the increase of the number of layers. When the number of layers reaches 20 layers, the band gap will not continue to increase but stabilize at 0.3 eV. The left and right, that is, the band gap of black phosphorus ranges from 0.3 eV to 2 eV.

Considering that the tunneling probability is inversely proportional to the band gap size, the excessively thick black phosphorus will make the gate electrode control the channel worse, resulting in an increase in the leakage rate of the tunneling field effect transistor, too thin black phosphorus (for example, a single layer of phosphonene). The olefin is too large and unstable, which is disadvantageous for preparing the tunneling field effect transistor. Therefore, in the embodiment of the invention, the channel 11 is made of a thin layer of black phosphorus, and the thickness of the thin layer of black phosphorus is greater than or equal to 2 nanometers, and The thickness of the thin black phosphorus is less than or equal to 30 nanometers. Further, the thickness of the thin black phosphorus is greater than or equal to 2 nanometers, and the thickness of the thin black phosphorus is less than or equal to 20 nanometers.

In the tunneling field effect transistor, along the length direction of the channel 11, that is, from the source region electrode 12 to the drain region electrode 13, the phosphorus atoms in the thin black phosphorus are arranged in a chair-type atom, as shown in FIG. It is shown that the electrons propagating in this direction have a small effective mass, which is advantageous for increasing the on-state current of the tunneling field effect transistor.

It should be noted that the size of the gap between the second gate electrode 18 and the first gate electrode 17 depends on the alignment precision of the photolithography process, and is usually greater than 4 nm.

Optionally, the second gate electrode 18 is a main gate electrode for controlling the opening or closing of the channel 11, and the voltage of the second gate electrode 18 is changed in real time according to an applied switching command. The first gate electrode 17 is a secondary gate electrode for controlling doping of the channel portion under the first gate electrode 17.

When the material used for the source region electrode 12 is a low work function metal, and the material of the drain region electrode 13 is a high work function metal, the material used for the first gate electrode 17 is a low work function metal, and the second gate electrode 18 is used. When a negative bias is formed between the source electrode 12 and the source region electrode 12, a P-type tunneling field effect transistor is formed.

Alternatively, when the material used for the source region electrode 12 is a high work function metal, and the material of the drain region electrode 13 is a low work function metal, the material used for the first gate electrode 17 is a high work function metal, and the second gate When a positive bias is formed between the electrode 18 and the source region electrode 12, an N-type tunneling field effect transistor is formed.

In this embodiment, the channel of the tunneling field effect transistor is prepared by using the thin black phosphorus, so that the tunneling field effect transistor has a large on-state current, which can well solve the problem that the on-state current of the silicon-based TFET is small; The embodiment of the invention combines the characteristics of black phosphorus to provide an electrostatic doping structure. The electrostatic doping structure can introduce doping in the form of an applied electric field to form a high-quality tunneling junction, which avoids ion implantation, ion activation, and the like. The process also solves the problem that the black phosphorus doping process is still immature, thereby improving the performance of the tunneling field effect transistor.

In addition, in consideration of the actual effect of the fabrication process, based on the structure shown in FIG. 1 above, as shown in FIG. 3, the gate dielectric layer 14 on the side of the source region electrode 12 adjacent to the first gate electrode 17 may further include A metal block 171. The material of the first metal block 171 is the same as the material of the first gate electrode 17.

Similarly, a third metal block 182 may be further included on the gate dielectric layer 14 on the side of the drain electrode 13 adjacent to the second gate electrode 18. The material of the third metal block 182 is the same as the material of the second gate electrode 18.

Further, the tunneling field effect transistor may further include: a first passivation layer 101. Referring to FIG. 3, the first passivation layer 101 covers the structure obtained after the formation of the first gate electrode 17 and the second gate electrode 18. The first passivation layer 101 is for insulating air and may have a thickness greater than or equal to 100 nanometers.

4 is a schematic structural view of Embodiment 2 of a tunneling field effect transistor according to the present invention. As shown in FIG. 4, the tunneling field effect transistor includes: a substrate 10, a channel 11, a source region electrode 12, a drain region electrode 13, a gate dielectric layer 14, a third gate electrode 15, an insulating dielectric layer 16, and a first Gate electrode 17 and second gate electrode 18.

Specifically, the channel 11 is disposed over the substrate 10, and the length of the channel 11 is smaller than the length of the substrate 10. The material used for the channel 11 is black phosphorus. Along the length direction of the substrate 10, the source region electrode 12 and the drain region electrode 13 are respectively disposed at both ends of the substrate 10, and a part of the source region electrode 12 and the drain region electrode 13 are disposed on the substrate 10, and the other portion is disposed. On the channel 11. The gate dielectric layer 14 covers the exposed portions of the substrate 10, the channel 11, the source region electrode 12, and the drain region electrode 13. The third gate electrode 15 is disposed on the gate dielectric layer 14 in a region between the source region electrode 12 and the drain region electrode 13. The insulating dielectric layer 16 covers the exposed portion of the third gate electrode 15. The first gate electrode 17 is provided on the gate dielectric layer 14, and is seamlessly connected to the gate dielectric layer 14 on the source region electrode 12 side and the insulating dielectric layer 16 on the third gate electrode 15 side. The second gate electrode 18 is provided on the gate dielectric layer 14, and is seamlessly connected to the gate dielectric layer 14 on the drain electrode 13 side and the insulating dielectric layer 16 on the third gate electrode 15 side.

It should be noted that the relationship between the area occupied by the third gate electrode 15 and the insulating dielectric layer 16 and the area occupied by the gap in FIG. 1 is not limited in the embodiment of the present invention, and the two may be equal or unequal.

In the above embodiment, the third gate electrode 15 is a main gate electrode for controlling the opening or closing of the channel 11, and the voltage of the third gate electrode 15 can be changed in real time according to an applied switching command. The first gate electrode 17 and the second gate electrode 18 are both auxiliary gate electrodes for controlling the doping of the respective lower channel portions, and the respective voltage magnitudes and polarities remain fixed.

Optionally, the magnitude of the voltage of the first gate electrode 17 and the voltage of the second gate electrode 18 are both between -0.5 volts (volts, abbreviated as: V) to 0.5V. For example, the voltage of the first gate electrode 17 is fixed to 0.3 V, and the voltage of the second gate electrode 18 is fixed to -0.3 V, so that the lower channel corresponding to the first gate electrode 17 is N-type doped, and the second gate electrode The corresponding lower channel of 18 is P-type doped.

The embodiment shown in FIG. 4 differs from the embodiment shown in FIG. 1 in that the third gate electrode 15 and the insulating dielectric layer 16 covered thereon are used instead of the second gate electrode 18 and the first gate electrode in the structure shown in FIG. a gap between 17 and thus, with respect to the structure shown in FIG. 1, the tunneling field effect transistor shown in FIG. 4 is easy to achieve self-alignment between the auxiliary gate electrode and the main gate electrode, and the tunneling field effect transistor has better performance; The tunneling field effect transistor shown in FIG. 1 has only two gate electrodes, so that its area is smaller than that of the tunneling field effect transistor shown in FIG.

In a specific implementation manner, the material used for the source region electrode 12 is a low work function metal, and the material of the drain region electrode 13 is a high work function metal. At this time, the voltage polarity of the first gate electrode 17 is the positive electrode, and the voltage polarity of the second gate electrode 18 is the negative electrode, forming a P-type tunneling field effect transistor.

Alternatively, in another specific implementation, the material used for the source region electrode 12 is a high work function metal, and the material of the drain region electrode 13 is a low work function metal. In this implementation, the voltage polarity of the first gate electrode 17 is a negative electrode, and the voltage polarity of the second gate electrode 18 is a positive electrode, forming an N-type tunneling field effect transistor.

Further, in the above P-type tunneling field effect transistor, the material used for the first gate electrode 17 is a low work function metal (for example, metal germanium), which can further strengthen the N-type of the channel below the first gate electrode 17 The doping effect; the material used for the second gate electrode 18 is a high work function metal (for example, metal platinum), which can further enhance the P-type doping effect of the second gate electrode 18 on the channel below it.

Similarly, in the above-mentioned N-type tunneling field effect transistor, the material used for the first gate electrode 17 is a high work function metal to further enhance the N-type doping effect of the first gate electrode 17 on the channel below it; The material used for the second gate electrode 18 is a low work function metal, which further enhances the P-type doping effect of the second gate electrode 18 on the channel below it.

In addition, in consideration of the actual effect of the fabrication process, on the basis of the structure shown in FIG. 4, as shown in FIG. 5, the gate dielectric layer 14 on the side of the source region electrode 12 adjacent to the first gate electrode 17 may further include A metal block 171 may further include a second metal block 172 on the insulating dielectric layer 16 on the side of the third gate electrode 15 adjacent to the first gate electrode 17. The material of the first metal block 171 and the second metal block 172 is the same as the material of the first gate electrode 17.

Similarly, a third metal block 182 may be further disposed on the gate dielectric layer 14 on the side of the drain electrode 13 adjacent to the second gate electrode 18, and the insulating dielectric layer 16 on the side of the second gate electrode 15 adjacent to the second gate electrode 15 A fourth metal block 181 may also be included. The materials of the third metal block 182 and the fourth metal block 181 are the same as those of the second gate electrode 18.

Further, the tunneling field effect transistor may further include: a second passivation layer 102. Referring to FIG. 5, the second passivation layer 102 covers the structure obtained after the formation of the first gate electrode 17 and the second gate electrode 18. The second passivation layer 102 is for insulating air and may have a thickness greater than or equal to 100 nanometers.

A method of fabricating a tunneling field effect transistor in an embodiment of the present invention will be described below.

FIG. 6 is a flowchart of Embodiment 1 of a method for fabricating a tunneling field effect transistor according to the present invention. As shown in FIG. 6, the method for fabricating the tunneling field effect transistor includes:

S601, forming a channel on the substrate, the length of the channel is smaller than the length of the substrate, the material of the channel is a thin layer of black phosphorus, the thickness of the thin black phosphorus is greater than or equal to 2 nanometers, and the thin layer of black phosphorus The thickness is less than or equal to 30 nanometers.

S602, forming a source region electrode and a drain region electrode, wherein the source region electrode and the drain region electrode are respectively disposed at two ends of the substrate along a length direction of the substrate, and a part of the source region electrode and the drain region electrode are disposed on the substrate, The other part is placed on the channel.

S603, forming a gate dielectric layer covering the exposed portions of the substrate, the channel, the source region electrode and the drain region electrode.

S604, forming a first gate electrode and a second gate electrode, the first gate electrode is disposed on the gate dielectric layer, and the first gate electrode is seamlessly connected to the gate dielectric layer on the source region electrode side, and the second gate electrode is disposed On the gate dielectric layer, the second gate electrode is seamlessly connected to the gate dielectric layer on the drain electrode side, and a gap is formed between the second gate electrode and the first gate electrode.

Through the above steps, the tunneling field effect transistor structure shown in FIG. 1 is obtained, and the principle and function thereof are similar, and details are not described herein again.

FIG. 7 is a flowchart of Embodiment 2 of a method for fabricating a tunneling field effect transistor according to the present invention. As shown in FIG. 7, the method for fabricating the tunneling field effect transistor includes:

S701, forming a channel on the substrate, the length of the channel is smaller than the length of the substrate, the material of the channel is a thin layer of black phosphorus, the thickness of the thin black phosphorus is greater than or equal to 2 nanometers, and the thin layer of black phosphorus The thickness is less than or equal to 30 nanometers.

S702, forming a source region electrode and a drain region electrode, wherein the source region electrode and the drain region electrode are respectively disposed at two ends of the substrate along a length direction of the substrate, and a part of the source region electrode and the drain region electrode are disposed on the substrate, The other part is placed on the channel.

S703, forming a gate dielectric layer covering the exposed portions of the substrate, the channel, the source region electrode and the drain region electrode.

S704, forming a third gate electrode, the third gate electrode is disposed on the gate dielectric layer, and is located in the source region The area between the pole and drain electrode.

S705. Form an insulating dielectric layer covering the exposed portion of the third gate electrode.

S706, forming a first gate electrode and a second gate electrode, the first gate electrode is disposed on the gate dielectric layer, and the first gate electrode and the gate dielectric layer on the source region electrode side and the insulating dielectric layer of the third gate electrode are absent The second gate electrode is disposed on the gate dielectric layer, and the second gate electrode is seamlessly connected to the gate dielectric layer on the drain electrode side and the insulating dielectric layer of the third gate electrode.

Through the above steps, the tunneling field effect transistor structure shown in FIG. 4 is obtained, and its principle and function are similar, and details are not described herein again.

Optionally, the forming the source region electrode and the drain region electrode may include: coating a layer of photoresist on the structure obtained after forming the channel 11 on the substrate 10, except for the positions of the source region and the drain region electrode. 51, and exposed, a structure as shown in Fig. 8 was obtained; the source region electrode 12 and the drain region electrode 13 were formed by plating or sputtering, and the photoresist was removed to obtain a structure as shown in Fig. 9. The coating film may be specifically a process such as thermal evaporation or electron beam evaporation.

Alternatively, the forming the gate dielectric layer may include forming the gate dielectric layer 14 by atomic layer deposition on the structure obtained after forming the source region drain electrode and the drain region electrode, thereby obtaining a structure as shown in FIG.

As for the forming the first gate electrode and the second gate electrode, the method may include: coating a layer of photoresist on the structure obtained after forming the insulating dielectric layer except the positions of the first gate electrode and the second gate electrode, and exposing The first gate electrode 17 and the second gate electrode 18 are formed by plating and sputtering, and the photoresist is removed to obtain the first gate electrode 17 and the second gate electrode 18 as shown in FIG. 1 or FIG.

Further, the forming the third gate electrode may include: coating a layer of photoresist on the structure obtained after forming the gate dielectric layer except the position of the third gate electrode, and exposing; passing the coating and sputtering The third gate electrode 15 is formed, and the photoresist is removed to obtain a structure as shown in FIG.

Wherein, the formation of the insulating dielectric layer may be specifically performed by placing the structure obtained after forming the third gate electrode in air or ozone to form the insulating dielectric layer 16, and obtaining a structure as shown in FIG.

On the basis of the above, the method for preparing the tunneling field effect transistor may further include: preparing the first passivation layer on the structure obtained after forming the first gate electrode and the second gate electrode by physical deposition or chemical deposition. A structure such as that shown in FIG. 3 is obtained.

Alternatively, the method for fabricating the tunneling field effect transistor may further include: preparing a second passivation layer on the structure obtained after forming the insulating dielectric layer by physical deposition or chemical deposition, A structure such as that shown in Fig. 5 is obtained.

In the embodiment shown in FIG. 6, when the material used in the source region electrode is a low work function metal, and the material used in the drain region electrode is a high work function metal, the material used in the first gate electrode is a low work function metal. When a negative bias voltage is formed between the second gate electrode and the source region electrode, a P-type tunneling field effect transistor is formed. Wherein, the first gate electrode forms an N-type doping effect on the lower channel thereof, and the second gate electrode forms a P-type doping on the lower channel thereof.

Alternatively, when the material used in the source region electrode is a high work function metal, and the material used in the drain region electrode is a low work function metal, the material used for the first gate electrode is a high work function metal, the second gate electrode and the source. When a positive bias is formed between the region electrodes, an N-type tunneling field effect transistor is formed. Wherein, the first gate electrode forms a P-type doping effect on the lower channel thereof, and the second gate electrode forms an N-type doping on the lower channel thereof.

In the embodiment shown in FIG. 7, the material used for the source region electrode may be a low work function metal, and the material used for the drain region electrode may be a high work function metal, when a positive voltage is applied to the first gate electrode, in the second When a negative voltage is applied to the gate electrode, a P-type tunneling field effect transistor is formed; or, the material used in the source region electrode may be a high work function metal, and the material used in the drain region electrode may be a low work function metal, when in the first A negative voltage is applied to the gate electrode, and an N-type tunneling field effect transistor is formed when a positive voltage is applied to the second gate electrode.

Optionally, in the P-type tunneling field effect transistor, the material used in the first gate electrode is a low work function metal, which further enhances the N-type doping effect of the first gate electrode on the channel below; The material used for the gate electrode is a high work function metal, which further enhances the P-type doping effect of the second gate electrode on the channel below it.

Alternatively, in the above-described N-type tunneling field effect transistor, the material used for the first gate electrode is a high work function metal to further enhance the N-type doping effect of the first gate electrode on the channel below it; the second gate electrode The material used is a low work function metal, which further enhances the P-type doping effect of the second gate electrode on the channel below it.

Simulation

The following is a simulation comparison of the tunneling field effect transistor (black phosphorus TFET) and the silicon-based TFET as shown in FIG. 5 prepared by the embodiment of the present invention under the same conditions, and the simulation result shown in FIG. 13 is obtained, wherein The horizontal axis represents the voltage V _GS between the third gate electrode and the source electrode, in volts (V); the vertical axis represents the drain electrode current I _DS per unit channel width, in amperes per micron (A/μm) T is temperature, unit: Kelvin (K); V _DS is the bias voltage between the drain electrode and the source electrode, in volts (V). As can be seen from FIG. 13, under the same conditions, the on-state current of the tunneling field effect transistor prepared by the embodiment of the present invention is about one order of magnitude larger than the on-state current of the silicon-based TFET.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

A tunneling field effect transistor, comprising:

Substrate

a channel disposed on the substrate, the length of the channel being less than a length of the substrate, the material of the channel being a thin layer of black phosphorus, the thickness of the thin layer of black phosphorus being greater than or equal to 2 nm, and the thickness of the thin layer of black phosphorus is less than or equal to 30 nm;

a source region electrode and a drain region electrode, the source region electrode and the drain region electrode are respectively disposed at both ends of the substrate along a length direction of the substrate, and the source region electrode and the drain region a portion of each of the region electrodes is disposed on the substrate, and another portion is disposed on the channel;

a gate dielectric layer covering the bare portion of the substrate, the channel, the source region electrode, and the drain region electrode;

a first gate electrode disposed on the gate dielectric layer and seamlessly connected to the gate dielectric layer on the source region electrode side;

The second gate electrode is disposed on the gate dielectric layer and is seamlessly connected to the gate dielectric layer on the drain electrode side, and a gap is formed between the second gate electrode and the first gate electrode.
The tunneling field effect transistor of claim 1 wherein

The second gate electrode is a main gate electrode for controlling opening or closing of the channel, and a voltage of the second gate electrode is changed in real time according to an applied switching instruction;

The first gate electrode is a auxiliary gate electrode for controlling doping of a channel portion under the first gate electrode.
A tunneling field effect transistor according to claim 2, wherein

When the material used for the source region electrode is a low work function metal, and the material used for the drain region electrode is a high work function metal, the material used for the first gate electrode is a low work function metal, When a negative bias voltage is formed between the second gate electrode and the source region electrode, a P-type tunneling field effect transistor is formed;

Or, when the material used in the source region electrode is a high work function metal, and the material used in the drain region electrode is a low work function metal, the material used in the first gate electrode is a high work function metal. When a positive bias is formed between the second gate electrode and the source region electrode, an N-type tunneling field effect transistor is formed.
The tunneling field effect transistor according to any one of claims 1 to 3, characterized in that Also includes:

The first passivation layer covers the structure obtained after forming the first gate electrode and the second gate electrode.
The tunneling field effect transistor of claim 1 further comprising:

a third gate electrode disposed on the gate dielectric layer and located between the source region electrode and the drain region electrode;

An insulating dielectric layer covering the exposed portion of the third gate electrode;

The first gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side, and the second gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side.
A tunneling field effect transistor according to claim 5, wherein

The third gate electrode is a main gate electrode for controlling opening or closing of the channel, and a voltage of the third gate electrode is changed in real time according to an applied switching instruction;

The first gate electrode and the second gate electrode are both auxiliary gate electrodes for controlling doping of the respective lower channel portions, and the respective voltage magnitudes and polarities remain fixed.
The tunneling field effect transistor according to claim 6, wherein a voltage magnitude of the first gate electrode and a voltage of the second gate electrode are both between -0.5 volts and 0.5 volts.
A tunneling field effect transistor according to any one of claims 5 to 7, wherein

When the material used for the source region electrode is a low work function metal, and the material used for the drain region electrode is a high work function metal, the voltage polarity of the first gate electrode is a positive electrode, and the second The voltage polarity of the gate electrode is a negative electrode, forming a P-type tunneling field effect transistor;

Or, when the material used in the source region electrode is a high work function metal, and the material used in the drain region electrode is a low work function metal, the voltage polarity of the first gate electrode is a negative electrode, The voltage polarity of the second gate electrode is a positive electrode, forming an N-type tunneling field effect transistor.
The tunneling field effect transistor of claim 8 wherein:

In the P-type tunneling field effect transistor, the material used for the first gate electrode is a low work function metal, and the material used for the second gate electrode is a high work function metal;

Alternatively, in the N-type tunneling field effect transistor, the material used for the first gate electrode is a high work function metal, and the material used for the second gate electrode is a low work function metal.
A tunneling field effect transistor according to any one of claims 5 to 9, wherein

Further, a first metal block is further disposed on the gate dielectric layer on a side of the source region electrode adjacent to the first gate electrode, and further includes an insulating dielectric layer on a side of the third gate electrode adjacent to the first gate electrode a second metal block, a material of the first metal block and the second metal block being the same as a material of the first gate electrode;

Further, a third metal block is further disposed on the gate dielectric layer of the drain electrode adjacent to the second gate electrode, and further includes an insulating dielectric layer on a side of the third gate electrode adjacent to the second gate electrode The material of the fourth metal block, the third metal block and the fourth metal block is the same as the material of the second gate electrode.
The tunneling field effect transistor according to any one of claims 5 to 10, further comprising:

The second passivation layer covers the structure obtained after forming the insulating dielectric layer.
A method for preparing a tunneling field effect transistor, comprising:

Forming a channel on the substrate, the length of the channel being smaller than the length of the substrate, the material of the channel being a thin layer of black phosphorus, the thickness of the thin layer of black phosphorus being greater than or equal to 2 nanometers, and The thickness of the thin layer of black phosphorus is less than or equal to 30 nanometers;

Forming a source region electrode and a drain region electrode, the source region electrode and the drain region electrode are respectively disposed at both ends of the substrate along a length direction of the substrate, and the source region electrode and the One of the drain region electrodes is disposed on the substrate, and another portion is disposed on the channel;

Forming a gate dielectric layer covering the bare portion of the substrate, the channel, the source region electrode, and the drain region electrode;

Forming a first gate electrode and a second gate electrode, the first gate electrode being disposed on the gate dielectric layer, and the first gate electrode being seamlessly connected to the gate dielectric layer on the source region electrode side, a second gate electrode is disposed on the gate dielectric layer, and the second gate electrode is seamlessly connected to the gate dielectric layer on the drain region electrode side, and between the second gate electrode and the first gate electrode Form a gap.
The method according to claim 12, wherein the forming the source region electrode and the drain region electrode comprises:

Forming a structure after forming a channel on the substrate, in addition to the position of the source region electrode and the drain region electrode, spin coating a layer of photoresist, and exposing;

Forming the source region electrode and the drain region electrode by plating or sputtering, and removing the Photoresist.
The method according to claim 12 or 13, wherein the forming the gate dielectric layer comprises:

The gate dielectric layer is formed by atomic layer deposition on a structure obtained after forming the source region electrode and the drain region electrode.
The method according to any one of claims 12 to 14, wherein the forming the first gate electrode and the second gate electrode comprises:

On the structure obtained after forming the insulating dielectric layer, in addition to the positions of the first gate electrode and the second gate electrode, spin coating a layer of photoresist and exposing;

The first gate electrode and the second gate electrode are formed by plating and sputtering, and the photoresist is removed.
The preparation method according to any one of claims 12 to 15, further comprising:

A first passivation layer is formed on the structure obtained after forming the first gate electrode and the second gate electrode by physical deposition or chemical deposition.
The preparation method according to any one of claims 12 to 16, wherein

When the material used for the source region electrode is a low work function metal, and the material used for the drain region electrode is a high work function metal, the material used for the first gate electrode is a low work function metal, When a negative bias voltage is formed between the second gate electrode and the source region electrode, a P-type tunneling field effect transistor is formed;

Or, when the material used in the source region electrode is a high work function metal, and the material used in the drain region electrode is a low work function metal, the material used in the first gate electrode is a high work function metal. When a positive bias is formed between the second gate electrode and the source region electrode, an N-type tunneling field effect transistor is formed.
The method according to claim 12, wherein before the forming the first gate electrode and the second gate electrode, the method further comprises:

Forming a third gate electrode, the third gate electrode being disposed on the gate dielectric layer, a region between the source region electrode and the drain region electrode;

Forming an insulating dielectric layer covering the exposed portion of the third gate electrode;

Wherein the first gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side, The second gate electrode is seamlessly connected to the insulating dielectric layer on the third gate electrode side.
The method according to claim 18, wherein the forming the third gate electrode comprises:

On the structure obtained after forming the gate dielectric layer, in addition to the position of the third gate electrode, spin coating a layer of photoresist and exposing;

The third gate electrode is formed by plating and sputtering, and the photoresist is removed.
The method according to claim 18 or 19, wherein the forming the insulating dielectric layer comprises:

The structure obtained after forming the third gate electrode is placed in air or ozone to form the insulating dielectric layer.
The method according to any one of claims 18 to 20, further comprising: after forming the insulating dielectric layer, further comprising:

A second passivation layer is prepared on the structure obtained after forming the insulating dielectric layer by physical deposition or chemical deposition.
The preparation method according to any one of claims 18 to 21, wherein

The material used for the source region electrode is a low work function metal, and the material of the drain region electrode is a high work function metal. When a positive voltage is applied to the first gate electrode, the second gate electrode is applied. At a negative voltage, a P-type tunneling field effect transistor is formed;

Alternatively, the material used for the source region electrode is a high work function metal, and the material of the drain region electrode is a low work function metal, when a negative voltage is applied to the first gate electrode, at the second gate When a positive voltage is applied to the electrodes, an N-type tunneling field effect transistor is formed.
The preparation method according to claim 22, wherein

In the P-type tunneling field effect transistor, the material used for the first gate electrode is a low work function metal, and the material used for the second gate electrode is a high work function metal;

Alternatively, in the N-type tunneling field effect transistor, the material used for the first gate electrode is a high work function metal, and the material used for the second gate electrode is a low work function metal.