WO2018012019A1 - Method for evaluating and manufacturing silicon wafer - Google Patents

Method for evaluating and manufacturing silicon wafer Download PDF

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Publication number
WO2018012019A1
WO2018012019A1 PCT/JP2017/006727 JP2017006727W WO2018012019A1 WO 2018012019 A1 WO2018012019 A1 WO 2018012019A1 JP 2017006727 W JP2017006727 W JP 2017006727W WO 2018012019 A1 WO2018012019 A1 WO 2018012019A1
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Prior art keywords
silicon wafer
thermal donor
single crystal
defect
region
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PCT/JP2017/006727
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French (fr)
Japanese (ja)
Inventor
和尚 鳥越
小野　敏昭
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株式会社Sumco
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Priority to KR1020187036819A priority Critical patent/KR102180784B1/en
Priority to DE112017003486.8T priority patent/DE112017003486T5/en
Priority to CN201780043227.6A priority patent/CN109477241B/en
Publication of WO2018012019A1 publication Critical patent/WO2018012019A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • the present invention relates to a silicon wafer evaluation method and manufacturing method, and more particularly to a crystal defect region evaluation method of a silicon wafer manufactured by the Czochralski method (hereinafter referred to as “CZ method”).
  • CZ method a crystal defect region evaluation method of a silicon wafer manufactured by the Czochralski method
  • the CZ method is a method of growing a single crystal by melting a polycrystalline raw material filled in a quartz crucible with a heater and then immersing a seed crystal in the melt and pulling it upward while rotating it.
  • the FZ method is a method in which a part of a polycrystalline raw material rod is heated and melted at a high frequency to form a melting zone, and a single crystal is grown while moving the melting zone. Since the CZ method makes it easy to form a crystal with a large diameter, a wafer cut from a silicon single crystal manufactured by the CZ method is used as a highly integrated semiconductor element substrate.
  • Silicon wafers manufactured by the CZ method are exposed to thermal oxidation treatment for 1 to 10 hours in an acidic atmosphere of 1000 to 1200 ° C., and appear to have an oxidation-induced stacking fault (hereinafter referred to as OSF (Oxidation-induced Stacking-Fault)) Ring)) may occur.
  • OSF Oxidation-induced Stacking-Fault
  • Ring oxidation-induced stacking fault
  • several types of minute defects hereinafter referred to as “Grown-in defects”.
  • the generation site of the OSF ring in the crystal includes a growth rate (pulling rate) V of the silicon single crystal and a temperature gradient G in the pulling axis direction in the temperature range from the melting point of the grown silicon single crystal to 1300 ° C.
  • the ratio V / G When the V / G is larger than the critical value at which the OSF ring disappears at the center of the crystal, the vacancies agglomerate to form an octahedral void defect of about 0.1 ⁇ m, and a MOS type LSI is manufactured. In this case, the breakdown voltage of the gate oxide film is deteriorated, or an isolation defect in the element isolation region is caused. In addition, when trench capacitor is used, characteristic defects such as punch-through between the capacitor are caused. On the other hand, when V / G is smaller than the critical value, interstitial silicon aggregates to form dislocation clusters, leading to characteristic defects such as PN junction leakage.
  • Patent Document 1 a ratio V / G between a pulling rate V and a temperature gradient G in a crystal is controlled in a single crystal growth so that no grown-in defect or OSF ring occurs (hereinafter referred to as a defect-free region). ) Has been proposed.
  • a method for evaluating a Grown-in defect or an OSF ring for example, a method of detecting a void defect by infrared scattering tomography or an OSF ring that is manifested by etching after the thermal oxidation treatment at 1000 to 1200 ° C. described above with a microscope is used. The observation method is known.
  • Patent Documents 2 and 3 describe a method for analyzing and evaluating crystal defects of a silicon wafer by a so-called copper decoration method.
  • the analysis method described in Patent Document 2 includes a step of forming a thermal oxide film having a predetermined thickness on the surface of a bare wafer, a step of etching a bag side of the bare wafer, and copper at a defective portion of the bare wafer. And a step of analyzing a defect portion of the wafer decorated with copper after the step of performing copper decorating.
  • the distribution and density of defect sites on the copper-decorated wafer are analyzed with the naked eye, and the morphology of the defect sites on the copper-decorated wafer is analyzed by transmission electron microscope (TEM) or scanning electron microscope (SEM). ) To analyze.
  • TEM transmission electron microscope
  • SEM scanning electron microscope
  • Patent Document 3 describes a method of evaluating crystal defects in a silicon single crystal manufactured by the CZ method by a copper decoration method in which a sample contaminated with copper is heat-treated and then rapidly cooled.
  • a copper decoration method is applied to a silicon single crystal having a low oxygen concentration with an interstitial oxygen concentration of 10 ⁇ 10 17 atoms / cm 3 (ASTM'79) or less in the crystal, and a nucleus that becomes OSF or OSF. The area where the is present is detected with high sensitivity.
  • the film thickness of an epitaxial layer or a DZ layer in an epitaxial wafer is measured by measuring the resistivity of the wafer by a thermal donor generated from interstitial oxygen when the silicon wafer is annealed at a low temperature of about 450 ° C.
  • a method for evaluating a wafer structure related to oxygen concentration distribution such as measurement is described.
  • JP-A-8-330316 Japanese Patent Laid-Open No. 10-227729 JP 2001-81000 A JP-A-9-82768
  • the conventional method for evaluating crystal defects of a general silicon wafer requires a plurality of heat treatments and etching processes according to the types of crystal defects, and there is a problem that the evaluation takes time and cost.
  • the silicon wafer crystal defect evaluation method using the copper decoration method can simultaneously evaluate the presence or absence of a grown-in defect region or an OSF ring region, but a heat treatment process of several tens of hours for copper decoration. Is necessary, and there is a problem of lack of simplicity.
  • an object of the present invention is to provide a silicon wafer evaluation method and manufacturing method capable of evaluating the presence and type of a crystal defect region of a silicon wafer by a simple method while saving time and cost.
  • a silicon wafer evaluation method is an evaluation method of a silicon wafer cut out from a silicon single crystal ingot grown by a CZ method, and a thermal donor generation heat treatment is performed on the silicon wafer. It is characterized in that the generation rate of a thermal donor that is sometimes generated is measured, and the presence or absence of a crystal defect region or the type of crystal defect is determined based on the generation rate of the thermal donor.
  • a thermal donor generation rate based on a change in specific resistance caused by heat treatment of a silicon wafer cut from a silicon single crystal ingot grown by the CZ method while controlling V / G is measured.
  • the presence / absence of a crystal defect region and the type of crystal defect can be easily evaluated.
  • the first silicon wafer cut out from the silicon single crystal ingot is subjected to the thermal donor generation heat treatment in a state where the first silicon wafer includes an oxygen cluster.
  • the first thermal donor generation rate which is the generation rate of the thermal donor generated at the measurement point, was obtained, and the donor killer process and the thermal donor generation heat treatment were sequentially performed on the second silicon wafer different from the first silicon wafer.
  • a second thermal donor generation rate that is a generation rate of a thermal donor generated at a second measurement point on the second silicon wafer is sometimes obtained, and a first thermal donor generation relative to the second thermal donor generation rate is obtained.
  • the state in which the silicon wafer includes oxygen clusters refers to a state before the donor killer process is performed on the silicon wafer in the as-grown state.
  • the defect-free region refers to a region that does not include a grown-in defect and does not generate an OSF ring after the evaluation heat treatment.
  • the present invention based on the first and second thermal donor generation rates obtained from the two types of wafers having the difference in the presence or absence of the donor killer process, the presence or absence of the crystal defect region and the crystal defect The type can be easily evaluated.
  • the silicon wafer evaluation method determines that the first measurement point on the first silicon wafer is a defect-free region when the thermal donor generation speed ratio is within the first speed range.
  • the thermal donor generation speed ratio is in a second speed range higher than the first speed range, it is determined that the first measurement point is a region including a void defect, and the thermal donor
  • the generation speed ratio is in a third speed range higher than the second speed range, it is preferable to determine that the first measurement point is a region including an OSF nucleus.
  • the thermal donor generation heat treatment is preferably a heat treatment at 430 ° C. to 480 ° C. for 2 hours to 4 hours, and more preferably at 450 ° C. for 4 hours. Under this heat treatment condition, it is possible to activate the oxygen cluster and evaluate the presence or absence of a crystal defect region and the type of crystal defect based on the thermal donor generation rate.
  • the first silicon when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours, the first silicon is used when the thermal donor generation rate ratio is 1.3 or more and less than 1.7.
  • the first measurement point on the wafer is determined to be a defect-free region, and the thermal donor generation rate ratio is 1.7 or more and less than 1.9, the first measurement point includes a void defect. It is preferable to determine that the first measurement point is a region containing OSF nuclei when the thermal donor generation rate ratio is 1.9 or more and less than 2.3. By such determination, it is possible to easily determine an OSF ring region, a region including a void defect, and a defect-free region.
  • the crystal defect map in the radial direction of the silicon wafer is measured by measuring the generation rate of the thermal donor at each of a plurality of measurement points provided along the radial direction of the silicon wafer. It is preferable to create
  • the specific resistance of the silicon wafer is measured, the carrier concentration is obtained from an Irbin curve based on the specific resistance, and the thermal donor is calculated based on the carrier concentration before and after the thermal donor generation heat treatment. It is preferable to determine the generation amount and determine the thermal donor generation rate from the relationship between the thermal donor generation heat treatment time and the thermal donor generation amount. In this case, it is preferable to measure the specific resistance of the silicon wafer by a four-probe method.
  • the silicon wafer manufacturing method includes a first silicon single crystal ingot grown by the Czochralski method and subjected to thermal donor generation heat treatment on the silicon wafer for evaluation cut out from the first silicon single crystal ingot. And measuring the generation rate of the thermal donor generated at the time, and determining the presence or absence of the crystal defect region or the type of crystal defect in the silicon wafer for evaluation based on the measurement result of the generation rate of the thermal donor.
  • the second silicon single crystal ingot growth condition is adjusted based on the growth condition of the silicon single crystal ingot and the determination result of the presence or absence of the crystal defect region in the silicon wafer for evaluation or the type of the crystal defect.
  • a silicon wafer for production is cut out from a silicon single crystal ingot.
  • the second silicon single crystal ingot having a defect-free region may be grown by adjusting a growth condition of the second silicon single crystal ingot.
  • the second silicon single crystal ingot having a region including it may be grown, or the second silicon single crystal ingot having a region including an OSF nucleus may be grown.
  • the product silicon wafer is preferably subjected to donor killer treatment. According to this, it is possible to provide a silicon wafer product that is not affected by the thermal donor.
  • the evaluation method and manufacturing method of a silicon wafer which can evaluate the presence or absence of the crystal defect area
  • FIG. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects.
  • FIG. 3 is a flowchart showing a thermal donor generation rate measurement step.
  • FIG. 4 is a flowchart showing a process of discriminating the presence / absence of a crystal defect region in the wafer and the type of crystal defect.
  • FIG. 5 is a graph showing the relationship between the thermal donor generation rate and the thermal donor generation heat treatment time of the wafer samples A1 to A3 and B1 to B3.
  • FIG. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects.
  • FIG. 3 is a flowchart showing a thermal donor generation rate measurement step.
  • FIG. 4 is a flowchart showing
  • FIG. 6 shows the result of determining the relationship between the thermal donor generation rate and the oxygen concentration in the OSF ring generation region, the region including void defects, and the defect-free region when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours. It is a graph which shows.
  • FIG. 7 is a graph in which the thermal donor generation rate at each measurement point of the wafer without donor killer treatment in FIG. 6 is normalized by the thermal donor generation rate at the same measurement point of the wafer with donor killer treatment.
  • FIG. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention.
  • the silicon single crystal manufacturing method includes a crystal growth step (S11) for growing a silicon single crystal ingot by the CZ method, and a slicing step (S12) for cutting a silicon wafer from the silicon single crystal ingot. ), Thermal donor generation rate measurement step (S13Y, S14) performed when the evaluation of the crystal defect region of the silicon wafer is necessary, and the presence / absence of the crystal defect region and the type of crystal defect from the measurement result of the thermal donor generation rate A discriminating step (S15), and an adjusting step (S16Y, S17) for adjusting the growth conditions of the subsequent silicon single crystal ingot based on the discriminating result of the presence / absence of a crystal defect region and the type of crystal defect. Yes.
  • the silicon single crystal manufacturing method includes a donor killer processing step (S18) performed when evaluation of a silicon wafer is unnecessary, and a product such as mirror polishing performed on the silicon wafer after the donor killer processing. And a processing step (S19).
  • the kind and distribution of crystal defects contained in a silicon single crystal grown by the CZ method depend on the ratio V / G between the pulling speed V of the silicon single crystal and the temperature gradient G in the crystal in the pulling axis direction. Therefore, in order to control the crystal quality in the silicon single crystal, it is necessary to precisely control V / G. However, whether or not a silicon single crystal ingot (first silicon single crystal ingot) grown under a certain condition has a desired crystal quality cannot be known without actually evaluating the crystal quality.
  • the presence / absence of a crystal defect region in the wafer cut out from the silicon single crystal ingot and the type of crystal defect are evaluated.
  • this evaluation result is fed back to the subsequent silicon single crystal ingot (second silicon single crystal ingot) growing process.
  • the crystal growth conditions such as the crystal pulling speed V are adjusted so that the desired crystal quality is obtained.
  • FIG. 2 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects.
  • V / G when V / G is large, vacancies become excessive and void defects that are aggregates of vacancies are generated.
  • a void defect is a crystal defect generally referred to as COP (Crystal Originated Particle).
  • V / G when V / G is small, the number of interstitial silicon atoms becomes excessive, and dislocation clusters that are aggregates of interstitial silicon are generated. Therefore, in order to produce a single crystal containing neither COP nor dislocation clusters, V / G must be controlled in both the radial direction and the length direction (crystal growth direction) of the single crystal.
  • an appropriate high temperature region is set in the chamber in order to keep the temperature gradient G in the radial direction within a predetermined range. Need to build.
  • the intra-crystal temperature gradient G in the radial direction is controlled by a heat shield provided above the silicon melt, whereby an appropriate hot zone can be constructed near the solid-liquid interface.
  • the temperature gradient G in the crystal in the length direction depends not only on the hot zone structure but also on the crystal pulling speed V, it is necessary to adjust the single crystal pulling speed V. At present, by strictly controlling the crystal pulling speed V, silicon single crystals having a diameter of 300 mm that do not contain COPs or dislocation clusters are mass-produced.
  • a silicon wafer that does not contain COP and dislocation clusters pulled up by controlling V / G is never homogeneous, and includes a plurality of regions that behave differently when heat-treated. For example, there are three regions, an OSF region, a Pv region, and a Pi region, in descending order of V / G between a region where COP occurs and a region where dislocation clusters occur.
  • the OSF region contains plate-like oxygen precipitates (OSF nuclei) in the as-grown state (the state in which no heat treatment is performed after single crystal growth), and is thermally oxidized at a high temperature of 1000 to 1200 ° C. This is a region where OSF occurs.
  • the Pv region includes oxygen precipitation nuclei in an as-grown state, and is a region where oxygen precipitates are easily generated when two-stage heat treatment is performed at a low temperature and a high temperature (for example, 800 ° C. and 1000 ° C.).
  • the Pi region is a region that hardly contains oxygen precipitation nuclei in an as-grown state and hardly generates oxygen precipitates even after heat treatment.
  • the control of V / G is performed mainly by adjusting the pulling speed V.
  • V / G is too large. Decrease the crystal pulling speed V.
  • V / G is too small and the crystal pulling speed V is increased. .
  • the time change of the thermal donor in the silicon wafer cut out from the ingot is measured.
  • oxygen dissolved from the quartz crucible is usually 10 ⁇ 10 17 atoms / cm 3 (ASTM F-121, 1979). This oxygen causes crystal defects in the wafer and causes device characteristic defects.
  • the wafer strength is increased to suppress deformation and heavy metals that cause device malfunction. It acts in a complicated manner, for example, by forming an oxygen precipitate having a gettering action for trapping the inside of the wafer.
  • oxygen atoms in silicon are electrically neutral and do not affect their electrical resistance.
  • a silicon single crystal produced by the CZ method is grown using a quartz crucible, it contains supersaturated oxygen in the crystal.
  • heat-treated at a low temperature of around 450 ° C. several oxygen atoms gather to form an oxygen cluster. It is known to form and become a donor that emits electrons.
  • the thermal donor formed by heat treatment at around 450 ° C. is affected by point defects, and the thermal donor generation rate differs depending on the difference in point defect concentration between the vacancy dominant region (COP region and OSF ring region) and the defect-free region. Therefore, in this embodiment, the presence / absence of a crystal defect region in the silicon wafer and the type of crystal defect are determined based on the generation rate of thermal donors generated in the silicon wafer.
  • thermal donor generation rate measuring step (S14) two silicon wafers for evaluation that are continuously cut out from the ingot by the slicing step (S12) are prepared.
  • the two evaluation wafers are preferably wafers cut out from the ingot by a wire saw and subjected to rough polishing.
  • one of the wafers (first wafer) is subjected to a thermal donor generation heat treatment step without performing donor killer treatment in advance, and the other wafer (second wafer) is subjected to donor killer treatment in advance and then subjected to thermal treatment.
  • a donor generation heat treatment is performed, and a thermal donor generation speed is obtained from a change in specific resistance before and after the thermal donor generation heat treatment of each of the first and second wafers.
  • FIG. 3 is a flowchart showing a thermal donor generation rate measurement step.
  • the thermal donor generation rate measurement step (S14) includes a preparation step (S20) for preparing the first and second wafers in the as-grown state, and a ratio for measuring the specific resistance of the first wafer.
  • a resistance measurement step (S21), a thermal donor generation heat treatment step (S22) for performing thermal donor generation heat treatment on the first wafer after the specific resistance measurement, and a specific resistance of the first wafer after the thermal donor generation heat treatment are measured.
  • the thermal donor generation rate measuring step (S14) includes a step of performing donor killer processing on the second wafer (S25), a resistance measuring step of measuring the specific resistance of the second wafer after donor killer processing (S26), and A thermal donor generation heat treatment step (S27) for performing the same thermal donor generation heat treatment as that of the first wafer on the second wafer after the specific resistance measurement, and a specific resistance of the second wafer after the thermal donor generation heat treatment are measured.
  • the temperature of the thermal donor-generated heat treatment is preferably 430 to 480 ° C, particularly preferably 450 ° C.
  • the heat treatment time for generating the thermal donor is preferably 1 to 4 hours, more preferably 2 to 4 hours.
  • the donor killer treatment is a short-time heat treatment performed in an inert gas atmosphere at 600 to 700 ° C., for example, and the heat treatment time is about 15 minutes, for example.
  • the specific resistance in the silicon wafer surface can be measured by a so-called four-probe method. Based on the measured specific resistance, the carrier concentration is determined from the Irvine curve, the amount of thermal donor generation is determined based on the carrier concentration before and after the thermal donor generation heat treatment, and from the relationship between the thermal donor generation heat treatment time and the amount of thermal donor generation The thermal donor generation rate can be determined.
  • a defect map in the radial direction of the silicon wafer can be created.
  • FIG. 4 is a flowchart showing a process for discriminating the presence / absence of a crystal defect region in the wafer and the type of crystal defect.
  • the ratio of the first thermal donor generation rate to the second thermal donor generation rate is calculated (S30).
  • the value is 1.3 or more and less than 1.7
  • the value is 1.7 or more and less than 1.9, it is a region including a void defect. It discriminate
  • the silicon wafer evaluation method cuts out a silicon wafer from a silicon single crystal ingot grown by the CZ method and performs thermal donor generation heat treatment on the silicon wafer. Since the generation rate is measured and the presence or absence of the crystal defect region or the type of crystal defect is determined based on the generation rate of the thermal donor, the region including the OSF nucleus, the region including the void defect, or the non-defect region can be quickly determined. It can be easily determined.
  • unlike the conventional evaluation method for example, it is not necessary to decorate copper, and evaluation can be performed with a relatively short time of low-temperature heat treatment. Existence and types of crystal defects can be evaluated.
  • the silicon wafer manufacturing method measures the thermal donor generation rate of the evaluation silicon wafer cut out from the preceding silicon single crystal ingot, and based on the measurement result of the thermal donor generation rate, the evaluation silicon wafer Since the presence / absence of the crystal defect region or the type of the crystal defect is discriminated, and the growth condition of the subsequent silicon single crystal ingot is adjusted based on the discrimination result, the crystal growth condition can be easily optimized.
  • the first and second silicon wafers cut from the silicon single crystal ingot in the thermal donor generation rate measuring step (S14) are prepared, and the donor killer process (S25) is performed on the second wafer.
  • the thermal donor generation heat treatment (S27) is performed to calculate the second thermal donor generation rate.
  • such a step of calculating the second thermal donor generation rate can be omitted.
  • the other silicon wafer equivalent to the second silicon wafer is subjected to donor killer treatment and thermal donor generation heat treatment, and the second thermal donor generation rate calculated in advance is made into a database to generate the second thermal donor generation.
  • the speed read from the database may be used, and only the first thermal donor generation speed may be measured to evaluate the presence / absence of a crystal defect region and the type of crystal defect.
  • the effect of the type of crystal defects on the thermal donor generation rate was evaluated.
  • a P-type silicon single crystal ingot having a diameter of 300 mm and a plane orientation (100) was grown by the CZ method.
  • a silicon single crystal ingot was grown while controlling V / G so as to include the OSF ring generation region.
  • the oxygen concentration of this silicon single crystal ingot was 5 ⁇ 10 17 to 20 ⁇ 10 17 atoms / cm 3 (ASTM F-121, 1979).
  • samples A1 and B1 of two silicon wafers including the OSF ring generation region were obtained.
  • the OSF ring generation region refers to a region where an OSF ring is generated after the evaluation heat treatment, and refers to a region including OSF nuclei in an as-grown state.
  • a silicon single crystal ingot is grown under the same conditions as Samples A1 and B1 except that the V / G is controlled so that a void defect area is included, and the silicon single crystal ingot is sliced to obtain a void defect.
  • Samples A2 and B2 of two silicon wafers including the region where the sapphire exists were obtained.
  • a silicon single crystal ingot is produced under the same conditions as those of the samples A1 and B1 except that V / G is controlled so as to be a defect-free region, and this silicon single crystal ingot is sliced to form 2 Two silicon wafer samples A3 and B3 were obtained.
  • a donor killer treatment was performed in a nitrogen atmosphere at 700 ° C. for 15 minutes.
  • Samples A1 to A3 of silicon wafers prepared by processes without donor killer treatment (Examples 1 to 3) and samples B1 to B3 of silicon wafers prepared by processes with donor killer treatment (Comparative Examples 1 to 3), respectively.
  • Thermal donor generation heat treatment was performed in a nitrogen atmosphere at 450 ° C. to generate a thermal donor.
  • FIG. 5 is a graph showing the relationship between the thermal donor generation rate of the wafer samples A1 to A3 and B1 to B3 and the thermal donor generation heat treatment time.
  • the horizontal axis represents the heat treatment time (h), and the vertical axis represents the thermal donor generation rate. (Cm ⁇ 3 / h) is shown respectively.
  • this graph is summarized only for wafers that satisfy the condition of oxygen concentration of 11 ⁇ 10 17 atoms / cm 3 .
  • the donor killer treatment is performed on the OSF ring generation region, the region including the void defect, and the non-defect region as compared with the case where the donor killer treatment is performed (samples B1, B2, and B3). None (samples A1, A2, A3) had a higher thermal donor generation rate.
  • the thermal donor generation rate was the same in any region with the donor killer treatment, but without the donor killer treatment, the thermal donor generation rate increased in the order of the OSF ring generation region, the void-containing region, and the defect-free region. became.
  • the thermal donor generation rate once increased and then decreased without the donor killer treatment.
  • the thermal donor generation rate decreased, and after 16 hours, the thermal donor generation rate became the same under all conditions.
  • FIG. 6 shows the result of determining the relationship between the thermal donor generation rate and the oxygen concentration in the OSF ring generation region, the region including void defects, and the defect-free region when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours.
  • the horizontal axis represents the oxygen concentration ( ⁇ 10 17 atoms / cm 3 ), and the vertical axis represents the thermal donor generation rate (cm ⁇ 3 / h).
  • the wafer with no donor killer treatment is the thermal donor at any oxygen concentration rather than the donor killer treatment (samples B1, B2, B3).
  • the generation rate was great.
  • the thermal donor generation rate was the same in all regions in the wafer with the donor killer process, but in the wafer without the donor killer process, the thermal donor was in the order of the OSF ring generation region, the region including the void defect, and the non-defect region. The generation rate has increased.
  • FIG. 7 is a graph in which the thermal donor generation rate at each measurement point of the wafer without donor killer treatment is normalized with the thermal donor generation rate at the same measurement point of the wafer with donor killer treatment in the graph of FIG.
  • the horizontal axis represents the oxygen concentration ( ⁇ 10 17 atoms / cm 3 ), and the vertical axis represents the thermal donor generation rate (standard value).
  • the thermal donor generation rate in the defect-free region of the wafer without donor killer treatment was 1.3 times or more and less than 1.7 times the thermal donor generation rate of the wafer with donor killer treatment.
  • the thermal donor generation rate in the region including the void defect of the wafer without donor killer treatment was 1.7 times or more and less than 1.9 times the thermal donor generation rate of the wafer with donor killer treatment.
  • the thermal donor generation rate in the OSF ring generation region of the wafer without donor killer treatment was 1.9 times or more and less than 2.3 times the thermal donor generation rate of the wafer with donor killer treatment.

Abstract

According to the present invention, the presence and types of defective regions in a silicon wafer are evaluated with a simple method while saving time and costs. This method for evaluating a silicon wafer, which is cut from a single crystal silicon ingot grown by using the Czochralski method, includes: (S14) measuring the generation rate of thermal donors generated when a thermal-donor-generating heat treatment is performed on the silicon wafer; and (S15) determining the presence of crystalline defective regions and the types of crystalline defects on the basis of the generation rate of thermal donors.

Description

シリコンウェーハの評価方法及び製造方法Silicon wafer evaluation method and manufacturing method
　本発明は、シリコンウェーハの評価方法及び製造方法に関し、特に、チョクラルスキー法（以下、「ＣＺ法」という）によって製造されたシリコンウェーハの結晶欠陥領域の評価方法に関するものである。 The present invention relates to a silicon wafer evaluation method and manufacturing method, and more particularly to a crystal defect region evaluation method of a silicon wafer manufactured by the Czochralski method (hereinafter referred to as “CZ method”).
　半導体材料に用いられるシリコン単結晶の製造には種々の方法があるが、一般にＣＺ（Czochralski）法、又は、ＦＺ（Floating Zone）法が用いられている。ＣＺ法は、石英ルツボに充填した多結晶原料をヒーターで加熱溶融した後、この融液に種結晶を浸し、これを回転させつつ上方に引き上げることによって単結晶を成長させる方法である。また、ＦＺ法は、多結晶原料ロッドの一部を高周波で加熱溶融して溶融帯域を作り、この溶融帯域を移動させながら単結晶を成長させる方法である。前記ＣＺ法は、大きな直径の結晶の形成が容易であるため、ＣＺ法で製造したシリコン単結晶から切り出したウェーハが、高集積度半導体素子基板として用いられている。 There are various methods for producing a silicon single crystal used as a semiconductor material, but generally, the CZ (Czochralski) method or the FZ (Floating Zone) method is used. The CZ method is a method of growing a single crystal by melting a polycrystalline raw material filled in a quartz crucible with a heater and then immersing a seed crystal in the melt and pulling it upward while rotating it. The FZ method is a method in which a part of a polycrystalline raw material rod is heated and melted at a high frequency to form a melting zone, and a single crystal is grown while moving the melting zone. Since the CZ method makes it easy to form a crystal with a large diameter, a wafer cut from a silicon single crystal manufactured by the CZ method is used as a highly integrated semiconductor element substrate.
　ＣＺ法によって製造されたシリコンウェーハは、１０００～１２００℃の酸性雰囲気下で１～１０時間の熱酸化処理を受けたとき、リング状に現れる酸化誘起積層欠陥（以下、ＯＳＦ（Oxidation induced Stacking Fault）リングという）が発生する場合がある。その他に、数種類の微小欠陥（以下、Ｇｒｏｗｎ－ｉｎ欠陥という）が形成される。 Silicon wafers manufactured by the CZ method are exposed to thermal oxidation treatment for 1 to 10 hours in an acidic atmosphere of 1000 to 1200 ° C., and appear to have an oxidation-induced stacking fault (hereinafter referred to as OSF (Oxidation-induced Stacking-Fault)) Ring)) may occur. In addition, several types of minute defects (hereinafter referred to as “Grown-in defects”) are formed.
　結晶内でのＯＳＦリングの発生部位は、シリコン単結晶の成長速度（引き上げ速度）Ｖと、育成されるシリコン単結晶の融点から１３００℃までの温度域内における引き上げ軸方向の結晶内温度勾配Ｇとの比Ｖ／Ｇによって決定される。ＯＳＦリングが結晶中心部で消滅する臨界値よりもＶ／Ｇが大きい場合には空孔が凝集して、０．１μｍ程度の八面体の空洞（ボイド）欠陥が形成され、ＭＯＳ型ＬＳＩを製造する場合にゲート酸化膜の耐圧を劣化させたり、素子分離領域の分離不良を生じさせたりする。さらにトレンチキヤパシターを用いる場合にキヤパシター間のパンチスルー等の特性不良を招く。一方、Ｖ／Ｇが臨界値より小さい場合には格子間シリコンが凝集して転位クラスターが形成され、ＰＮ接合リーク等の特性不良を招く。 The generation site of the OSF ring in the crystal includes a growth rate (pulling rate) V of the silicon single crystal and a temperature gradient G in the pulling axis direction in the temperature range from the melting point of the grown silicon single crystal to 1300 ° C. The ratio V / G. When the V / G is larger than the critical value at which the OSF ring disappears at the center of the crystal, the vacancies agglomerate to form an octahedral void defect of about 0.1 μm, and a MOS type LSI is manufactured. In this case, the breakdown voltage of the gate oxide film is deteriorated, or an isolation defect in the element isolation region is caused. In addition, when trench capacitor is used, characteristic defects such as punch-through between the capacitor are caused. On the other hand, when V / G is smaller than the critical value, interstitial silicon aggregates to form dislocation clusters, leading to characteristic defects such as PN junction leakage.
　このような問題に対応するため、従来から多くの方法が提案されている。例えば、特許文献１では、単結晶育成時の引上げ速度Ｖと結晶内の温度勾配Ｇの比Ｖ／Ｇを制御して、いかなるＧｒｏｗｎ－ｉｎ欠陥もＯＳＦリングも発生しない領域（以下、無欠陥領域）を育成する方法が提案されている。 In the past, many methods have been proposed to deal with such problems. For example, in Patent Document 1, a ratio V / G between a pulling rate V and a temperature gradient G in a crystal is controlled in a single crystal growth so that no grown-in defect or OSF ring occurs (hereinafter referred to as a defect-free region). ) Has been proposed.
　Ｇｒｏｗｎ－ｉｎ欠陥やＯＳＦリングの評価方法としては、例えば、赤外散乱トモグラフによってボイド欠陥を検出する方法や上述した１０００～１２００℃の熱酸化処理後にエッチングすることによって顕在化するＯＳＦリングを顕微鏡で観察する方法などが知られている。 As a method for evaluating a Grown-in defect or an OSF ring, for example, a method of detecting a void defect by infrared scattering tomography or an OSF ring that is manifested by etching after the thermal oxidation treatment at 1000 to 1200 ° C. described above with a microscope is used. The observation method is known.
　また特許文献２、３には、いわゆる銅デコレーション法によりシリコンウェーハの結晶欠陥を分析・評価する方法が記載されている。例えば特許文献２に記載された分析方法は、ベアウェーハの表面上に所定の厚さの熱酸化膜を形成させる段階と、ベアウェーハのバッグサイドをエッチングする段階と、ベアウェーハの欠陥部位に銅のデコレーティングを遂行する段階と、銅のデコレーティング遂行段階の以後に銅がデコレーションされたウェーハの欠陥部位を分析する段階を備えている。分析段階では、銅がデコレーションされたウェーハの欠陥部位の分布及び密度が肉眼で分析することの他、銅でデコレーションされたウェーハの欠陥部位のモルホロジーを透過電子顕微鏡（ＴＥＭ）又は走査電子顕微鏡（ＳＥＭ）で分析する。 Patent Documents 2 and 3 describe a method for analyzing and evaluating crystal defects of a silicon wafer by a so-called copper decoration method. For example, the analysis method described in Patent Document 2 includes a step of forming a thermal oxide film having a predetermined thickness on the surface of a bare wafer, a step of etching a bag side of the bare wafer, and copper at a defective portion of the bare wafer. And a step of analyzing a defect portion of the wafer decorated with copper after the step of performing copper decorating. In the analysis stage, the distribution and density of defect sites on the copper-decorated wafer are analyzed with the naked eye, and the morphology of the defect sites on the copper-decorated wafer is analyzed by transmission electron microscope (TEM) or scanning electron microscope (SEM). ) To analyze.
　さらに、特許文献３には、銅で汚染した試料を熱処理した後に急冷する銅デコレーション法により、ＣＺ法で製造したシリコン単結晶中の結晶欠陥を評価する方法が記載されている。この評価方法では、結晶中の格子間酸素濃度が１０×１０１７ａｔｏｍｓ／ｃｍ３（ＡＳＴＭ'７９）以下の低酸素濃度のシリコン単結晶に対して銅デコレーション法を施し、ＯＳＦ又はＯＳＦとなる核が存在する領域を高感度で検出する。 Further, Patent Document 3 describes a method of evaluating crystal defects in a silicon single crystal manufactured by the CZ method by a copper decoration method in which a sample contaminated with copper is heat-treated and then rapidly cooled. In this evaluation method, a copper decoration method is applied to a silicon single crystal having a low oxygen concentration with an interstitial oxygen concentration of 10 × 10 17 atoms / cm 3 (ASTM'79) or less in the crystal, and a nucleus that becomes OSF or OSF. The area where the is present is detected with high sensitivity.
　特許文献４には、シリコンウェーハを４５０℃程度の低温でアニールしたときに格子間酸素から生成されるサーマルドナーによるウェーハの抵抗率を測定することによって、エピタキシャルウェーハにおけるエピタキシャル層やＤＺ層の膜厚測定など、酸素濃度分布に関連したウェーハ構造を評価する方法が記載されている。 In Patent Document 4, the film thickness of an epitaxial layer or a DZ layer in an epitaxial wafer is measured by measuring the resistivity of the wafer by a thermal donor generated from interstitial oxygen when the silicon wafer is annealed at a low temperature of about 450 ° C. A method for evaluating a wafer structure related to oxygen concentration distribution such as measurement is described.
特開平８－３３０３１６号公報JP-A-8-330316 特開平１０－２２７７２９号公報Japanese Patent Laid-Open No. 10-227729 特開２００１－８１０００号公報JP 2001-81000 A 特開平９－８２７６８号公報JP-A-9-82768
　しかしながら、従来の一般的なシリコンウェーハの結晶欠陥の評価方法は、結晶欠陥の種類に応じた複数の熱処理やエッチング工程を必要とするものであり、評価に時間とコストがかかるという問題がある。 However, the conventional method for evaluating crystal defects of a general silicon wafer requires a plurality of heat treatments and etching processes according to the types of crystal defects, and there is a problem that the evaluation takes time and cost.
　また、銅デコレーション法を利用したシリコンウェーハの結晶欠陥の評価方法は、Ｇｒｏｗｎ－ｉｎ欠陥領域やＯＳＦリング領域の有無を同時に評価することができるものの、銅のデコレーションのために数十時間という熱処理工程が必要であり、簡便さに欠けるという問題がある。 In addition, the silicon wafer crystal defect evaluation method using the copper decoration method can simultaneously evaluate the presence or absence of a grown-in defect region or an OSF ring region, but a heat treatment process of several tens of hours for copper decoration. Is necessary, and there is a problem of lack of simplicity.
　したがって、本発明の目的は、時間とコストを抑えて簡便な方法でシリコンウェーハの結晶欠陥領域の有無及び種類を評価することが可能なシリコンウェーハの評価方法及び製造方法を提供することにある。 Therefore, an object of the present invention is to provide a silicon wafer evaluation method and manufacturing method capable of evaluating the presence and type of a crystal defect region of a silicon wafer by a simple method while saving time and cost.
　上記課題を解決するため、本発明によるシリコンウェーハの評価方法は、ＣＺ法によって育成されたシリコン単結晶インゴットから切り出したシリコンウェーハの評価方法であって、前記シリコンウェーハにサーマルドナー発生熱処理を施したときに発生するサーマルドナーの発生速度を測定し、当該サーマルドナーの発生速度に基づいて結晶欠陥領域の有無又は結晶欠陥の種類を判別することを特徴とする。 In order to solve the above problems, a silicon wafer evaluation method according to the present invention is an evaluation method of a silicon wafer cut out from a silicon single crystal ingot grown by a CZ method, and a thermal donor generation heat treatment is performed on the silicon wafer. It is characterized in that the generation rate of a thermal donor that is sometimes generated is measured, and the presence or absence of a crystal defect region or the type of crystal defect is determined based on the generation rate of the thermal donor.
　本発明によれば、Ｖ／Ｇを制御しながらＣＺ法によって育成されたシリコン単結晶インゴットから切り出されたシリコンウェーハに熱処理を施したことによる比抵抗の変化に基づくサーマルドナー発生速度を測定することによって結晶欠陥領域の有無及び結晶欠陥の種類を簡便に評価することができる。 According to the present invention, a thermal donor generation rate based on a change in specific resistance caused by heat treatment of a silicon wafer cut from a silicon single crystal ingot grown by the CZ method while controlling V / G is measured. Thus, the presence / absence of a crystal defect region and the type of crystal defect can be easily evaluated.
　本発明によるシリコンウェーハの評価方法は、前記シリコン単結晶インゴットから切り出した第１のシリコンウェーハが酸素クラスターを含む状態において前記サーマルドナー発生熱処理を施したときに前記第１のシリコンウェーハ上の第１の測定ポイントに発生するサーマルドナーの発生速度である第１のサーマルドナー発生速度を求め、前記第１のシリコンウェーハと異なる第２のシリコンウェーハにドナーキラー処理及び前記サーマルドナー発生熱処理を順に施したときに前記第２のシリコンウェーハ上の第２の測定ポイントに発生するサーマルドナーの発生速度である第２のサーマルドナー発生速度を求め、前記第２のサーマルドナー発生速度に対する第１のサーマルドナー発生速度の比であるサーマルドナー発生速度比に基づいて、前記第１のシリコンウェーハ上の前記第１の測定ポイントがＯＳＦ核を含む領域、ボイド欠陥を含む領域又は無欠陥領域のいずれに該当するかを判別することが好ましい。ここで、シリコンウェーハが酸素クラスターを含む状態とは、as-grown状態のシリコンウェーハに対してドナーキラー処理を施す前の状態のことを言う。また無欠陥領域とは、Ｇｒｏｗｎ－ｉｎ欠陥を含まず、且つ、評価熱処理後にＯＳＦリングが発生しない領域のことを言う。このように、本発明によれば、ドナーキラー処理の有無の違いを持つ２種類のウェーハからそれぞれ求めた第１及び第２のサーマルドナー発生速度に基づいて、結晶欠陥領域の有無及び結晶欠陥の種類を簡便に評価することができる。 In the silicon wafer evaluation method according to the present invention, the first silicon wafer cut out from the silicon single crystal ingot is subjected to the thermal donor generation heat treatment in a state where the first silicon wafer includes an oxygen cluster. The first thermal donor generation rate, which is the generation rate of the thermal donor generated at the measurement point, was obtained, and the donor killer process and the thermal donor generation heat treatment were sequentially performed on the second silicon wafer different from the first silicon wafer. A second thermal donor generation rate that is a generation rate of a thermal donor generated at a second measurement point on the second silicon wafer is sometimes obtained, and a first thermal donor generation relative to the second thermal donor generation rate is obtained. Based on thermal donor generation rate ratio, which is the rate ratio , It is preferable to determine whether the first measurement point on the first silicon wafer area including the OSF nucleus, corresponds to one region or a defect-free region includes a void defects. Here, the state in which the silicon wafer includes oxygen clusters refers to a state before the donor killer process is performed on the silicon wafer in the as-grown state. The defect-free region refers to a region that does not include a grown-in defect and does not generate an OSF ring after the evaluation heat treatment. As described above, according to the present invention, based on the first and second thermal donor generation rates obtained from the two types of wafers having the difference in the presence or absence of the donor killer process, the presence or absence of the crystal defect region and the crystal defect The type can be easily evaluated.
　本発明によるシリコンウェーハの評価方法は、前記サーマルドナー発生速度比が第１の速度範囲内にある場合に、前記第１のシリコンウェーハ上の前記第１の測定ポイントが無欠陥領域であると判別し、前記サーマルドナー発生速度比が前記第１の速度範囲よりも高い第２の速度範囲内にある場合に、前記第１の測定ポイントがボイド欠陥を含む領域であると判別し、前記サーマルドナー発生速度比が前記第２の速度範囲よりも高い第３の速度範囲内にある場合に、前記第１の測定ポイントがＯＳＦ核を含む領域であると判別することが好ましい。このような判別により、ＯＳＦリング領域、ボイド欠陥を含む領域、及び無欠陥領域を簡便に判定することができる。 The silicon wafer evaluation method according to the present invention determines that the first measurement point on the first silicon wafer is a defect-free region when the thermal donor generation speed ratio is within the first speed range. When the thermal donor generation speed ratio is in a second speed range higher than the first speed range, it is determined that the first measurement point is a region including a void defect, and the thermal donor When the generation speed ratio is in a third speed range higher than the second speed range, it is preferable to determine that the first measurement point is a region including an OSF nucleus. By such determination, it is possible to easily determine an OSF ring region, a region including a void defect, and a defect-free region.
　本発明において、前記サーマルドナー発生熱処理は、４３０℃以上４８０℃以下で２時間以上４時間以下の熱処理であることが好ましく、４５０℃で４時間の熱処理であることがさらに好ましい。この熱処理条件であれば、酸素クラスターを活性化させてサーマルドナー発生速度に基づく結晶欠陥領域の有無及び結晶欠陥の種類の評価を行うことが可能である。 In the present invention, the thermal donor generation heat treatment is preferably a heat treatment at 430 ° C. to 480 ° C. for 2 hours to 4 hours, and more preferably at 450 ° C. for 4 hours. Under this heat treatment condition, it is possible to activate the oxygen cluster and evaluate the presence or absence of a crystal defect region and the type of crystal defect based on the thermal donor generation rate.
　本発明によるシリコンウェーハの評価方法は、４５０℃で４時間の前記サーマルドナー発生熱処理を施したとき、前記サーマルドナー発生速度比が１．３以上１．７未満である場合に前記第１のシリコンウェーハ上の前記第１の測定ポイントが無欠陥領域であると判別し、前記サーマルドナー発生速度比が１．７以上１．９未満である場合に前記第１の測定ポイントがボイド欠陥を含む領域であると判別し、前記サーマルドナー発生速度比が１．９以上２．３未満である場合に前記第１の測定ポイントがＯＳＦ核を含む領域であると判別することが好ましい。このような判別により、ＯＳＦリング領域、ボイド欠陥を含む領域、無欠陥領域を簡便に判定することができる According to the silicon wafer evaluation method of the present invention, when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours, the first silicon is used when the thermal donor generation rate ratio is 1.3 or more and less than 1.7. When the first measurement point on the wafer is determined to be a defect-free region, and the thermal donor generation rate ratio is 1.7 or more and less than 1.9, the first measurement point includes a void defect. It is preferable to determine that the first measurement point is a region containing OSF nuclei when the thermal donor generation rate ratio is 1.9 or more and less than 2.3. By such determination, it is possible to easily determine an OSF ring region, a region including a void defect, and a defect-free region.
　本発明によるシリコンウェーハの評価方法は、前記シリコンウェーハの径方向に沿って設けた複数の測定ポイントの各々において前記サーマルドナーの発生速度を測定することにより、前記シリコンウェーハの径方向の結晶欠陥マップを作成することが好ましい。 According to the silicon wafer evaluation method of the present invention, the crystal defect map in the radial direction of the silicon wafer is measured by measuring the generation rate of the thermal donor at each of a plurality of measurement points provided along the radial direction of the silicon wafer. It is preferable to create
　本発明によるシリコンウェーハの評価方法は、前記シリコンウェーハの比抵抗を測定し、前記比抵抗をもとにキャリア濃度をアービンカーブから求め、前記サーマルドナー発生熱処理前後のキャリア濃度をもとにサーマルドナー発生量を求め、前記サーマルドナー発生熱処理の時間と前記サーマルドナー発生量との関係から前記サーマルドナー発生速度を求めることが好ましい。この場合、前記シリコンウェーハの比抵抗を４探針法により測定することが好ましい。 According to the silicon wafer evaluation method of the present invention, the specific resistance of the silicon wafer is measured, the carrier concentration is obtained from an Irbin curve based on the specific resistance, and the thermal donor is calculated based on the carrier concentration before and after the thermal donor generation heat treatment. It is preferable to determine the generation amount and determine the thermal donor generation rate from the relationship between the thermal donor generation heat treatment time and the thermal donor generation amount. In this case, it is preferable to measure the specific resistance of the silicon wafer by a four-probe method.
　また、本発明によるシリコンウェーハの製造方法は、第１のシリコン単結晶インゴットをチョクラルスキー法によって育成し、前記第１のシリコン単結晶インゴットから切り出した評価用シリコンウェーハにサーマルドナー発生熱処理を施したときに発生するサーマルドナーの発生速度を測定し、当該サーマルドナーの発生速度の測定結果に基づいて前記評価用シリコンウェーハ中の結晶欠陥領域の有無又は結晶欠陥の種類を判別し、前記第１のシリコン単結晶インゴットの育成条件及び前記評価用シリコンウェーハ中の結晶欠陥領域の有無又は結晶欠陥の種類の判別結果に基づいて、第２のシリコン単結晶インゴットの育成条件を調整し、前記第２のシリコン単結晶インゴットから製品用シリコンウェーハを切り出すことを特徴とする。 The silicon wafer manufacturing method according to the present invention includes a first silicon single crystal ingot grown by the Czochralski method and subjected to thermal donor generation heat treatment on the silicon wafer for evaluation cut out from the first silicon single crystal ingot. And measuring the generation rate of the thermal donor generated at the time, and determining the presence or absence of the crystal defect region or the type of crystal defect in the silicon wafer for evaluation based on the measurement result of the generation rate of the thermal donor. The second silicon single crystal ingot growth condition is adjusted based on the growth condition of the silicon single crystal ingot and the determination result of the presence or absence of the crystal defect region in the silicon wafer for evaluation or the type of the crystal defect. A silicon wafer for production is cut out from a silicon single crystal ingot.
　本発明によるシリコンウェーハの製造方法は、前記第２のシリコン単結晶インゴットの育成条件を調整することによって、無欠陥領域を有する前記第２のシリコン単結晶インゴットを育成してもよく、ボイド欠陥を含む領域を有する前記第２のシリコン単結晶インゴットを育成してもよく、ＯＳＦ核を含む領域を有する前記第２のシリコン単結晶インゴットを育成してもよい。また本発明においては、前記第２のシリコン単結晶インゴットの育成条件として、前記第２のシリコン単結晶インゴットの引き上げ速度を調整することが好ましい。このように、サーマルドナー発生速度に基づく評価結果を用いて、様々なタイプのシリコンウェーハを作り分けることができる。 In the method for manufacturing a silicon wafer according to the present invention, the second silicon single crystal ingot having a defect-free region may be grown by adjusting a growth condition of the second silicon single crystal ingot. The second silicon single crystal ingot having a region including it may be grown, or the second silicon single crystal ingot having a region including an OSF nucleus may be grown. In the present invention, it is preferable to adjust a pulling rate of the second silicon single crystal ingot as a growth condition for the second silicon single crystal ingot. In this way, various types of silicon wafers can be made using the evaluation results based on the thermal donor generation rate.
　本発明においては、前記製品用シリコンウェーハにドナーキラー処理を施すことが好ましい。これによれば、サーマルドナーの影響がないシリコンウェーハ製品を提供することができる。 In the present invention, the product silicon wafer is preferably subjected to donor killer treatment. According to this, it is possible to provide a silicon wafer product that is not affected by the thermal donor.
　本発明によれば、時間とコストを抑えて簡便な方法でシリコンウェーハの結晶欠陥領域の有無及び結晶欠陥の種類を評価することが可能なシリコンウェーハの評価方法及び製造方法を提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, the evaluation method and manufacturing method of a silicon wafer which can evaluate the presence or absence of the crystal defect area | region of a silicon wafer and the kind of crystal defect by a simple method restraining time and cost can be provided. .
図１は、本発明の実施の形態によるシリコンウェーハの製造方法を説明するためのフローチャートである。FIG. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention. 図２は、Ｖ／Ｇと結晶欠陥の種類及び分布との一般的な関係を示す図である。FIG. 2 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects. 図３は、サーマルドナー発生速度測定工程を示すフローチャートである。FIG. 3 is a flowchart showing a thermal donor generation rate measurement step. 図４は、ウェーハ中の結晶欠陥領域の有無及び結晶欠陥の種類の判別工程を示すフローチャートである。FIG. 4 is a flowchart showing a process of discriminating the presence / absence of a crystal defect region in the wafer and the type of crystal defect. 図５は、上記ウェーハサンプルＡ１～Ａ３、Ｂ１～Ｂ３のサーマルドナー発生速度とサーマルドナー発生熱処理時間との関係を示すグラフである。FIG. 5 is a graph showing the relationship between the thermal donor generation rate and the thermal donor generation heat treatment time of the wafer samples A1 to A3 and B1 to B3. 図６は、４５０℃で４時間のサーマルドナー発生熱処理を施したときの、ＯＳＦリング発生領域、ボイド欠陥を含む領域、無欠陥領域での、サーマルドナー発生速度と酸素濃度の関係を求めた結果を示すグラフである。FIG. 6 shows the result of determining the relationship between the thermal donor generation rate and the oxygen concentration in the OSF ring generation region, the region including void defects, and the defect-free region when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours. It is a graph which shows. 図７は、図６において、ドナーキラー処理なしのウェーハの各測定ポイントでのサーマルドナー発生速度をドナーキラー処理ありのウェーハの同一測定ポイントでのサーマルドナー発生速度で規格化したグラフである。FIG. 7 is a graph in which the thermal donor generation rate at each measurement point of the wafer without donor killer treatment in FIG. 6 is normalized by the thermal donor generation rate at the same measurement point of the wafer with donor killer treatment.
　以下、添付図面を参照しながら、本発明の好ましい実施の形態について詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
　図１は、本発明の実施の形態によるシリコンウェーハの製造方法を説明するためのフローチャートである。 FIG. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention.
　図１に示すように、本実施形態によるシリコン単結晶の製造方法は、シリコン単結晶インゴットをＣＺ法により育成する結晶育成工程（Ｓ１１）と、シリコン単結晶インゴットからシリコンウェーハを切り出すスライス工程（Ｓ１２）と、シリコンウェーハの結晶欠陥領域の評価が必要な場合に行われるサーマルドナー発生速度測定工程（Ｓ１３Ｙ，Ｓ１４）と、サーマルドナーの発生速度の測定結果から結晶欠陥領域の有無及び結晶欠陥の種類を判別する判別工程（Ｓ１５）と、結晶欠陥領域の有無及び結晶欠陥の種類の判別結果に基づいて後続のシリコン単結晶インゴットの育成条件を調整する調整工程（Ｓ１６Ｙ，Ｓ１７）とを有している。 As shown in FIG. 1, the silicon single crystal manufacturing method according to the present embodiment includes a crystal growth step (S11) for growing a silicon single crystal ingot by the CZ method, and a slicing step (S12) for cutting a silicon wafer from the silicon single crystal ingot. ), Thermal donor generation rate measurement step (S13Y, S14) performed when the evaluation of the crystal defect region of the silicon wafer is necessary, and the presence / absence of the crystal defect region and the type of crystal defect from the measurement result of the thermal donor generation rate A discriminating step (S15), and an adjusting step (S16Y, S17) for adjusting the growth conditions of the subsequent silicon single crystal ingot based on the discriminating result of the presence / absence of a crystal defect region and the type of crystal defect. Yes.
　また本実施形態によるシリコン単結晶の製造方法は、シリコンウェーハの評価が不要な場合に行われるドナーキラー処理工程（Ｓ１８）と、ドナーキラー処理後のシリコンウェーハに対して行われる鏡面研磨等の製品加工工程（Ｓ１９）とを有している。 In addition, the silicon single crystal manufacturing method according to the present embodiment includes a donor killer processing step (S18) performed when evaluation of a silicon wafer is unnecessary, and a product such as mirror polishing performed on the silicon wafer after the donor killer processing. And a processing step (S19).
　ＣＺ法により育成されるシリコン単結晶に含まれる結晶欠陥の種類や分布は、シリコン単結晶の引き上げ速度Ｖと引き上げ軸方向の結晶内温度勾配Ｇとの比Ｖ／Ｇに依存する。そのため、シリコン単結晶中の結晶品質を制御するためにはＶ／Ｇを精密に制御する必要がある。しかし、ある条件下で育成されたシリコン単結晶インゴット（第１のシリコン単結晶インゴット）が所望の結晶品質を有するかどうかは、実際に結晶品質を評価してみなければ分からない。 The kind and distribution of crystal defects contained in a silicon single crystal grown by the CZ method depend on the ratio V / G between the pulling speed V of the silicon single crystal and the temperature gradient G in the crystal in the pulling axis direction. Therefore, in order to control the crystal quality in the silicon single crystal, it is necessary to precisely control V / G. However, whether or not a silicon single crystal ingot (first silicon single crystal ingot) grown under a certain condition has a desired crystal quality cannot be known without actually evaluating the crystal quality.
　そこで本実施形態ではシリコン単結晶インゴットから切り出したウェーハ中の結晶欠陥領域の有無及び結晶欠陥の種類を評価する。結晶欠陥領域の有無及び結晶欠陥の種類を評価した結果、所望の結晶品質を満たさない場合には、この評価結果が後続のシリコン単結晶インゴット（第２のシリコン単結晶インゴット）の育成工程にフィードバックされ、所望の結晶品質となるように結晶引き上げ速度Ｖ等の結晶育成条件が調整される。 Therefore, in this embodiment, the presence / absence of a crystal defect region in the wafer cut out from the silicon single crystal ingot and the type of crystal defect are evaluated. As a result of evaluating the presence / absence of a crystal defect region and the type of crystal defect, if the desired crystal quality is not satisfied, this evaluation result is fed back to the subsequent silicon single crystal ingot (second silicon single crystal ingot) growing process. The crystal growth conditions such as the crystal pulling speed V are adjusted so that the desired crystal quality is obtained.
　図２は、Ｖ／Ｇと結晶欠陥の種類及び分布との一般的な関係を示す図である。 FIG. 2 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects.
　図２に示すように、Ｖ／Ｇが大きい場合には空孔が過剰となり、空孔の凝集体であるボイド欠陥が発生する。ボイド欠陥は一般的にＣＯＰ（Crystal Originated Particle）と称される結晶欠陥である。一方、Ｖ／Ｇが小さい場合には格子間シリコン原子が過剰となり、格子間シリコンの凝集体である転位クラスターが発生する。したがって、ＣＯＰも転位クラスターも含まない単結晶を製造するためには、単結晶の径方向及び長さ方向（結晶成長方向）の両方に対してＶ／Ｇを制御しなければならない。 As shown in FIG. 2, when V / G is large, vacancies become excessive and void defects that are aggregates of vacancies are generated. A void defect is a crystal defect generally referred to as COP (Crystal Originated Particle). On the other hand, when V / G is small, the number of interstitial silicon atoms becomes excessive, and dislocation clusters that are aggregates of interstitial silicon are generated. Therefore, in order to produce a single crystal containing neither COP nor dislocation clusters, V / G must be controlled in both the radial direction and the length direction (crystal growth direction) of the single crystal.
　結晶引き上げ速度Ｖは単結晶の径方向のどの位置でも一定であるため、径方向の結晶内温度勾配Ｇを所定の範囲内に収めるためには、チャンバー内に適切な高温領域（ホットゾーン）を構築する必要がある。径方向の結晶内温度勾配Ｇは、シリコン融液の上方に設けられた熱遮蔽体によって制御され、これにより固液界面付近に適切なホットゾーンを構築することができる。一方、長さ方向の結晶内温度勾配Ｇはホットゾーン構造のみならず結晶引き上げ速度Ｖに依存するので、単結晶引き上げ速度Ｖを調整する必要がある。現在では、結晶引き上げ速度Ｖを厳密に制御することによって、ＣＯＰや転位クラスターを含まない直径３００ｍｍのシリコン単結晶が量産されている。 Since the crystal pulling speed V is constant at any position in the radial direction of the single crystal, an appropriate high temperature region (hot zone) is set in the chamber in order to keep the temperature gradient G in the radial direction within a predetermined range. Need to build. The intra-crystal temperature gradient G in the radial direction is controlled by a heat shield provided above the silicon melt, whereby an appropriate hot zone can be constructed near the solid-liquid interface. On the other hand, since the temperature gradient G in the crystal in the length direction depends not only on the hot zone structure but also on the crystal pulling speed V, it is necessary to adjust the single crystal pulling speed V. At present, by strictly controlling the crystal pulling speed V, silicon single crystals having a diameter of 300 mm that do not contain COPs or dislocation clusters are mass-produced.
　しかしながら、Ｖ／Ｇを制御して引き上げられたＣＯＰ及び転位クラスターを含まないシリコンウェーハはその全面が決して均質ではなく、熱処理された場合の挙動が異なる複数の領域を含んでいる。例えば、ＣＯＰが発生する領域と転位クラスターが発生する領域との間には、Ｖ／Ｇが大きいほうから順に、ＯＳＦ領域、Ｐｖ領域、Ｐｉ領域の三つの領域が存在する。 However, a silicon wafer that does not contain COP and dislocation clusters pulled up by controlling V / G is never homogeneous, and includes a plurality of regions that behave differently when heat-treated. For example, there are three regions, an OSF region, a Pv region, and a Pi region, in descending order of V / G between a region where COP occurs and a region where dislocation clusters occur.
　ＯＳＦ領域とは、as-grown状態（単結晶成長後に何の熱処理も行っていない状態）で板状酸素析出物（ＯＳＦ核）を含んでおり、１０００～１２００℃の高温で熱酸化処理した場合にＯＳＦが発生する領域である。Ｐｖ領域とは、as-grown状態で酸素析出核を含んでおり、低温及び高温（例えば８００℃と１０００℃）の２段階の熱処理を施した場合に酸素析出物が発生しやすい領域である。Ｐｉ領域とは、as-grown状態で酸素析出核をほとんど含んでおらず、熱処理を施しても酸素析出物が発生しにくい領域である。 The OSF region contains plate-like oxygen precipitates (OSF nuclei) in the as-grown state (the state in which no heat treatment is performed after single crystal growth), and is thermally oxidized at a high temperature of 1000 to 1200 ° C. This is a region where OSF occurs. The Pv region includes oxygen precipitation nuclei in an as-grown state, and is a region where oxygen precipitates are easily generated when two-stage heat treatment is performed at a low temperature and a high temperature (for example, 800 ° C. and 1000 ° C.). The Pi region is a region that hardly contains oxygen precipitation nuclei in an as-grown state and hardly generates oxygen precipitates even after heat treatment.
　上記のように、Ｖ／Ｇの制御は、主に引き上げ速度Ｖを調整することにより行われる。例えば、無欠陥領域を主に含むウェーハを望んでいるにもかかわらず、ボイド欠陥を含む領域やＯＳＦリング領域を多く含むウェーハが製造された場合には、Ｖ／Ｇが大きすぎると判断し、結晶引き上げ速度Ｖを小さくする。逆にＯＳＦリング領域を主に含むウェーハを望んでいるにもかかわらず無欠陥領域を多く含むウェーハが製造された場合には、Ｖ／Ｇが小さすぎると判断し、結晶引き上げ速度Ｖを大きくする。このような引き上げ速度Ｖの調整により、所望の結晶品質を有するシリコン単結晶インゴットを製造することができる。 As described above, the control of V / G is performed mainly by adjusting the pulling speed V. For example, in the case where a wafer including mainly a defect-free region is desired but a wafer including a void defect or a lot of OSF ring regions is manufactured, it is determined that V / G is too large. Decrease the crystal pulling speed V. On the other hand, when a wafer containing many defect-free regions is manufactured despite the desire for a wafer mainly containing the OSF ring region, it is determined that V / G is too small and the crystal pulling speed V is increased. . By adjusting the pulling speed V in this manner, a silicon single crystal ingot having a desired crystal quality can be manufactured.
　シリコン単結晶インゴットが所望の結晶品質を満たすかどうかを判断するため、本実施形態においては、当該インゴットから切り出したシリコンウェーハ中のサーマルドナーの時間変化を測定する。 In order to determine whether or not the silicon single crystal ingot satisfies the desired crystal quality, in this embodiment, the time change of the thermal donor in the silicon wafer cut out from the ingot is measured.
　ＣＺ法において、シリコン単結晶は、石英ルツボに充填した多結晶シリコン原料を溶解し、その融液から育成されるため、石英ルツボから溶け出した酸素を通常１０×１０１７ａｔｏｍｓ／ｃｍ３（ＡＳＴＭ　Ｆ－１２１，１９７９）程度含有している。この酸素は、ウェーハに結晶欠陥を生じさせ、デバイスの特性不良の原因となるが、一方ではデバイスの製造過程においてウェーハの強度を高めて変形を抑止したり、デバイスの動作不良の原因となる重金属をトラップするゲッタリング作用を有する酸素析出物をウェーハ内部に形成させるなど、複雑に作用する。 In the CZ method, since the silicon single crystal dissolves the polycrystalline silicon raw material filled in the quartz crucible and is grown from the melt, oxygen dissolved from the quartz crucible is usually 10 × 10 17 atoms / cm 3 (ASTM F-121, 1979). This oxygen causes crystal defects in the wafer and causes device characteristic defects. On the other hand, in the device manufacturing process, the wafer strength is increased to suppress deformation and heavy metals that cause device malfunction. It acts in a complicated manner, for example, by forming an oxygen precipitate having a gettering action for trapping the inside of the wafer.
　通常、シリコン中の酸素原子は電気的に中性であり、その電気抵抗に影響を及ぼさない。しかしながら、ＣＺ法で製造したシリコン単結晶は石英ルツボを用いて育成されるため、結晶中に過飽和な酸素を含有し、４５０℃前後の低温で熱処理すると数個の酸素原子が集まって酸素クラスターを形成し、電子を放出するドナーとなることが知られている。 Normally, oxygen atoms in silicon are electrically neutral and do not affect their electrical resistance. However, since a silicon single crystal produced by the CZ method is grown using a quartz crucible, it contains supersaturated oxygen in the crystal. When heat-treated at a low temperature of around 450 ° C., several oxygen atoms gather to form an oxygen cluster. It is known to form and become a donor that emits electrons.
　４５０℃前後の熱処理によって形成されるサーマルドナーは点欠陥の影響を受け、空孔優勢領域（ＣＯＰ領域、ＯＳＦリング領域）と無欠陥領域の点欠陥濃度の違いによってサーマルドナー発生速度が異なる。そこで本実施形態では、シリコンウェーハ中に発生するサーマルドナーの発生速度に基づいて、シリコンウェーハ中の結晶欠陥領域の有無及び結晶欠陥の種類を判別するものである。 The thermal donor formed by heat treatment at around 450 ° C. is affected by point defects, and the thermal donor generation rate differs depending on the difference in point defect concentration between the vacancy dominant region (COP region and OSF ring region) and the defect-free region. Therefore, in this embodiment, the presence / absence of a crystal defect region in the silicon wafer and the type of crystal defect are determined based on the generation rate of thermal donors generated in the silicon wafer.
　サーマルドナー発生速度測定工程（Ｓ１４）では、スライス工程（Ｓ１２）によりインゴットから連続して切り出された２枚の評価用シリコンウェーハを用意する。２枚の評価用ウェーハは、インゴットからワイヤソーによって切り出され、粗研磨が施されたウェーハであることが好ましい。そして、一方のウェーハ（第１のウェーハ）にはドナーキラー処理を予め施すことなくサーマルドナー発生熱処理工程を行い、また他方のウェーハ（第２のウェーハ）にはドナーキラー処理を予め施した後にサーマルドナー発生熱処理を行い、これら第１及び第２のウェーハの各々のサーマルドナー発生熱処理前後での比抵抗の変化からサーマルドナー発生速度が求められる。 In the thermal donor generation rate measuring step (S14), two silicon wafers for evaluation that are continuously cut out from the ingot by the slicing step (S12) are prepared. The two evaluation wafers are preferably wafers cut out from the ingot by a wire saw and subjected to rough polishing. Then, one of the wafers (first wafer) is subjected to a thermal donor generation heat treatment step without performing donor killer treatment in advance, and the other wafer (second wafer) is subjected to donor killer treatment in advance and then subjected to thermal treatment. A donor generation heat treatment is performed, and a thermal donor generation speed is obtained from a change in specific resistance before and after the thermal donor generation heat treatment of each of the first and second wafers.
　図３は、サーマルドナー発生速度測定工程を示すフローチャートである。 FIG. 3 is a flowchart showing a thermal donor generation rate measurement step.
　図３に示すように、サーマルドナー発生速度測定工程（Ｓ１４）は、as-grown状態の第１及び第２のウェーハを用意する準備工程（Ｓ２０）、第１のウェーハの比抵抗を測定する比抵抗測定工程（Ｓ２１）と、比抵抗測定後の第１のウェーハにサーマルドナー発生熱処理を行うサーマルドナー発生熱処理工程（Ｓ２２）と、サーマルドナー発生熱処理後の第１のウェーハの比抵抗を測定する比抵抗測定工程（Ｓ２３）と、サーマルドナー発生熱処理前後の２つの比抵抗測定値から第１のサーマルドナー発生速度を算出する工程（Ｓ２４）とを有している。 As shown in FIG. 3, the thermal donor generation rate measurement step (S14) includes a preparation step (S20) for preparing the first and second wafers in the as-grown state, and a ratio for measuring the specific resistance of the first wafer. A resistance measurement step (S21), a thermal donor generation heat treatment step (S22) for performing thermal donor generation heat treatment on the first wafer after the specific resistance measurement, and a specific resistance of the first wafer after the thermal donor generation heat treatment are measured. A specific resistance measurement step (S23) and a step (S24) of calculating a first thermal donor generation rate from two specific resistance measurement values before and after thermal donor generation heat treatment.
　またサーマルドナー発生速度測定工程（Ｓ１４）は、第２のウェーハにドナーキラー処理を行う工程（Ｓ２５）と、ドナーキラー処理後の第２のウェーハの比抵抗を測定する抵抗測定工程（Ｓ２６）と、比抵抗測定後の第２のウェーハに第１のウェーハと同様のサーマルドナー発生熱処理を行うサーマルドナー発生熱処理工程（Ｓ２７）と、サーマルドナー発生熱処理後の第２のウェーハの比抵抗を測定する比抵抗測定工程（Ｓ２８）と、サーマルドナー発生熱処理前後の２つの比抵抗測定値から第２のサーマルドナー発生速度を算出する工程（Ｓ２９）とを有している。 The thermal donor generation rate measuring step (S14) includes a step of performing donor killer processing on the second wafer (S25), a resistance measuring step of measuring the specific resistance of the second wafer after donor killer processing (S26), and A thermal donor generation heat treatment step (S27) for performing the same thermal donor generation heat treatment as that of the first wafer on the second wafer after the specific resistance measurement, and a specific resistance of the second wafer after the thermal donor generation heat treatment are measured. A specific resistance measurement step (S28) and a step (S29) of calculating a second thermal donor generation rate from two specific resistance measurement values before and after thermal donor generation heat treatment.
　サーマルドナー発生熱処理の温度は４３０～４８０℃であることが好ましく、４５０℃であることが特に好ましい。またサーマルドナー発生熱処理の時間は１～４時間であることが好ましく、２～４時間であることがさらに好ましい。ドナーキラー処理は、例えば６００～７００℃の不活性ガス雰囲気中で行う短時間の熱処理であり、熱処理時間は例えば１５分程度である。 The temperature of the thermal donor-generated heat treatment is preferably 430 to 480 ° C, particularly preferably 450 ° C. The heat treatment time for generating the thermal donor is preferably 1 to 4 hours, more preferably 2 to 4 hours. The donor killer treatment is a short-time heat treatment performed in an inert gas atmosphere at 600 to 700 ° C., for example, and the heat treatment time is about 15 minutes, for example.
　シリコンウェーハ面内の比抵抗は、いわゆる４探針法によって測定することができる。測定した比抵抗をもとにキャリア濃度をアービンカーブから求め、サーマルドナー発生熱処理前後のキャリア濃度をもとにサーマルドナー発生量を求め、サーマルドナー発生熱処理の時間とサーマルドナー発生量との関係からサーマルドナー発生速度を求めることができる。 The specific resistance in the silicon wafer surface can be measured by a so-called four-probe method. Based on the measured specific resistance, the carrier concentration is determined from the Irvine curve, the amount of thermal donor generation is determined based on the carrier concentration before and after the thermal donor generation heat treatment, and from the relationship between the thermal donor generation heat treatment time and the amount of thermal donor generation The thermal donor generation rate can be determined.
　本実施形態においては、シリコンウェーハの径方向に沿って複数の測定ポイントを設定し、各測定ポイントにおいて抵抗測定を行い、測定結果からサーマルドナーの発生速度を算出することが好ましい。こうして測定ポイントごとに結晶欠陥領域の有無及び結晶欠陥の種類を評価することにより、シリコンウェーハの径方向の欠陥マップを作成することができる。 In the present embodiment, it is preferable to set a plurality of measurement points along the radial direction of the silicon wafer, perform resistance measurement at each measurement point, and calculate the generation rate of the thermal donor from the measurement result. Thus, by evaluating the presence / absence of a crystal defect region and the type of crystal defect for each measurement point, a defect map in the radial direction of the silicon wafer can be created.
　図４は、ウェーハ中の結晶欠陥領域の有無及び結晶欠陥の種類の判別工程を示すフローチャートである。 FIG. 4 is a flowchart showing a process for discriminating the presence / absence of a crystal defect region in the wafer and the type of crystal defect.
　図４に示すように、結晶欠陥領域の有無及び結晶欠陥の種類の判別工程（Ｓ１５）では、第２のサーマルドナー発生速度に対する第１のサーマルドナー発生速度の比を算出し（Ｓ３０）、この値が１．３以上１．７未満である場合には無欠陥領域であると判別し（Ｓ３１Ｙ，Ｓ３４）、１．７以上１．９未満である場合にはボイド欠陥を含む領域であると判別し（Ｓ３１Ｎ，Ｓ３２Ｙ，Ｓ３５）、１．９以上２．３未満であるにはＯＳＦ核を含む領域であると判別する（Ｓ３１Ｎ，Ｓ３２Ｎ，Ｓ３３Ｙ，Ｓ３６）。さらにいずれの数値範囲にも該当しない場合には判別不可（Ｓ３１Ｎ，Ｓ３２Ｎ，Ｓ３３Ｎ，Ｓ３７）と判別する。 As shown in FIG. 4, in the step of determining the presence / absence of a crystal defect region and the type of crystal defect (S15), the ratio of the first thermal donor generation rate to the second thermal donor generation rate is calculated (S30). When the value is 1.3 or more and less than 1.7, it is determined that the region is a defect-free region (S31Y, S34). When the value is 1.7 or more and less than 1.9, it is a region including a void defect. It discriminate | determines (S31N, S32Y, S35), and if it is 1.9 or more and less than 2.3, it will discriminate | determine that it is an area | region containing an OSF nucleus (S31N, S32N, S33Y, S36). Furthermore, when it does not correspond to any numerical range, it is determined that the determination is impossible (S31N, S32N, S33N, S37).
　以上説明したように、本実施形態によるシリコンウェーハの評価方法は、ＣＺ法によって育成されたシリコン単結晶インゴットからシリコンウェーハを切り出し、シリコンウェーハにサーマルドナー発生熱処理を施したときに発生するサーマルドナーの発生速度を測定し、当該サーマルドナーの発生速度に基づいて結晶欠陥領域の有無又は結晶欠陥の種類を判別するので、ＯＳＦ核を含む領域、ボイド欠陥を含む領域、又は無欠陥領域を短時間で簡便に判別することができる。また、従来の評価方法のように例えば銅のデコレーションを施す必要もなく、比較的短時間の低温熱処理で評価が可能であり、時間とコストを抑えて簡便な方法でシリコンウェーハの結晶欠陥領域の有無及び結晶欠陥の種類を評価することができる。 As described above, the silicon wafer evaluation method according to the present embodiment cuts out a silicon wafer from a silicon single crystal ingot grown by the CZ method and performs thermal donor generation heat treatment on the silicon wafer. Since the generation rate is measured and the presence or absence of the crystal defect region or the type of crystal defect is determined based on the generation rate of the thermal donor, the region including the OSF nucleus, the region including the void defect, or the non-defect region can be quickly determined. It can be easily determined. In addition, unlike the conventional evaluation method, for example, it is not necessary to decorate copper, and evaluation can be performed with a relatively short time of low-temperature heat treatment. Existence and types of crystal defects can be evaluated.
　また、本実施形態によるシリコンウェーハの製造方法は、先行のシリコン単結晶インゴットから切り出した評価用シリコンウェーハのサーマルドナー発生速度を測定し、当該サーマルドナー発生速度の測定結果に基づいて評価用シリコンウェーハ中の結晶欠陥領域の有無又は結晶欠陥の種類を判別し、この判別結果に基づいて後続のシリコン単結晶インゴットの育成条件を調整するので、結晶育成条件を簡便に最適化することができる。 Further, the silicon wafer manufacturing method according to the present embodiment measures the thermal donor generation rate of the evaluation silicon wafer cut out from the preceding silicon single crystal ingot, and based on the measurement result of the thermal donor generation rate, the evaluation silicon wafer Since the presence / absence of the crystal defect region or the type of the crystal defect is discriminated, and the growth condition of the subsequent silicon single crystal ingot is adjusted based on the discrimination result, the crystal growth condition can be easily optimized.
　以上、本発明の好ましい実施形態について説明したが、本発明は、上記の実施形態に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。 The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.
　例えば、上記実施形態においては、サーマルドナー発生速度測定工程（Ｓ１４）においてシリコン単結晶インゴットから切り出した第１及び第２のシリコンウェーハを用意し、第２のウェーハに対してドナーキラー処理（Ｓ２５）の後にサーマルドナー発生熱処理（Ｓ２７）を行って第２のサーマルドナー発生速度を算出しているが、本発明ではそのような第２のサーマルドナー発生速度の算出工程を省略することも可能である。すなわち、第２のシリコンウェーハと同等の他のシリコンウェーハにドナーキラー処理及びサーマルドナー発生熱処理を行って第２のサーマルドナー発生速度を予め算出したものをデータベース化しておき、第２のサーマルドナー発生速度についてはデータベースから読み出したものを用い、第１のサーマルドナー発生速度のみを測定して、結晶欠陥領域の有無及び結晶欠陥の種類を評価するようにしてもよい。 For example, in the above embodiment, the first and second silicon wafers cut from the silicon single crystal ingot in the thermal donor generation rate measuring step (S14) are prepared, and the donor killer process (S25) is performed on the second wafer. After that, the thermal donor generation heat treatment (S27) is performed to calculate the second thermal donor generation rate. However, in the present invention, such a step of calculating the second thermal donor generation rate can be omitted. . In other words, the other silicon wafer equivalent to the second silicon wafer is subjected to donor killer treatment and thermal donor generation heat treatment, and the second thermal donor generation rate calculated in advance is made into a database to generate the second thermal donor generation. The speed read from the database may be used, and only the first thermal donor generation speed may be measured to evaluate the presence / absence of a crystal defect region and the type of crystal defect.
　結晶欠陥の種類がサーマルドナー発生速度に与える影響を評価した。この評価試験では、直径３００ｍｍ、面方位（１００）のＰ型シリコン単結晶インゴットをＣＺ法により育成した。その際、ＯＳＦリング発生領域が含まれるようにＶ／Ｇを制御しながらシリコン単結晶インゴットを育成した。このシリコン単結晶インゴットの酸素濃度は５×１０１７～２０×１０１７ａｔｏｍｓ／ｃｍ３（ＡＳＴＭ　Ｆ－１２１，１９７９）であった。このシリコン単結晶インゴットをスライスすることで、ＯＳＦリング発生領域を含む２枚のシリコンウェーハのサンプルＡ１，Ｂ１を得た。ここで、ＯＳＦリング発生領域とは、評価熱処理後にＯＳＦリングが発生する領域のことを言い、as-grown状態でＯＳＦ核を含む領域のことを言う。 The effect of the type of crystal defects on the thermal donor generation rate was evaluated. In this evaluation test, a P-type silicon single crystal ingot having a diameter of 300 mm and a plane orientation (100) was grown by the CZ method. At that time, a silicon single crystal ingot was grown while controlling V / G so as to include the OSF ring generation region. The oxygen concentration of this silicon single crystal ingot was 5 × 10 17 to 20 × 10 17 atoms / cm 3 (ASTM F-121, 1979). By slicing the silicon single crystal ingot, samples A1 and B1 of two silicon wafers including the OSF ring generation region were obtained. Here, the OSF ring generation region refers to a region where an OSF ring is generated after the evaluation heat treatment, and refers to a region including OSF nuclei in an as-grown state.
　ボイド欠陥が存在する領域が含まれるようにＶ／Ｇを制御した点以外はサンプルＡ１，Ｂ１と同じ条件下でシリコン単結晶インゴットを育成し、このシリコン単結晶インゴットをスライスすることで、ボイド欠陥が存在する領域を含む２枚のシリコンウェーハのサンプルＡ２，Ｂ２を得た。 A silicon single crystal ingot is grown under the same conditions as Samples A1 and B1 except that the V / G is controlled so that a void defect area is included, and the silicon single crystal ingot is sliced to obtain a void defect. Samples A2 and B2 of two silicon wafers including the region where the sapphire exists were obtained.
　無欠陥領域となるようにＶ／Ｇを制御した点以外はサンプルＡ１，Ｂ１と同じ条件下でシリコン単結晶インゴットを作製し、このシリコン単結晶インゴットをスライスすることで、無欠陥領域からなる２枚のシリコンウェーハのサンプルＡ３，Ｂ３を得た。 A silicon single crystal ingot is produced under the same conditions as those of the samples A1 and B1 except that V / G is controlled so as to be a defect-free region, and this silicon single crystal ingot is sliced to form 2 Two silicon wafer samples A3 and B3 were obtained.
　その後、シリコンウェーハのサンプルＢ１，Ｂ２，Ｂ３の結晶育成中に発生したサーマルドナーを消去するため、７００℃の窒素雰囲気で１５分のドナーキラー処理を行った。 Thereafter, in order to erase the thermal donor generated during crystal growth of the silicon wafer samples B1, B2, and B3, a donor killer treatment was performed in a nitrogen atmosphere at 700 ° C. for 15 minutes.
　ドナーキラー処理なしのプロセスによりそれぞれ準備したシリコンウェーハのサンプルＡ１～Ａ３（実施例１～３）並びにドナーキラー処理ありのプロセスによりそれぞれ準備したシリコンウェーハのサンプルＢ１～Ｂ３（比較例１～３）に４５０℃の窒素雰囲気でサーマルドナー発生熱処理を行い、サーマルドナーを発生させた。 Samples A1 to A3 of silicon wafers prepared by processes without donor killer treatment (Examples 1 to 3) and samples B1 to B3 of silicon wafers prepared by processes with donor killer treatment (Comparative Examples 1 to 3), respectively. Thermal donor generation heat treatment was performed in a nitrogen atmosphere at 450 ° C. to generate a thermal donor.
　ＪＩＳ Ｈ ０６０２：１９９５に規定された４探針法による比抵抗率測定方法に従い、各シリコンウェーハのサンプルＡ１～Ａ３，Ｂ１～Ｂ３の比抵抗を測定し、この比抵抗をもとにキャリア濃度をアービンカーブから求めた。さらに、サーマルドナー発生熱処理前後のキャリア濃度をもとに、サーマルドナー発生量を求め、さらに熱処理時間とサーマルドナー発生量の関係からサーマルドナー発生速度を求めた。 Measure the specific resistance of each of the silicon wafer samples A1 to A3 and B1 to B3 in accordance with the specific resistance measurement method based on the four-probe method specified in JIS H２0602: 1995, and determine the carrier concentration based on this specific resistance. Obtained from Irvine curve. Furthermore, the thermal donor generation amount was determined based on the carrier concentration before and after the thermal donor generation heat treatment, and the thermal donor generation rate was determined from the relationship between the heat treatment time and the thermal donor generation amount.
　図５は、上記ウェーハサンプルＡ１～Ａ３、Ｂ１～Ｂ３のサーマルドナー発生速度とサーマルドナー発生熱処理時間との関係を示すグラフであり、横軸は熱処理時間（ｈ）、縦軸はサーマルドナー発生速度（ｃｍ－３／ｈ）をそれぞれ示している。また特に、このグラフは酸素濃度が１１×１０１７ａｔｏｍｓ／ｃｍ３の条件を満たすウェーハのみでまとめたものである。 FIG. 5 is a graph showing the relationship between the thermal donor generation rate of the wafer samples A1 to A3 and B1 to B3 and the thermal donor generation heat treatment time. The horizontal axis represents the heat treatment time (h), and the vertical axis represents the thermal donor generation rate. (Cm −3 / h) is shown respectively. In particular, this graph is summarized only for wafers that satisfy the condition of oxygen concentration of 11 × 10 17 atoms / cm 3 .
　図５に示すように、熱処理時間が４時間以内では、ＯＳＦリング発生領域、ボイド欠陥を含む領域、及び無欠陥領域いずれも、ドナーキラー処理あり（サンプルＢ１，Ｂ２，Ｂ３）よりもドナーキラー処理なし（サンプルＡ１，Ａ２，Ａ３）のほうがサーマルドナー発生速度は大きかった。また、ドナーキラー処理ありではいずれの領域でもサーマルドナー発生速度は同じであったが、ドナーキラー処理なしでは、ＯＳＦリング発生領域、ボイド欠陥を含む領域、無欠陥領域の順にサーマルドナー発生速度は大きくなった。熱処理時間が４時間を越えると、ドナーキラー処理なしではサーマルドナー発生速度は一旦上昇したのち減少した。一方で、ドナーキラー処理ありではサーマルドナー発生速度は減少し、１６時間以降は全ての条件でサーマルドナー発生速度は同じになった。 As shown in FIG. 5, when the heat treatment time is within 4 hours, the donor killer treatment is performed on the OSF ring generation region, the region including the void defect, and the non-defect region as compared with the case where the donor killer treatment is performed (samples B1, B2, and B3). None (samples A1, A2, A3) had a higher thermal donor generation rate. In addition, the thermal donor generation rate was the same in any region with the donor killer treatment, but without the donor killer treatment, the thermal donor generation rate increased in the order of the OSF ring generation region, the void-containing region, and the defect-free region. became. When the heat treatment time exceeded 4 hours, the thermal donor generation rate once increased and then decreased without the donor killer treatment. On the other hand, with donor killer treatment, the thermal donor generation rate decreased, and after 16 hours, the thermal donor generation rate became the same under all conditions.
　図６は、４５０℃で４時間のサーマルドナー発生熱処理を施したときの、ＯＳＦリング発生領域、ボイド欠陥を含む領域、無欠陥領域での、サーマルドナー発生速度と酸素濃度の関係を求めた結果を示すグラフであって、横軸は酸素濃度（×１０１７ａｔｏｍｓ／ｃｍ３）、縦軸はサーマルドナー発生速度（ｃｍ－３／ｈ）をそれぞれ示している。 FIG. 6 shows the result of determining the relationship between the thermal donor generation rate and the oxygen concentration in the OSF ring generation region, the region including void defects, and the defect-free region when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours. The horizontal axis represents the oxygen concentration (× 10 17 atoms / cm 3 ), and the vertical axis represents the thermal donor generation rate (cm −3 / h).
　図６に示すように、いずれの酸素濃度でも図１と同様に、ドナーキラー処理あり（サンプルＢ１，Ｂ２，Ｂ３）よりもドナーキラー処理なし（サンプルＡ１，Ａ２，Ａ３）のウェーハのほうがサーマルドナー発生速度は大きかった。また、ドナーキラー処理ありのウェーハではいずれの領域もサーマルドナー発生速度は同じであったが、ドナーキラー処理なしのウェーハでは、ＯＳＦリング発生領域、ボイド欠陥を含む領域、無欠陥領域の順にサーマルドナー発生速度は大きくなった。 As shown in FIG. 6, as in FIG. 1, the wafer with no donor killer treatment (samples A1, A2, A3) is the thermal donor at any oxygen concentration rather than the donor killer treatment (samples B1, B2, B3). The generation rate was great. In addition, the thermal donor generation rate was the same in all regions in the wafer with the donor killer process, but in the wafer without the donor killer process, the thermal donor was in the order of the OSF ring generation region, the region including the void defect, and the non-defect region. The generation rate has increased.
　図７は、図６のグラフにおいて、ドナーキラー処理なしのウェーハの各測定ポイントでのサーマルドナー発生速度をドナーキラー処理ありのウェーハの同一測定ポイントでのサーマルドナー発生速度で規格化したものであって、横軸は酸素濃度（×１０１７ａｔｏｍｓ／ｃｍ３）、縦軸はサーマルドナー発生速度（規格値）をそれぞれ示している。 FIG. 7 is a graph in which the thermal donor generation rate at each measurement point of the wafer without donor killer treatment is normalized with the thermal donor generation rate at the same measurement point of the wafer with donor killer treatment in the graph of FIG. The horizontal axis represents the oxygen concentration (× 10 17 atoms / cm 3 ), and the vertical axis represents the thermal donor generation rate (standard value).
　図７に示すように、ドナーキラー処理なしのウェーハの無欠陥領域でのサーマルドナー発生速度は、ドナーキラー処理ありのウェーハのサーマルドナー発生速度の１．３倍以上１．７倍未満であった。また、ドナーキラー処理なしのウェーハのボイド欠陥を含む領域でのサーマルドナー発生速度は、ドナーキラー処理ありのウェーハのサーマルドナー発生速度の１．７倍以上１．９倍未満であった。さらに、ドナーキラー処理なしのウェーハのＯＳＦリング発生領域でのサーマルドナー発生速度は、ドナーキラー処理ありのウェーハのサーマルドナー発生速度の１．９倍以上２．３倍未満であった。 As shown in FIG. 7, the thermal donor generation rate in the defect-free region of the wafer without donor killer treatment was 1.3 times or more and less than 1.7 times the thermal donor generation rate of the wafer with donor killer treatment. . In addition, the thermal donor generation rate in the region including the void defect of the wafer without donor killer treatment was 1.7 times or more and less than 1.9 times the thermal donor generation rate of the wafer with donor killer treatment. Furthermore, the thermal donor generation rate in the OSF ring generation region of the wafer without donor killer treatment was 1.9 times or more and less than 2.3 times the thermal donor generation rate of the wafer with donor killer treatment.
Ｓ１１　　結晶育成工程
Ｓ１２　　スライス工程
Ｓ１３，Ｓ１４　　サーマルドナー発生速度測定工程
Ｓ１５　　判別工程
Ｓ１６，Ｓ１７　　結晶育成条件調整工程
Ｓ２０　　ウェーハ準備工程
Ｓ２１　　第１のウェーハの比抵抗測定工程
Ｓ２２　　第１のウェーハのサーマルドナー発生熱処理工程
Ｓ２３　　第１のウェーハの比抵抗測定工程
Ｓ２４　　第１のサーマルドナー発生速度算出工程
Ｓ２５　　第２のウェーハのドナーキラー処理工程
Ｓ２６　　第２のウェーハの比抵抗測定工程
Ｓ２７　　第２のウェーハのサーマルドナー発生熱処理工程
Ｓ２８　　第２のウェーハの比抵抗測定工程
Ｓ２９　　第２のサーマルドナー発生速度算出工程 S11 Crystal growth step S12 Slice step S13, S14 Thermal donor generation rate measurement step S15 Discrimination step S16, S17 Crystal growth condition adjustment step S20 Wafer preparation step S21 Specific resistance measurement step S22 of the first wafer Thermal donor generation of the first wafer Heat treatment step S23 First wafer specific resistance measurement step S24 First thermal donor generation rate calculation step S25 Second wafer donor killer processing step S26 Second wafer specific resistance measurement step S27 Second wafer thermal donor Generation heat treatment step S28 Second wafer specific resistance measurement step S29 Second thermal donor generation rate calculation step

Claims (15)

  1. 　チョクラルスキー法によって育成されたシリコン単結晶インゴットから切り出したシリコンウェーハの評価方法であって、前記シリコンウェーハにサーマルドナー発生熱処理を施したときに発生するサーマルドナーの発生速度を測定し、当該サーマルドナーの発生速度に基づいて結晶欠陥領域の有無又は結晶欠陥の種類を判別することを特徴とするシリコンウェーハの評価方法。 An evaluation method of a silicon wafer cut out from a silicon single crystal ingot grown by the Czochralski method, measuring the generation rate of a thermal donor generated when a thermal donor generation heat treatment is performed on the silicon wafer, A silicon wafer evaluation method, wherein the presence or absence of a crystal defect region or the type of crystal defect is determined based on a donor generation rate.
  2. 　前記シリコン単結晶インゴットから切り出した第１のシリコンウェーハが酸素クラスターを含む状態において前記サーマルドナー発生熱処理を施したときに前記第１のシリコンウェーハ上の第１の測定ポイントに発生するサーマルドナーの発生速度である第１のサーマルドナー発生速度を求め、
    　前記第１のシリコンウェーハと異なる第２のシリコンウェーハにドナーキラー処理及び前記サーマルドナー発生熱処理を順に施したときに前記第２のシリコンウェーハ上の第２の測定ポイントに発生するサーマルドナーの発生速度である第２のサーマルドナー発生速度を求め、
    　前記第２のサーマルドナー発生速度に対する第１のサーマルドナー発生速度の比であるサーマルドナー発生速度比に基づいて、前記第１のシリコンウェーハ上の前記第１の測定ポイントがＯＳＦ核を含む領域、ボイド欠陥を含む領域又は無欠陥領域のいずれに該当するかを判別する、請求項１に記載のシリコンウェーハの評価方法。     Generation of a thermal donor generated at a first measurement point on the first silicon wafer when the thermal donor generation heat treatment is performed in a state where the first silicon wafer cut out from the silicon single crystal ingot includes an oxygen cluster. A first thermal donor generation rate, which is a rate,
    The generation rate of the thermal donor generated at the second measurement point on the second silicon wafer when the second silicon wafer different from the first silicon wafer is subjected to the donor killer process and the thermal donor generation heat treatment in order. A second thermal donor generation rate of
    Based on a thermal donor generation rate ratio, which is a ratio of a first thermal donor generation rate to the second thermal donor generation rate, a region where the first measurement point on the first silicon wafer includes OSF nuclei, The silicon wafer evaluation method according to claim 1, wherein it is determined whether the region corresponds to a void defect-containing region or a defect-free region.
  3. 　前記サーマルドナー発生速度比が第１の速度範囲内にある場合に、前記第１のシリコンウェーハ上の前記第１の測定ポイントが無欠陥領域であると判別し、
    　前記サーマルドナー発生速度比が前記第１の速度範囲よりも高い第２の速度範囲内にある場合に、前記第１のシリコンウェーハ上の前記第１の測定ポイントがボイド欠陥を含む領域であると判別し、
    　前記サーマルドナー発生速度比が前記第２の速度範囲よりも高い第３の速度範囲内にある場合に、前記第１のシリコンウェーハ上の前記第１の測定ポイントがＯＳＦ核を含む領域であると判別する、請求項２に記載のシリコンウェーハの評価方法。     When the thermal donor generation speed ratio is within a first speed range, it is determined that the first measurement point on the first silicon wafer is a defect-free region;
    When the thermal donor generation speed ratio is in a second speed range higher than the first speed range, the first measurement point on the first silicon wafer is a region including a void defect. Discriminate,
    When the thermal donor generation speed ratio is in a third speed range higher than the second speed range, the first measurement point on the first silicon wafer is a region including OSF nuclei. The silicon wafer evaluation method according to claim 2, wherein discrimination is performed.
  4. 　前記サーマルドナー発生熱処理は、４３０℃以上４８０℃以下で２時間以上４時間以下の熱処理である、請求項１乃至３のいずれか一項に記載のシリコンウェーハの評価方法。 The method for evaluating a silicon wafer according to any one of claims 1 to 3, wherein the thermal donor-generated heat treatment is a heat treatment at 430 ° C or higher and 480 ° C or lower for 2 hours or longer and 4 hours or shorter.
  5. 　４５０℃で４時間の前記サーマルドナー発生熱処理を施したとき、前記サーマルドナー発生速度比が１．３以上１．７未満である場合に、前記第１のシリコンウェーハ上の前記第１の測定ポイントが無欠陥領域であると判別する、請求項２に記載のシリコンウェーハの評価方法。 The first measurement point on the first silicon wafer when the thermal donor generation rate ratio is not less than 1.3 and less than 1.7 when the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours. The silicon wafer evaluation method according to claim 2, wherein it is determined that is a defect-free region.
  6. 　４５０℃で４時間の前記サーマルドナー発生熱処理を施したとき、前記サーマルドナー発生速度比が１．７以上１．９未満である場合に、前記第１の測定ポイントがボイド欠陥を含む領域であると判別する、請求項２又は５に記載のシリコンウェーハの評価方法。 When the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours, when the thermal donor generation rate ratio is 1.7 or more and less than 1.9, the first measurement point is a region including void defects. The silicon wafer evaluation method according to claim 2, wherein:
  7. 　４５０℃で４時間の前記サーマルドナー発生熱処理を施したとき、前記サーマルドナー発生速度比が１．９以上２．３未満である場合に、前記第１の測定ポイントがＯＳＦ核を含む領域であると判別する、請求項２、５又は６に記載のシリコンウェーハの評価方法。 When the thermal donor generation heat treatment is performed at 450 ° C. for 4 hours and the thermal donor generation rate ratio is 1.9 or more and less than 2.3, the first measurement point is a region containing OSF nuclei. The silicon wafer evaluation method according to claim 2, 5 or 6.
  8. 　前記シリコンウェーハの径方向に沿って設けた複数の測定ポイントの各々において前記サーマルドナーの発生速度を測定することにより、前記シリコンウェーハの径方向の結晶欠陥マップを作成する、請求項１乃至７のいずれか一項に記載のシリコンウェーハの評価方法。 The crystal defect map in the radial direction of the silicon wafer is created by measuring the generation rate of the thermal donor at each of a plurality of measurement points provided along the radial direction of the silicon wafer. The evaluation method of the silicon wafer as described in any one of Claims.
  9. 　前記シリコンウェーハの比抵抗を測定し、前記比抵抗をもとにキャリア濃度をアービンカーブから求め、前記サーマルドナー発生熱処理前後のキャリア濃度をもとにサーマルドナー発生量を求め、前記サーマルドナー発生熱処理の時間と前記サーマルドナー発生量との関係から前記サーマルドナー発生速度を求める、請求項１乃至８のいずれか一項に記載のシリコンウェーハの評価方法。 The specific resistance of the silicon wafer is measured, the carrier concentration is determined from an Irvin curve based on the specific resistance, the thermal donor generation amount is determined based on the carrier concentration before and after the thermal donor generation heat treatment, and the thermal donor generation heat treatment 9. The method for evaluating a silicon wafer according to claim 1, wherein the thermal donor generation rate is obtained from a relationship between the time of generation and the thermal donor generation amount.
  10. 　第１のシリコン単結晶インゴットをチョクラルスキー法によって育成し、
    　前記第１のシリコン単結晶インゴットから切り出した評価用シリコンウェーハにサーマルドナー発生熱処理を施したときに発生するサーマルドナーの発生速度を測定し、当該サーマルドナーの発生速度の測定結果に基づいて前記評価用シリコンウェーハ中の結晶欠陥領域の有無又は結晶欠陥の種類を判別し、
    　前記第１のシリコン単結晶インゴットの育成条件及び前記評価用シリコンウェーハ中の結晶欠陥領域の有無又は結晶欠陥の種類の判別結果に基づいて、第２のシリコン単結晶インゴットの育成条件を調整し、前記第２のシリコン単結晶インゴットから製品用シリコンウェーハを切り出すことを特徴とするシリコンウェーハの製造方法。     Growing the first silicon single crystal ingot by the Czochralski method,
    The generation rate of a thermal donor generated when a thermal donor generation heat treatment is performed on the evaluation silicon wafer cut out from the first silicon single crystal ingot is measured, and the evaluation is performed based on the measurement result of the generation rate of the thermal donor. Determine the presence or absence of crystal defects in the silicon wafer for use or the type of crystal defects,
    Based on the growth condition of the first silicon single crystal ingot and the determination result of the presence or absence of the crystal defect region in the silicon wafer for evaluation or the type of crystal defect, the growth condition of the second silicon single crystal ingot is adjusted, A silicon wafer production method, wherein a product silicon wafer is cut out from the second silicon single crystal ingot.
  11. 　前記第２のシリコン単結晶インゴットの育成条件を調整することによって、無欠陥領域を有する前記第２のシリコン単結晶インゴットを育成する、請求項１０に記載のシリコンウェーハの製造方法。 The method for producing a silicon wafer according to claim 10, wherein the second silicon single crystal ingot having a defect-free region is grown by adjusting a growth condition of the second silicon single crystal ingot.
  12. 　前記第２のシリコン単結晶インゴットの育成条件を調整することによって、ボイド欠陥を含む領域を有する前記第２のシリコン単結晶インゴットを育成する、請求項１０に記載のシリコンウェーハの製造方法。 The method for producing a silicon wafer according to claim 10, wherein the second silicon single crystal ingot having a region including a void defect is grown by adjusting a growth condition of the second silicon single crystal ingot.
  13. 　前記第２のシリコン単結晶インゴットの育成条件を調整することによって、ＯＳＦ核を含む領域を有する前記第２のシリコン単結晶インゴットを育成する、請求項１０に記載のシリコンウェーハの製造方法。 The method for producing a silicon wafer according to claim 10, wherein the second silicon single crystal ingot having a region including an OSF nucleus is grown by adjusting a growth condition of the second silicon single crystal ingot.
  14. 　前記第２のシリコン単結晶インゴットの育成条件として、前記第２のシリコン単結晶インゴットの引き上げ速度を調整する、請求項１０乃至１３のいずれか一項に記載のシリコンウェーハの製造方法。 The method for producing a silicon wafer according to any one of claims 10 to 13, wherein a pulling rate of the second silicon single crystal ingot is adjusted as a growth condition for the second silicon single crystal ingot.
  15. 　前記製品用シリコンウェーハにドナーキラー処理を施す、請求項１０乃至１４のいずれか一項に記載のシリコンウェーハの製造方法。 The method for producing a silicon wafer according to any one of claims 10 to 14, wherein the product silicon wafer is subjected to a donor killer treatment.
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