WO2018006010A1 - Procédés et systèmes de soudage de nanofils semi-conducteurs - Google Patents

Procédés et systèmes de soudage de nanofils semi-conducteurs Download PDF

Info

Publication number
WO2018006010A1
WO2018006010A1 PCT/US2017/040362 US2017040362W WO2018006010A1 WO 2018006010 A1 WO2018006010 A1 WO 2018006010A1 US 2017040362 W US2017040362 W US 2017040362W WO 2018006010 A1 WO2018006010 A1 WO 2018006010A1
Authority
WO
WIPO (PCT)
Prior art keywords
nanowires
nanowire
nws
film
welding
Prior art date
Application number
PCT/US2017/040362
Other languages
English (en)
Inventor
James F. CAHOON
David John Hill
Thomas Anthony CELANO
Original Assignee
The University Of North Carolina At Chapel Hill
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The University Of North Carolina At Chapel Hill filed Critical The University Of North Carolina At Chapel Hill
Publication of WO2018006010A1 publication Critical patent/WO2018006010A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • the presently disclosed subject matter is directed to methods and systems for capillarity-driven welding of semiconductor nanowires for flexible three-dimensional networks with ohmic interconnects.
  • NWs Nanowires
  • flow-alignment 4 mechanical transfer printing 5
  • dip coating 6 dip coating 6
  • electric- field assisted placement 7 top-down patterning strategies 8 .
  • electrically-active networks have been developed as a class of transparent and conductive thin films with silver 9 (Ag), copper 10 (Cu), and gold 1 1 (Au) NWs, as well as carbon nanotubes 12 .
  • Ohmic connections between these components have been formed through a variety of techniques 13 , including cold welding 14 , plasmonic welding, 15 thermal annealing 16 , mechanical pressure 17 , diffusion bonding 18 , and electron-beam induced welding 19 .
  • semiconductor NWs could offer a wide range of more advanced functionality by encoding field-effect transistors 20 , p-n junctions 21 , and memory bits 22 within the individual NWs of the network 23 .
  • NWs grown by a vapor-liquid-solid (VLS) mechanism has been limited to junctions formed either by electrical biasing individual wires, 29 patterning NWs to intersect during the VLS process, 30"32 or using a multi-step VLS processes to create branched nanowires 33"35 .
  • VLS vapor-liquid-solid
  • these strategies are generally limited to a low number of NWs and interconnection points.
  • methods of synthesizing electrical connections between semiconductor nanowires (NWs) by capillarity-induced welding comprising creating or providing two or more NWs, aligning the two or more NWs to yield at least one inter- nanowire point-of-contact on each NW, and welding the two or more NWs together at the at least one inter-nanowire point-of-contact on each NW by capillarity-driven surface diffusion to form an electrical connection between the two or more NWs, wherein the electrical connection forms an Ohmic junction between the two or more NWs.
  • the welding the two or more NWs together creates at least one inter-nanowire point-of- contact on each NW by capillarity-driven surface diffusion.
  • provided herein are flexible and conductive thin NW films formed by the disclosed methods, wherein the NWs in the film have Ohmic junctions.
  • NW film materials comprising a plurality of NWs overlapping in a random orientation to form a film material, wherein the NWs in the film material are welded at a point-of- contact where two or more NWs overlap to form an electrical connection therebetween, wherein the electrical connections between the plurality of overlapping NWs forms Ohmic junctions.
  • FIGS. 1 A through 1 C are schematic illustrations of a three-step process, including NW growth, collapse, and welding, to create conductive semiconductor NW networks.
  • FIGS. 2A and 2B are transmission electron microscopy (TEM) images of two junctions (labeled by arrows) formed between three crossed NWs, with FIG 2A being a high-resolution transmission electron microscopy (HR- TEM) image, and FIG. 2B being an energy-dispersive x-ray spectroscopy (EDS) elemental map of oxygen (O) using scanning TEM (STEM).
  • TEM transmission electron microscopy
  • FIGS. 2C through 2H are electron microscopy images of NWs illustrating properties of a single, welded junction between two NWs.
  • FIG 2C is a TEM image and FIGS. 2D, 2E and 2F are EDS elemental maps of Si, O, and P, respectively, for a single, welded NW junction within the network of NW junctions.
  • FIG. 2G is a combined Si and O map, and FIG. 2H is a corresponding elemental line scan.
  • FIGS. 3A, 3C and 3D are high-resolution TEM images of a crossed junction of two NWs, while FIG. 3B is a schematic of the image of FIG. 3A.
  • FIGS. 4A and 4B are TEM images of two adjacent, welded NWs, with
  • FIG. 4B being a close-up view of a portion of FIG. 4A.
  • FIGS. 5A through 5K illustrate the diameter and temperature dependence of the welding process.
  • FIG. 5A is a plot showing the suitable temperature for welding dependent on the diameter of the wire to be welded, where circles represent optimal temperatures, squares represent temperatures too low, and triangles represent temperatures too high.
  • FIGS. 5B through 5D are SEM images of optimally welded NWs of different diameters.
  • FIGS. 5E through 5G are SEM images of NWs with the approximately same diameter welded at temperatures too high, optimal, and too low, respectively.
  • FIG 5H is an SEM image of welded Ge NWs.
  • FIGS. 51 through 5K are simulated schematics of the welding process as time increases, or as temperature increases for fixed time.
  • FIGS. 7A and 7B are cross-sectional SEM images of collapsed and welded NWs about 30 nm (FIG. 7A) and about 60 nm (FIG. 7B) in diameter.
  • FIGS. 8A through 8C are schematic illustrations of the fabrication of flexible and conductive Si NW networks.
  • Figure 9 is a plot of the resistance multiplied by channel width as a function of electrode separation (i.e. channel length) for about 50 nm diameter NW networks measured on the Si growth substrate (squares) and on the substrate-free NW-PDMS film (triangles).
  • Figure 1 0 is a plot of the /-Vdata for the NW-PDMS film when straight and in a bent conformation with a radius of curvature of about 4 mm.
  • the term "about,” when referring to a value or to an amount of a composition, mass, weight, temperature, time, volume, concentration, percentage, etc., is meant to encompass variations of in some embodiments ⁇ 20%, in some embodiments ⁇ 10%, in some embodiments ⁇ 5%, in some embodiments ⁇ 1 %, in some embodiments ⁇ 0.5%, and in some embodiments ⁇ 0.1 % from the specified amount, as such variations are appropriate to perform the disclosed methods or employ the disclosed compositions.
  • the phrase “consisting of” excludes any element, step, or ingredient not specified in the claim.
  • the phrase “consists of” appears in a clause of the body of a claim, rather than immediately following the preamble, it limits only the element set forth in that clause; other elements are not excluded from the claim as a whole.
  • nanowires can in some embodiments refer to any high-aspect ratio structure with a cross-sectional size of about 1 micron or less and with variable cross sectional shapes, including for example a circle, ellipse, square, rectangle, hexagon, octagon, etc.
  • VLS vapor-liquid-solid
  • such methods of synthesizing electrical connections between semiconductor NWs by capillarity-induced welding can comprise creating, i.e. synthesizing, or otherwise providing, two or more NWs, and aligning the two or more NWs to yield at least one inter-nanowire point-of- contact on each NW.
  • Such an alignment can be random or intentional so long as the NWs overlap at least at one point to form a point-of-contact or junction point.
  • the two or more NWs can be welded together by capillarity-driven surface diffusion to form an electrical connection or junction between the two or more NWs.
  • the electrical connection forms an Ohmic junction between the two or more NWs. Completing these steps on a large scale for multiple NWs can allow for the synthesis of a network of interconnected NWs having Ohmic junctions.
  • NWs can be grown by, for example, a VLS mechanism using Au catalysts and then collapsed using liquid capillary forces to yield multiple inter-nanowire points-of- contact on each NW.
  • NWs can in some embodiments be welded by a capillarity-driven surface diffusion process for about 1 minute to about 240 minutes, or about 1 , 2, 3, 4, 5, 10, 15, 20, 25, 30, 60, 1 20 or 240 minutes, at temperatures ranging from about 100°C to about 1 ,000°C below the bulk melting point, or about 100, 200, 300, 400, 500, 600, 700, 800, 900 or 1 ,000°C below the bulk melting point, in some embodiments about 4 minutes at temperatures of about 400-600 °C below the bulk melting point (see Methods for all experimental details). NWs grown by other mechanisms and systems other than VLS are equally applicable to the disclosed methods of welding by capillarity-driven surface diffusion.
  • FIG. 1 A illustrates that NWs 102 can be provided or grow on a substrate or growth substrate 104 using any suitable NW growth technique including those discussed herein.
  • NWs 102 can be collapsed C using any suitable collapse method including but not limited to those described herein. See, e.g. FIG. 1 B.
  • NWs 102 are randomly oriented along a planar surface of substrate 104. Within this three-dimensional layer of randomly oriented NWs 102 the NWs 102 overlap one another forming points-of-contact 106, or overlaps, as shown in FIG. 1 B.
  • a weld portion or junction 108 is formed at the overlap of each NW 102.
  • the three- dimensional layer of randomly oriented NWs 102 forms a three-dimensional film of joined NWs 102, as discussed further herein.
  • one example method of NW synthesis includes the vapor-liquid- solid (VLS) process.
  • VLS process can comprise a two-step growth procedure that avoids vapor-solid overcoating on a NW surface.
  • VLS NW synthesis can include the creation of NWs on a growth wafer or other suitable substrate.
  • the NWs can also be doped with phosphorus (P) to create doped or degenerately-doped n-type Si NWs, or doped with boron (B) to create doped or degenerately-doped p-type Si.
  • P phosphorus
  • B doped with boron
  • the NWs can be doped with any material typical used in the art.
  • the NWs can be composed of a semiconductor material such as Si or Ge, or any other semiconductor material made in a NW morphology.
  • suitable methods of synthesizing and/or creating NWs for the disclosed capillarity-driven welding methods include a top-down fabrication method, a vapor-phase deposition process (such as but not limited to chemical vapor deposition, metal organic chemical vapor deposition, vapor-phase epitaxy, and molecular beam epitaxy), a liquid-phase deposition process, and an electrochemical deposition process.
  • suitable NWs can comprise any high-aspect ratio structure with a cross- sectional size of about 1 micron or less and with variable cross sectional shapes, including a circle, ellipse, square, rectangle, hexagon and/or octagon.
  • the alignment of the NWs prior to welding can in some aspects comprise a step of collapsing the NWs on the growth substrate.
  • collapsing the NWs comprises using a liquid capillary force, such as for example using liquid nitrogen or other inert or passivating liquid to cause the collapse of the NWs on the growth substrate.
  • liquid nitrogen can be suitable, particularly since in some embodiments the use of liquid nitrogen can avoid or substantially avoid the formation of an oxide layer on the NW surface prior to welding.
  • any procedure sufficient to cause the NWs to touch, overlap and/or otherwise come into sufficient contact with a point of curvature sufficient for the subsequent welding can be used.
  • a plurality of inter-nanowire points-of-contact on each NW can be achieved.
  • suitable NWs can also be provided in a suspended solution and then deposited on a substrate in a random or oriented manner causing the NWs to overlay or touch to form inter-nanowire points-of-contact between the NWs. Any suitable method of arranging a plurality of NWs such that they are overlapping and/or contacting one another in a random or organized manner is within the scope of the instant disclosure and provides a suitable arrangement of NWs for the disclosed welding method.
  • the NWs can in some embodiments be welded by a capillarity-driven surface diffusion process over a range of times and temperatures depending on the desired outcome and operating conditions.
  • the NWs are welded by capillarity-driven surface diffusion for about 1 minute to about 10 minutes at a temperature of about 400 °C to about 600 °C below a bulk melting point.
  • Such welding reshapes the inter-nanowire point-of-contact between each NW to form a high density of interconnections.
  • the welding reshapes the inter-nanowire point-of-contact between each NW to form a compositionally- uniform and oxygen-free interface between each NW.
  • the interface formation caused by the welding is a self-limited process (see Examples for further details).
  • the disclosed methods can further comprise removing any oxide layer present on the NWs prior to welding.
  • the disclosed methods and systems for capillarity-driven welding of semiconductor nanowires for flexible three-dimensional networks is based at least in part on the discovery that such methodologies result in NW networks with Ohmic junctions.
  • NW networks or films can have an l-V curve that is substantially linear over a broad voltage range.
  • the volume density of Ohmic junctions can meet or exceed 1 ⁇ 3 .
  • Such conductive films are three dimensional and can have a thickness of about 5 ⁇ to about 10 ⁇ , or in some embodiments ranging from about the thickness of one NW to 100 ⁇ or more.
  • fabrication of flexible and conductive Si NW networks can in some embodiments comprise a NW-PDMS lift-off process.
  • a NW-PDMS lift-off process can comprise, for example, PDMS deposition on the growth wafer (FIG. 8A), wet- chemical etching of Ge (FIG. 8B), and lift off of the NW-PDMS film (FIG. 8C).
  • Large-area, flexible networks can be created by depositing a sacrificial germanium (Ge) layer 308 on a growth wafer 306 prior to Au catalyst dispersal. This layer can be removed by wet-chemical etching 304 in hydrogen peroxide (FIG.
  • the NW can be infiltrated with poly-dimethyl siloxane (PDMS) prior to Ge etching to provide additional handling stability, leading to the lift-off process illustrated in FIGS. 8A through 8C.
  • PDMS poly-dimethyl siloxane
  • the resulting NW film can in some embodiments have high optical transparency, which matches finite-element optical simulations of the transmittance spectrum.
  • the transparency and color of the NW films can in some embodiments strongly depend on diameter-dependent Lorentz-Mie scattering, and optical tuning is possible simply by changing the diameters in the sample.
  • Si and Ge NWs are used as examples.
  • the presently disclosed methods, systems, processes and resulting products are not limited to Si and Ge NWs, but are applicable to any element or material suitable for NW synthesis under the conditions disclosed and discussed herein.
  • suitable NWs can be made of semiconductors including but not limited to group IV, group lll-V, group ll-VI, and group IV-VI semiconductors as well as alloys and combinations thereof.
  • these may be Si, Ge, Si x Gei-x, GaN, GaP, GaAs, GaSb, AIN, AIP, AIAs, AlSb, InN, InP, InAs, InSb, ZnO, ZnS, ZnSe, CdO, CdS, CdTe, PbO, PbS, PbSe, and alloys thereof.
  • liquid nitrogen can in some embodiments be used in the collapse process, this is only one exemplary procedure.
  • any collapse procedure can be used so long as the synthesized NWs are caused to touch, overlap or otherwise come into sufficient contact with a point of curvature sufficient for the subsequent welding procedure.
  • NWs can be suspended in a solution and then deposited on a substrate in a random or oriented manner causing them to overlay or touch.
  • NW networks can be used in solar energy and battery electrodes, bioelectronic scaffolds, and a platform for neuromorphic computation.
  • the volume density of junctions can meet or exceed 1 urn "3 , which is comparable to the density, about 1 0 9 mm "3 , of synapses in the human brain 55 .
  • semiconductor NW networks have promise for a variety of applications without the use of advanced lithography or assembly methods.
  • a home-built chemical vapor deposition (CVD) system was used for all syntheses and includes a quartz-tube furnace (Lindberg Blue M), hydrogen (H 2 ) and Argon (Ar) carrier gases (Matheson Trigas; 5N semiconductor grade), and reactive gases (Voltaix/Air Liquide Advanced Materials) silane (SiH 4 ), germane (GeH 4 ; 1 0% in H 2 ), diborane (B 2 H 6 ; 1 00 ppm in H 2 ), and phosphine (PH 3 ; 1000 ppm in H 2 ).
  • NW growth substrates consisted of Si/Si0 2 wafers (Nova Electronic Materials; B-doped 1 -10 ⁇ -cm Si wafers with 600 nm thermal oxide) and were optionally coated with about 200 nm sacrificial Ge layer following a modified literature procedure 50 . Briefly, substrates were annealed for 1 0 minutes at 600 °C with 100 standard cubic centimeters per minute (seem) of H 2 , a seed layer was deposited for 1 min at 350°C and 20 Torr using 1 seem SiH 4 and 10 seem B 2 H 6 with 60 seem Ar, and Ge was deposited for 75 min at 330°C and 5 Torr using 10 seem of GeH 4 and 1 00 seem H 2 .
  • Si/Si0 2 or Si/Si0 2 /Ge substrates were then placed in an ultraviolet/ozone cleaner (Samco UV-1 ) and functionalized with a 1 0:1 water: poly-L-lysine (0.1 % in H 2 0, Sigma Aldrich) solution followed by dispersion of citrate-stabilized Au colloids (BBI international) with diameters of about 30-100 nm.
  • N-type Si NWs were grown in the CVD system following a modified literature procedure 21 ,27 using a 5 min 450 °C nucleation step followed by a ramp (1 °C/min cooling rate) to 420°C with 200 seem H 2 , 2 seem SiH 4 , 10 seem PH 3 , and a total growth time of 5 hours.
  • NW arrays were collapsed by sliding the growth substrate directly from the quartz tube into liquid nitrogen (N 2 ) while flowing 200 seem Ar. The substrate was then reinserted into the quartz tube, and the tube was evacuated to vacuum. Evaporation of liquid N 2 caused collapse of the NWs without formation of an oxide layer.
  • N 2 liquid nitrogen
  • the welding process was performed by raising the temperature to 800-900 °C under 200 seem H 2 at 8 Torr. At the desired temperature, the H 2 flow was reduced to 60 seem, the pressure was ramped to 25 Torr, the conditions were held for 4 min, and the system was then cooled to room temperature.
  • Ge NW networks were synthesized by modifying the procedure for Si NWs. Ge NWs were nucleated for 30 min at 320 °C under 1 00 seem Ar and 15 seem GeH 4 at 300 Torr followed by a ramp (5°C/min cooling rate) to 260°C and continued growth for 4 hours. Ge networks were welded using the same procedure as for Si NWs but with a temperature of 600 °C rather than 800-900 .
  • Electron microscopy imaging SEM imaging was performed using an FEI Helios 600 Nanolab Dual Beam system. Samples for HR-TEM and STEM were prepared by mechanical contact-transfer directly on to lacey-carbon TEM grids (Ted-Pella #01895). STEM imaging was performed on a Tecnai Osiris operating at 200 kV with a sub-nm probe with a current of 2 nA (spot size 3, 4k extraction voltage). Drift-corrected STEM-EDS maps were obtained using the Bruker Esprit software. Acquisition time for each map was about 1 5 minutes. Standardless Cliff-Lorimer quantification was performed on the deconvoluted spectra from sub-sections of the EDS maps. STEM images were obtained before and after map acquisition to note any change in the sample.
  • the geometric models were created using version 2.70 of the program Surface Evolver 41 .
  • the initial crossed NW geometry begins as a simplicial complex constructed from two perpendicular icosahedral prisms that intersect at four points to form a continuous body.
  • the surface is refined and allowed to evolve towards a minimal energy configuration via a gradient descent method under isochoric conditions.
  • the three simulations results in FIGS. 5I through 5K represent successive time points along a progression dictated by the mean curvature.
  • the models were imported into COMSOL Multiphysics, and the surface gradient of the curvature was calculated with a weak-form boundary partial differential equation formulation.
  • the surface velocity, v s was then calculated as given by equation 2 (below).
  • Si/SiO 2 /Ge substrates were used for NW growth, and PDMS (Sylgard 184 Silicone Elastomer) was spun cast onto the NW networks (500 rpm for 5 seconds and 1500 rpm for 30 seconds). The substrates were cured for 60 min at 60°C. Polymer was removed from the edges of the substrate, and the substrate was immersed in 30% hydrogen peroxide at 80 °C for several days to remove the Ge layer.
  • PDMS Sylgard 184 Silicone Elastomer
  • Ti/Pd contacts For measurements on NW networks, titanium/palladium (Ti/Pd) contacts (5/200 nm) were evaporated, after a brief BHF etch, onto the exposed NW networks via a shadow mask in an electron beam evaporator (Thermionics VE-1 00).
  • welded NWs were mechanically transferred onto devices substrates (Nova Electronic Materials; B-doped 1 -1 0 ⁇ -cm Si wafers with 100 nm thermal oxide and 200 nm silicon nitride).
  • Electron-beam lithography was used to pattern electrical contacts to individual NWs, and Ti/Pd contacts (3/200 nm) were evaporated after a brief etch in BHF.
  • I-V data for both NW networks and single welded junctions were collected with a Keithley 2636A SourceMeter in conjunction with Signatone micropositioners (S-725) and probe tips (SE-TL) or a Lake Shore Cryotronics PS-100 probe station. NW diameters and channel lengths were measured by SEM. For measurements in a bent configuration, NW-PDMS films were wrapped around a pencil to demonstrate the durability of the networks.
  • the 10 pJ/pulse pump beam and 1 .5 pJ/pulse probe beam were recombined using a dichroic beam splitter and directed onto the back aperture of a 50x (0.8 NA) objective that focused them to diffraction- limited spots on the welded structures.
  • the probe beam was collected with a condenser lens, filtered to remove pump light, and directed onto a balanced photodiode. Pump-induced changes in the intensity of the probe pulse were monitored with a digital lock-in amplifier. For kinetic traces, the probe beam was increased in intensity to 2.5 pJ/pulse. Errors for the reported time constants reflect two standard deviations.
  • junction transmittance spectra were measured with a microspectrophotometer (20/30 PV UV-Visible-NIR from Craic Industries) using a 10x objective (Ultrafluor 10x 0.2 NA 7.4 mm WD) in conjunction with a xenon arc lamp source and CCD array detector.
  • Optical simulations were performed using COMSOL Multiphasics.
  • the two-dimensional simulation domain consisted of a Si NW with a circular cross-section placed in a vacuum encapsulated by perfectly matched layers (PMLs) to prevent reflection/scattering effects from the simulation boundaries.
  • a three-step process including NW growth, collapse, and welding, can create conductive semiconductor NW networks.
  • NWs can first be grown by the VLS mechanism using Au catalysts and then collapsed using liquid capillary forces to yield multiple inter-nanowire points-of-contact on each NW, or substantially each NW. Then, in some embodiments, the NWs can be welded by a capillarity-driven surface diffusion process for about 4 minutes at temperatures of about 400-600 °C below the bulk melting point (see Methods for all experimental details).
  • NWs 102 can be provided or grow on a substrate or growth substrate 104 using any suitable NW growth technique including those discussed herein.
  • NWs 102 can be collapsed C using any suitable collapse method including but not limited to those described herein.
  • NWs 102 are randomly oriented along a planar surface of substrate 104.
  • the NWs 102 overlap one another forming points-of-contact 106, or overlaps, as shown in FIG. 1 B.
  • a weld portion or junction 108 is formed at the overlap of each NW 102.
  • the three-dimensional layer of randomly oriented NWs 102 forms a three-dimensional film of joined NWs 102, as discussed further herein.
  • the VLS process was performed using a two-step growth procedure that avoids vapor-solid overcoating on the wire surface 22 .
  • NWs were doped with phosphorus (P) to create degenerately-doped n-type Si.
  • the collapse process was performed with liquid nitrogen to avoid formation of an oxide layer on the wire surface prior to welding.
  • the NW networks were exposed to ambient conditions, causing formation of a 2-3 nm native oxide on the surface.
  • FIGS. 2A and 2B show a high-resolution transmission electron microscopy (HR-TEM) image (FIG. 2A) and an energy-dispersive x-ray spectroscopy (EDS) elemental map (FIG. 2B) of oxygen (O) using scanning TEM (STEM) of two junctions (labeled by arrows) formed between three crossed NWs.
  • HR-TEM transmission electron microscopy
  • EDS energy-dispersive x-ray spectroscopy
  • FIGS. 2C through 2H further illustrate properties of a single, welded junction between two NWs.
  • FIG 2C is a TEM image
  • FIGS. 2D, 2E and 2F are EDS elemental maps of Si, O, and P, respectively, for a single, welded NW junction within the network of NW junctions.
  • FIGS. 2D, 2E and 2F are EDS elemental maps of Si, O, and P, respectively, for a single, welded NW junction within the network of NW junctions.
  • FIG. 2F shows that a native oxide layer has formed uniformly on the surface of the wires and the junction but not at the interface between the two wires, as evidenced by the O signal at the junction being equivalent in amplitude to the signal along the individual NWs.
  • a combined Si and O map (FIG. 2G), and corresponding elemental line scan (FIG. 2H), of a second welded junction further confirm the absence of an oxide layer at the interface between the wires.
  • FIGS. 2C through 2H Compositional analysis of welded NW junctions
  • the images in FIGS. 2C through 2H demonstrate that the two wires have locally fused to form a compositionally-uniform and oxygen-free interface.
  • High-resolution TEM images of a second crossed junction FIG.
  • FIGS. 3C and 3D are close-up views of insets 1 and 2 from FIG. 3A showing junction 108 of NW
  • FIGS. 4A and 4B Additional TEM images for two adjacent, welded NWs are shown in FIGS. 4A and 4B.
  • the image of FIG 4A shows that the process can in some embodiments fuse two NWs, NW 102c and 102d, leaving a single zig-zag grain boundary or junction.
  • FIG. 4B is a close-up view of inset 124 in FIG.
  • FIGS. 5A through 5K The diameter and temperature dependence of the welding process was examined, as shown in FIGS. 5A through 5K.
  • the temperature suitable in some embodiments for welding shows a strong dependence on diameter, and the qualitative results from multiple wire diameters and temperatures are summarized in FIG. 5A.
  • Three regimes were observed: absence of welding (squares below dashed line), optimal welding (circles above dashed line but below dashed-dotted line), and structural instability (triangles above dashed- dotted line).
  • temperatures of about 25 °C higher resulted in structural instability at the junction (FIG. 5E) whereas temperatures about 25 °C lower resulted in no noticeable morphological change (FIG. 5G), as exemplified by the SEM images in FIGS. 5E through 5G for NWs of about 80 nm in diameter.
  • the morphology of the weld as a function of the process time was also examined. Although 4 minutes was typically used, longer weld times resulted in no additional change to the junction or NW morphology for the optimal weld conditions, indicating that the junction formation can in some embodiments be a self-limited process. In addition, no welding was observed for NWs that had been exposed to ambient conditions prior to the weld process, an observation that in some embodiments can be attributed to formation of a thin native oxide layer that inhibits the welding mechanism.
  • the welding process was also performed on Ge nanowires (FIG. 5H), and a substantially lower temperature of 600 °C was necessary to create high- quality junctions. The results on Si and Ge NWs indicates that the weld process can in some embodiments be successful with high-quality, oxide- free NW surfaces at temperatures of about 400-600 °C below the bulk melting temperature of the NW material.
  • the strong dependence of the weld temperature on diameter suggests that the weld results from a physical process that depends on surface curvature.
  • Capillarity-induced surface diffusion a process in which a change in curvature creates a free-energy gradient that drives atoms away from areas of high curvature, can in some embodiments occur in spherical and cylindrical nanostructures.
  • the effects of this phenomenon can in some embodiments include the blunting of W tips and necking or sintering of nanoparticles.
  • Equation 1 K is (1 //? ⁇ +1 //3 ⁇ 4), fli and /3 ⁇ 4 are the principle radii of curvature for a two-dimensional surface, D s (7) is the temperature-dependent surface diffusion coefficient, ⁇ is the surface tension (1 .6 N/m), ⁇ is the atomic volume of .020 nm 3 , fc B is the Boltzmann constant, T is temperature, and V S K is the surface gradient of the curvature.
  • the normal velocity of the surface, v s which describes the deformation of the NW junction, can be calculated as:
  • Simulations were performed using a surface-evolving simulation 41 combined with finite-element calculations of v s (see Methods). Simulations of the welding process showing initial (FIG. 5I), intermediate (FIG. 5J), and final (FIG. 5K) junction formation.
  • the axis reflects the velocity of the surface normal with positive (+1 0) and negative (-10) values indicating increasing and decreasing diameters, respectively; scale bars, 100 nm.
  • Insets cross-sectional profile of each simulation in the plane that longitudinally bisects the upper NW and passes through the center of the junction; scale bars, 50 nm.
  • FIG. 5I As shown in the first simulation image (FIG. 5I) at a 7 " of 850°C and corresponding D of 1 .8 x 10 "12 m 2 /s 42 , a large surface diffusional flux toward the junction area 108 of NWs 102a and 102b is predicted, producing a v s as high as about 1 1 2 nm/s.
  • the process drives the system to reduce curvature by forming the welded geometry, as shown in the second (FIG. 5 J) and third (FIG. 5K) simulation snapshots with maximum v s of about 10 and about 3 nm/s, respectively.
  • the weld eliminates the high curvature interface between the two wires, such as in FIG. 5K, and the dramatic reduction of v s as the weld evolves explains the self-limited nature of the process.
  • the higher curvature in smaller-diameter crossed junctions, causing higher v s can give rise to the diameter-dependence of the process.
  • the presence of three regimes (no welding, optimal welding, and structural instability; FIG. 5A) over a relatively narrow temperature range can in some embodiments be explained by the Arrhenius dependence of D S (T), which for Si varies by one order of magnitude from 800 to 900 °C.
  • the welded junctions are consistent with the local sintering of Ag nNWs observed upon thermal annealing, and the structural instability is consistent with the onset of Plateau-Rayleigh instability and spheroidization of Ag NWs upon extended annealing. Furthermore, the capillarity-driven formation mechanism explains the absence of any morphological change in regions far from the junction that have nearly uniform curvature, for which v s is approximately zero because there is negligible change in curvature ⁇ i.e. V S K is zero).
  • FIGS. 6A through 6F illustrate the electrical transport properties and recombination dynamics in single, welded Si junctions.
  • FIG. 6A is a SEM image of electrodes E, labeled 1 -4, on two NWs, 102a and 102b, with a single welded junction 108; scale bar, 2 ⁇ .
  • FIG. 6B is a SEM image of the junction 108 and the two electrodes E adjacent to the junction 108; scale bar, 1 ⁇ .
  • FIG. 6C is a four-point probe l-V measurement of the junction shown in FIG. 6A collected by sourcing current on electrodes 1 and 4 and measuring the voltage across electrodes 2 and 3.
  • FIG. 6A is a SEM image of electrodes E, labeled 1 -4, on two NWs, 102a and 102b, with a single welded junction 108; scale bar, 2 ⁇ .
  • FIG. 6B is a SEM image of the junction 108 and the two electrodes E adjacent to the junction 108; scale bar
  • FIG. 6D and 6E are SEM images of the NW junction probed by time-resolved pump-probe microscopy, showing the junction region (FIG. 6D; scale bar, 200 nm) and the entire region probed region (FIG. 6E; scale bar, 500 nm). Circles in FIG. 6E denote the regions in which kinetic traces were collected. Pump-probe images of charge carrier dynamics were collected at time delays of 0 ps, 13 ps, 27 ps and 67 ps, with all normalized relative to the maximum intensity at 0 ps, and analyzed, the results of which are shown in FIG. 6F.
  • FIG. 6F SEM images of the NW junction probed by time-resolved pump-probe microscopy
  • 6F shows the kinetic traces for pump-probe dynamics collected at regions denoted by the numbered circles in panel FIG 6C.
  • the number 5 trace reflects kinetics at the junction while other traces (1 , 2, 3 and 4) represent dynamics in the four arms adjacent to the junction.
  • the electrical transport properties of a single junction were probed by fabricating electrodes (FIG. 6A and 6B) on two crossed NWs degenerately- doped at an encoded P doping level of 2.5 x 10 20 cm "3 .
  • the l-V curve (FIG. 6C) collected using a four-point-probe configuration is linear and yields a junction resistance of 65 ⁇ 1 0 k .. Table 1 provides details of the resistance measurements.
  • the junction resistance, R was calculated from:
  • R sxp is the measured resistance between contacts 2 and 3 as measured by the four-point probe configuration in Figure 4
  • i 2 is the distance from contact 2 to the junction
  • 3 is the distance from contact 3 to the junction
  • r i 2 is the radius of the NW with contacts 1 and 2
  • r 3 4 is the radius of the NW with contacts 3 and 4.
  • Radius and segment lengths were determined from SEM images. The resistivity p was determined from a four-point probe measurement (not shown) on a single NW taken from the same growth substrate as the welded NW junction.
  • the resistivity value is in good agreement with prior measurements of the resistivity for NWs encoded at the same doping level, 44 and the value is consistent with an active doping level of about 4 x 1 0 19 cm "3 .
  • Table 1 summarizes all of the measured values for the NW device shown in FIGS. 6A and 6B.
  • junction resistance demonstrates that the welding process forms relatively low-resistance and Ohmic connections between NWs.
  • the resistance of the junction is approximately equal to the resistance associated with an about 30 ⁇ length of a NW 1 00 nm in diameter, using the measured NW resistivity of about 0.0018 ⁇ -cm.
  • the ratio of junction resistance to wire resistance is comparable to the ratio observed in Ag NWs, and for lower Si doping levels and thus higher resistivity wires, the junction resistance is expected to be negligible compared to the NW resistance.
  • the material quality in the vicinity of a welded junction (FIG. 6D) was probed using ultrafast pump-probe optical microscopy with a time resolution of about 500 fs, an experiment that has been shown to directly probe interfacial charge carrier (electron and hole) recombination dynamics in single NWs.
  • a 425 nm pump pulse focused to a diffraction-limited spot photoexcites the NW at a specific spatial location, generating charge carriers that are probed by a time-delayed, spatially- overlapped probe pulse at 850 nm.
  • the individual optical images were generated by raster scanning the spatially-overlapped pump-probe pulses over the NW junction at a fixed pump-probe time delay and measuring the change in intensity, AI, of the probe beam.
  • the charge carriers induce an optical bleach (AI > 0) that decays in amplitude as the photogenerated carriers recombine on a time scale of tens to hundreds of picoseconds.
  • Kinetic traces collected at the center and four arms of the crossed junction (locations indicated by numbered circles) are displayed in FIG. 6F. The traces in the four arms are similar, giving rise to an average recombination time constant of 66 ⁇ 1 ps when fit to single exponential functions.
  • the kinetic trace in the junction produces a recombination time constant of 47 ⁇ 1 ps, which is about 29% shorter than the arms.
  • the small difference between the recombination time in the junction and arms indicates a marginal decrease in the material quality, which is consistent with a grain boundary between the two NWs that slightly increases charge-carrier recombination.
  • the combination of ultrafast microscopy data and electrical transport measurements confirm the high electrical and material quality of the welded junctions.
  • FIGS. 7A and 7B are cross-sectional SEM images of collapsed and welded NWs about 30 nm (FIG. 7A) and about 60 nm (FIG. 7B) in diameter.
  • the Si substrates contain a 200 nm layer of Ge and 600 nm layer of Si0 2 (scale bars, 5 ⁇ ).
  • the networks 202 formed are three-dimensional (FIG. 7A and 7B) with the effective thickness of the network 202 determined in some embodiments by the density or diameter, or combination of both, of the NWs.
  • the diameter of the NW can in some embodiments strongly influence the thickness of the 3D network 202, creating films of about 5 and about 10 ⁇ thick for NW diameters of 30 and 60 nm, respectively, as exemplified by the SEM images in FIG. 7A and 7B.
  • FIGS. 8A through 8C are schematic illustrations of the fabrication of flexible and conductive Si NW networks. More particularly, these figures are schematic illustrations of the NW-PDMS lift-off process, showing PDMS deposition on the growth wafer (FIG. 8A), wet-chemical etching of Ge (FIG. 8B), and lift off of the NW-PDMS film (FIG. 8C).
  • Large-area, flexible networks were created by depositing an about 200 nm thick sacrificial germanium (Ge) layer 308 on a growth wafer 50 306 prior to Au catalyst dispersal. This layer can be removed by wet-chemical etching 304 in hydrogen peroxide, releasing the network 302 from the substrate 306 to create a free-standing film 310.
  • Ge sacrificial germanium
  • the Ge layer 308 can be etched to release a flexible, free-standing NW-PDMS film 310.
  • the film can in some embodiments have high optical transparency, which matches finite-element optical simulations of the transmittance spectrum.
  • the transparency and color of the NW films can in some embodiments strongly depend on diameter-dependent Lorentz-Mie scattering, and optical tuning is possible simply by changing the diameters in the sample.
  • the electrical transport characteristics of the centimeter-scale NW networks or film 310 were probed before and after lift-off from the growth substrate.
  • Networks were constructed of 50 nm diameter n-type NWs with an encoded doping level of 2.5 x 1 0 20 cm "3 , and they were grown on both Si/Si0 2 substrates and, for lift off, Si/Si0 2 /Ge substrates.
  • FIG. 9 is a plot of the resistance multiplied by channel width as a function of electrode separation (i.e. channel length) for about 50 nm diameter NW networks measured on the Si growth substrate (squares) and on the substrate-free NW-PDMS film (triangles). Dashed lines represent linear fits to the data (dashed corresponds to the squares, dashed-dotted corresponds to the triangles), and the vertical offset of the dashed line reflects a contact resistance of 30 ⁇ 13 kQ-cm for the NW-PDMS film. Inset: l-V curve measured on the Si growth substrate for an electrode separation of 1 .5 mm. The substrate-free NW-PDMS film showed only a slight increase in resistance compared to networks on the substrate.
  • the approximate sheet resistance values of the two networks are 170 ⁇ 1 1 and 1 64 ⁇ 29 kQ/square for the on-substrate (square) and substrate-free (triangles) films, respectively, showing no significant difference as a result of the lift-off process.
  • the sheet resistances of the two films are the same.
  • the fits yielded contact resistances from the y-intercepts of 2.2 ⁇ 4.4 kQ-cm and 30 ⁇ 13 kQ-cm for the on- substrate and substrate-free films, respectively.
  • the measurements yield contact resistances of 1 .4 ⁇ 2.9 kQ and 39 ⁇ 1 7 kQ for the on-substrate and substrate-free films, respectively.
  • the contact resistance is thus zero within error for the on-substrate film but considerable for the substrate-free NW- PDMS film.
  • the l-V curves of the films are linear over a broad voltage range (inset), demonstrating the high-quality of the Ohmic connections between the NWs.
  • Figure 1 0 is a plot of the /-Vdata for the NW-PDMS film when straight and in a bent conformation with a radius of curvature of about 4 mm.
  • the performance of NW-PDMS films under strain was probed by bending the films.
  • I-V data show a small, less than 50% increase in resistance under strain when measured across a 6 mm channel, demonstrating the mechanical robustness of the electrical conductivity through the network. This behavior is consistent with flexibility observed in Ag NW networks.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Silicon Compounds (AREA)

Abstract

Procédés et systèmes de soudage par capillarité de nanofils semi-conducteurs pour réseaux tridimensionnels flexibles avec interconnexions ohmiques. Des procédés de synthèse de connexions électriques entre des nanofils semi-conducteurs par soudage induit par capillarité peuvent consister à créer ou à fournir des nanofils, à aligner les nanofils pour produire des points de contact entre nanofils, et à souder les nanofils ensemble au niveau des points de contact entre nanofils sur chaque nanofil par diffusion de surface par capillarité. L'invention porte également sur des films minces de nanofils conducteurs et flexibles qui ont des jonctions ohmiques. L'invention porte également sur des matériaux de film de nanofil tridimensionnel, comprenant une pluralité de nanofils se chevauchant selon une orientation aléatoire et soudés ensemble pour former des jonctions ohmiques.
PCT/US2017/040362 2016-06-30 2017-06-30 Procédés et systèmes de soudage de nanofils semi-conducteurs WO2018006010A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662357071P 2016-06-30 2016-06-30
US62/357,071 2016-06-30

Publications (1)

Publication Number Publication Date
WO2018006010A1 true WO2018006010A1 (fr) 2018-01-04

Family

ID=60787644

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/040362 WO2018006010A1 (fr) 2016-06-30 2017-06-30 Procédés et systèmes de soudage de nanofils semi-conducteurs

Country Status (1)

Country Link
WO (1) WO2018006010A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111092155A (zh) * 2019-10-28 2020-05-01 温州大学 含金属纳米粒子单壁碳纳米管分子内结及其制备方法和应用

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060079455A1 (en) * 2003-01-07 2006-04-13 Ramot At Tel Aviv University Ltd. Peptide nanostructures encapsulating a foreign material and method of manufacturing same
US20100193768A1 (en) * 2005-06-20 2010-08-05 Illuminex Corporation Semiconducting nanowire arrays for photovoltaic applications
US20160027846A1 (en) * 2013-04-05 2016-01-28 President And Fellow Of Harvard College Three-dimensional networks comprising nanoelectronics

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060079455A1 (en) * 2003-01-07 2006-04-13 Ramot At Tel Aviv University Ltd. Peptide nanostructures encapsulating a foreign material and method of manufacturing same
US20100193768A1 (en) * 2005-06-20 2010-08-05 Illuminex Corporation Semiconducting nanowire arrays for photovoltaic applications
US20160027846A1 (en) * 2013-04-05 2016-01-28 President And Fellow Of Harvard College Three-dimensional networks comprising nanoelectronics

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ZHIYONG GU ET AL.: "Reflow and Electrical Characteristics of Nanoscale Solder", vol. 2, 2006, pages 225 - 229, XP055450770 *
ZHIYONG GU ET AL.: "Three-Dimensional Electrically Interconnected Nanowire Networks Formed by Diffusion Bonding", LANGMUIR, vol. 23, no. 3, 2007, pages 979 - 982, XP002547983 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111092155A (zh) * 2019-10-28 2020-05-01 温州大学 含金属纳米粒子单壁碳纳米管分子内结及其制备方法和应用
CN111092155B (zh) * 2019-10-28 2023-01-17 温州大学 含金属纳米粒子单壁碳纳米管分子内结及其制备方法和应用

Similar Documents

Publication Publication Date Title
Pudasaini et al. High efficiency hybrid silicon nanopillar–polymer solar cells
Lin et al. Graphene/semiconductor heterojunction solar cells with modulated antireflection and graphene work function
US20090050204A1 (en) Photovoltaic device using nanostructured material
Yu et al. Bismuth-catalyzed and doped silicon nanowires for one-pump-down fabrication of radial junction solar cells
US8747942B2 (en) Carbon nanotube-based solar cells
Zhang et al. Large-scale fabrication of silicon nanowires for solar energy applications
FR2937055A1 (fr) Procede de fabrication a basse temperature de nanofils semiconducteurs a croissance laterale et transistors a base de nanofils, obtenus par ce procede
Baek et al. Preparation of hybrid silicon wire and planar solar cells having ZnO antireflection coating by all-solution processes
Nalamati et al. Hybrid GaAsSb/GaAs heterostructure core–shell nanowire/graphene and photodetector applications
KR101142545B1 (ko) 태양전지 및 그 제조 방법
US20110240099A1 (en) Photovoltaic nanowire device
JP2006261666A (ja) 高効率無機ナノロッド強化光起電素子
Hong et al. Nanostructuring methods for enhancing light absorption rate of Si-based photovoltaic devices: A review
KR20110099005A (ko) 기판 표면상의 나노와이어, 이의 제조방법 및 그 사용
Wu et al. Direct synthesis of high-density lead sulfide nanowires on metal thin films towards efficient infrared light conversion
EP2686888B1 (fr) Dispositif à base de nano/microfils stabilisé mécaniquement et aux propriétés optiques améliorées et son procédé de réalisation.
Zhang et al. Advanced radial junction thin film photovoltaics and detectors built on standing silicon nanowires
Ahmed et al. Development of silicon nanowires with optimized characteristics and fabrication of radial junction solar cells with< 100 nm amorphous silicon absorber layer
KR101100414B1 (ko) 태양전지 및 그 제조 방법
EP2243169A2 (fr) Structures composites à base de nanobarres pour la production d&#39;électricité
Feng et al. Intact Vertical 3D–0D–2D Carbon‐Based p–n Junctions for Use in High‐Performance Photodetectors
Abrand et al. Localized self-assembly of InAs nanowire arrays on reusable Si substrates for substrate-free optoelectronics
WO2018006010A1 (fr) Procédés et systèmes de soudage de nanofils semi-conducteurs
Murthy et al. Efficient photogeneration of charge carriers in silicon nanowires with a radial doping gradient
Iyer et al. GaAs 1-x Sb x nanowires on a graphitic substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17821389

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 24/06/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17821389

Country of ref document: EP

Kind code of ref document: A1