WO2018001277A1 - 一种系统级芯片和终端 - Google Patents

一种系统级芯片和终端 Download PDF

Info

Publication number
WO2018001277A1
WO2018001277A1 PCT/CN2017/090591 CN2017090591W WO2018001277A1 WO 2018001277 A1 WO2018001277 A1 WO 2018001277A1 CN 2017090591 W CN2017090591 W CN 2017090591W WO 2018001277 A1 WO2018001277 A1 WO 2018001277A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus interface
scenario
security
soc
data
Prior art date
Application number
PCT/CN2017/090591
Other languages
English (en)
French (fr)
Inventor
潘时林
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to KR1020197001334A priority Critical patent/KR20190018506A/ko
Priority to JP2018566878A priority patent/JP2019520653A/ja
Priority to EP17819274.6A priority patent/EP3467667B1/en
Publication of WO2018001277A1 publication Critical patent/WO2018001277A1/zh
Priority to US16/234,980 priority patent/US20190138702A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
    • G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/38—Payment protocols; Details thereof
    • G06Q20/40—Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check credit lines or negative lists
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/321—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices using wearable devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/326—Payment applications installed on the mobile devices

Definitions

  • the present application relates to the field of information technology, and more particularly, to a system on chip (SOC) and a terminal.
  • SOC system on chip
  • Mobile payment also known as mobile payment, refers to a service that allows mobile users to use their mobile terminals (usually mobile phones) to pay for goods or services they consume.
  • mobile terminals usually mobile phones
  • An all-in-one solution is implemented by an embedded Secure Element (eSE).
  • the eSE is also called an external security component. It is a combination of a Secure Element (SE) chip on a mobile phone product board to complete financial and other application services.
  • SE Secure Element
  • the all-terminal solution is that the mobile phone and the Point of Sales (POS) machine perform contactless card swiping, and NFC and SE (pre-bank application and data) work together to complete the payment transaction.
  • POS Point of Sales
  • the touch screen is the only device that allows users to easily enter passwords or other data.
  • the data input by the user to the touch screen is not a truly secure input.
  • the input touch points and the data of the screen are theoretically intercepted by malicious applications. To obtain security sensitive data such as the user's bank password.
  • the SOC chip and the touch screen are directly connected through an Inter-Integrated Circuit (I2C) or other bus, and the input touch screen data and the displayed position data are firstly on the SOC.
  • I2C Inter-Integrated Circuit
  • the Application Processor (AP) knows that the security level is low.
  • the embodiment of the present application provides a system-level chip and a terminal, which can improve the security of the input.
  • a system-on-chip SOC including: a bus interface integrated in the SOC, a secure element SE, and a first component; the bus interface for connecting an input/output I/O device; the SE, For accessing the I/O device through the bus interface, acquiring the first data input by the I/O device, performing security processing on the first data, and controlling the first component in a common scenario.
  • the access to the I/O device wherein the security scenario represents a scenario that requires secure input, the common scenario represents a scenario that does not require secure input; the first component is used to control by the SE, in the normal scenario Obtaining the second data input by the I/O device.
  • the SE can directly access the bus interface, so that the input data in the security scenario is directly obtained by the SE and does not pass through the first component, thereby improving the security of the input.
  • the SE is further configured to control the I/O device to display a data input interface in the security scenario.
  • the SE is also used to send the securely processed data to the server.
  • the SE displays an interface for inputting a password to the user through the bus interface; the user inputs a password on the interface; the SE acquires the password data input by the user through the bus interface, and encrypts the password data with the PIN key saved in the SE.
  • the encrypted data is sent to the verification server of the financial industry for verification, which can improve the security of payment.
  • the SE is further configured to determine, according to an application currently accessing the I/O device, that the current application environment is the security scenario or the common scenario.
  • the SE is configured to access the I/O device through the bus interface, acquire the second data, and send the second data to the first component in the normal scenario.
  • the bus interface is disposed in the SE.
  • the bus interface is controlled by system software running in the SE.
  • the SE is configured to configure the access mode of the bus interface to be only the SE access in the security scenario, and the access mode of the bus interface is configured to be accessed by the first component in the normal scenario.
  • the SE can configure an access mode of the bus interface, and the first component cannot configure an access mode of the bus interface.
  • the access mode of the bus interface includes only the SE access and access by the first component.
  • the bus interface includes a first bus interface and a second bus interface; the SE is configured to control the second bus interface to connect with the I/O device in the security scenario, and pass the first The second bus interface accesses the I/O device; in the non-secure scenario, the first bus interface is controlled to be connected to the I/O device such that the first component accesses the I/O device through the first bus interface.
  • the SOC further includes a multiplexer; the SE is configured to control the multiplexer switch in the security scenario, so that the second bus interface is connected to the I/O device in the common scenario.
  • the multiplexer switch is controlled such that the first bus interface is connected to the I/O device.
  • the multiplexer is disposed in the SE.
  • the second bus interface is disposed in the SE.
  • the SE is further configured to send a security indication to the user when determining to enter the security scenario.
  • the SE may determine that a security input is required for the application in the SE according to an application that needs to be input, that is, determine to enter the security scenario.
  • the SE is specifically configured to control the lighting of the security indicator when determining to enter the security scenario.
  • the I/O device includes a data acquisition sensor, a touch screen, or a display.
  • the bus interface includes an inter-integrated circuit bus I2C interface or a mobile industry processor interface MIPI.
  • the first component comprises an application processor, a processor core in a trusted environment TEE, a digital signal processor, or an application specific integrated circuit.
  • the SOC of the embodiment of the present application can achieve SE level security.
  • the mobile phone or other mobile terminal open platform adopting the SOC of the embodiment of the present application has the security input capability of the POS machine, in other words, the mobile phone or other mobile terminal device may have the POS function.
  • a terminal comprising the SOC of the first aspect or any of the possible implementations of the first aspect, and an I/O device.
  • FIG. 1a is an application architecture diagram of an embodiment of the present application.
  • FIG. 1b is a schematic block diagram of an SOC of an embodiment of the present application.
  • FIG. 2 is a schematic block diagram of an SOC of another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an SOC according to still another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an SOC according to still another embodiment of the present application.
  • FIG. 5 is a schematic block diagram of a SOC of still another embodiment of the present application.
  • FIG. 6a is a schematic structural diagram of a SOC according to still another embodiment of the present application.
  • FIG. 6b is a schematic structural diagram of an SOC according to still another embodiment of the present application.
  • FIG. 7 is a schematic block diagram of a terminal according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a terminal according to another embodiment of the present application.
  • the SOC chip of the embodiment of the present application can be applied to a terminal (for example, a mobile phone) supporting mobile payment for improving the security of input or output of the terminal.
  • a terminal for example, a mobile phone
  • the Secure Element is a tamper-proof chip that ensures that data is stored in a safe place and that the information is only open to authorized applications and personnel. It is similar to the user's personal and device. Its own identity card. For example, in secure payment, the SE stores the bank's applications and data.
  • eSE embedded Secure Element
  • eSEs also known as external SEs
  • eSE can be more convenient and secure to implement management and control of financial applications in mobile payment products.
  • the SE is built in the SOC chip, which is called an integrated secure element (inSE), that is, the SE subsystem is integrated in the SOC instead of the embedded SE (eSE).
  • inSE can also be expressed as In-SOC SE.
  • the SE may include at least one processor for performing various operations of the SE, such as data access, data processing, control, etc., to implement the corresponding SE in the embodiment of the present application.
  • the SE may further include: a memory for storing data or instructions, and the like; and a communication interface for communicating with other components. It should be understood that the above is only a specific implementation form of the SE, which is not limited in this application. That is to say, the SE may also adopt other possible implementation forms that can implement the corresponding functions of the SE in the embodiment of the present application.
  • the first component is a processing component other than the SE in the chip, for example, the first component may be an application processor, or a processor running in a Trust Execute Environment (TEE). Core, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), etc.
  • TEE Trust Execute Environment
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FIG. 1a is an application architecture diagram of an embodiment of the present application.
  • the SE is integrated in the SOC chip instead of using the eSE.
  • the processing elements other than SE in the SOC chip are referred to as first elements.
  • the processor and the memory are illustrated in Figure 1a, but this application is not limited thereto. That is, more or fewer components or modules may be included in the SE and the first component, ie the number and type of components or modules therein may be set according to actual needs.
  • the bus interface that interfaces with an input/output (I/O) device is set in the SE or controlled by the SE, thereby Can achieve true SE level security.
  • I/O input/output
  • FIG. 1b shows a schematic block diagram of a SOC 100 in accordance with an embodiment of the present application.
  • the SOC 100 includes a bus interface 110, an SE 120, and a first component 130 integrated within the SOC 100.
  • the SE 120 is integrated in the SOC 100.
  • the tamper-resistant data is stored in the SE 120.
  • the SE stores the bank's application and data, such as a Personal Identification Number (PIN) key.
  • PIN Personal Identification Number
  • the bus interface 110 is used to connect I/O devices.
  • the I/O device is a terminal input/output device, for example, the I/O device can be a data acquisition sensor, a touch screen or a display.
  • the data acquisition sensor is a sensor having a data acquisition function, and includes a sensor that collects data through an interactive manner such as a body sense, an iris, and an electroencephalogram, such as a touch sensor.
  • the touch screen may include a touch sensor and a liquid crystal display (LCD).
  • LCD liquid crystal display
  • the display may include an LCD, an Organic Light-Emitting Diode (OLED) screen, an electronic ink screen, a Plasma Display Panel (PDP), and the like.
  • LCD Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • PDP Plasma Display Panel
  • the bus interface 110 can be an I2C interface, a Mobile Industry Processor Interface (MIPI) or other bus interface that can be connected to an I/O device.
  • MIPI Mobile Industry Processor Interface
  • I/O device and the bus interface 110 is only for the purpose of helping the person skilled in the art to better understand the embodiments of the present application, and does not limit the scope of the embodiments of the present application.
  • an I/O device is used as a touch sensor
  • a bus interface 110 is an I2C interface as an example.
  • the SE 120 is configured to access the I/O device through the bus interface 110 in a security scenario, acquire the first data input by the I/O device, perform security processing on the first data, and control the first component 130 to be in a normal scenario. Access to I/O devices.
  • a security scenario indicates a scenario that requires secure input, such as a scenario that requires secure input and display during secure payment; a normal scenario represents a scenario that does not require secure input.
  • the SE 120 may determine that the current application environment is a security scenario or a common scenario according to an application that currently accesses the I/O device. For example, an application that needs to input data of the I/O device is an application in the SE 120, and the SE 120 can determine that a security input is required, that is, the current application environment is a security scenario, otherwise it is a normal scenario.
  • the SE 120 accesses the I/O device through the bus interface 110 in a security scenario, that is, the SE 120 can directly access the bus interface 110 in a security scenario, thereby accessing the I/O device and acquiring the I/O.
  • the first data does not pass through the first component 130, thereby improving the security of the input in a security scenario.
  • the SE 120 is further configured to control the I/O device to display a data input interface in a security scenario.
  • the SE 120 determines that a security input is required for an application in the SE 120 according to an application that is currently required to be input, and the SE 120 accesses the I/O device through the bus interface 110, and first outputs a display interface to the user; The user inputs the first data according to the display interface; the SE 120 acquires the first data input by the user through the bus interface 110.
  • the SE 120 is further configured to perform security processing on the first data, and send the security processed data to the verification server.
  • the SE 120 displays an interface for inputting a password to the user through the bus interface 110; the user inputs a password at the interface; the SE 120 acquires the password data input by the user through the bus interface 110, and uses the PIN key saved in the SE 120.
  • the password data is encrypted, and the encrypted data is sent to the verification server of the financial industry for verification, which can improve the security of payment.
  • operations such as data access, data processing, and control may be implemented by a processor in the SE, and data transmission may be implemented through a communication interface in the SE, but the present application does not limit this. .
  • the first component 130 is configured to acquire the second data input by the I/O device in a normal scenario by the control of the SE 120.
  • the first component 130 can acquire the second data input by the I/O device under the control of the SE 120.
  • the location and connection relationship between the SE 120 and the bus interface 110 may be in various manners. Accordingly, the SE 120 may have multiple control modes, which are separately described below.
  • the SE 120 accesses the I/O device through the bus interface 110 in a common scenario, acquires the second data, and sends the second data to the first component 130.
  • the SE 120 can directly access the bus interface 110, while the first component 130 cannot directly access the bus interface 110.
  • the bus interface 110 is disposed in the SE 120. Since the SE 120 is integrated within the SOC 100, the performance and delay response of the SE 120 can be better.
  • the bus interface 110 is placed directly into the integrated SE 120 and is controlled by the SE 120 (e.g., system software running in the SE 120).
  • access to the bus interface 110 by the first component 130 is forwarded by the SE 120 for a normal scenario, ie, a scenario that does not require secure input.
  • a security scenario that is, a scenario requiring secure input
  • the SE 120 no longer forwards data, that is, only the SE 120 can acquire data input by the user through the bus interface 110, thereby improving the security of the input.
  • the SE 120 may also send a security indication to the user when determining to enter the security scenario.
  • the control lights the security indicator and the user is prompted to enter the security scene by illuminating the security indicator.
  • the SE 120 determines that a security input is required for the application in the SE 120 according to the application currently required to be input, that is, determines to enter the security scenario.
  • FIG. 3 is an example of a SOC of an embodiment of the present application.
  • the I2C interface 310 is disposed in the SE 320.
  • the SE 320 corresponds to the foregoing SE 120.
  • the SE 320 may specifically include a processor 321 for performing various operations of the SE 320, a memory 322, a General Purpose Input Output (GPIO) 323, etc., and the GPIO 323 is connected securely.
  • Indicator light 340 It should be understood that other modules may be included in the SE 320, and the number and types of the modules in the SE 320 may be set according to actual needs, which is not limited in this application.
  • the AP 330 corresponds to the front
  • the first component 130, the AP 330 may specifically include a processor 331, a memory 332, and the like. It should be understood that other modules may be included in the AP 330, and the number and types of the modules in the AP 330 may be set according to actual needs, which is not limited in this application.
  • the I2C interface 310 is connected to the touch sensor 350, and the MIPI 360 is connected to the LCD 370.
  • the message and data of the touch sensor 350 are forwarded by the SE 320's Chip Operation System (COS) (for example, by mailbox communication) to the primary AP 330; when the COS system software determines that security input is required
  • COS Chip Operation System
  • the security indicator 340 is illuminated (or other security indication that can notify the user, the application is not limited to the security indicator)
  • the message and data of the touch sensor 350 are no longer forwarded to the primary AP 330 until the user input is completed.
  • the I2C interface 310 is set in the SE 320 and the MIPI 360 is not in the SE 320. It should be understood that the MIPI 360 of the docking LCD 370 can also be placed in the SE 320. In other words, the I2C interface 310 and the MIPI 360 can both be disposed in the SE 320, which is not limited in this application.
  • the SE 120 configures the access mode of the bus interface 110 to be only the SE 120 access in the security scenario, and configures the access mode of the bus interface 110 to be accessed by the first component 130 in the normal scenario.
  • SE 120 can configure the access mode of bus interface 110, while first component 130 cannot configure the access mode of bus interface 110.
  • the access mode of the SE 120 configuration bus interface 110 is only SE120 access. In this scenario, only the SE 120 accesses the bus interface 110, the first component 130 cannot access the bus interface 110; when exiting the security scenario, the SE 120 is configured.
  • the access mode of the bus interface 110 is accessed by the first component 130, in which case the first component 130 can access the bus interface 110.
  • the SE 120 may also send a security indication to the user when determining to enter the security scenario.
  • the control lights the security indicator and the user is prompted to enter the security scene by illuminating the security indicator.
  • FIG. 4 is another example of a chip of an embodiment of the present application.
  • SE 420 configures the access mode of I2C interface 410.
  • the SE 420 corresponds to the foregoing SE 120.
  • the SE 420 may specifically include a processor 421 for performing various operations of the SE 420, a memory 422, a GPIO 423, etc., and the GPIO 423 is connected to the security indicator 440. It should be understood that other modules may be included in the SE 420, and the number and types of the modules in the SE 420 may be set according to actual needs, which is not limited in this application.
  • the AP 430 corresponds to the foregoing first component 130.
  • the AP 430 may specifically include a processor 431, a memory 432, and the like. It should be understood that other modules may be included in the AP 430, and the number and types of the modules in the AP 430 may be set according to actual needs, which is not limited in this application.
  • the I2C interface 410 is connected to the touch sensor 450, and the MIPI 460 is connected to the LCD 470.
  • the SE 420 configures the I2C interface 410 of the docked touch sensor 450 to be SE Access Only, that is, only the processor 421 of the SE 420 can access, and any other processor, such as the processor 431, cannot access.
  • the SE 420 can configure the I2C interface 410 to exit the SE Access Only mode.
  • the processor of the first component for example, the processor 431, can access the I2C interface 410.
  • SE 420 configures the access mode of I2C interface 410, and SE 420 does not configure the access mode of MIPI 460. It should be understood that the SE 420 can also configure the access mode of the MIPI 460. In other words, both the I2C interface 410 and the MIPI 460 can control the access mode by the SE 420, which is not limited in this application.
  • the bus interface 110 may include a first bus interface 111 and a second bus interface 112.
  • the SE 120 accesses the second bus interface 112.
  • the second bus interface 112 can be disposed in the SE 120.
  • the first component 130 accesses the first bus interface 111.
  • the SE 120 controls the second bus interface 112 to connect with the I/O device in a security scenario, and accesses the I/O device through the second bus interface 112; controls the first bus interface 111 and I in a normal scenario.
  • the /O device is connected such that the first component 130 accesses the I/O device through the first bus interface 111.
  • the pins of the docking I/O device are internally multiplexed, and the first bus interface 111 and the second bus interface 112 are respectively switched to be connected to the I/O device, wherein the switching is controlled by the SE 120.
  • the SE 120 controls the second bus interface 112 to connect with the I/O device in a security scenario, such that the SE 120 accesses the I/O device through the second bus interface 112; the SE 120 controls the first bus interface 111 in a normal scenario.
  • the I/O device is connected such that the first component 130 accesses the I/O device through the first bus interface 111.
  • switching can be accomplished by multiplexer 140.
  • the SE 120 controls the multiplexer 140 to switch in a security scenario such that the second bus interface 112 is connected to the I/O device, such that the SE 120 accesses the I/O device through the second bus interface 112; the SE 120 is in a normal scenario.
  • the lower control multiplexer 140 switches such that the first bus interface 111 is connected to the I/O device such that the first component 130 accesses the I/O device through the first bus interface 111.
  • the multiplexer 140 can be disposed in the SE 120.
  • the SE 120 may also send a security indication to the user when determining to enter the security scenario.
  • the control lights the security indicator and the user is prompted to enter the security scene by illuminating the security indicator.
  • Figure 6a is another example of a chip of an embodiment of the present application.
  • SE 620 controls multiplexer 680 to switch I2C interface 611 and I2C interface 612 to touch sensor 650, respectively.
  • the SE 620 corresponds to the foregoing SE 120.
  • the SE 620 may specifically include a processor 621 for performing various operations of the SE 620, a memory 622, a GPIO 623, etc., and the GPIO 623 is connected to the security indicator 640.
  • the SE 620 can also control the multiplexer 680 via the GPIO 623.
  • the SE 620 can also control the multiplexer 680 by other means, such as by controlling the multiplexer 680 via the set register logic.
  • the AP 630 corresponds to the foregoing first component 130.
  • the AP 630 may specifically include a processor 631, a memory 632, and the like. It should be understood that other modules may be included in the AP 630, and the number and types of the modules in the AP 630 may be set according to actual needs, which is not limited in this application.
  • the MIPI 660 is connected to the LCD 670.
  • the SE 620 controls the multiplexer 680 to switch to the I2C interface 611 to connect with the touch sensor 650, and the data input by the user is directly sent to the I2C interface 611 for access by the AP 630; when the COS system software determines that it needs to be performed
  • the security indicator 640 is illuminated (or other safety indication that can notify the user, the application is not limited to the security indicator), and the control multiplexer 680 is switched to the I2C interface 612 to be connected to the touch sensor 650, and the I2C interface 611
  • the data of the touch sensor 650 can no longer be obtained until the user input is completed, and the user clicks OK to turn off the security indicator 640, and then the multiplexer 680 can be controlled to switch to the I2C interface 611 to connect with the touch sensor 650 to continue working.
  • MIPI 660 can also be designed with a dual interface and controlled by the SE 620, which is not limited in this application.
  • Figure 6b is another example of a chip of an embodiment of the present application.
  • multiplexer 680 is placed in SE 620 and is directly controlled by SE 620.
  • the specific working process of the chip in FIG. 6b is similar to that of FIG. 6a, and details are not described herein again.
  • the SE can directly access the bus interface, so that the input data in the security scenario is directly obtained by the SE, does not pass through the first component, and thus is not intercepted by the malicious application software, thereby being able to High input security.
  • the SOC of the embodiment of the present application can achieve SE level security.
  • the mobile phone or other mobile terminal open platform adopting the SOC of the embodiment of the present application has the security input capability of the POS machine, in other words, the mobile phone or other mobile terminal device may have the POS function.
  • FIG. 7 shows a schematic block diagram of a terminal 700 in accordance with an embodiment of the present application.
  • the terminal 700 may include the SOC 100 of the foregoing embodiment of the present application, and the I/O device 710.
  • the I/O device 710 may be the I/O device described in the foregoing embodiment of the present application.
  • the terminal 700 can support the mobile payment.
  • the SOC of the embodiment of the present application can implement the security of the SE level and has the security input capability of the POS machine, that is, can be used as a POS machine.
  • the terminal 700 may further include other components not shown in FIG. 7.
  • the terminal 700 when the terminal 700 is used as a mobile phone, the terminal 700 may further include a radio frequency (RF) circuit and the like. .
  • RF radio frequency
  • FIG. 8 shows a schematic structural diagram of a terminal 800 according to an embodiment of the present application.
  • terminal 800 can include a processor 810, an I/O device 820, a transceiver 830, and an antenna 840.
  • the processor 810 may be the SOC of the foregoing embodiment of the present application, and is not described herein for brevity.
  • the I/O device 820 can be the I/O device described in the foregoing embodiments of the present application.
  • Transceiver 830 communicates with other devices via antenna 840. It will be understood by those skilled in the art that the terminal structure shown in FIG. 8 does not constitute a limitation on the terminal, and the terminal may include more or less components than those illustrated, or combine some components, or split some components. Or different parts arrangement.
  • the disclosed apparatus may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, It can be stored on a computer readable storage medium. Based on such understanding, the technical solution of the present application may be in essence or part of the contribution to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

Abstract

一种系统级芯片SOC和终端。该SOC包括集成在该SOC内的总线接口(110)、安全元件SE(120)以及第一元件(130)；该总线接口(110)用于连接I/O设备(710)；该SE(120)用于在安全场景下通过该总线接口(110)访问该I/O设备(710)，获取该I/O设备(710)输入的第一数据，并对第一数据进行安全处理，以及控制该第一元件(130)在普通场景下对该I/O设备(710)的访问，其中，该安全场景表示需要安全输入的场景，该普通场景表示不需要安全输入的场景；该第一元件(130)用于通过该SE(120)的控制，在该普通场景下，获取该I/O设备(710)输入的第二数据。SOC和终端，能够提高输入的安全性。

Description

一种系统级芯片和终端
本申请要求于2016年7月1日提交中国专利局、申请号为201610512240.9、申请名称为“一种系统级芯片和终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信息技术领域，并且更具体地，涉及一种系统级芯片(System on Chip，SOC)和终端。
背景技术
手机支付也称为移动支付(Mobile Payment)，是指允许移动用户使用其移动终端(通常是手机)对所消费的商品或服务进行账务支付的一种服务方式。手机实现移动支付目前主要有三种方式，分别是通过安全数字(Secure Digital，SD)卡，通过客户识别模块(Subscriber Identity Module，SIM)卡，或通过近场通信(Near Field Communication，NFC)和嵌入式安全元件(embedded Secure Element，eSE)的全终端方案来实现。eSE也称为外置安全元件，是将安全元件(Secure Element，SE)芯片组合到手机产品板上，完成金融等应用服务。全终端方案是手机与销售点(Point of Sales，POS)机进行非接触式刷卡，NFC和SE(预置银行的应用以及数据)共同作用，完成支付交易。
当前智能机，触摸屏是唯一可以让用户便捷的输入密码或其他数据的装置，然而用户输入到触摸屏的数据并不是真正安全的输入，输入的触摸点以及屏幕的数据理论上存在被恶意应用软件截获，从而获得用户的银行密码等安全敏感数据。
对于目前的SD卡，SIM卡以及eSE的方案，SOC芯片与触摸屏通过集成电路间总线(Inter－Integrated Circuit，I2C)或者其他总线直接连接，输入的触摸屏数据和显示的位置数据都先由SOC上的应用处理器(Application Processor，AP)获知，安全性级别较低。
申请内容
本申请实施例提供了一种系统级芯片和终端，能够提高输入的安全性。
第一方面，提供了一种系统级芯片SOC，包括：集成在该SOC内的总线接口、安全元件SE以及第一元件；该总线接口，用于连接输入/输出I/O设备；该SE，用于在安全场景下，通过该总线接口访问该I/O设备，获取该I/O设备输入的第一数据，并对该第一数据进行安全处理，以及控制该第一元件在普通场景下对该I/O设备的访问，其中，该安全场景表示需要安全输入的场景，该普通场景表示不需要安全输入的场景；该第一元件，用于通过该SE的控制，在该普通场景下，获取该该I/O设备输入的第二数据。
本申请实施例的SOC中，SE可以直接访问总线接口，这样，安全场景下的输入数据直接由SE获得，不会通过第一元件，从而能够提高输入的安全性。
在一些可能的实现方式中，该SE还用于在该安全场景下，控制该I/O设备显示数据输入界面。
在一些可能的实现方式中，该SE还用于将安全处理后的数据发送给服务器。
例如，在安全支付时，SE通过总线接口向用户显示输入密码的界面；用户在此界面输入密码；SE通过总线接口获取用户输入的密码数据，并用SE中保存的PIN密钥对密码数据进行加密，将加密后的数据发送给金融行业的校验服务器进行校验，这样能够提高支付的安全性。
在一些可能的实现方式中，该SE还用于根据当前访问所述I/O设备的应用，确定当前的应用环境为该安全场景或该普通场景。
在一些可能的实现方式中，该SE用于在该普通场景下，通过该总线接口访问该I/O设备，获取该第二数据，并将该第二数据发送给该第一元件。
在一些可能的实现方式中，该总线接口设置于该SE中。
在一些可能的实现方式中，该总线接口由运行在该SE中的系统软件控制。
在一些可能的实现方式中，该SE用于在该安全场景下配置该总线接口的访问模式为仅该SE访问，在该普通场景下配置该总线接口的访问模式为该第一元件访问。
在一些可能的实现方式中，该SE可以配置该总线接口的访问模式，该第一元件不能配置总线接口的访问模式。
该总线接口的访问模式包括仅该SE访问和该第一元件访问。
在一些可能的实现方式中，该总线接口包括第一总线接口和第二总线接口；该SE用于，在该安全场景下控制该第二总线接口与该I/O设备连接，并通过该第二总线接口访问该I/O设备；在该非安全场景下控制该第一总线接口与该I/O设备连接，以使该第一元件通过该第一总线接口访问该I/O设备。
在一些可能的实现方式中，该SOC还包括多路开关；该SE用于在该安全场景下控制该多路开关切换，使得该第二总线接口与该I/O设备连接，在该普通场景下控制该多路开关切换，使得该第一总线接口与该I/O设备连接。
在一些可能的实现方式中，该多路开关设置于该SE中。
在一些可能的实现方式中，该第二总线接口设置于该SE中。
在一些可能的实现方式中，该SE还用于在确定进入该安全场景时，向该用户发送安全指示。
在一些可能的实现方式中，该SE可以根据当前需要输入的应用为该SE中的应用确定需要安全输入，即确定进入该安全场景。
在一些可能的实现方式中，该SE具体用于在确定进入该安全场景时，控制点亮安全指示灯。
在一些可能的实现方式中，该I/O设备包括数据采集传感器、触摸屏或显示器。
在一些可能的实现方式中，该总线接口包括集成电路间总线I2C接口或移动产业处理器接口MIPI。
在一些可能的实现方式中，该第一元件包括应用处理器、可信环境TEE中的处理器核、数字信号处理器或专用集成电路。
本申请实施例的SOC能够实现SE级别的安全。
采用本申请实施例的SOC的手机或其他移动终端开放平台具有POS机的安全输入能力，换言之，手机或其他移动终端设备可以具有POS机功能。
第二方面，提供了一种终端，该终端包括第一方面或第一方面的任一种可能的实现方式中的SOC，以及I/O设备。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a是本申请实施例的一个应用架构图。
图1b是本申请一个实施例的SOC的示意性框图。
图2是本申请另一实施例的SOC的示意性框图。
图3是本申请又一实施例的SOC的示意性结构图。
图4是本申请又一实施例的SOC的示意性结构图。
图5是本申请又一实施例的SOC的示意性框图。
图6a是本申请又一实施例的SOC的示意性结构图。
图6b是本申请又一实施例的SOC的示意性结构图。
图7是本申请一个实施例的终端的示意性框图。
图8是本申请另一实施例的终端的示意性结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请的一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都应属于本申请保护的范围。
本申请实施例的SOC芯片可以应用于支持移动支付的终端(例如手机)中，用于提高终端的输入或输出的安全性。
为了便于理解本申请实施例的技术方案，下面首先对本申请实施例中的相关术语进行说明。
现有技术中，安全元件(Secure Element，SE)为一种防篡改的芯片，它能确保数据存储在安全的地方，且信息仅对经授权的应用程序和人员开放，它类似用户个人和设备本身的身份证。例如，在安全支付时，SE中存储银行的应用以及数据。
移动支付产品经过多种形态的迭代，手机、可穿戴设备等产品逐步成为实现移动支付的主流应用承载对象，其易用性、安全性、可携带性、交互界面等方面相较传统方式有着较大优势。目前这些产品的金融功能都基于一个核心组件——嵌入式安全元件(embedded Secure Element，eSE)。eSE也称为外置SE，其大小不一，设计也可不同，并可嵌入在任意一种移动设备中。eSE可以较为方便安全的实现在移动支付产品中对金融应用的管理和控制。
在本申请实施例中，在SOC芯片中内置SE，称为集成安全元件(integrated Secure Element，inSE)，也就是说，在SOC中集成SE子系统，而不是采用嵌入式SE(eSE)。inSE也可以表示为In-SOC SE。
在本申请实施例中，可选地，SE可以包括至少一个处理器，用于执行SE的各种操作，例如，数据访问、数据处理、控制等操作，以实现本申请实施例中SE的相应功能。 可选地，SE中还可以包括：存储器，用于存储数据或指令等；通信接口，用于与其他部件之间进行通信。应理解，以上只是SE的一种具体实现形式，本申请对此并不限定，也就是说，SE还可以采用其他可能的可以实现本申请实施例中SE的相应功能的实现形式。
在本申请实施例中，第一元件为芯片中除SE之外的处理元件，例如，第一元件可以为应用处理器，或者，在可信环境(Trust Execute Environment，TEE)中运行的处理器核，数字信号处理器(Digital Signal Processor，DSP)，专用集成电路(Application Specific Integrated Circuit，ASIC)等。
图1a是本申请实施例的一个应用架构图。如图1a所示，在本申请实施例中，在SOC芯片中集成SE，而不是采用eSE。SOC芯片中除SE之外的处理元件称为第一元件。对于SE和第一元件，图1a中以处理器和存储器示例，但本申请对此并不限定。也就是说，SE和第一元件中可以包括更多或更少的部件或模块，即其中的部件或模块的数量和种类可以根据实际需要而设置。
本申请实施例在集成SE的SOC芯片中，将与输入/输出(input/output，I/O)设备(例如触摸传感器)对接的总线接口设置在SE中或由SE控制对其的访问，从而可以做到真正的SE级别的安全。
图1b示出了根据本申请实施例的SOC 100的示意性框图。如图1b所示，该SOC 100包括集成在该SOC 100内的总线接口110、SE 120和第一元件130。
在本申请实施例中，在SOC 100中集成SE 120。SE 120中存储防篡改的数据。例如，在安全支付时，SE中存储银行的应用以及数据，如个人身份号码(Personal Identification Number，PIN)密钥。
总线接口110用于连接I/O设备。I/O设备为终端的输入/输出设备，例如，I/O设备可以为数据采集传感器、触摸屏或显示器。
数据采集传感器为具有数据采集功能的传感器(sensor)，包括通过体感、虹膜、脑电波等交互方式进行数据的采集的传感器，例如触控传感器。
触摸屏可以包括触控传感器和液晶显示器(Liquid Crystal Display，LCD)。
显示器可以包括LCD、有机发光二极管(Organic Light-Emitting Diode，OLED)屏、电子墨水屏、等离子显示板(Plasma Display Panel，PDP)等。
总线接口110可以为I2C接口，移动产业处理器接口(Mobile Industry Processor Interface，MIPI)或者其他可以与I/O设备连接的总线接口。
应理解，上述对I/O设备和总线接口110的举例说明，只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围。以下为了描述方便，以I/O设备为触摸传感器，总线接口110为I2C接口为例进行说明。
SE 120用于在安全场景下，通过总线接口110访问I/O设备，获取I/O设备输入的第一数据，并对第一数据进行安全处理，以及控制第一元件130在普通场景下对I/O设备的访问。
安全场景表示需要安全输入的场景，例如在安全支付时需要安全输入和显示的场景；普通场景表示不需要安全输入的场景。
可选地，SE 120可以根据当前访问所述I/O设备的应用，确定当前的应用环境为安全场景或普通场景。例如，当前需要所述I/O设备输入数据的应用为SE 120中的应用，SE 120可以确定需要安全输入，即当前的应用环境为安全场景，否则为普通场景。
在本申请实施例中，SE 120在安全场景下通过总线接口110访问I/O设备，即SE 120可以在安全场景下直接对总线接口110进行访问，进而访问I/O设备，获取I/O设备输入的第一数据。该第一数据不会通过第一元件130，从而能够提高安全场景下输入的安全性。
可选地，SE 120还用于在安全场景下，控制I/O设备显示数据输入界面。
具体而言，在需要安全输入时，例如，SE 120根据当前需要输入的应用为SE 120中的应用确定需要安全输入，SE 120通过总线接口110访问I/O设备，先向用户输出显示界面；用户根据显示界面输入第一数据；SE 120再通过总线接口110获取用户输入的第一数据。
可选地，SE 120还用于对第一数据进行安全处理，并将安全处理后的数据发送给校验服务器。
例如，在安全支付时，SE 120通过总线接口110向用户显示输入密码的界面；用户在此界面输入密码；SE 120通过总线接口110获取用户输入的密码数据，并用SE 120中保存的PIN密钥对密码数据进行加密，将加密后的数据发送给金融行业的校验服务器进行校验，这样能够提高支付的安全性。
应理解，在本申请的各种实施例中，数据访问、数据处理、控制等操作可以通过SE中的处理器实现，数据发送可以通过SE中的通信接口实现，但本申请对此并不限定。
第一元件130用于通过SE 120的控制，在普通场景下，获取I/O设备输入的第二数据。
在普通场景下，即不需要安全输入的场景，第一元件130可以在SE 120的控制下，获取I/O设备输入的第二数据。
在本申请实施例中，SE 120与总线接口110的位置以及连接关系可以有多种方式，相应地，SE 120的控制方式也可以有多种，以下分别进行说明。
可选地，在本申请一个实施例中，SE 120在普通场景下，通过总线接口110访问I/O设备，获取该第二数据，并将该第二数据发送给第一元件130。
在本实施例中，SE 120可以直接访问总线接口110，而第一元件130不能直接访问总线接口110。例如，如图2所示，总线接口110设置于SE 120中。由于SOC 100内集成SE 120，SE 120的性能和延迟响应可以做到较好。直接将总线接口110放到集成的SE120中，由SE 120(例如，运行在SE 120中的系统软件)控制。在这种情况下，对于普通场景，即不需要安全输入的场景，第一元件130对总线接口110的访问通过SE 120转发。对于安全场景，即需要安全输入的场景，SE 120不再转发数据，即仅SE 120能够通过总线接口110获取用户输入的数据，从而提高输入的安全性。
可选地，SE 120还可以在确定进入安全场景时，向用户发送安全指示。例如，控制点亮安全指示灯，通过点亮安全指示灯通知用户进入安全场景。
例如，SE 120根据当前需要输入的应用为SE 120中的应用确定需要安全输入，即确定进入安全场景。
图3为本申请实施例的SOC的一个示例。如图3所示，I2C接口310设置于SE 320中。SE 320对应于前述SE 120，SE 320中具体可以包括处理器321，用于执行SE 320的各种操作，存储器322，通用输入/输出(General Purpose Input Output，GPIO)323等，GPIO 323连接安全指示灯340。应理解，SE 320中还可以包括其他模块，并且SE 320中模块的数量和种类可以根据实际需要而设置，本申请对此并不限定。AP 330对应于前 述第一元件130，AP 330中具体可以包括处理器331，存储器332等。应理解，AP 330中还可以包括其他模块，并且AP 330中模块的数量和种类可以根据实际需要而设置，本申请对此也不限定。
I2C接口310连接触摸传感器350，MIPI 360连接LCD 370。
当不是安全输入的场景时，触摸传感器350的消息和数据由SE 320的芯片操作系统(Chip Operation System，COS)转发(例如通过邮箱通信)给主AP 330；当COS系统软件判断需要进行安全输入时，点亮安全指示灯340(或其他可以通知用户的安全指示，本申请不限定为安全指示灯)，并不再将触摸传感器350的消息和数据转发给主AP 330，直到用户输入完成，用户点击确认(OK)，灭掉安全指示灯340后，方可继续转发给AP 330。
在图3中，I2C接口310设置于SE 320中，MIPI 360不在SE 320中。应理解，对接LCD 370的MIPI 360也可以放入SE 320中，换句话说，I2C接口310和MIPI 360可以都设置于SE 320中，本申请对此并不限定。
可选地，在本申请另一个实施例中，SE 120在安全场景下配置总线接口110的访问模式为仅SE 120访问，在普通场景下配置总线接口110的访问模式为第一元件130访问。
在本实施例中，SE 120可以配置总线接口110的访问模式，而第一元件130不能配置总线接口110的访问模式。在安全场景下SE 120配置总线接口110的访问模式为仅SE120访问，在此场景下，仅SE 120访问总线接口110，第一元件130不能访问总线接口110；当退出安全场景时，SE 120配置总线接口110的访问模式为第一元件130访问，在此场景下，第一元件130可以访问总线接口110。
可选地，SE 120还可以在确定进入安全场景时，向用户发送安全指示。例如，控制点亮安全指示灯，通过点亮安全指示灯通知用户进入安全场景。
例如，图4为本申请实施例的芯片的另一个示例。在图4中，SE 420配置I2C接口410的访问模式。SE 420对应于前述SE 120，SE 420中具体可以包括处理器421，用于执行SE 420的各种操作，存储器422，GPIO 423等，GPIO 423连接安全指示灯440。应理解，SE 420中还可以包括其他模块，并且SE 420中模块的数量和种类可以根据实际需要而设置，本申请对此并不限定。AP 430对应于前述第一元件130，AP 430中具体可以包括处理器431，存储器432等。应理解，AP 430中还可以包括其他模块，并且AP 430中模块的数量和种类可以根据实际需要而设置，本申请对此也不限定。
I2C接口410连接触摸传感器450，MIPI 460连接LCD 470。
安全场景下，SE 420将对接触摸传感器450的I2C接口410配置为仅SE访问(SE Access Only)，即仅SE 420的处理器421能够访问，其他任何处理器，例如处理器431，都不能访问；当退出安全场景时，只有SE 420能够配置将I2C接口410退出SE Access Only模式，退出后，第一元件的处理器，例如，处理器431，可以访问I2C接口410。
在图4中，SE 420配置I2C接口410的访问模式，SE 420不配置MIPI 460的访问模式。应理解，SE 420也可以配置MIPI 460的访问模式。换句话说，I2C接口410和MIPI460都可以由SE 420控制访问模式，本申请对此并不限定。
可选地，在本申请另一个实施例中，如图5所示，总线接口110可以包括第一总线接口111和第二总线接口112。
SE 120访问第二总线接口112。可选地，第二总线接口112可设置于SE 120中。
第一元件130访问第一总线接口111。
在这种情况下，SE 120在安全场景下控制第二总线接口112与I/O设备连接，并通过第二总线接口112访问I/O设备；在普通场景下控制第一总线接口111与I/O设备连接，以使第一元件130通过第一总线接口111访问I/O设备。
在本实施例中，对对接I/O设备的管脚进行内部复用，即可切换第一总线接口111和第二总线接口112分别与I/O设备连接，其中切换由SE 120控制。具体地，SE 120在安全场景下控制第二总线接口112与I/O设备连接，这样，SE 120通过第二总线接口112访问I/O设备；SE 120在普通场景下控制第一总线接口111与I/O设备连接，这样，第一元件130通过第一总线接口111访问I/O设备。
可选地，切换可以通过多路开关140实现。具体地，SE 120在安全场景下控制多路开关140切换，使得第二总线接口112与I/O设备连接，这样，SE 120通过第二总线接口112访问I/O设备；SE 120在普通场景下控制多路开关140切换，使得第一总线接口111与I/O设备连接，这样，第一元件130通过第一总线接口111访问I/O设备。
可选地，多路开关140可设置于SE 120中。
可选地，SE 120还可以在确定进入安全场景时，向用户发送安全指示。例如，控制点亮安全指示灯，通过点亮安全指示灯通知用户进入安全场景。
例如，图6a为本申请实施例的芯片的另一个示例。在图6a中，SE 620控制多路开关680以切换I2C接口611和I2C接口612分别与触摸传感器650连接。SE 620对应于前述SE 120，SE 620中具体可以包括处理器621，用于执行SE 620的各种操作，存储器622，GPIO 623等，GPIO 623连接安全指示灯640。可选地，SE 620还可以通过GPIO 623控制多路开关680。SE 620也可以通过其他方式控制多路开关680，例如通过设置的寄存器逻辑控制多路开关680。应理解，SE 620中还可以包括其他模块，并且SE 620中模块的数量和种类可以根据实际需要而设置，本申请对此并不限定。AP 630对应于前述第一元件130，AP 630中具体可以包括处理器631，存储器632等。应理解，AP 630中还可以包括其他模块，并且AP 630中模块的数量和种类可以根据实际需要而设置，本申请对此也不限定。
MIPI 660连接LCD 670。
当不是安全输入的场景时，SE 620控制多路开关680切换为I2C接口611与触摸传感器650连接，用户输入的数据直接送给I2C接口611，以便于AP 630访问；当COS系统软件判断需要进行安全输入时，点亮安全指示灯640(或其他可以通知用户的安全指示，本申请不限定为安全指示灯)，并控制多路开关680切换为I2C接口612与触摸传感器650连接，I2C接口611不再能获得触摸传感器650的数据，直到用户输入完成，用户点击OK，灭掉安全指示灯640后，方可控制多路开关680切换为I2C接口611与触摸传感器650连接以继续工作。
应理解，MIPI 660也可以采用双接口设计，并由SE 620控制切换，本申请对此并不限定。
图6b为本申请实施例的芯片的另一个示例。在图6b中，多路开关680设置于SE 620中，由SE 620直接控制。图6b中芯片的具体工作过程与图6a类似，在此不再赘述。
本申请实施例的SOC芯片中，SE可以直接访问总线接口，这样，安全场景下的输入数据直接由SE获得，不会通过第一元件，因此不会被恶意应用软件截获，从而能够提 高输入的安全性。
因此，本申请实施例的SOC能够实现SE级别的安全。采用本申请实施例的SOC的手机或其他移动终端开放平台具有POS机的安全输入能力，换言之，手机或其他移动终端设备可以具有POS机功能。
图7示出了根据本申请实施例的终端700的示意性框图。如图7所示，该终端700可以包括前述本申请实施例的SOC 100，以及I/O设备710，其中I/O设备710可以为前述本申请实施例中描述的I/O设备。
终端700可以支持移动支付，采用本申请实施例的SOC，能够实现SE级别的安全，具有POS机的安全输入能力，即可以作为POS机。
本领域技术人员可以理解，终端700还可以包括图7中未示出的其他部件，例如，终端700作为手机时还可以包括射频(Radio Frequency，RF)电路等部件，本申请对此并不限定。
例如，图8示出了根据本申请实施例的终端800的示意性结构图。如图8所示，终端800可以包括处理器810、I/O设备820、收发器830和天线840。处理器810可以为前述本申请实施例的SOC，为了简洁，在此不再赘述。I/O设备820可以为前述本申请实施例中描述的I/O设备。收发器830通过天线840实现与其他设备的通信。本领域技术人员可以理解，图8中示出的终端结构并不构成对终端的限定，终端可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。
应理解，以上描述中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时， 可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种系统级芯片SOC，其特征在于，包括集成在所述SOC内的总线接口、安全元件SE以及第一元件；
    所述总线接口，用于连接输入/输出I/O设备；
    所述SE，用于在安全场景下，通过所述总线接口访问所述I/O设备，获取所述I/O设备输入的第一数据，并对所述第一数据进行安全处理，以及控制所述第一元件在普通场景下对所述I/O设备的访问，其中，所述安全场景表示需要安全输入的场景，所述普通场景表示不需要安全输入的场景；
    所述第一元件，用于通过所述SE的控制，在所述普通场景下，获取所述I/O设备输入的第二数据。
  2. 根据权利要求1所述的SOC，其特征在于，所述SE还用于在所述安全场景下，控制所述I/O设备显示数据输入界面。
  3. 根据权利要求1或2所述的SOC，其特征在于，所述SE还用于将安全处理后的数据发送给服务器。
  4. 根据权利要求1至3中任一项所述的SOC，其特征在于，所述SE还用于根据当前访问所述I/O设备的应用，确定当前的应用环境为所述安全场景或所述普通场景。
  5. 根据权利要求1至4中任一项所述的SOC，其特征在于，所述SE用于在所述普通场景下，通过所述总线接口访问所述I/O设备，获取所述第二数据，并将所述第二数据发送给所述第一元件。
  6. 根据权利要求5所述的SOC，其特征在于，所述总线接口设置于所述SE中。
  7. 根据权利要求1至4中任一项所述的SOC，其特征在于，所述SE用于在所述安全场景下配置所述总线接口的访问模式为仅所述SE访问，在所述普通场景下配置所述总线接口的访问模式为所述第一元件访问。
  8. 根据权利要求1至4中任一项所述的SOC，其特征在于，所述总线接口包括第一总线接口和第二总线接口；
    所述SE用于，在所述安全场景下控制所述第二总线接口与所述I/O设备连接，并通过所述第二总线接口访问所述I/O设备；
    在所述非安全场景下控制所述第一总线接口与所述I/O设备连接，以使所述第一元件通过所述第一总线接口访问所述I/O设备。
  9. 根据权利要求8所述的SOC，其特征在于，所述SOC还包括多路开关；
    所述SE用于在所述安全场景下控制所述多路开关切换，使得所述第二总线接口与所述I/O设备连接，在所述普通场景下控制所述多路开关切换，使得所述第一总线接口与所述I/O设备连接。
  10. 根据权利要求9所述的SOC，其特征在于，所述多路开关设置于所述SE中。
  11. 根据权利要求8至10中任一项所述的SOC，其特征在于，所述第二总线接口设置于所述SE中。
  12. 根据权利要求1至11中任一项所述的SOC，其特征在于，所述SE还用于在确定进入所述安全场景时，向所述用户发送安全指示。
  13. 根据权利要求1至12中任一项所述的SOC，其特征在于，所述I/O设备包括数据采集传感器、触摸屏或显示器。
  14. 根据权利要求1至13中任一项所述的SOC，其特征在于，所述总线接口包括集成电路间总线I2C接口或移动产业处理器接口MIPI。
  15. 根据权利要求1至14中任一项所述的SOC，其特征在于，所述第一元件包括应用处理器、可信环境TEE中的处理器核、数字信号处理器或专用集成电路。
  16. 一种终端，其特征在于，包括根据权利要求1至15中任一项所述的系统级芯片SOC，以及输入/输出I/O设备。
PCT/CN2017/090591 2016-07-01 2017-06-28 一种系统级芯片和终端 WO2018001277A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020197001334A KR20190018506A (ko) 2016-07-01 2017-06-28 시스템 온 칩 및 단말기
JP2018566878A JP2019520653A (ja) 2016-07-01 2017-06-28 システムオンチップおよび端末
EP17819274.6A EP3467667B1 (en) 2016-07-01 2017-06-28 System-on-chip and terminal
US16/234,980 US20190138702A1 (en) 2016-07-01 2018-12-28 System on chip and terminal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610512240.9A CN107562689A (zh) 2016-07-01 2016-07-01 一种系统级芯片和终端
CN201610512240.9 2016-07-01

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/234,980 Continuation US20190138702A1 (en) 2016-07-01 2018-12-28 System on chip and terminal

Publications (1)

Publication Number Publication Date
WO2018001277A1 true WO2018001277A1 (zh) 2018-01-04

Family

ID=60785951

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/090591 WO2018001277A1 (zh) 2016-07-01 2017-06-28 一种系统级芯片和终端

Country Status (6)

Country Link
US (1) US20190138702A1 (zh)
EP (1) EP3467667B1 (zh)
JP (1) JP2019520653A (zh)
KR (1) KR20190018506A (zh)
CN (1) CN107562689A (zh)
WO (1) WO2018001277A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10775890B2 (en) 2017-09-27 2020-09-15 Apple Inc. Electronic device having a piezoelectric body for friction haptics
WO2019144267A1 (zh) * 2018-01-23 2019-08-01 深圳市大疆创新科技有限公司 芯片、处理器、计算机系统和可移动设备
CN109347791B (zh) * 2018-09-02 2021-04-20 黄策 双i/o总线sim卡
WO2020132962A1 (zh) * 2018-12-26 2020-07-02 华为技术有限公司 安全元件、数据处理装置及数据处理方法
CN110321317B (zh) * 2019-06-28 2021-10-01 兆讯恒达科技股份有限公司 一种多接口和多协处理器的芯片
WO2024069088A1 (fr) * 2022-09-30 2024-04-04 Ledger Smartphone intégrant un portefeuille matériel de stockage de clés cryptographiques mettant en œuvre un multiplexage logiciel de l'afficheur du smartphone
FR3140463A1 (fr) * 2022-09-30 2024-04-05 Ledger Smartphone intégrant un portefeuille matériel de stockage de clés cryptographiques mettant en œuvre un multiplexage matériel de l'afficheur du smartphone

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201917963U (zh) * 2010-12-21 2011-08-03 北京同方微电子有限公司 用于移动支付的安全终端装置
CN104471586A (zh) * 2012-07-13 2015-03-25 高通股份有限公司 用于将一部分安全单元组件集成在片上系统上的方法和装置
US20150186879A1 (en) * 2012-10-17 2015-07-02 Edison U. ORTIZ Virtualization and secure processing of data
CN104778401A (zh) * 2014-01-13 2015-07-15 恩智浦有限公司 数据处理设备和用于执行应用程序的方法
US20160078223A1 (en) * 2012-12-05 2016-03-17 Broadcom Corporation Hardware Isolated Secure Processing System Within A Secure Element

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8559921B2 (en) * 2005-08-17 2013-10-15 Freescale Semiconductor, Inc. Management of security features in a communication network
US20110016310A1 (en) * 2009-07-20 2011-01-20 Infineon Technologies Ag Secure serial interface with trusted platform module
WO2013081406A1 (en) * 2011-12-02 2013-06-06 Samsung Electronics Co., Ltd. Method and apparatus for securing touch input
CA3118235A1 (en) * 2012-04-13 2013-10-17 Ologn Technologies Ag Apparatuses, methods and systems for computer-based secure transactions
US9436940B2 (en) * 2012-07-09 2016-09-06 Maxim Integrated Products, Inc. Embedded secure element for authentication, storage and transaction within a mobile terminal
US8955039B2 (en) * 2012-09-12 2015-02-10 Intel Corporation Mobile platform with sensor data security
US20140244513A1 (en) * 2013-02-22 2014-08-28 Miguel Ballesteros Data protection in near field communications (nfc) transactions
US9594917B2 (en) * 2013-06-28 2017-03-14 Nxp B.V. Secured multi-directional, multi-interface transaction processing
US9704355B2 (en) * 2014-10-29 2017-07-11 Clover Network, Inc. Secure point of sale terminal and associated methods
KR20170077943A (ko) * 2015-12-28 2017-07-07 삼성전자주식회사 접근 제어 유닛을 포함하는 시스템 온 칩 및 시스템 온 칩을 포함하는 모바일 장치
US20170325088A1 (en) * 2016-05-05 2017-11-09 Qualcomm Incorporated Securing sensor status by leveraging always-on processor and host-based trusted execution

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201917963U (zh) * 2010-12-21 2011-08-03 北京同方微电子有限公司 用于移动支付的安全终端装置
CN104471586A (zh) * 2012-07-13 2015-03-25 高通股份有限公司 用于将一部分安全单元组件集成在片上系统上的方法和装置
US20150186879A1 (en) * 2012-10-17 2015-07-02 Edison U. ORTIZ Virtualization and secure processing of data
US20160078223A1 (en) * 2012-12-05 2016-03-17 Broadcom Corporation Hardware Isolated Secure Processing System Within A Secure Element
CN104778401A (zh) * 2014-01-13 2015-07-15 恩智浦有限公司 数据处理设备和用于执行应用程序的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3467667A4 *

Also Published As

Publication number Publication date
US20190138702A1 (en) 2019-05-09
EP3467667A4 (en) 2019-05-01
EP3467667A1 (en) 2019-04-10
KR20190018506A (ko) 2019-02-22
JP2019520653A (ja) 2019-07-18
CN107562689A (zh) 2018-01-09
EP3467667B1 (en) 2022-06-22

Similar Documents

Publication Publication Date Title
WO2018001277A1 (zh) 一种系统级芯片和终端
TWI576778B (zh) 針對遺失的電子裝置停用行動付款
KR102660519B1 (ko) 외부 장치를 인식하는 방법 및 이를 지원하는 전자 장치
CN106605233B (zh) 使用处理器提供可信执行环境
CN105684009B (zh) 针对基于nfc的支付使用生物特征认证
US9495524B2 (en) Secure user authentication using a master secure element
TWI605397B (zh) 用於金融交易之安全元件及攜帶型電子裝置
US10194318B2 (en) Systems and methods for NFC access control in a secure element centric NFC architecture
EP2648129B1 (en) Method and apparatus for securing touch input
EP2706699B1 (en) User terminal and payment system
US20130145475A1 (en) Method and apparatus for securing touch input
EP3291126A1 (en) Data verification via independent processors of a device
US10496975B2 (en) Point of sale system with secure and unsecure modes
JP6552714B2 (ja) データ処理方法およびシステム、ならびにウェアラブル電子デバイス
KR20160100151A (ko) 보안 정보의 처리
US11250421B2 (en) Storing secure credential information in different regions
US20240015156A1 (en) Electronic device for controlling access to device resource and operation method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17819274

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018566878

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20197001334

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2017819274

Country of ref document: EP

Effective date: 20190103