WO2018001188A1 - 电池片组件、电池片矩阵和太阳能电池组件 - Google Patents

电池片组件、电池片矩阵和太阳能电池组件 Download PDF

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Publication number
WO2018001188A1
WO2018001188A1 PCT/CN2017/089820 CN2017089820W WO2018001188A1 WO 2018001188 A1 WO2018001188 A1 WO 2018001188A1 CN 2017089820 W CN2017089820 W CN 2017089820W WO 2018001188 A1 WO2018001188 A1 WO 2018001188A1
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Prior art keywords
electrode
battery
layer
region
disposed
Prior art date
Application number
PCT/CN2017/089820
Other languages
English (en)
French (fr)
Inventor
孙翔
姚云江
田野
范北
姜占锋
Original Assignee
比亚迪股份有限公司
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Publication date
Priority claimed from CN201620686961.7U external-priority patent/CN205863186U/zh
Priority claimed from CN201610510202.XA external-priority patent/CN107564985A/zh
Application filed by 比亚迪股份有限公司 filed Critical 比亚迪股份有限公司
Priority to JP2018568419A priority Critical patent/JP6802298B2/ja
Priority to KR1020187037842A priority patent/KR102144795B1/ko
Priority to US16/309,693 priority patent/US11088294B2/en
Priority to EP17819185.4A priority patent/EP3480860B1/en
Publication of WO2018001188A1 publication Critical patent/WO2018001188A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H01L31/0508—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module the interconnection means having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H01L31/0516—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module specially adapted for interconnection of back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present disclosure relates to the field of solar cell technologies, and in particular, to a battery chip assembly, a battery chip matrix, and a solar cell module.
  • the backlight surface and the light receiving surface respectively have 2-3 silver main gate lines as the positive and negative electrodes of the battery sheet, and these silver main gate lines not only consume a large amount of silver paste, but also block incident light. This results in a decrease in the efficiency of the battery.
  • the positive and negative electrodes are respectively distributed on the backlight surface and the light receiving surface of the battery sheet, when the battery sheets are connected in series, it is necessary to use a conductive tape to solder the negative electrode of the light receiving surface of the battery sheet to the positive electrode of the backlight surface of the adjacent battery sheet. As a result, the welding process is cumbersome and the welding material is used more.
  • the battery sheets and the conductive tape are easily broken during soldering and subsequent lamination processes.
  • the matrix of the battery in the related art is usually composed of 72 pieces or 60 pieces of cells in series, which constitutes three circuits composed of six strings of battery strings. At this time, at least three diodes are generally required to make each circuit.
  • the diode is usually disposed in the junction box of the battery, the cost of the integrated junction box is increased, resulting in an increase in the structural complexity of the battery.
  • the series components in which a plurality of battery cells are connected in series are connected in series again, the amount of the connecting cable is large, and the material is wasted a lot, resulting in an increase in the cost of the power station.
  • the present disclosure is intended to address at least one of the technical problems existing in the prior art. To this end, the present disclosure is directed to a battery chip assembly that has high power.
  • the present disclosure also proposes a battery chip matrix having the above-described battery chip assembly.
  • the present disclosure also proposes a solar cell module having the above-described battery chip matrix.
  • a battery chip assembly includes: a plurality of battery sheets arranged in a longitudinal direction, each of the battery sheets each including a silicon wafer, a front conductive member provided on a light receiving surface of the silicon wafer, and Two electrodes on the back surface of the silicon wafer, and side conductive members disposed on a side surface of the silicon wafer and electrically connected between the front conductive member and one of the two electrodes, wherein two The electrodes all extend in a lateral direction and are spaced apart in the longitudinal direction; a conductive strip, the conductive strips are the same as the extending direction of the electrodes, and are adjacent to each other and respectively located on two adjacent two of the battery sheets The electrodes are electrically connected to turn on two of the electrodes located on two adjacent ones of the cells, such that two adjacent ones The cells are connected in series or in parallel.
  • the use length of the conductive tape can be effectively reduced, the amount of use of the conductive tape can be reduced, the thermal effect caused by the conductive strip can be reduced, and the overall power of the cell assembly can be improved.
  • the conductive strip in the extending direction of the conductive strip, has an extended length greater than or equal to an extension length of each of the electrodes electrically conducted by the conductive strip, and both ends of the conductive strip Exceeding or flushing respectively with respective ends of each of the electrodes that are conducted by the conductive strip.
  • the conductive strip has a span greater than or equal to a sum of spans of the two electrodes electrically conducted by the conductive strip in a direction perpendicular to a direction in which the conductive strip extends, and the conductive strip The two sides are respectively beyond or flush with the two sides of the two electrodes that are electrically connected by the conductive strip away from each other.
  • the conductive strips comprise two halves of the same structure and arranged in sequence perpendicular to the direction in which the strips extend, the two halves each covering exactly two of the conductive strips The electrodes.
  • the gap between two adjacent ones of the cells is less than or equal to 0.1 mm in a direction perpendicular to the direction in which the conductive strip extends.
  • the silicon wafer has a span of 20 mm to 60 mm in a direction perpendicular to a side surface of the side conductive member.
  • the silicon wafer is a rectangular sheet and is divided by a regular square wafer body according to a rule of constant length.
  • the silicon wafer is a rectangular sheet, and the two electrodes on each of the battery sheets are respectively disposed adjacent to the two long sides of the silicon wafer and are both along the length of the silicon wafer.
  • the side conductive member is provided on one long side surface of the silicon wafer.
  • the two electrodes on each of the battery sheets are a first electrode electrically connected to the side conductive member and a second electrode not electrically connected to the side conductive member
  • the silicon The sheet includes: a silicon substrate, a front first diffusion layer, and a back spacer, wherein the backlight surface of the silicon substrate includes a first region and a second region, and the front first diffusion layer is disposed on the silicon a light-receiving surface of the substrate, the front conductive member is disposed on the front first diffusion layer, the back spacer is only disposed on and covered on the first region, and the first electrode is disposed on The second electrode is disposed on the second region and is not in contact with the first electrode, wherein at least a portion of the back spacer is an insulating layer or first with the front surface A diffusion layer of the same type as the diffusion layer.
  • the silicon wafer further includes: a side spacer disposed on a side surface of the silicon substrate, the side conductive member being disposed on the side spacer, At least a portion of the side spacer is an insulating layer or a diffusion layer of the same type as the front first diffusion layer.
  • each of the battery sheets further includes: a backing layer disposed on the second region, the second electrode being disposed on the backing layer and The backing layer is electrically connected.
  • each of the battery sheets further includes: a back second gate line layer, the back second gate line layer and the second electrode are both disposed on the second area, and the The two electrodes are electrically connected to the second gate line layer on the back surface and do not overlap each other.
  • the silicon wafer further includes a back surface second type diffusion layer different from the front type first diffusion layer type, and the back surface second type diffusion layer is disposed only and filled with the second type In the region, the back second gate line layer and the second electrode are both disposed on the back surface type II diffusion layer.
  • each of the battery sheets further includes: a back first gate line layer, the back first gate line layer and the first electrode are both disposed on the back spacer, and the An electrode is electrically connected to the back first gate line layer and does not overlap each other.
  • the backside spacer is a backside first type of diffusion layer of the same type as the front first diffusion layer, and the backside first diffusion layer is only disposed and filled in the first In the region, the back first gate line layer and the first electrode are both disposed on the back type first diffusion layer.
  • the first region and the second region are both non-discrete regions.
  • the first region and the second region are in a cross-shaped distribution, wherein the first region includes a first connectivity region and a plurality of first dispersion regions, and the plurality of first dispersions The regions are spaced apart in a length direction of the first communication region and are both in communication with the first communication region, the second region includes a second communication region and a plurality of second dispersion regions, and the plurality of the second dispersions The regions are spaced apart in the length direction of the second communication region and are both in communication with the second communication region, wherein the first communication region is disposed in parallel with the second communication region, and the plurality of the first dispersions are The region and the plurality of the second dispersion regions alternate one another between the first communication region and the second communication region.
  • a battery chip matrix according to a second aspect of the present disclosure which is formed by a plurality of battery cell parallel components connected in series, wherein each of the battery chip parallel components is formed by a plurality of battery chip series components connected in parallel, wherein each of the battery cells
  • the sheet series components are all the battery sheet assemblies according to the first aspect of the present disclosure, and a plurality of the battery sheets in each of the battery sheet assemblies are sequentially connected in series by the conductive strips.
  • the overall power of the cell stack matrix is improved.
  • the battery cell parallel assembly is two, and each of the battery chip parallel assemblies includes three of the battery chip series components.
  • a solar cell module comprising a first panel, a first bonding layer, a battery, a second bonding layer, and a second panel disposed in order from a light receiving side to a backlight side, wherein the battery is based
  • the solar cell module of the present disclosure by providing the cell sheet matrix of the above second aspect or the above first aspect
  • the cell assembly improves the overall performance of the solar module.
  • FIG. 1 is a schematic view of a battery chip assembly in accordance with an embodiment of the present disclosure
  • Figure 2 is a schematic view of the cell sheet assembly shown in Figure 1 with the conductive strip removed;
  • FIG. 3 is a schematic diagram of a battery chip matrix in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of the battery chip matrix shown in FIG.
  • FIG. 5 is a schematic diagram of a light receiving side of a battery sheet according to Embodiment 1 of the present disclosure
  • Figure 6 is a schematic view of the backlight side of the battery chip shown in Figure 5;
  • Figure 7 is a schematic view of one side of the battery chip shown in Figure 5;
  • Figure 8 is a schematic view showing the two battery sheets shown in Figure 6 connected by a conductive strip
  • Figure 9 is a schematic view of the two battery sheets shown in Figure 8 with the conductive strip removed;
  • Figure 10 is a schematic side view of a light receiving side of a battery sheet according to Embodiment 2 of the present disclosure.
  • Figure 11 is a schematic view of the backlight side of the battery chip shown in Figure 10;
  • Figure 12 is a schematic view of one side of the battery chip shown in Figure 10;
  • Figure 13 is a schematic view showing the two battery sheets shown in Figure 11 connected by a conductive strip;
  • Figure 14 is a schematic view of the two battery sheets shown in Figure 13 with the conductive strip removed;
  • FIG. 15 is a schematic view showing a light receiving side of a battery sheet according to Embodiment 3 of the present disclosure.
  • Figure 16 is a schematic view of the backlight side of the battery chip shown in Figure 15;
  • Figure 17 is a schematic illustration of one side of the battery sheet shown in Figure 15;
  • Figure 18 is a schematic view showing the two battery sheets shown in Figure 16 connected by a conductive strip;
  • Figure 19 is a schematic view of the two battery sheets shown in Figure 18 with the conductive strip removed;
  • FIG. 20 is a schematic diagram of a light receiving side of a battery sheet according to Embodiment 4 of the present disclosure.
  • Figure 21 is a schematic view of the backlight side of the battery chip shown in Figure 20;
  • Figure 22 is a schematic illustration of one side of the battery chip shown in Figure 20;
  • Figure 23 is a schematic view showing the two battery sheets shown in Figure 21 connected by a conductive strip;
  • Figure 24 is a schematic view showing the removal of the conductive strip by the two battery sheets shown in Figure 23;
  • Figure 25 is a schematic side view of a light receiving side of a battery sheet according to Embodiment 5 of the present disclosure.
  • Figure 26 is a schematic view of the backlight side of the battery chip shown in Figure 25;
  • Figure 27 is a schematic illustration of one side of the battery sheet shown in Figure 25;
  • Figure 28 is a schematic view showing another side of the battery sheet shown in Figure 25;
  • Figure 29 is a view showing a process of preparing a backlight side of the battery chip shown in Figure 26;
  • Figure 30 is a schematic view showing the two battery sheets shown in Figure 26 connected by a conductive strip;
  • Figure 31 is a schematic view showing the removal of the conductive strips of the two battery sheets shown in Figure 30;
  • FIG. 32 is a schematic diagram of a light receiving side of a battery sheet according to Embodiment 6 of the present disclosure.
  • Figure 33 is a schematic view of the backlight side of the battery chip shown in Figure 32;
  • Figure 34 is a schematic view showing one side of the battery chip shown in Figure 32;
  • Figure 35 is a schematic view showing another side of the battery chip shown in Figure 32;
  • Figure 36 is a diagram showing the preparation process of the backlight side of the battery chip shown in Figure 33;
  • Figure 37 is a schematic view showing the two battery sheets shown in Figure 33 connected by a conductive strip;
  • Figure 38 is a schematic view showing the removal of the conductive strips of the two battery sheets shown in Figure 37;
  • FIG. 39 is a schematic side view of a light receiving side of a battery sheet according to Embodiment 7 of the present disclosure.
  • Figure 40 is a schematic view of the backlight side of the battery chip shown in Figure 39;
  • Figure 41 is a schematic illustration of one side of the battery sheet shown in Figure 39;
  • Figure 42 is a schematic view showing another side of the battery sheet shown in Figure 39;
  • Figure 43 is a view showing a process of preparing a backlight side of the battery chip shown in Figure 40;
  • Figure 44 is a schematic view showing the two battery sheets shown in Figure 40 connected by a conductive strip;
  • Figure 45 is a schematic illustration of the removal of the conductive strips for the two cell sheets shown in Figure 44.
  • Cell series assembly 1000 battery parallel assembly 2000; battery matrix 10000;
  • Cell sheet 100 cell sheet A; cell sheet B; electrode A1; electrode A2; electrode B1; electrode B2;
  • Silicon wafer 1 silicon substrate 11; anti-reflection layer 101; passivation layer 102;
  • a front type first diffusion layer 12 a side spacer 13; a back spacer 14; a back type second diffusion layer 15;
  • a second gate line layer 6 on the back surface a second sub-gate line 61 on the back surface; an electrical back layer 60;
  • a battery sheet assembly 100A according to an embodiment of the first aspect of the present disclosure will be described below with reference to FIGS. 1 to 45.
  • the battery chip assembly 100A includes at least two battery sheets 100 and at least one conductive tape 1001.
  • the battery chip 100 is a back contact solar cell.
  • each of the battery sheets 100 includes a silicon wafer 1, a front surface conductive member (for example, the front gate line layer 2 described below) disposed on the light receiving surface of the silicon wafer 1, and is disposed on the backlight surface of the silicon wafer 1.
  • Two electrodes for example, the first electrode 4 and the second electrode 5 described below
  • side conductive members provided on the side surface of the silicon wafer 1 and electrically connected between the front surface conductive member and one of the two electrodes 3, wherein the two electrodes are positive and negative electrodes of opposite polarity and not in contact with each other.
  • the front surface conductive member can collect a kind of electric charge from the light-receiving surface of the silicon wafer 1 and transmit it to one of the two electrodes electrically connected thereto through the side conductive member 3, and the other one.
  • the electrode obtains another kind of electric charge on the backlight surface side of the silicon wafer 1, whereby the two electrodes can output electric energy.
  • the light-receiving surfaces of the plurality of battery sheets 100 are all oriented toward the same side, for example, facing the sun, and the backlight surfaces are all oriented in the longitudinal direction toward the same side, for example, all facing away from the sun.
  • the two electrodes on each of the cell sheets 100 extend in the lateral direction and are spaced apart in the longitudinal direction to ensure that the two electrodes are not in contact with each other to avoid short circuits.
  • extension direction of the electrode described herein refers to the length direction of the electrode
  • the "direction of extension of the conductive tape 1001" described hereinafter refers to the length direction of the conductive tape 1001.
  • lateral refers to the direction in which the transverse lines extend, such as the horizontal direction shown in FIGS. 1 and 2, and “longitudinal” refers to the direction in which the longitudinal lines extend, for example.
  • the transverse line and the longitudinal line are mutually perpendicular straight lines; in addition, “extending in the lateral direction” is to be understood broadly, that is, it should include “extending in a direction parallel to the transverse line” and “Extended in a direction that is less than 45° from the transverse line.”
  • the conductive strip 1001 is the same as the extending direction of the electrode to be sufficiently electrically connected to the electrode to improve the conductive efficiency, wherein the conductive strip 1001 is electrically connected to the two electrodes adjacent to each other and located on the adjacent two battery sheets 100, respectively.
  • the connection turns on the two electrodes located on two adjacent ones of the cells such that two adjacent cells 100 are connected in series or in parallel.
  • two adjacent battery sheets 100 are a battery sheet A and a battery sheet B, respectively, and the battery sheet A has electrodes A1 and A2 spaced apart in the longitudinal direction.
  • the battery sheet B has electrodes B1 and B2 spaced apart in the longitudinal direction.
  • the electrodes A1 and The pole A2, the electrode B1 and the electrode B2 are arranged in the longitudinal direction. At this time, the electrode A2 and the electrode B1 are close to each other, and the electrode A1 and the electrode B2 are apart from each other. At this time, the conductive strip 1001 is electrically connected with the electrode A2 and the electrode B1 to connect the electrode A2. And the electrode B1 is turned on.
  • the cell sheet A and the cell sheet B can be connected in parallel, and when the electrode A2 and the electrode B1 are When the polarities are different (i.e., one is a positive electrode and the other is a negative electrode), the cell A and the cell B can be connected in series.
  • a plurality of battery sheets 100 are sequentially arranged in the longitudinal direction, wherein two electrodes on each of the battery sheets 100 extend in the lateral direction and are spaced apart in the longitudinal direction so that each of the battery sheets
  • the upper and lower portions of 100 each have an electrode, whereby the upper electrode (e.g., electrode B1) of the remaining battery sheet 100 (e.g., battery sheet B) except the uppermost battery sheet 100 (e.g., battery sheet A) is above
  • the lower electrodes (e.g., the electrodes A2) of the battery sheets 100 (e.g., the battery sheets A) are close to each other and can be electrically conducted through the conductive strips 1001, that is, the batteries other than the lowermost battery sheet 100 (e.g., the battery sheets B)
  • the lower electrode (e.g., electrode A2) of the sheet 100 (e.g., the battery sheet A) and the upper electrode (e.g., the electrode B1) of the battery sheet 100 (e.g., the battery sheet B) below it are
  • the total area of the conductive strip 1001 can be effectively reduced, the thermal effect caused by the conductive strip 1001 can be reduced, the amount of the conductive strip 1001 used can be reduced, and the overall power of the cell sheet assembly 100A can be improved.
  • the conductive strip 1001 can be a solder ribbon.
  • the cell assembly 100A is a cell series assembly 1000.
  • the cell matrix 10000 is comprised of a plurality of cell parallel assemblies 2000 in series, wherein each cell parallel assembly 2000 is formed by a plurality of cell series assemblies 1000 connected in parallel. That is to say, the plurality of cell series units 1000 are first connected in parallel to form a plurality of cell parallel units 2000, and the plurality of cell parallel units 2000 are connected in series to form a cell matrix 10000.
  • the power of the cell matrix 10000 is effectively increased, and the diode is not required to be bypass protected, thereby reducing the cost of the battery.
  • the positive and negative junction boxes can be distributed on both sides of the cell matrix 10000, thereby reducing The amount of connecting cables between adjacent components reduces the cost of the power station.
  • each of the battery-parallel assemblies 2000 is formed by three battery-series series assemblies 1000 in parallel. That is to say, the six cell series series components 1000 are formed into a cell matrix 10000 by using the method of “first three and then two strings”, that is, the six cells are connected in series to the first assembly. Parallel into two cell parallel assemblies 2000, and then two battery parallel assemblies 2000 are connected in series to a cell matrix 10000.
  • the battery chip matrix in the related art generally includes 60 battery cells connected in series, wherein each of the 10 battery cells is first connected in series to form a battery chip string, and the six battery chip strings are sequentially connected in series, thereby 60.
  • the battery cells can all be connected in series.
  • the voltage of each cell is 0.5V
  • the voltage of 60 cells connected in series is 30V.
  • the entire cell matrix will not work properly, so It is necessary to connect three diodes in parallel, so that even if there is a problem with the battery string, the circuit will form a loop through the parallel diodes, and the cell matrix can continue to work normally, not to be scrapped, but the power is smaller.
  • the production cost of the diode is high.
  • the junction box is disposed at the edge of the width direction of the panel, and the positive and negative poles are led out through the junction box, and the integrated wiring used in the assembly.
  • the box also increases production costs.
  • the junction box is in the center of the assembly, when the components are connected in series with the components, the amount of the connection cable is large, material is wasted, and the power station cost is also increased.
  • the width of the battery sheet 100 herein may be 1/4 of the width of the conventional battery sheet.
  • a voltage of 40V can be achieved, so that the operating voltage can be effectively achieved.
  • the cell matrix 10000 is constructed by the above-mentioned "first three and then two strings" manner, since the parallel structure itself can protect the parallel bypass, it is not necessary to add another diode. Road protection reduces production costs.
  • the positive and negative junction boxes can be distributed on both sides of the cell matrix 10000, the amount of components and component connection cables is reduced, further reducing the cost of the power station.
  • a solar cell module according to an embodiment of the third aspect of the present disclosure is described below.
  • the solar cell module includes a first panel, a first bonding layer, a battery, a second bonding layer, and a second panel disposed in order from the light receiving side to the backlight side.
  • the battery may be the battery chip assembly 100A of the first aspect of the above embodiment, or may be the battery chip matrix 10000 of the second embodiment.
  • a method of preparing a solar cell module according to an embodiment of the fourth aspect of the present disclosure is described below.
  • the adjacent two battery cells 100 may be first connected in series or in parallel using the conductive tape 1001 to obtain the battery chip assembly 100A, and then the battery chip assembly is used by the bus bar 1002.
  • the positive electrode and the negative electrode of 100A are respectively taken out.
  • the adjacent two battery cells 100 may be first connected in series using the conductive tape 1001 to obtain a plurality of battery chip series components 1000, and then the plurality of batteries are used by the bus bars 1002.
  • the chip series components 1000 are connected in parallel to obtain a plurality of cell parallel components 2000, and then the plurality of cells are connected by the bus bars 1002.
  • the chip parallel assemblies 2000 are connected in series to obtain a cell matrix 10000, and finally the bus bar 1002 is used to respectively connect the positive electrode and the negative electrode of the cell array 10000.
  • first panel, the first bonding layer, the battery, the second bonding layer, and the second panel are sequentially laid in the up and down direction to obtain a laminated structure, and then the laminated structure is laminated and packaged.
  • a first panel eg, glass
  • a first bonding layer eg, EVA
  • a battery e.g. EVA
  • a second bonding layer e.g, EVA
  • the battery back sheet or glass is used to obtain a laminated structure.
  • the laminated structure in the previous step is laminated in a laminator, and the junction box and the bezel are mounted, thereby realizing packaging and fabrication of the solar cell module.
  • a battery sheet 100 according to various embodiments of the present disclosure will be described below with reference to FIGS. 1 and 2 and in conjunction with FIGS. 5 to 45.
  • the conductive strip 1001 in the extending direction of the conductive strip 1001, has an extended length greater than or equal to the extension length of each of the electrodes that are electrically conducted by the conductive strip 1001, and the two ends of the conductive strip 1001 respectively exceed Or flush with the respective ends of each of the electrodes that are conducted by the conductive strip 1001. It should be noted, however, that when both ends of the conductive strip 1001 exceed the respective ends of each of the electrodes that are conducted by the conductive strip 1001, the conductive strip 1001 needs to be guided with the conductive strip 1001 on each of the silicon wafers 1 The conductive medium carrying the opposite polarity carried by the electrodes maintains a safe distance to avoid shorting of the two electrodes on the same silicon wafer 1.
  • the electrode A2 and the electrode B1 both extend in the lateral direction, and the conductive strip 1001 also extends in the lateral direction.
  • the length of the conductive strip 1001 in the lateral direction is greater than or equal to the length of the electrode A2 in the lateral direction, and It is also greater than or equal to the length of the electrode B1 in the lateral direction.
  • the two ends of the conductive strip 1001 in the lateral direction are respectively left and right ends, and the left end of the conductive strip 1001 is leftward or left flush with the left end of the electrode A2, and at the same time, the conductive strip 1001
  • the left end of the conductive strip 1001 is also leftward or rightward to the left end of the electrode B1, and the right end of the conductive strip 1001 is beyond or flush with the right end of the electrode A2, and the right end of the conductive strip 1001 is also laterally beyond or flush with
  • the right end of the electrode B1 at the same time, the left and right ends of the conductive strip 1001 are also respectively separated from the electrode A1, the conductive medium electrically connected to the electrode A1, the electrode B2, and the conductive medium electrically connected to the electrode B2 to maintain a certain safe distance to avoid the electrode A1 and electrode A2 are short-circuited while avoiding short-circuiting of electrode B1 and electrode B2.
  • the conductive strip 1001 is sufficiently connected to the electrodes, the total area of the conductive strips 1001 is reduced, the thermal effect caused by the conductive strips 1001 is reduced, the amount of the conductive strips 1001 is reduced, and the overall power of the cell sheet assembly 100A is improved.
  • the span of the conductive strip 1001 is greater than or equal to the sum of the spans of the two electrodes that are conducted by the conductive strip 1001 in a direction perpendicular to the direction in which the conductive strip 1001 extends, and both sides of the conductive strip 1001 The sides are respectively beyond or flush with the two sides of the two electrodes that are electrically connected by the conductive strip 1001 away from each other.
  • the conductive strip 1001 needs to be associated with each of the silicon wafers 1
  • the conductive medium carrying the opposite polarity carried by the conductive strips of the conductive strip 1001 maintains a certain safe distance to avoid shorting of the two electrodes on the same silicon wafer 1.
  • both the electrode A2 and the electrode B1 extend in the lateral direction, and the conductive strip 1001 also extends in the lateral direction.
  • the width of the conductive strip 1001 in the longitudinal direction is greater than or equal to the width of the electrode A2 in the longitudinal direction and the electrode.
  • B1 in portrait The upper side of the conductive strip 1001 is the upper and lower sides, and the upper side of the conductive strip 1001 is upwardly or flush with the upper side of the electrode A2 and the lower side of the conductive strip 1001.
  • the side of the conductive strip 1001 is electrically connected to the electrode A1, the electrode B2, and the electrode B2, respectively
  • the conductive medium maintains a certain safe distance to avoid short circuit of the electrode A1 and the electrode A2, and avoid short circuit of the electrode B1 and the electrode B2. Thereby, it is ensured that the conductive strip 1001 is sufficiently connected to the electrodes, the total area of the conductive strips 1001 is reduced, the thermal effect caused by the conductive strips 1001 is reduced, the amount of the conductive strips 1001 is reduced, and the overall power of the cell sheet assembly 100A is improved.
  • the conductive strip 1001 includes two halves that are identical in structure and are sequentially disposed in a direction perpendicular to the direction in which the conductive strips 1001 extend, the two halves each covering exactly the conductive strip 1001.
  • Two electrodes For example, in the examples shown in FIGS. 1 and 2, the conductive strip 1001 extends in the lateral direction and includes upper and lower halves arranged in this order in the longitudinal direction, wherein the upper half just covers the electrode A2, that is, the upper side The outer contour of the half coincides with the outer contour of the electrode A2, and the lower half just covers the electrode B1, that is, the outer contour of the lower half coincides with the outer contour of the electrode B1.
  • the conductive strip 1001 is sufficiently connected to the electrodes, the total area of the conductive strips 1001 is reduced, the thermal effect caused by the conductive strips 1001 is reduced, the amount of the conductive strips 1001 is reduced, and the overall power of the cell sheet assembly 100A is improved.
  • the gap between the adjacent two battery sheets 100 is less than or equal to 0.1 mm in a direction perpendicular to the direction in which the conductive strip 1001 extends. That is, the gap between the adjacent two battery sheets 100 is 0 mm to 0.1 mm.
  • the conductive strip 1001 extends in the lateral direction, and the battery sheet A and the battery sheet B are sequentially arranged in the longitudinal direction, at this time, the lower edge of the battery sheet A and the upper edge of the battery sheet B are The distance between the cells is the gap between the battery sheet A and the battery sheet B.
  • the gap between the adjacent two battery sheets 100 in the direction perpendicular to the extending direction of the conductive strip 1001 is defined to be 0.1 mm or less, the total area of the conductive strip 1001 can be further reduced, and the thermal effect caused by the conductive strip 1001 can be reduced. The amount of use of the conductive strip 1001 is reduced, and the overall power of the cell assembly 100A is increased. In addition, when there is a certain small gap between the two battery sheets 100, it may be avoided due to irregular shape or operation error of the battery sheet 100. Adjacent cell sheets 100 overlap the problem.
  • the span of the silicon wafer 1 in a direction perpendicular to the side surface of the side conductive member 3 is 20 mm to 60 mm. That is, the silicon wafer 1 includes a set of (two) oppositely disposed side surfaces, one of which is provided with side conductive members 3, and the distance between the set of side surfaces is 20 mm to 60 mm.
  • the silicon wafer 1 is a rectangular sheet body, for example, a rectangular sheet body, and the side surface conductive member 3 is provided on one long side surface of the silicon wafer 1, the silicon wafer 1 is The width is 20mm ⁇ 60mm.
  • the silicon wafer 1 is a rectangular sheet and the side conductive members 3 are provided on one wide side surface of the silicon wafer 1
  • the silicon wafer 1 The length is 20mm ⁇ 60mm.
  • the path of charge transfer from the light receiving surface of the silicon wafer 1 to the backlight surface can be shortened, thereby improving charge transfer.
  • the rate which in turn increases the power of the cell 100.
  • the "rectangular sheet” is understood as a broad sense, that is, not limited to a rectangular sheet in a strict sense, such as a generally rectangular sheet, such as a rectangular sheet having rounded or chamfered corners at four corners. Etc. also falls within the scope of protection of the present disclosure. Thereby, the processing of the battery sheet 100 is facilitated, and the connection between the battery sheet 100 and the battery sheet 100 is facilitated.
  • the silicon wafer 1 is a rectangular sheet, and is formed by a square conventional silicon wafer body divided according to a rule of constant length (only “separating” rather than "taking a cutting process"). That is to say, the square-sized silicon wafer body can be divided into a plurality of rectangular wafer-shaped silicon wafers 1 in a manner of constant length. At this time, the length of each silicon wafer 1 is equal to the length of the square-sized silicon wafer body. And the sum of the widths of the plurality of silicon wafers 1 is equal to the width of the square-sized silicon wafer body.
  • the silicon wafer 1 is a rectangular sheet body, and the two electrodes are respectively disposed adjacent to the two long sides of the silicon wafer 1 to be spaced apart in the width direction of the silicon wafer 1, and both extend along the length direction of the silicon wafer 1, and the side conductive members are respectively 3 is provided on one long side surface of the silicon wafer 1, that is, on one side surface in the width direction of the silicon wafer 1.
  • the charge transmission path is shorter, the power of the battery sheet 100 is higher, and the processing of the battery sheet 100 is more convenient, and the connection between the battery sheet 100 and the battery sheet 100 is further facilitated.
  • both electrodes may be rectangular and have the same length as the length of the silicon wafer 1, so that the two broad sides and one long side of each electrode may be respectively long and two long sides and one long side of the silicon wafer 1. The edges are aligned, thereby making full use of the space, increasing the power of the battery sheet 100, and facilitating the connection of the subsequent battery sheet 100 to the battery sheet 100.
  • the side conductive member 3 may be configured in a sheet shape and occupy one side side surface in the width direction of the silicon wafer 1, so that the power of the battery sheet 100 can be improved.
  • the specific structure of the side conductive member 3 and the electrode is not limited thereto.
  • the side conductive member 3 and the electrode may also be composed of discrete electrode electrodes by a plurality of sub-electrodes spaced apart.
  • the two electrodes on each of the battery sheets 100 are a first electrode 4 electrically connected to the side conductive member 3 and a second electrode 5 not electrically connected to the side conductive member 3, silicon.
  • the sheet 1 includes a silicon substrate 11, a front first diffusion layer 12, and a back spacer 14, wherein the backlight surface of the silicon substrate 11 includes a first region and a second region, and the front first diffusion layer 12 is disposed on the silicon.
  • the front conductive member is disposed on the front first diffusion layer 12, the back spacer 14 is disposed only on the first region, and the first electrode 4 is disposed on the back spacer 14.
  • the second electrode 5 is disposed on the second region and is not in contact with the first electrode 4, wherein at least a portion of the back spacer 14 is an insulating layer or a diffusion layer of the same type as the front first diffusion layer 12.
  • the silicon wafer 1 further includes a side spacer 13 provided on the side surface of the silicon substrate 11, and the side conductive member 3 is disposed on the side spacer 13, and the side spacer At least a portion of the layer 13 is an insulating layer or a diffusion layer of the same type as the front first diffusion layer 12.
  • each of the battery sheets 100 further includes: a backing layer 60, the backing layer 60 is disposed on the second region, and the second electrode 5 is disposed on the backing layer 60 and electrically connected to the backing layer 60 .
  • each of the battery sheets 100 further includes: a second gate line layer 6 on the back surface, and a back surface
  • the second gate line layer 6 and the second electrode 5 are both disposed on the second region, and the second electrode 5 is electrically connected to the back second gate line layer 6 and does not overlap each other.
  • the silicon wafer 1 further includes a back surface second type diffusion layer 15 different from the front type first diffusion layer 12, and the back surface second type diffusion layer 15 is only disposed and covered.
  • the second gate line layer 6 and the second electrode 5 on the back surface are both disposed on the back diffusion layer 15 of the second type.
  • each of the battery sheets 100 further includes: a back first gate line layer 7, and a back first gate line layer 7 and a first electrode 4 are disposed on the back spacer 14, and first The electrode 4 is electrically connected to the back first gate line layer 7 and does not overlap each other.
  • the back surface layer 14 is a back type first type diffusion layer of the same type as the front type first diffusion layer 12, and the back type first diffusion layer is only disposed and filled with In a region, the first gate line layer 7 and the first electrode 4 on the back surface are both disposed on the back diffusion layer of the first type.
  • the first region and the second region are both non-discrete regions. That is, when the first area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas may be connected into one continuous first area.
  • the arbitrary layer is also a non-discrete layer, that is, a continuous layer; when the second area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas can be connected into one A continuous second area.
  • the arbitrary layer is also a non-discrete layer, ie, a continuous layer.
  • the first area and the second area are both rectangular areas for ease of processing.
  • the first area and the second area are distributed in a cross shape.
  • the first area includes a first communication area and a plurality of first dispersion areas, and the plurality of first dispersion areas are in the first One of the connected regions is spaced apart in the longitudinal direction and is both in communication with the first communication region
  • the second region includes a second communication region and a plurality of second dispersion regions, and the plurality of second dispersion regions are spaced apart in the length direction of the second communication region Opening and communicating with the second communication region, wherein the first communication region is disposed in parallel with the second communication region, and the plurality of first dispersion regions and the plurality of second dispersion regions are between the first communication region and the second communication region An alternation.
  • the battery sheet 100 includes: a silicon wafer 1, a front conductive member, a side conductive member 3, a first electrode 4, a backing layer 60, and a second electrode 5, wherein the front conductive member is a front gate layer 2, the silicon wafer 1 may include a silicon substrate 11, a front first diffusion layer 12, a side spacer 13, and a back spacer 14.
  • the silicon substrate 11 has a sheet shape, and the two surfaces in the thickness direction of the silicon substrate 11 are respectively a light receiving surface and a backlight surface, and the light receiving surface is connected to the backlight surface through the side surface.
  • the front first diffusion layer 12 is disposed on the light receiving surface of the silicon substrate 11.
  • the front first diffusion layer 12 is covered on the light receiving surface of the silicon substrate 11. Therefore, the processing difficulty of the front type first diffusion layer 12 is reduced, the processing efficiency is improved, and the processing cost is reduced.
  • the side spacers 13 are provided on the side surface of the silicon substrate 11.
  • the side spacers 13 may be provided only on one side surface of the silicon substrate 11, or may be provided on a plurality of side surfaces at the same time.
  • the side spacer 13 is provided only on one side surface of the silicon substrate 11 and is covered on the side surface. Thereby, the processing and manufacture of the side spacers 13 are facilitated.
  • the side conductive members 3 are disposed on the side spacers 13, that is, the side conductive members 3 may be directly or indirectly disposed on the side spacers 13. At this time, the side conductive members 3 are disposed on the side surfaces of the silicon wafer 1 and The side spacers 13 correspond, that is, in a direction perpendicular to the side surface in which the side spacers 13 are located, and the side conductive members 3 do not extend beyond the outline of the side spacers 13.
  • the side conductive members 3 are disposed on the side surface of the silicon wafer 1 and are not embedded in the interior of the silicon wafer 1, the processing difficulty of the entire battery sheet 100 can be reduced, the processing process can be simplified, the processing efficiency can be improved, and the processing cost can be reduced. .
  • the backlight surface of the silicon substrate 11 includes a first region and a second region, and the first region and the second region have no intersection.
  • the first area and the second area may be in contact with each other or not in contact with each other, that is, the contour lines of the first area and the contour lines of the second area may or may not contact each other.
  • the portion of the backside barrier layer 14 that is in contact with the backing layer 60 is an insulating layer
  • the first region and the second region may be in contact with each other
  • the portion of the backside barrier layer 14 that is in contact with the backing layer 60 is When the diffusion layer of the same type as the front type first diffusion layer 12 is the same, the first region and the second region may not contact each other.
  • the first region and the second region are non-discrete regions.
  • the backside barrier layer 14 is disposed only on the first region, that is, the back surface layer 14 is not provided on the backlight surface of the silicon substrate 11 except for the first region. Further, the backside barrier layer 14 is covered with the first layer. In a region, such that when the first region is a non-discrete continuous region, the backside barrier layer 14 can be disposed non-discretely, i.e., continuously, on the silicon substrate 11. Thus, since the backside barrier layer 14 is disposed continuously, i.e., non-discretely, on the silicon substrate 11, rather than discretely, i.e., discontinuously, for example, discrete forms such as scatters, zebra strips, etc. are dispersed on the silicon substrate. 11 , thereby greatly reducing the processing difficulty of the back compartment 14 , improving the processing efficiency, reducing the processing cost, and effectively improving the power of the battery sheet 100 .
  • the front gate line layer 2 is disposed on the front first diffusion layer 12, that is, the front gate line layer 2 may be directly or indirectly disposed on the front first diffusion layer 12, and the front gate line layer 2 is disposed at
  • the light-receiving surface of the silicon wafer 1 corresponds to the front-surface first-type diffusion layer 12, in other words, in the thickness direction of the silicon wafer 1, and the front gate line layer 2 does not exceed the outline of the front-surface first-type diffusion layer 12.
  • the silicon wafer 1 may further include an anti-reflection layer 101, and the anti-reflection layer 101 may be disposed on the front-first diffusion layer 12.
  • the front gate line layer 2 can be directly provided on the anti-reflection layer 101.
  • the front gate line layer 2 may be directly disposed on the front first diffusion layer 12.
  • the first electrode 4 is disposed on the back surface layer 14, that is, the first electrode 4 can be directly or indirectly disposed on the back surface layer 14. At this time, the first electrode 4 is disposed on the backlight surface of the silicon wafer 1 and The first region corresponds, in other words, projected in the thickness direction of the silicon wafer 1, and the first electrode 4 does not extend beyond the first region.
  • the first electrode 4 may also be provided on the backside barrier layer 14 indirectly through a passivation layer.
  • the backing layer 60 and the second electrode 5 are both disposed on the second region, that is, the backing layer 60 and the second electrode 5 may be directly or indirectly disposed on the second region of the backlight surface of the silicon substrate 11.
  • the backing layer 60 and the second electrode 5 are disposed on the backlight surface of the silicon wafer 1 and correspond to the second region, that is, projected along the thickness direction of the silicon wafer 1, and the back layer
  • the 60 and second electrodes 5 do not extend beyond the second region.
  • the backing layer 60 and the second electrode 5 may also be provided indirectly on the backlight surface of the silicon substrate 11 through a passivation layer.
  • the first electrode 4 is neither in contact with the backing layer 60 nor in contact with the second electrode 5.
  • the backing layer 60 and the second electrode 5 may be non-overlapping and in contact with each other. At this time, the backing layer 60 and the second electrode 5 are respectively disposed at The backlight surface of the silicon wafer 1 is directly in contact with the electrical connection, so that the space can be utilized to increase the power of the battery panel 100.
  • the backing layer 60 and the second electrode 5 can also be stacked on each other. In this case, the surface of the back surface of the silicon wafer 1 is disposed on the surface of the back surface of the silicon wafer 1 with the back surface layer 60 and the second electrode 5 stacked.
  • the conductive medium (directly or indirectly through the anti-reflection layer, the passivation layer) is disposed on the front first diffusion layer 12, or (directly or indirectly through the anti-reflection layer, the passivation layer)
  • the front type first diffusion layer 12 such as the side first diffusion layer and the back first diffusion layer as described below
  • one type of charge can be collected; and when the conductive medium is directly Or indirectly through the passivation layer) on the surface of the silicon substrate 11 which does not have the front first type diffusion layer 12, or (directly or indirectly through the passivation layer) is disposed opposite to the front type first diffusion type 12
  • a diffusion layer such as the back type second diffusion layer described below
  • another kind of charge can be collected.
  • the principle that the conductive medium collects charges on the silicon wafer should be well known to those skilled in the art and will not be described in detail herein.
  • the entire light-receiving surface of the silicon wafer 1 and the outermost surface of one side surface in the embodiments 1-7 herein may each have an anti-reflection layer, and the silicon wafer 1 in the embodiments 2-7 herein.
  • the outermost surface of the entire backlight surface may also have a passivation layer to facilitate processing and fabrication.
  • the concepts of the anti-reflection layer and the passivation layer described herein are well known to those skilled in the art, and are mainly used to reduce reflection and enhance charge collection.
  • the materials of the anti-reflection layer and the passivation layer may include, but are not limited to, TiO2, Al2O3, SiNxOy, SiNxCy.
  • the front first diffusion layer 12 may be a phosphorus diffusion layer, and the conductive medium disposed on the phosphorus diffusion layer may collect a negative charge and be disposed on the non-phosphorus diffusion layer.
  • the conductive medium collects a positive charge.
  • the front gate line layer 2 is disposed on the front side first type diffusion layer 12 (for example, directly or through the anti-reflection layer 101), the front gate line layer 2 can collect the first type of charge (for example, negative Charge).
  • the backing layer 60 is disposed on the backlight surface of the silicon substrate 11 (eg, directly or indirectly through the passivation layer) such that the positive backing layer 60 can collect a second type of charge (eg, a positive charge).
  • the first electrode 4 is electrically connected to the front gate line layer 2 through the side conductive members 3, so that the first type of charge (eg, negative charge) collected by the front gate line layer 2 can be transferred to the first electrode 4 (eg, the negative electrode).
  • the second electrode 5 is electrically connected to the backing layer 60 such that a second type of charge (eg, a positive charge) collected by the backing layer 60 can be transferred to the second electrode 5 (eg, a positive electrode).
  • the first electrode 4 and the second electrode 5 can output electric energy as positive and negative poles of the battery sheet 100.
  • the side conductive member 3 is provided on the side of the silicon wafer 1, it can be easily and conveniently passed through the side conductive member 3
  • the surface wiring layer 2 and the first electrode 4 are effectively electrically connected together to ensure the reliability of the operation of the battery chip 100.
  • first electrode 4 and the second electrode 5 need to be electrodes of opposite polarity, and need to be insulated, that is, not electrically connected to each other, and do not form an electrical connection with each other.
  • first electrode 4 And all components electrically connected to the first electrode 4 and the second electrode 5, and all components electrically connected to the second electrode 5 are not directly conductive, and cannot be indirectly conducted through any external conductive medium, for example, may not be in contact. Or isolated by an insulating material or the like to avoid short-circuiting of the first electrode 4 and the second electrode 5.
  • the back surface layer 14 is configured to prevent the first electrode 4 from being short-circuited by the silicon substrate 11 and the second electrode 5, that is, to prevent the first electrode 4 from directly contacting the silicon substrate 11 to cause a short circuit.
  • the back surface layer 14 may be The diffusion layer and/or the insulating layer of the same type as the front diffusion layer, that is, the back spacer 14 may all be the same type of diffusion layer as the front diffusion layer, or may be all of the insulating layer, or may be of the same type as the front diffusion layer.
  • the diffusion layer and the remaining part are insulating layers.
  • the first electrode 4 When the first electrode 4 is provided on the silicon substrate 11 through the insulating layer, the first electrode 4 can be directly insulated from the silicon substrate 11 to prevent the first electrode 4 from being collected from the silicon substrate 11 and collected by the second electrode 5.
  • the charge of the same type of charge can effectively prevent the first electrode 4 from being electrically connected to the second electrode 5 through the silicon substrate 11 to cause a short circuit, that is, avoiding direct contact between the first electrode 4 and the silicon substrate 11 to cause a short circuit.
  • the first electrode 4 When the first electrode 4 is provided on the silicon substrate 11 through a diffusion layer of the same type as the front diffusion layer, the first electrode 4 can collect the type of charge collected from the diffused silicon substrate 11 and the front gate line layer 2. The same charge, that is, the charge opposite to the type of charge collected by the second electrode 5, can also prevent the first electrode 4 and the second electrode 5 from being short-circuited, and the power of the cell 100 can be improved.
  • the side spacer 13 is configured to prevent the side conductive member 3 from being short-circuited by the silicon substrate 11 and the second electrode 5, thereby preventing the first electrode 4 and the second electrode 5 from being short-circuited, that is, avoiding the side conductive member 3 and the silicon substrate 11 directly. Contact caused a short circuit.
  • the side spacers 13 may be the same type of diffusion layer and/or insulating layer as the front diffusion layer, that is, the side spacers 13 may all be the same type of diffusion layer as the front diffusion layer, or may be all insulating layers. One part is the same type of diffusion layer as the front diffusion layer, and the other part is an insulating layer.
  • the side conductive member 3 When the side conductive member 3 is provided on the silicon substrate 11 through the insulating layer, the side conductive member 3 can be directly insulated from the silicon substrate 11 to prevent the side conductive member 3 from being collected from the silicon substrate 11 and collected by the second electrode 5.
  • the charge of the same type of charge can effectively prevent the side conductive member 3 from being electrically connected to the second electrode 5 through the silicon substrate 11 to cause a short circuit, that is, to avoid short-circuiting of the side conductive member 3 in direct contact with the silicon substrate 11.
  • the side conductive member 3 When the side conductive member 3 is provided on the silicon substrate 11 through a diffusion layer of the same type as the front diffusion layer, the side conductive member 3 can collect the type of charge collected from the diffused silicon substrate 11 and the front gate line layer 2.
  • the same electric charge that is, the electric charge opposite to the type of electric charge collected by the second electrode 5, can also avoid short-circuiting of the side conductive member 3 and the second electrode 5, that is, avoiding direct contact between the side conductive member 3 and the silicon substrate 11 to cause a short circuit.
  • the power of the battery chip 100 can be increased.
  • At least a portion of at least one of the side spacer 13 and the back spacer 14 is of the same diffusion type as the front first diffusion layer 12, that is, either a side spacer At least part of the diffusion layer 13 is of the same type as the front type first diffusion layer 12, or at least part of the back surface layer 14 is of the same diffusion type as the front first diffusion layer 12, thereby ensuring not only the first electrode 4 but also the first electrode 4
  • the power of the battery sheet 100 can also be improved by the insulating effect with the second electrode 5.
  • the backside barrier layer 14 is all of the same type of diffusion layer as the front first type of diffusion layer 12, that is, the backside barrier layer 14 is a backside first diffusion layer that is overlaid on the first region.
  • the side spacers 13 are all of the same type of diffusion layer as the front type first diffusion layer 12, that is, the side spacers 13 are side diffusion layers which are covered on the side surface of the silicon substrate 11. Thereby, the processing is convenient and the insulation reliability is good.
  • the concepts of the silicon substrate, the diffusion layer, the anti-reflection layer, the passivation layer, and the like, and the principle that the conductive medium collects charges from the silicon wafer are well known to those skilled in the art and will not be described in detail herein.
  • the front gate line layer 2, and the back second gate line layer 6 and the back first gate line layer 7 described later may each be provided by a plurality of spaced apart openings.
  • the conductive medium layer formed by the conductive fine gate lines, wherein the fine gate lines may be composed of a silver material, so that the conductive rate can be increased on the one hand, and the light-shielding area can be reduced on the other hand, thereby increasing the power of the battery sheet 100 in a disguised manner.
  • the backing layer 60 can be an aluminum layer, that is, an aluminum back field, so that on the one hand, the conduction rate can be increased, and on the other hand, the cost can be reduced.
  • the battery sheet 100 of the embodiment of the present disclosure since at least a portion of at least one of the back surface layer 14 and the side spacer layer 13 is of the same diffusion type as the front type first diffusion layer 12, not only the first layer can be ensured
  • the insulation of the one electrode 4 and the second electrode 5 can also effectively increase the power of the battery chip 100.
  • the first electrode on the light receiving surface of the conventional battery sheet can be transferred from the light receiving side of the silicon wafer to the backlight side to prevent the first electrode from receiving light on the silicon wafer.
  • the side is shielded so that the power of the battery sheet 100 of the present disclosure is higher than that of the existing battery sheet.
  • the first electrode 4 and the second electrode 5 of the cell sheet 100 of the present disclosure are located on the same side of the silicon wafer 1, thereby facilitating electrical connection between the plurality of battery sheets 100, reducing soldering difficulty, reducing solder usage, and reducing soldering. The probability of breakage of the cell sheet 100 during the subsequent and subsequent lamination process.
  • the processing difficulty of the battery sheet 100 is greatly reduced (for example, it is not necessary to process the openings on the silicon wafer 1 and inject a conductive medium into the openings). Process), which further increases the processing rate and reduces the processing failure rate and processing cost.
  • the side conductive member 3 is provided on one side surface in the width direction of the silicon substrate 11, the path of transferring charges from the light receiving side to the backlight side of the silicon wafer 1 can be effectively shortened, and the charge transfer rate can be improved. Thereby, the power of the battery chip 100 is increased in a disguised manner.
  • the first region and the second region are non-discrete regions, and there is no intersection and no contact with each other, and when the silicon wafer 1 is a rectangular sheet, the first region and the second region may both be rectangular regions. And spaced apart in the width direction of the silicon wafer 1.
  • the first electrode 4 and the backing layer 60 having a larger area may be processed, optionally, projected in the thickness direction of the silicon wafer 1, The outer edge of the first electrode 4 falls on the outline of the first region, the backing layer 60 is covered on the second region, and the second electrode 5 is disposed on the backing layer 60.
  • the first region and the second region can be utilized to the maximum, and the power of the battery sheet 100 can be improved.
  • the "outer edge” refers to its outline, and for the linear member ( For example, in the case of a fine grid line as described herein, the "outer edge” refers to the ends of its ends.
  • the front gate line layer 2 includes a plurality of front sub-gate line layers 21 extending in a direction perpendicular to the length of the side conductive members 3, that is, each of the front sub-gate line layers 21 is perpendicular to the length direction of the side conductive members 3.
  • the charge transfer path of the front sub-gate line layer 21 can be shortened, the charge transfer efficiency can be improved, and the power of the cell sheet 100 can be improved.
  • Step a1 aliquoting a square conventional silicon substrate body (for example, a conventional silicon substrate having a size of 156 mm*156 mm) by laser and cutting into 3-15 parts (optionally 5-10 parts) of a rectangular sheet shape having a constant length
  • the silicon substrate 11 (for example, each having a length of 156 mm) is then subjected to a subsequent process of fabricating the cell 100.
  • a rectangular sheet-like silicon substrate 11 may be obtained by other means or processes.
  • the square conventional silicon substrate body can be divided into three or more parts, thereby shortening the distance that the electric charge migrates from the light receiving surface to the backlight surface, so that the charge collection is efficient and easy, thereby improving the battery sheet 100.
  • Power and, when the square conventional silicon substrate body is divided into fifteen parts and fifteen or less parts, the cutting process is easy, and the subsequent series-parallel cell sheet 100 consumes less solder, thereby improving the overallity of the cell sheets 100 after being connected in series and in parallel. Power, reduce costs.
  • Step a2 cleaning and texturing: cleaning and removing dirt on each surface of the silicon substrate 11, and the texturing reduces the reflectance of each surface of the silicon substrate 11;
  • Step a4 mask protection: using paraffin to protect the diffusion layer on the first region (that is, used as the back diffusion layer 14) and the diffusion layer on the side surface adjacent to the first region (ie, used as the side diffusion layer 13);
  • Step a5 etching: removing the side surface of the silicon substrate 11 and the back surface of the backlight surface that is not protected by paraffin;
  • Step a6 removing paraffin protection, removing the phosphosilicate glass, thereby obtaining the back diffusion layer 14 and the side diffusion layer 13 under paraffin protection;
  • Step a7 vapor deposition of the anti-reflection layer 101 on the front diffusion layer 12, the material of the anti-reflection layer 101 includes but is not limited to TiO2, Al2O3, SiNxOy, SiNxCy;
  • Step a8 screen printing the back electrode layer 60 in the longitudinal direction in the second region, screen printing the second electrode 5 on the back electrode layer 60 in the longitudinal direction, and screen printing the first electrode in the length direction on the back diffusion layer 14. 4, and drying, wherein the first electrode 4 coincides with the back diffusion layer 14, a certain safety distance between the backing layer 60 and the first electrode 4, to avoid short circuit;
  • Step a9 screen printing the gate line layer 2 on the front diffusion layer 12 in the width direction such that each of the gate line layers 2 is perpendicular to the second electrode 5, and dried;
  • step a10 the side conductive member 3 is screen printed on the side diffusion layer 13 in the longitudinal direction and dried.
  • the structure of the embodiment 2 is substantially the same as that of the embodiment 1, wherein the same components are given the same reference numerals, except that the second region in the embodiment 1 is provided with a backlight.
  • the second electrode 5 is disposed on the backing layer 60.
  • the second region is provided with a back diffusion layer 15 and the second diffusion layer 15 is provided with a second gate.
  • Layer 6 and second electrode 5 are provided in the second embodiment.
  • the battery sheet 100 includes: a silicon wafer 1, a front conductive member, a side conductive member 3, a first electrode 4, a back second gate line layer 6, and a second electrode 5, wherein the front conductive member is a front gate line layer 2, a silicon wafer 1 may include a silicon substrate 11, a front first diffusion layer 12, a back second diffusion layer 15, a side spacer 13, and a back spacer 14, wherein the side spacer 13 may be a front first diffusion layer 12 of the same type of side diffusion layer, the backside barrier layer 14 may be of the same type as the front first type of diffusion layer 12 of the first type of diffusion layer.
  • the back type second diffusion layer 15 includes a plurality of back surface second sub-gate lines 61 extending in a direction perpendicular to the length of the second electrode 5, that is, each of the back second sub-gate lines 61 is perpendicular to the first The length direction of the two electrodes 5.
  • the charge transfer path of the second sub-gate line layer 61 on the back surface can be shortened, the charge transfer efficiency can be improved, and the power of the cell sheet 100 can be improved.
  • the backlight surface of the silicon substrate 11 includes a first region and a second region, and the first region and the second region have no intersection and do not contact each other, that is, the contour of the first region and the contour of the second region. not in contact.
  • the back diffusion layer of the first type is disposed only on the first region, that is, the remaining surface of the backlight surface of the silicon substrate 11 except the first region does not have the first diffusion layer of the back surface, and further, the first type of the back surface
  • the diffusion layer is overlaid on the first region such that when the first region is a non-discrete continuous region, the back first diffusion layer may be non-discrete, i.e., continuously disposed on the silicon substrate 11.
  • the first type of diffusion layer on the back side is disposed continuously, that is, non-discretely on the silicon substrate 11, it is not discrete, that is, discontinuous, for example, discrete forms such as scatter, zebra strips, etc. are dispersed in the silicon.
  • the processing difficulty of the first type of diffusion layer on the back surface is greatly reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery sheet 100 can be effectively improved.
  • the back type second diffusion layer 15 is provided only on the second region, that is, the other surface than the second region on the backlight surface of the silicon substrate 11 does not have the back surface second diffusion layer 15. Further, the back type second diffusion layer 15 is covered on the second region, such that when the second region is a non-discrete continuous region, the back second diffusion layer 15 may be non-discrete, that is, continuously arranged on the silicon substrate. On the film 11. Thereby, since the back surface type second diffusion layer 15 is continuously, that is, non-discretely disposed on the silicon substrate 11, it is not discretely, that is, discontinuously, for example, scattered in the form of scatter, zebra strips, etc. On the silicon substrate 11, the processing difficulty of the second type diffusion layer 15 on the back surface is greatly reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery sheet 100 can be effectively improved.
  • the first electrode 4 is disposed on the back diffusion layer of the first type, that is, the first electrode 4 can be directly or indirectly disposed on the back diffusion layer of the first type. At this time, the first electrode 4 is disposed on the backlight of the silicon wafer 1. On the surface and corresponding to the first region, that is, projected in the thickness direction of the silicon wafer 1, the first electrode 4 does not exceed the first region.
  • the silicon wafer 1 may further include a passivation layer 102, which may be provided on the back diffusion layer of the first type. Thus, when the silicon wafer 1 includes the passivation layer 102, the first electrode 4 can be directly disposed on the passivation layer 102. In some embodiments of the present disclosure, when the silicon wafer 1 does not include the passivation layer 102, the first electrode 4 may be directly disposed on the back diffusion layer of the first type.
  • the second gate line layer 6 and the second electrode 5 on the back surface are respectively disposed on the back diffusion layer 15 of the second type, that is, the second gate line layer 6 and the second electrode 5 on the back surface may be directly or indirectly disposed on the back side of the second type.
  • the back second gate line layer 6 and the second electrode 5 are disposed on the backlight surface of the silicon wafer 1 and opposed to the second region, that is, projected in the thickness direction of the silicon wafer 1, and the back surface
  • the second gate line layer 6 and the second electrode 5 do not extend beyond the second region.
  • the first electrode 4 is neither in contact with the second gate line layer 6 on the back surface nor in contact with the second electrode 5.
  • the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the back type second diffusion layer 15.
  • the back second gate line layer 6 and the second electrode 5 may be directly disposed on the passivation layer 102.
  • the back second gate line layer 6 and the second electrode 5 may be directly disposed on the back surface second type diffusion layer 15.
  • the second gate line layer 6 and the second electrode 5 on the back surface may be non-overlapping and in contact with each other.
  • the second gate line layer 6 and the second layer on the back surface The electrodes 5 are respectively disposed on the backlight surface of the silicon wafer 1 and the edges are directly in contact with the electrical connection, so that the space can be utilized to improve the power of the battery sheet 100.
  • the second gate line layer on the back surface The second electrode 5 and the second electrode 5 may also be stacked on each other. At this time, the surface of the back surface of the second gate line layer 6 and the second electrode 5 after being stacked on both sides is disposed on the backlight surface of the silicon wafer 1.
  • the first electrode 4 having a larger area can be processed, so that the second gate line layer 6 and the second electrode 5 having a larger area can be processed.
  • the film is projected along the thickness direction of the silicon wafer 1, the outer edge of the first electrode 4 falls on the contour line of the first region, and the outer edge of the entire second gate line layer 6 and the second electrode 5 falls on the second edge. The outline of the area.
  • the first region and the second region can be utilized to the maximum, and the power of the battery sheet 100 can be improved.
  • first type of diffusion layer and the “second type of diffusion layer” described herein are two different kinds of diffusion layers, when the conductive medium is provided (for example, directly or through the text)
  • the anti-reflection layer or the passivation layer is indirectly disposed on the first type of diffusion layer and the second type of diffusion layer, different kinds of charges can be collected.
  • the concepts of the anti-reflection layer and the passivation layer described herein are well known to those skilled in the art, and both of them mainly serve to reduce reflection and enhance charge collection.
  • the front first type of diffusion layer, the back side first type of diffusion layer, and the side first type of diffusion layer described herein in the "first type of diffusion layer” are the same type of diffusion layer, when the conductive medium is provided When collecting on the first type of diffusion layer, it can be collected The first type of charge; and the second type of diffusion layer in the "second type diffusion layer” is another type of diffusion layer, and when the conductive medium is disposed on the second type of diffusion layer, the second type can be collected. Charge.
  • the principle that the conductive medium collects charges on the silicon wafer should be well known to those skilled in the art and will not be described in detail herein.
  • the first type of diffusion layer may be a phosphorus diffusion layer, and the conductive medium disposed on the phosphorus diffusion layer may collect negative charges, and the second type of diffusion layer may be boron diffusion.
  • the layer, the conductive medium disposed on the boron diffusion layer can collect a positive charge.
  • the “first diffusion layer” may be a boron diffusion layer, and the “second diffusion layer” may be a phosphorus diffusion layer, which will not be described herein.
  • the front gate line layer 2 is provided on the first type of diffusion layer (for example, directly or through the anti-reflection layer 101), the front gate line layer 2 can collect the first type of charge (for example, a negative charge).
  • the second gate line layer 6 on the back surface is disposed on the second type of diffusion layer (for example, directly or through the passivation layer 102), so that the second gate line layer 6 on the back surface can collect the second type of charge (for example, positive Charge).
  • the first electrode 4 is electrically connected to the front gate line layer 2 through the side conductive members 3, so that the first type of charge (eg, negative charge) collected by the front gate line layer 2 can be transferred to the first electrode 4 (eg, the negative electrode).
  • the second electrode 5 is electrically connected to the back second gate line layer 6, so that the second kind of charge (for example, positive charge) collected by the back second gate line layer 6 can be transferred to the second electrode 5 (for example, the positive electrode).
  • the first electrode 4 and the second electrode 5 can output electric energy as positive and negative poles of the battery sheet 100.
  • the first electrode 4 can collect the first type of charge through the front gate line layer 2 on the light receiving side of the silicon wafer 1
  • the second electrode 5 can collect the second layer by the second gate line layer 6 on the back side of the wafer 1 backlight side.
  • the type of electric charge is effective to improve the space utilization rate, and further increase the power of the battery sheet 100, so that the battery sheet 100 can be an aesthetically pleasing and efficient double-sided battery.
  • the method for preparing the battery sheet 100 in the second embodiment is substantially the same as the method for preparing the battery sheet 1 in the first embodiment, except that when the silicon wafer 1 in the second embodiment is prepared,
  • the silicon substrate 11 is subjected to different types of diffusion on both sides, even if the light-receiving surface and the backlight surface of the silicon substrate 11 are respectively diffused by diffusion layers of different types, and the diffusion layer on the light-receiving surface is extended from one side surface of the silicon substrate 11.
  • the passivation layer 102 of the same material as that of the anti-reflection layer 101 is evaporated on the diffusion-like layer 15 and the silicon substrate 11, and then the second gate line layer 6 on the back surface is screen-printed on the passivation layer 102.
  • the structure of the embodiment 3 is substantially the same as that of the embodiment 2, wherein the same components are given the same reference numerals, except that the first region and the second region in the embodiment 2 are absent.
  • the intersections of the first region and the second region in the third embodiment do not intersect and contact each other, that is, the contour of the first region is in contact with the contour of the second region.
  • the first region and the second region have no intersection and are in contact with each other, and the first electrode 4 is disposed on the first region, that is, the first electrode 4 can be directly or indirectly disposed on the first region.
  • An electrode 4 is provided on the backlight surface of the silicon wafer 1 and corresponds to the first region, that is, projected in the thickness direction of the silicon wafer 1, and the first electrode 4 does not extend beyond the first region and is located outside the second region.
  • the second gate line layer 6 and the second electrode 5 on the back surface are both disposed on the second region and are not in contact with the first electrode 4, that is, the second gate line layer 6 and the second electrode 5 on the back surface may be directly or indirectly provided.
  • the second gate line layer 6 and the second electrode 5 on the back surface Provided on the backlight surface of the silicon wafer 1 and corresponding to the second region, that is, projected in the thickness direction of the silicon wafer 1, the second gate line layer 6 and the second electrode 5 on the back surface do not exceed the second region and are located at the Outside an area. Thereby, the short circuit caused by the contact of the first electrode 4 and the second electrode 5 can be effectively avoided.
  • the structure of the embodiment 4 is substantially the same as that of the embodiment 3, wherein the same components are given the same reference numerals, except that the side spacer 13 in the embodiment 3 is the first side.
  • the diffusion-like layer and the back spacer 14 are the first diffusion layers on the back side, and the side spacers 13 and the back spacers 14 in the fourth embodiment are both insulating layers.
  • the method for preparing the battery sheet 100 in the fourth embodiment is substantially the same as the method for preparing the battery sheet 1 in the second embodiment, except that when the silicon wafer 1 in the fourth embodiment is prepared,
  • the silicon substrate 11 is diffused by different types on both sides, and even if the light-receiving surface and the backlight surface of the silicon substrate 11 are respectively diffused into different types of diffusion layers, the front-side diffusion layer 12 and the second diffusion layer 15 on the back surface are obtained.
  • an insulating layer is processed on one side of the backlight surface of the silicon substrate 11 and the side surface adjacent to the side to obtain the back surface layer 14 and the side spacer layer 13.
  • the structure of the embodiment 5 is substantially the same as that of the embodiment 3, wherein the same components are given the same reference numerals, except that the first type of diffusion on the back side of the first embodiment 3 is Only the first electrode 4 is disposed on the layer (ie, the back surface layer 14), and the back surface of the first type of diffusion layer (ie, the back surface layer 14) in the fifth embodiment is further provided with a back surface electrically connected to the first electrode 4.
  • the first region and the second region in the fifth embodiment are in a contact finger cross distribution.
  • the first gate line layer 7 and the first electrode 4 are disposed on the back diffusion layer of the first type, that is, the surface of the first gate line and the first electrode 4 may be directly or indirectly disposed on the diffusion layer of the first type on the back surface.
  • the back first gate line layer 7 and the first electrode 4 are disposed on the backlight surface of the silicon wafer 1 and correspond to the first region, that is, projected in the thickness direction of the silicon wafer 1, and the first gate on the back surface
  • the wire layer 7 and the first electrode 4 do not extend beyond the first region and are located outside the second region.
  • the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the back diffusion layer of the first type.
  • the back first gate line layer 7 and the first electrode 4 may be directly disposed on the passivation layer 102.
  • the back first gate line layer 7 and the first electrode 4 may be directly disposed on the back type first diffusion layer.
  • the back first gate line layer 7 and the first electrode 4 may be non-overlapping and in contact with each other.
  • the back first gate line layer 7 and the first The electrodes 4 are respectively disposed completely on the backlight surface of the silicon wafer 1 and the edges are in direct contact with the electrical connection, so that the space can be utilized to improve the power of the battery sheet 100; in still other embodiments of the present disclosure, the first gate line layer on the back side 7 and the first electrode 4 may also be stacked on each other. At this time, the surface of the back surface of the first gate line layer 7 and the first electrode 4 after being stacked on both sides is disposed on the backlight surface of the silicon wafer 1.
  • the front gate line layer 2 and the back surface first gate line layer 7 connected to the first electrode 4 are respectively processed on the light receiving surface and the backlight surface of the silicon wafer 1, and passed through the silicon
  • the backlight surface of the sheet 1 processes the back second gate line layer 6 connected to the second electrode 5, so that the battery sheet 100 can be a double-sided battery with higher power.
  • the first area and the second area are in a contact-shaped cross-shaped distribution, that is, the contour of the first area is in contact with the contour of the second area, for example, the first area and the second area may be completely seamlessly interposed, Form a continuous, complete, non-porous non-discrete area.
  • the first region and the second region may be covered with the backlight surface of the silicon substrate 11. Thereby, the space can be utilized and the power of the battery sheet 100 can be improved.
  • the "finger cross shape” refers to a shape in which the fingers of the left and right hands cross each other without overlapping.
  • the first area includes a first communication area and a plurality of first dispersion areas, and the plurality of first dispersion areas are spaced apart in the longitudinal direction of the first connection area and both communicate with the first communication area
  • the second area includes a second communication region and a plurality of second dispersion regions, the plurality of second dispersion regions being spaced apart in the longitudinal direction of the second communication region and each communicating with the second communication region.
  • the number of the plurality of first dispersion regions and the plurality of second dispersion regions is not limited, and the shapes of the first communication region, the plurality of first dispersion regions, the second communication region, and the plurality of second dispersion regions are not limited.
  • the plurality of first dispersion regions and the plurality of second dispersion regions may each be formed into a triangle, a semicircle, a rectangle, or the like, and the plurality of first dispersion regions and the plurality of second dispersion regions may be formed into a rectangular shape, a wavy band shape, or the like. Wait.
  • the first connected area is opposite to the second connected area, for example, the first connected area and the second connected area are parallel or substantially parallel (having a small angle), the plurality of first dispersed areas and the plurality of second dispersed
  • the region alternates between the first connected region and the second connected region, that is, sequentially arranges a first dispersed region along the length direction of the first connected region, that is, along the length direction of the second connected region.
  • a second dispersed region, a further first dispersed region, and a second dispersed region, and so on, the plurality of first dispersed regions and the plurality of second dispersed regions are alternately alternately alternately distributed.
  • the contour line of the first communication region is in contact with the contour line of the plurality of second dispersion regions, and the contour line of the second communication region is in contact with the contour lines of the plurality of first dispersion regions, respectively. Thereby, it can be ensured that the first area and the second area are arranged in a contact finger cross arrangement.
  • the first electrode 4 is disposed on the first communication region, and the back first gate line layer 7 is disposed on the plurality of first dispersion regions.
  • the first electrode 4 is disposed corresponding to the first communication region, and the first gate line layer 7 on the back side and the plurality of first points
  • the scattered area is set accordingly. That is, projected in the thickness direction of the silicon wafer 1, the first electrode 4 does not exceed the outline of the first connected region, and the back first gate line layer 7 does not exceed the outline of the plurality of first dispersed regions and is located in the second region. Outside the outline. Thereby, the layout of the first electrode 4 and the back first gate line layer 7 is reasonable and simple, and it is easy to process on the back diffusion layer of the first type.
  • the back first gate line layer 7 includes a plurality of back first sub-gate line layers 71 extending perpendicular to the length of the first via region and spaced apart in the length direction of the first via region.
  • the back first gate line layer 7 can transfer the collected charges to the first electrode 4 in a shorter path, thereby improving the charge transfer efficiency and increasing the power of the cell sheet 100.
  • the second electrode 5 is disposed on the second communication region, and the second gate line layer 6 on the back surface is disposed on the plurality of second dispersion regions.
  • the second electrode 5 is disposed corresponding to the second communication region, and the second gate line layer 6 on the back surface is disposed corresponding to the plurality of second dispersion regions. That is, projected in the thickness direction of the silicon wafer 1, the second electrode 5 does not exceed the outline of the second communication region, and the second gate line layer 6 on the back side does not exceed the outline of the plurality of second dispersion regions and is located in the first region. Outside the outline.
  • the layout of the second electrode 5 and the second gate line layer 6 on the back surface is rational and simple, and it is easy to process on the back diffusion layer 15 of the second type.
  • the back second gate line layer 6 includes a plurality of back second sub-gate lines 61 extending in a length direction perpendicular to the second via region and spaced apart in the length direction of the second via region.
  • the back second gate line layer 6 can transfer the collected charges to the second electrode 5 in a shorter path, thereby improving the charge transfer efficiency and increasing the power of the cell sheet 100.
  • the contour line of each of the back first sub-gate line layers 71 is not in contact with the second communication region and the plurality of second dispersion regions, that is, each of the back first sub-gate line layer 71 and the back second portion
  • the gate line layer 61 and the second electrode 5 are not in contact.
  • the contour line of each of the back second sub-gate line layers 61 is not in contact with the first communication region and the plurality of first dispersion regions, that is, each of the back second sub-gate line layer 61 and the back first portion
  • the gate line layer 71 and the first electrode 4 are not in contact.
  • the method for preparing the battery sheet 100 in the embodiment 5 is substantially the same as the method for preparing the battery sheet 1 in the second embodiment, except that after the silicon wafer 1 is prepared, the second type is on the back side.
  • the back second sub-gate line layer 61 is processed on the diffusion layer 15.
  • the structure of the embodiment 6 is substantially the same as that of the embodiment 5, wherein the same components are given the same reference numerals, except that the first region and the second region in the embodiment 5 are formed.
  • the contact type refers to a cross distribution, and the first area and the second area in the present embodiment 6 are non-contact type cross-distribution.
  • the contour line of the first communication region is not in contact with the contour line of the second communication region and the contour lines of the plurality of second dispersion regions, and the contour line of the second communication region and the contour line of the first communication region and the plurality of first dispersions
  • the outline of the area is not in contact. Thereby, it can be ensured that the first region and the second region are not in the form of a cross-reference of the contact fingers.
  • the first child on each back The outline of the gate line layer 71 is not in contact with both the second communication region and the second dispersion region, that is, each of the back first sub-gate line layer 71 and the back second sub-gate line layer 61 and the second electrode 5 not in contact.
  • each of the back second sub-gate line layers 61 is not in contact with the first communication region and the first dispersion region, that is, each of the back second sub-gate line layer 61 and the back first sub-gate line Both the layer 71 and the first electrode 4 are not in contact.
  • the structure of the present embodiment 7 is substantially the same as that of the embodiment 5, wherein the same components are given the same reference numerals, except that the second region in the embodiment 5 is covered with the back surface.
  • the second type of diffusion layer 15 is not provided with the second type of diffusion layer on the second region in the seventh embodiment.
  • the second electrode 5 and the back second gate line layer 6 may be disposed directly or indirectly on the second region.
  • the second region may be covered with a passivation layer 102, and the second gate line layer 6 and the second electrode 5 may be directly disposed on the passivation layer 102.
  • the back second gate line layer 6 and the second electrode 5 may be directly disposed on the second region.
  • the terms “installation”, “connected”, “connected”, “fixed”, and the like, are to be understood broadly, and may be directly connected or intermediate. Indirectly connected, it can be the internal communication of two components or the interaction of two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features pass through an intermediate medium, unless otherwise explicitly stated and defined. Indirect contact.

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Abstract

一种电池片组件、电池片矩阵和太阳能电池组件，电池片组件(100A)包括：沿纵向依次排布的多个电池片(100)和导电带(1001)，每个电池片(100)均包括硅片(1)、设在硅片(1)受光面上的正面导电件(2)、设在硅片(1)背光面上的两个电极(4，5)、以及设在硅片(1)侧表面上且电连接在正面导电件(2)和一个电极(4)之间的侧面导电件(3)，其中，两个电极(4，5)均沿横向延伸且在纵向上间隔开分布，导电带(1001)与电极(4，5)的延伸方向相同、且与彼此靠近且分别位于相邻两个电池片(100)上的两个电极(4，5)电连接以使相邻的两个电池片(100)串联或并联。

Description

电池片组件、电池片矩阵和太阳能电池组件 技术领域
本公开涉及太阳能电池技术领域，尤其是涉及一种电池片组件、电池片矩阵和太阳能电池组件。
背景技术
相关技术中的晶体硅太阳能电池片，背光面和受光面分别有2-3根银主栅线作为电池片的正负极，这些银主栅线不仅消耗大量的银浆，而且因为遮挡入射光从而造成了电池片的效率下降。另外，由于正负极分别分布在电池片的背光面和受光面上，当电池片串联时，需要采用导电带将电池片受光面的负电极焊接到相邻电池片背光面的正电极上，从而造成焊接工艺繁琐，焊接材料使用较多的问题。而且，焊接时和后续层压工艺中电池片及导电带容易破损。
另外，相关技术中的电池片矩阵通常是由72片或者60片电池片依次串联组成，构成六串电池串组成的三个回路，此时，一般至少需要三个二极管，以使每个回路上设置一个二极管进行旁路保护，由于二极管通常设置于电池的接线盒内，从而增加了集成接线盒的成本，致使电池的结构复杂性提高。而且，当由多个电池片串联而成的串联组件再次进行串联时，连接电缆用量很大，材料浪费很多，致使电站成本增高。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一。为此，本公开在于提出一种电池片组件，所述电池片组件的功率高。
本公开还提出一种具有上述电池片组件的电池片矩阵。
本公开还提出一种具有上述电池片矩阵的太阳能电池组件。
根据本公开第一方面的电池片组件，包括：沿纵向依次排布的多个电池片，每个所述电池片均包括硅片、设在所述硅片受光面上的正面导电件、设在所述硅片背光面上的两个电极、以及设在所述硅片侧表面上且电连接在所述正面导电件和两个电极中的一个之间的侧面导电件，其中，两个所述电极均沿横向延伸且在所述纵向上间隔开分布；导电带，所述导电带与所述电极的延伸方向相同、且与彼此靠近且分别位于相邻两个所述电池片上的两个所述电极电连接以导通位于相邻两个所述电池片上的两个所述电极，使相邻的两个所 述电池片串联或并联。
根据本公开的电池片组件，可以有效地降低导电带的使用长度，减少导电带的使用量，降低导电带引发的热效应，提高电池片组件的整体功率。
在一些实施例中，在所述导电带的延伸方向上，所述导电带的延伸长度大于等于由所述导电带导通的每个所述电极的延伸长度，且所述导电带的两端分别超出于或平齐于由所述导电带导通的每个所述电极的相应端。
在一些实施例中，在垂直于所述导电带延伸方向的方向上，所述导电带的跨度大于等于由所述导电带导通的两个所述电极的跨度之和，且所述导电带的两侧边分别超出于或平齐于由所述导电带导通的两个所述电极彼此远离的两侧边。
在一些实施例中，所述导电带包括结构相同且在垂直于所述导电带延伸方向上依次布置的两个半部，两个所述半部恰好分别覆盖由所述导电带导通的两个所述电极。
在一些实施例中，在垂直于所述导电带延伸方向的方向上，相邻的两个所述电池片之间的间隙小于等于0.1mm。
在一些实施例中，所述硅片在垂直于所述侧面导电件所在侧表面方向上的跨度为20mm-60mm。
在一些实施例中，所述硅片为长方形片体且由正方形常规硅片本体按照长度不变的规则分割而成。
在一些实施例中，所述硅片为长方形片体，每个所述电池片上的两个所述电极分别贴靠所述硅片的两条长边设置且均沿所述硅片的长度方向延伸，所述侧面导电件设在所述硅片的一个长边侧表面上。
在一些实施例中，每个所述电池片上的两个所述电极分别为与所述侧面导电件电连接的第一电极和非与所述侧面导电件电连接的第二电极，所述硅片包括：硅基片、正面第一类扩散层以及背面隔层，其中，所述硅基片的背光面包括第一区域和第二区域，所述正面第一类扩散层设在所述硅基片的受光面上，所述正面导电件设在所述正面第一类扩散层上，所述背面隔层仅设在且布满在所述第一区域上，所述第一电极设在所述背面隔层上，所述第二电极设在所述第二区域上且与所述第一电极不接触，其中，所述背面隔层的至少部分为绝缘层或与所述正面第一类扩散层类型相同的扩散层。
在一些实施例中，所述硅片还包括：侧面隔层，所述侧面隔层设在所述硅基片的侧表面上，所述侧面导电件设在所述侧面隔层上，所述侧面隔层的至少部分为绝缘层或与所述正面第一类扩散层类型相同的扩散层。
在一些实施例中，每个所述电池片还包括：背电层，所述背电层设在所述第二区域上，所述第二电极设在所述背电层上且与所述背电层电连接。
在一些实施例中，每个所述电池片还包括：背面第二栅线层，所述背面第二栅线层和所述第二电极均设在所述第二区域上，且所述第二电极与所述背面第二栅线层电连接且互不叠置。
在一些实施例中，所述硅片还包括与所述正面第一类扩散层类型不同的背面第二类扩散层，所述背面第二类扩散层仅设在且布满在所述第二区域上，所述背面第二栅线层和所述第二电极均设在所述背面第二类扩散层上。
在一些实施例中，每个所述电池片还包括：背面第一栅线层，所述背面第一栅线层和所述第一电极均设在所述背面隔层上，且所述第一电极与所述背面第一栅线层电连接且互不叠置。
在一些实施例中，所述背面隔层为与所述正面第一类扩散层类型相同的背面第一类扩散层，所述背面第一类扩散层仅设在且布满在所述第一区域上，所述背面第一栅线层和所述第一电极均设在所述背面第一类扩散层上。
在一些实施例中，所述第一区域与所述第二区域均为非离散区域。
在一些实施例中，所述第一区域与所述第二区域呈指交叉形分布，其中，所述第一区域包括第一连通区域和多个第一分散区域，多个所述第一分散区域在所述第一连通区域的长度方向上间隔开且均与所述第一连通区域连通，所述第二区域包括第二连通区域和多个第二分散区域，多个所述第二分散区域在所述第二连通区域的长度方向上间隔开且均与所述第二连通区域连通，其中，所述第一连通区域与所述第二连通区域平行设置，多个所述第一分散区域和多个所述第二分散区域在所述第一连通区域和所述第二连通区域之间一一交替。
根据本公开第二方面的电池片矩阵，由多个电池片并联组件串联而成，其中，每个所述电池片并联组件由多个电池片串联组件并联而成，其中，每个所述电池片串联组件均为根据本公开第一方面的电池片组件，每个所述电池片组件中的多个所述电池片由所述导电带依次串联。
根据本公开的电池片矩阵，通过设置上述第一方面的电池片组件，从而提高了电池片矩阵的整体功率。
在一些实施例中，所述电池片并联组件为两个，每个所述电池片并联组件包括三个所述电池片串联组件。
根据本公开第三方面的太阳能电池组件，包括从受光侧到背光侧依次设置的第一面板、第一粘结层、电池、第二粘结层以及第二面板，其中，所述电池为根据本公开第一方面的电池片组件或根据本公开第二方面的电池片矩阵。
根据本公开的太阳能电池组件，通过设置上述第二方面的电池片矩阵或上述第一方面 的电池片组件，从而提高了太阳能电池组件的整体性能。
本公开的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
图1是根据本公开实施例的电池片组件的示意图；
图2是图1中所示的电池片组件去除导电带的示意图；
图3是根据本公开实施例的电池片矩阵的示意图；
图4是图3中所示的电池片矩阵的电路示意图。
图5是根据本公开实施例1的电池片受光侧示意图；
图6是图5中所示的电池片的背光侧的示意图；
图7是图5中所示的电池片的一个侧面的示意图；
图8是两个图6中所示的电池片采用导电带相连的示意图；
图9是图8中所示的两个电池片去除导电带的示意图；
图10是根据本公开实施例2的电池片受光侧示意图；
图11是图10中所示的电池片的背光侧的示意图；
图12是图10中所示的电池片的一个侧面的示意图；
图13是两个图11中所示的电池片采用导电带相连的示意图；
图14是图13中所示的两个电池片去除导电带的示意图；
图15是根据本公开实施例3的电池片受光侧示意图；
图16是图15中所示的电池片的背光侧的示意图；
图17是图15中所示的电池片的一个侧面的示意图；
图18是两个图16中所示的电池片采用导电带相连的示意图；
图19是图18中所示的两个电池片去除导电带的示意图；
图20是根据本公开实施例4的电池片受光侧示意图；
图21是图20中所示的电池片的背光侧的示意图；
图22是图20中所示的电池片的一个侧面的示意图；
图23是两个图21中所示的电池片采用导电带相连的示意图；
图24是图23中所示的两个电池片去除导电带的示意图；
图25是根据本公开实施例5的电池片受光侧示意图；
图26是图25中所示的电池片的背光侧的示意图；
图27是图25中所示的电池片的一个侧面的示意图；
图28是图25中所示的电池片的另一个侧面的示意图；
图29是图26中所示的电池片的背光侧的制备过程图；
图30是两个图26中所示的电池片采用导电带相连的示意图；
图31是图30中所示的两个电池片去除导电带的示意图；
图32是根据本公开实施例6的电池片受光侧示意图；
图33是图32中所示的电池片的背光侧的示意图；
图34是图32中所示的电池片的一个侧面的示意图；
图35是图32中所示的电池片的另一个侧面的示意图；
图36是图33中所示的电池片的背光侧的制备过程图；
图37是两个图33中所示的电池片采用导电带相连的示意图；
图38是图37中所示的两个电池片去除导电带的示意图；
图39是根据本公开实施例7的电池片受光侧示意图；
图40是图39中所示的电池片的背光侧的示意图；
图41是图39中所示的电池片的一个侧面的示意图；
图42是图39中所示的电池片的另一个侧面的示意图；
图43是图40中所示的电池片的背光侧的制备过程图；
图44是两个图40中所示的电池片采用导电带相连的示意图；
图45是图44中所示的两个电池片去除导电带的示意图。
附图标记：
电池片串联组件1000；电池片并联组件2000；电池片矩阵10000；
导电带1001；汇流条1002；电池片组件100A；
电池片100；电池片A；电池片B；电极A1；电极A2；电极B1；电极B2；
硅片1；硅基片11；减反层101；钝化层102；
正面第一类扩散层12；侧面隔层13；背面隔层14；背面第二类扩散层15；
正面栅线层2；正面子栅线21；
侧面导电件3；第一电极4；第二电极5；
背面第二栅线层6；背面第二子栅线61；背电层60；
背面第一栅线层7；背面第一子栅线71。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描 述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下文提供了许多不同的实施例或例子用来实现本公开的不同结构。为了简化本公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本公开。此外，本公开可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本公开提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用性和/或其他材料的使用。
下面参考附图1-图45描述根据本公开第一方面实施例的电池片组件100A。
根据本公开第一方面实施例的电池片组件100A，包括：至少两个电池片100和至少一个导电带1001。其中，电池片100为背接触式太阳能电池片。
在一个实施例中，每个电池片100均包括硅片1、设在硅片1受光面上的正面导电件(例如下文所述的正面栅线层2)、设在硅片1背光面上的两个电极(例如下文所述的第一电极4和第二电极5)、以及设在硅片1侧表面上且电连接在正面导电件和两个电极中的一个之间的侧面导电件3，其中，两个电极为极性相反且互不接触的正电极和负电极。这样，当硅片1的受光面受光照射时，正面导电件可以从硅片1的受光面收集一个种类的电荷并通过侧面导电件3传递给与其电连接的两个电极中的一个，另外一个电极在硅片1的背光面侧获得另一个种类的电荷，由此两个电极可以输出电能。
在一个实施例中，多个电池片100的受光面均朝向同一侧、例如均面向太阳，且背光面均朝向同一侧、例如均背向太阳的方式沿纵向依次排列。每个电池片100上的两个电极均沿横向延伸且在纵向上间隔开分布，以确保两个电极互不接触避免短路。需要说明的是，本文中所述的“电极的延伸方向”指的是电极的长度方向，下文所述的“导电带1001的延伸方向”指的是导电带1001的长度方向。这里，需要说明的是，本文中所述的“横向”指的是横向线的延伸方向、例如图1和图2中所示的水平方向，“纵向”指的是纵向线的延伸方向、例如图1和图2中所示的竖直方向，横向线与纵向线为相互垂直的直线；另外，“沿横向延伸”当作广义理解，即应当包括“沿与横向线平行的方向延伸”和“沿与横向线成夹角小于45°的方向延伸”。
在一个实施例中，导电带1001与电极的延伸方向相同以与电极充分电连接，提高导电效率，其中，导电带1001与彼此靠近且分别位于相邻两个电池片100上的两个电极电连接导通位于相邻两个所述电池片上的两个所述电极，以使相邻的两个电池片100串联或并联。这里，为了清楚表达，举例说明，参照图1和图2，假设相邻的两个电池片100分别为电池片A和电池片B，电池片A上具有沿纵向间隔开的电极A1和电极A2，电池片B上具有沿纵向间隔开的电极B1和电极B2，当电池片A和电池片B沿纵向依次排列时，电极A1、电 极A2、电极B1和电极B2沿纵向依次排列，此时，电极A2和电极B1彼此靠近，电极A1和电极B2彼此远离，此时，导电带1001与电极A2和电极B1电连接以将电极A2和电极B1导通，此时，当电极A2和电极B1的极性相同(即均为正电极或均为负电极)时，电池片A和电池片B可以并联，而当电极A2和电极B1的极性不同(即一个为正电极、另一个为负电极)时，电池片A和电池片B可以串联。
下面，仅以图1和图2中所示的竖直方向为“纵向”，图1和图2中所示的水平方向为“横向”为例进行说明，当然，本领域技术人员在阅读了下面的技术方案后，显然可以理解其他方向为“纵向”的技术方案。另外，需要说明的是，本申请附图中所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
如图1和图2所示，多个电池片100在纵向上依次排列，其中，每个电池片100上的两个电极均沿横向延伸，且在纵向上间隔开分布，从而每个电池片100的上部和下部均分别具有一个电极，由此，除最上方的电池片100(例如电池片A)以外的其余电池片100(例如的电池片B)的上部电极(例如电极B1)与其上方的电池片100(例如电池片A)的下部电极(例如电极A2)彼此靠近且可以通过导电带1001导通，也就是说，除最下方的电池片100(例如电池片B)以外的其余电池片100(例如的电池片A)的下部电极(例如电极A2)与其下方的电池片100(例如电池片B)的上部电极(例如电极B1)彼此靠近且可以通过导电带1001导通。
由此，根据本公开实施例的电池片组件100A，可以有效地减小导电带1001的总面积，降低导电带1001引发的热效应，减少导电带1001的使用量，提高电池片组件100A的整体功率。其中，导电带1001可以为焊带。
下面，参考附图3和图4描述根据本公开第二方面实施例的电池片矩阵10000。
在一个实施例中，当电池片组件100A中的多个电池片100由导电带1001依次串联时，电池片组件100A为电池片串联组件1000。电池片矩阵10000由串联的多个电池片并联组件2000组成，其中每个电池片并联组件2000由多个电池片串联组件1000并联而成。也就是说，多个电池片串联组件1000首先并联而成多个电池片并联组件2000，多个电池片并联组件2000再串联而成电池片矩阵10000。由此，有效地增大了电池片矩阵10000的功率，而且不需要加入二极管进行旁路保护，减少了电池的成本，另外，正负接线盒可以分布在电池片矩阵10000的两侧，从而减少了相邻组件之间连接电缆的用量，降低了电站成本。
例如在本公开的一个实施例中，电池片并联组件2000为两个，每个电池片并联组件2000由三个电池片串联组件1000并联而成。也就是说，采用“先三并再两串”的方式将六个电池片串联组件1000组成电池片矩阵10000，即先将六个电池片串联组件1000三三 并联成两个电池片并联组件2000，然后将两个电池片并联组件2000串联成电池片矩阵10000。
这里，需要说明的是，相关技术中的电池片矩阵通常包括60个依次串联的电池片，其中，每10个电池片先串联成一个电池片串，6个电池片串再依次串联，从而60个电池片可以全部依次串联起来。当每个电池片的电压为0.5V时，串联在一起的60个电池片的电压就是30V，此时，如果有一个电池片串出了问题，那么整个电池片矩阵就无法正常工作了，所以就需要并联三个二极管，这样即使有一个电池片串出了问题，那么电路还是会通过并联的二极管形成回路，电池片矩阵还是可以继续正常工作的、不至于报废，只是功率小些而已。但是，一方面二极管的生产成本较高，另一方面由于二极管需设置于接线盒内，接线盒设置于电池板中间靠宽度方向的边缘，正负极通过接线盒引出，组件中使用的集成接线盒也提高了生产成本。另外，由于接线盒处于组件中央，在组件与组件进行串联时，连接电缆用量大，浪费材料，也增加了电站成本。
相较之，本文的电池片100的宽度可以为常规电池片宽度的1/4，此时，由10个电池片100串联成的电池片串联组件1000的总电压就是20V(即40×0.5V＝20V)，那么，将两个这样的电池片串联组件1000串联起来就可以达到40V的电压，从而可以有效地达到使用电压。另外，当采用上文所述的“先三并再两串”的方式构成电池片矩阵10000时，由于并联结构本身就可以对并联的旁路进行保护，从而就不需要另外再加入二极管进行旁路保护，减少了生产成本。另外，由于正负接线盒可以分布在电池片矩阵10000的两边，从而减少了组件与组件连接电缆的用量，进一步降低了电站成本。
下面描述根据本公开第三方面实施例的太阳能电池组件。
在一个实施例中，太阳能电池组件包括：从受光侧到背光侧依次设置的第一面板、第一粘结层、电池、第二粘结层以及第二面板。其中，电池可以为上述第一方面实施例的电池片组件100A，也可以为上述第二方面实施例的电池片矩阵10000。由此，太阳能电池组件的功率更好、能效更好、加工更加简便、成本更低。
下面描述根据本公开第四方面实施例的太阳能电池组件的制备方法。
首先，制备电池。
在一个实施例中，当电池为电池片组件100A时，可以首先采用导电带1001将相邻的两个电池片100串联或并联以得到电池片组件100A，然后再采用汇流条1002将电池片组件100A的正电极和负电极分别接出。
在一个实施例中，当电池为电池片矩阵10000时，可以首先采用导电带1001将相邻的两个电池片100串联以得到多个电池片串联组件1000，然后采用汇流条1002将多个电池片串联组件1000并联以得到多个电池片并联组件2000，接着采用汇流条1002将多个电池 片并联组件2000串联以得到电池片矩阵10000，最后采用汇流条1002将电池片矩阵10000的正电极和负电极分别接出。
接着，在上下方向上顺次铺设第一面板、第一粘结层、电池、第二粘结层以及第二面板以得到层压结构，然后将层压结构层压并封装即可。例如，可以先按照从下到上的顺序，依次铺设第一面板(例如玻璃)、第一粘结层(例如EVA)、电池、第二粘结层(例如EVA)、以及第二面板(例如电池背板或玻璃)以得到层压结构，接着，将前一步骤中的层压结构放入层压机层压，安装接线盒和边框，从而实现太阳能电池组件的封装及制作。
下面将参考附图1和图2、并结合图5-图45描述根据本公开多个实施例的电池片100。
在本公开的一个实施例中，在导电带1001的延伸方向上，导电带1001的延伸长度大于等于由导电带1001导通的每个电极的延伸长度，且导电带1001的两端分别超出于或平齐于由导电带1001导通的每个电极的相应端。但应注意的是，当导电带1001的两端分别超出于由导电带1001导通的每个电极的相应端时，导电带1001需要与每个硅片1上的与被该导电带1001导通的电极所携带电荷相反的导电介质保持一定安全距离，以避免同一硅片1上的两个电极短路。
例如在图1和图2所示的示例中，电极A2和电极B1均沿横向延伸，导电带1001也沿横向延伸，导电带1001在横向上的长度大于等于电极A2在横向上的长度、同时也大于等于电极B1在横向上的长度，导电带1001的在横向上的两端分别为左右两端，导电带1001的左端向左超出于或平齐于电极A2的左端、同时，导电带1001的左端也向左超出于或平齐于电极B1的左端，导电带1001的右端向右超出于或平齐于电极A2的右端、同时，导电带1001的右端也向右超出于或平齐于电极B1的右端，同时导电带1001的左右两端也要分别与电极A1、与电极A1电连接的导电介质、电极B2、以及与电极B2电连接的导电介质均保持一定安全距离，以避免电极A1和电极A2短路，同时避免电极B1和电极B2短路。由此，可以确保导电带1001与电极充分相连，减小导电带1001的总面积，降低导电带1001引发的热效应，减少导电带1001的使用量，提高电池片组件100A的整体功率。
在本公开的一个实施例中，在垂直于导电带1001延伸方向的方向上，导电带1001的跨度大于等于由导电带1001导通的两个电极的跨度之和，且导电带1001的两侧边分别超出于或平齐于由导电带1001导通的两个电极彼此远离的两侧边。但应注意的是，当导电带1001的两侧边分别超出于由导电带1001导通的两个电极彼此远离的两侧边时，导电带1001需要与每个硅片1上的与被该导电带1001导通的电极所携带电荷相反的导电介质保持一定安全距离，以避免同一硅片1上的两个电极短路。
例如在图1和图2所示的示例中，电极A2和电极B1均沿横向延伸，导电带1001也沿横向延伸，导电带1001在纵向上的宽度大于等于电极A2在纵向上的宽度和电极B1在纵向 上的宽度之和，导电带1001的在纵向上的两侧边分别为上下侧边，导电带1001的上侧边向上超出于或平齐于电极A2的上侧边、导电带1001的下侧边向下超出于或平齐于电极B1的下侧边，同时导电带1001的上下侧边也要分别与电极A1、与电极A1电连接的导电介质、电极B2、以及与电极B2电连接的导电介质均保持一定安全距离，以避免电极A1和电极A2短路，同时避免电极B1和电极B2短路。由此，可以确保导电带1001与电极充分相连，减小导电带1001的总面积，降低导电带1001引发的热效应，减少导电带1001的使用量，提高电池片组件100A的整体功率。
在本公开的一个可选实施例中，导电带1001包括结构相同且在垂直于导电带1001延伸方向上依次布置的两个半部，两个半部恰好分别覆盖由导电带1001导通的的两个电极。例如在图1和图2所示的示例中，导电带1001沿横向延伸且包括在纵向上依次布置的上半部和下半部，其中，上半部恰好覆盖电极A2，也就是说，上半部的外轮廓线与电极A2的外轮廓线重合，下半部恰好覆盖电极B1，也就是说，下半部的外轮廓线与电极B1的外轮廓线重合。由此，可以确保导电带1001与电极充分相连，减小导电带1001的总面积，降低导电带1001引发的热效应，减少导电带1001的使用量，提高电池片组件100A的整体功率。
可选地，在垂直于导电带1001延伸方向的方向上，相邻的两个电池片100之间的间隙小于等于0.1mm。也就是说，相邻的两个电池片100之间的间隙为0mm～0.1mm。例如在图1和图2所示的示例中，导电带1001沿横向延伸，电池片A和电池片B在纵向上依次布置，此时，电池片A的下边缘与电池片B的上边缘之间的距离为电池片A和电池片B之间的间隙。由此，当将相邻两个电池片100在垂直于导电带1001延伸方向上的间隙限定为小于等于0.1mm时，可以进一步减小导电带1001的总面积，降低导电带1001引发的热效应，减少导电带1001的使用量，提高电池片组件100A的整体功率，另外，当两个电池片100之间具有一定较小间隙时，可以避免由于电池片100的形状不规则或者操作误差而引起的相邻电池片100叠置问题。
在本公开的一些实施例中，硅片1在垂直于侧面导电件3所在侧表面方向上的跨度为20mm-60mm。也就是说，硅片1包括一组(两个)相对设置的侧表面，其中一个侧表面上设有侧面导电件3，这组侧表面之间的距离为20mm～60mm。例如在图1和图2所示的示例中，当硅片1为矩形片体、例如长方形片体、且侧面导电件3设在硅片1的一个长边侧表面上时，硅片1的宽度为20mm～60mm。例如在本公开的另一个示例中(图未示出该示例)，当硅片1为长方形片体、且侧面导电件3设在硅片1的一个宽边侧表面上时，硅片1的长度为20mm～60mm。
由此，可以缩短电荷从硅片1的受光面向背光面传输的路径，从而提高了电荷的传递 速率，进而提高了电池片100的功率。这里，需要说明的是，“矩形片体”当作广义理解，即不限于严格意义上的矩形片体，例如大体矩形片体、如四个顶角处具有圆角或倒角的矩形片体等也落入本公开的保护范围之内。由此，方便电池片100的加工，且方便电池片100与电池片100之间的连接。
可选地，硅片1为长方形片体，且由正方形常规硅片本体按照长度不变的规则分割(仅指“分开”而非特指“采取切割工艺”)而成。也就是说，由正方形规格硅片本体按照长度不变的方式可以分割成多个长方形片体状的硅片1，此时，每个硅片1的长度均与正方形规格硅片本体的长度相等、且多个硅片1的宽度之和与正方形规格硅片本体的宽度相等。
硅片1为长方形片体，两个电极分别贴靠硅片1的两条长边设置、以在硅片1的宽度方向上间隔开，且均沿硅片1的长度方向延伸，侧面导电件3设在硅片1的一个长边侧表面上、即设在硅片1宽度方向上的一侧侧表面上。由此，电荷的传输路径更短，电池片100的功率更高，且电池片100的加工更加简便，更加便于电池片100与电池片100之间的连接。
可选地，两个电极均可以为矩形片体且长度与硅片1的长度相等，从而每个电极的两条宽边和一条长边可以分别与硅片1的两条宽边和一条长边对齐，进而可以充分地利用空间，提高电池片100的功率，且方便后续电池片100与电池片100的连接。另外，侧面导电件3也可以构造为片体状且占满硅片1宽度方向上的一侧侧表面上，从而可以提高电池片100的功率。当然，侧面导电件3和电极的具体结构不限于此，例如，侧面导电件3和电极还可以分别由间隔开分布的多个子电极组成离散型的电极。
参照下文实施例1-实施例7，每个电池片100上的两个电极分别为与侧面导电件3电连接的第一电极4和非与侧面导电件3电连接的第二电极5，硅片1包括：硅基片11、正面第一类扩散层12以及背面隔层14，其中，硅基片11的背光面包括第一区域和第二区域，正面第一类扩散层12设在硅基片11的受光面上，正面导电件设在正面第一类扩散层12上，背面隔层14仅设在且布满在第一区域上，第一电极4设在背面隔层14上，第二电极5设在第二区域上且与第一电极4不接触，其中，背面隔层14的至少部分为绝缘层或与正面第一类扩散层12类型相同的扩散层。由此，电池片100的结构简单，便于加工和实现。
参照下文实施例1-实施例7，硅片1还包括：侧面隔层13，侧面隔层13设在硅基片11的侧表面上，侧面导电件3设在侧面隔层13上，侧面隔层13的至少部分为绝缘层或与正面第一类扩散层12类型相同的扩散层。参照下文实施例1，每个所电池片100还包括：背电层60，背电层60设在第二区域上，第二电极5设在背电层60上且与背电层60电连接。
参照下文实施例2-实施例7，每个所电池片100还包括：背面第二栅线层6，背面第 二栅线层6和第二电极5均设在第二区域上，且第二电极5与背面第二栅线层6电连接且互不叠置。进一步地，参照下文实施例2-实施例6，硅片1还包括与正面第一类扩散层12类型不同的背面第二类扩散层15，背面第二类扩散层15仅设在且布满在第二区域上，背面第二栅线层6和第二电极5均设在背面第二类扩散层15上。
参照下文实施例5-实施例7，每个电池片100还包括：背面第一栅线层7，背面第一栅线层7和第一电极4均设在背面隔层14上，且第一电极4与背面第一栅线层7电连接且互不叠置。进一步地，参照下文实施例5-实施例7，背面隔层14为与正面第一类扩散层12类型相同的背面第一类扩散层，背面第一类扩散层仅设在且布满在第一区域上，背面第一栅线层7和第一电极4均设在背面第一类扩散层上。
参照下文实施例1-实施例7，第一区域与第二区域均为非离散区域。也就是说，当将第一区域任意划分成多个子区域时，多个子区域都可以连通成一个连续的第一区域。当任意层仅设在且布满在第一区域上时，该任意层也为非离散层、即连续层；当将第二区域任意划分成多个子区域时，多个子区域都可以连通成一个连续的第二区域。当任意层仅设在且布满在第二区域上时，该任意层也为非离散层、即连续层。
参照下文实施例1-实施例4，第一区域与第二区域均为矩形区域以方便加工。参照下文实施例5-实施例7，第一区域与第二区域呈指交叉形分布，此时，第一区域包括第一连通区域和多个第一分散区域，多个第一分散区域在第一连通区域的长度方向上间隔开且均与第一连通区域连通，第二区域包括第二连通区域和多个第二分散区域，多个第二分散区域在第二连通区域的长度方向上间隔开且均与第二连通区域连通，其中，第一连通区域与第二连通区域平行设置，多个第一分散区域和多个第二分散区域在第一连通区域和第二连通区域之间一一交替。
实施例1
参照图5-图9，电池片100包括：硅片1、正面导电件、侧面导电件3、第一电极4、背电层60以及第二电极5，其中，正面导电件为正面栅线层2，硅片1可以包括硅基片11、正面第一类扩散层12、侧面隔层13、以及背面隔层14。
硅基片11为片体状，且硅基片11的厚度方向上的两个表面分别为受光面和背光面，受光面与背光面通过侧表面相连。其中，正面第一类扩散层12设在硅基片11的受光面上，例如在本公开的一个可选实施例中，正面第一类扩散层12布满在硅基片11的受光面上，从而降低了正面第一类扩散层12的加工难度，提高了加工效率，降低了加工成本。
侧面隔层13设在硅基片11的侧表面上，例如，侧面隔层13可以仅设在硅基片11的一个侧表面上、也可以同时设在多个侧表面上。可选地，侧面隔层13仅设在硅基片11的一个侧表面上且布满在该侧表面上。由此，方便侧面隔层13的加工和制造。
侧面导电件3设在侧面隔层13上，也就是说，侧面导电件3可以直接或者间接设在侧面隔层13上，此时，侧面导电件3设在硅片1的侧表面上且与侧面隔层13相对应，也就是说，沿垂直于侧面隔层13所在侧表面方向投影，侧面导电件3不超出侧面隔层13的轮廓线。
由于侧面导电件3设在硅片1的侧表面上，而并不是嵌设在硅片1的内部的，从而可以降低电池片100整体的加工难度、简化加工工艺、提高加工效率、降低加工成本。
硅基片11的背光面包括第一区域和第二区域，第一区域和第二区域无交集。其中，第一区域与第二区域可以互相接触或者互不接触，也就是说，第一区域的轮廓线与第二区域的轮廓线可以互相接触或者互不接触。例如，当背面隔层14的与背电层60相接触的部分为绝缘层时，第一区域和第二区域可以互相接触，而当背面隔层14的与背电层60相接触的部分为与正面第一类扩散层12类型相同的扩散层时，第一区域与第二区域可以互不接触。其中，第一区域和第二区域均为非离散型区域。
背面隔层14仅设在第一区域上，即硅基片11的背光面上的除第一区域以外的其余表面上都不具有背面隔层14，进一步地，背面隔层14布满在第一区域上，这样，当第一区域为非离散的连续区域时，背面隔层14可以非离散、即连续地布置在硅基片11上。由此，由于背面隔层14连续、即非离散地布置在硅基片11上，而并不是离散地、即不连续地，例如呈现散点状、斑马条状等离散形式散布在硅基片11上，从而极大地降低了背面隔层14的加工难度，提高了加工效率，降低了加工成本，且可以有效地提高电池片100的功率。
正面栅线层2设在正面第一类扩散层12上，也就是说，正面栅线层2可以直接或者间接设在正面第一类扩散层12上，此时，正面栅线层2设在硅片1的受光面上且与正面第一类扩散层12相对应，换言之，沿硅片1的厚度方向投影，正面栅线层2不超出正面第一类扩散层12的轮廓线。
硅片1还可以包括减反层101，减反层101可以设在正面第一类扩散层12上。这样，当硅片1包括减反层101时，正面栅线层2可以直接设在减反层101上。而当硅片1不包括减反层101时，正面栅线层2可以直接设在正面第一类扩散层12上。
第一电极4设在背面隔层14上，也就是说，第一电极4可以直接或者间接设在背面隔层14上，此时，第一电极4设在硅片1的背光面上且与第一区域相对应，换言之，沿硅片1的厚度方向投影，第一电极4不超出第一区域。例如，第一电极4还可以通过钝化层间接设在背面隔层14上。
背电层60和第二电极5均设在第二区域上，也就是说，背电层60和第二电极5可以直接或者间接设在硅基片11的背光面上的第二区域上，此时，背电层60和第二电极5设在硅片1的背光面上且与第二区域相对应，也就是说，沿硅片1的厚度方向投影，背电层 60和第二电极5不超出第二区域。例如，背电层60和第二电极5还可以通过钝化层间接设在硅基片11的背光面上。其中，第一电极4既不与背电层60接触、也不与第二电极5接触。
另外，需要说明的是，在本公开的一些实施例中，背电层60和第二电极5可以互不叠置且接触相连，此时，背电层60和第二电极5分别完全设在硅片1的背光面上且直接接触电连接，从而可以充分地利用空间，提高电池片100的功率；在本公开的另外一些实施例中，背电层60和第二电极5还可以相互叠置，此时，背电层60和第二电极5以其两者叠置后的并集表面设在硅片1的背光面上。
这里，需要说明的是，当将导电介质(直接或通过减反层、钝化层间接)设在正面第一类扩散层12上、或者(直接或通过减反层、钝化层间接)设在与正面第一类扩散层12类型相同扩散层(如下文所述的侧面第一类扩散层和背面第一类扩散层)上时，可以收集一个种类的电荷；而当将导电介质(直接或通过钝化层间接)设在硅基片11上的不具有正面第一类扩散层12的表面上、或者(直接或通过钝化层间接)设在与正面第一类扩散12类型相反的扩散层(例如下文所述的背面第二类扩散层)时，可以收集另一个种类的电荷。这里，需要说明的是，导电介质在硅片上收集电荷的原理应为本领域技术人员所熟知，这里不再详述。
另外，需要说明的是，本文实施例1-7中的硅片1的整个受光面和一个侧表面的最外层表面上可以均具有减反层，本文实施例2-7中的硅片1的整个背光面的最外层表面上还可以均具有钝化层，从而方便加工和制造。此外，需要说明的是，本文所述的减反层和钝化层的概念应为本领域技术人员所熟知，其主要起减少反射、加强电荷收集的作用。例如，减反层和钝化层的材料可以包括但不限于TiO2、Al2O3、SiNxOy、SiNxCy。
例如，当硅基片11为P型硅时，正面第一类扩散层12可以为磷扩散层，此时设置在磷扩散层上的导电介质可以收集负电荷，而设在非磷扩散层上的导电介质可以收集正电荷。这样，由于正面栅线层2设在(例如直接设在或通过减反层101间接设在)正面第一类扩散层12上，从而正面栅线层2可以收集第一种类的电荷(例如负电荷)。而背电层60设在(例如直接设在或通过钝化层间接设在)硅基片11的背光面上，从而正背电层60可以收集第二种类的电荷(例如正电荷)。
具体地，第一电极4通过侧面导电件3电连接至正面栅线层2，从而正面栅线层2收集的第一种类电荷(例如负电荷)可以传递给第一电极4(例如负电极)；第二电极5电连接至背电层60，从而背电层60收集的第二种类电荷(例如正电荷)可以传递给第二电极5(例如正电极)。由此，第一电极4和第二电极5可以作为电池片100的正负两极输出电能。另外，由于侧面导电件3设在硅片1的侧面，从而可以简单方便地通过侧面导电件3将正 面栅线层2和第一电极4有效地电连接在一起，确保电池片100工作的可靠性。
本领域技术人员可以理解的是，第一电极4与第二电极5需要为极性相反的电极，需要绝缘、即互不导通、相互之间不构成电连接，此时，第一电极4、以及与第一电极4电连接的所有部件与第二电极5、以及与第二电极5电连接的所有部件均不能直接导通、也不能通过任何外界导电介质间接导通，例如可以不接触或通过绝缘材料隔离开等，从而避免第一电极4与第二电极5短路。
背面隔层14构造成避免第一电极4通过硅基片11与第二电极5短路，也就是说，避免第一电极4与硅基片11直接接触造成短路，例如，背面隔层14可以为与正面扩散层类型相同的扩散层和/或绝缘层，即背面隔层14可以全部为与正面扩散层类型相同的扩散层，也可以全部为绝缘层，也可以一部分为与正面扩散层类型相同的扩散层、其余一部分为绝缘层。
当将第一电极4通过绝缘层设在硅基片11上时，第一电极4可以直接与硅基片11绝缘，避免第一电极4从硅基片11上收集与第二电极5收集的电荷类型相同的电荷，从而可以有效地避免第一电极4通过硅基片11与第二电极5导通导致短路，即避免第一电极4与硅基片11直接接触造成短路。
当将第一电极4通过与正面扩散层类型相同的扩散层设在硅基片11上时，第一电极4可以从扩散后的硅基片11上收集与正面栅线层2收集的电荷类型相同的电荷、即与第二电极5收集的电荷类型相反的电荷，从而也可以避免第一电极4与第二电极5短路，而且可以提高电池片100的功率。
其中，侧面隔层13构造成避免侧面导电件3通过硅基片11与第二电极5短路，从而避免第一电极4与第二电极5短路，即避免侧面导电件3与硅基片11直接接触造成短路。例如，侧面隔层13可以为与正面扩散层类型相同的扩散层和/或绝缘层，即侧面隔层13可以全部为与正面扩散层类型相同的扩散层，也可以全部为绝缘层，也可以一部分为与正面扩散层类型相同的扩散层、其余一部分为绝缘层。
当将侧面导电件3通过绝缘层设在硅基片11上时，侧面导电件3可以直接与硅基片11绝缘，避免侧面导电件3从硅基片11上收集与第二电极5收集的电荷类型相同的电荷，从而可以有效地避免侧面导电件3通过硅基片11与第二电极5导通导致短路，即避免侧面导电件3与硅基片11直接接触造成短路。
当将侧面导电件3通过与正面扩散层类型相同的扩散层设在硅基片11上时，侧面导电件3可以从扩散后的硅基片11上收集与正面栅线层2收集的电荷类型相同的电荷、即与第二电极5收集的电荷类型相反的电荷，从而也可以避免侧面导电件3与第二电极5的短路，即避免侧面导电件3与硅基片11直接接触造成短路，而且可以提高电池片100的功率。
具体地，在本公开的实施例中，侧面隔层13和背面隔层14中的至少一个的至少部分为与正面第一类扩散层12类型相同的扩散层，也就是说，要么侧面隔层13的至少部分为与正面第一类扩散层12类型相同的扩散层，要么背面隔层14的至少部分为与正面第一类扩散层12类型相同的扩散层，从而不但可以确保第一电极4与第二电极5的绝缘效果，还可以提高电池片100的功率。
可选地，背面隔层14全部为与正面第一类扩散层12类型相同的扩散层，即背面隔层14为布满在第一区域上的背面第一扩散层。由此，方便加工且绝缘可靠性好。可选地，侧面隔层13全部为与正面第一类扩散层12类型相同的扩散层，即侧面隔层13为布满在硅基片11的侧表面上的侧面扩散层。由此，方便加工且绝缘可靠性好。
这里，需要说明的是，硅基片、扩散层、减反层、钝化层等概念、以及导电介质从硅片上收集电荷的原理均为本领域技术人员所熟知，这里不再详述。
另外，在本公开的可选实施例中，正面栅线层2、以及后文所述的背面第二栅线层6、背面第一栅线层7均可以为由多条间隔开设置的可导电细栅线构成的导电介质层，其中，细栅线可以由银材构成，从而一方面可以提高导电速率，另一方面可以缩小遮光面积，从而变相增加电池片100的功率。背电层60可以为铝制层，即铝背场，从而一方面可以提高导电速率，另一方面可以降低成本。
综上，根据本公开实施例的电池片100，由于背面隔层14和侧面隔层13中的至少一个的至少部分为与正面第一类扩散层12类型相同的扩散层，从而不但可以确保第一电极4与第二电极5的绝缘，还可以有效地提高电池片100的功率。
而且，通过在硅基片11的侧面设置侧面导电件3，可以将现有电池片受光面上的第一电极由硅片的受光侧迁移至背光侧，以防止第一电极对硅片的受光侧遮光，从而本公开的电池片100的功率相较现有电池片更高。且本公开电池片100的第一电极4和第二电极5位于硅片1的同一侧，从而便于多个电池片100之间的电连接，降低焊接难度，减少焊料使用量，同时降低了焊接时及后续层压工艺中电池片100的破损几率。
另外，通过将侧面导电件3设在硅片1的侧表面上，从而极大地降低了电池片100的加工难度(例如无需在硅片1上加工开孔并向开孔内注入导电介质等加工工序)，进而提高了加工速率，降低了加工失败率和加工成本。另外，当将侧面导电件3设在硅基片11的宽度方向上的一侧侧表面上时，可以有效地缩短从硅片1的受光侧向背光侧传递电荷的路径，提高电荷传递速率，从而变相地提高了电池片100的功率。
可选地，当第一区域和第二区域均为非离散区域、且无交集、互不接触时，且当硅片1为长方形片体时，第一区域和第二区域可以均为矩形区域且在硅片1的宽度方向上间隔开布置。可以加工面积较大的第一电极4和背电层60，可选地，沿硅片1的厚度方向投影、 第一电极4的外边缘落在第一区域的轮廓线上，背电层60布满在第二区域上，第二电极5设在背电层60上。由此，可以最大化地利用第一区域和第二区域，提高电池片100的功率。这里，需要说明的是，对于面形部件(例如本文所述的矩形片体状的第一电极4和第二电极5)而言，“外边缘”指的是其轮廓线，对于线形部件(例如本文所述的细栅线)而言，“外边缘”指的是其两端端点。
正面栅线层2包括沿垂直于侧面导电件3长度方向延伸的多条正面子栅线层21，也就是说，每个正面子栅线层21均垂直于侧面导电件3的长度方向。由此，可以缩短正面子栅线层21的电荷传输路径，提高电荷传输效率，提高电池片100的功率。
下面，简要介绍本实施例1的电池片100的制备方法。
步骤a1、通过激光将正方形常规硅基片本体(例如规格为156mm*156mm的常规硅基片)等分并切割成3-15份(可选5-10份)长度不变的长方形片体状的硅基片11(例如长度均为156mm)，然后再进行后续的电池片100制作工序。当然，本公开不限于此，还可以采用其他方式或工艺获得长方形片体状的硅基片11。这里，需要说明的是，正方形常规硅基片本体可选均分成三份及三份以上，从而减短电荷由受光面向背光面迁移的距离，使电荷的收集高效容易，从而提高电池片100的功率，而且，当正方形常规硅基片本体均分成十五份及十五份以下时，容易切割加工，且后续串并联电池片100消耗的焊料较少，从而提高电池片100串并联后的整体功率，降低成本。
步骤a2、清洗制绒：清洗去除硅基片11各个表面的污垢，制绒降低硅基片11各个表面的反射率；
步骤a3、扩散制结：通过扩散炉对硅基片11进行双面扩散制备P-N结，使硅基片11的各个表面都具有同一类型的扩散层；
步骤a4、掩膜保护：用石蜡保护第一区域上的扩散层(即用作为背面扩散层14)以及与第一区域相邻的侧表面上的扩散层(即用作为侧面扩散层13)；
步骤a5、蚀刻：去除硅基片11侧表面以及背光面上的未被石蜡保护的背结；
步骤a6、去除石蜡保护，去除磷硅玻璃，从而得到石蜡保护下的背面扩散层14和侧面扩散层13；
步骤a7、在正面扩散层12上蒸镀减反层101，减反层101的材料包括但不限于TiO2、Al2O3、SiNxOy、SiNxCy；
步骤a8、在第二区域沿长度方向丝网印刷背电层60、在背电层60上沿长度方向丝网印刷第二电极5、在背面扩散层14上沿长度方向丝网印刷第一电极4、并烘干，其中，第一电极4正好与背面扩散层14重合，背电层60与第一电极4之间存在一定安全距离，避免短路；
步骤a9、在正面扩散层12上沿宽度方向丝网印刷栅线层2以使栅线层2中的每条子栅线21均垂直于第二电极5，并烘干；
步骤a10、在侧面扩散层13上沿长度方向丝网印刷侧面导电件3，并烘干。
实施例2
参照图10-图14，本实施例2与实施例1的结构大致相同，其中相同的部件采用相同的附图标记，不同之处仅在于：实施例1中的第二区域上设有背电层60，背电层60上设有第二电极5，而本实施例2中第二区域上设有背面第二类扩散层15、背面第二类扩散层15上设有背面第二栅线层6和第二电极5。
电池片100包括：硅片1、正面导电件、侧面导电件3、第一电极4、背面第二栅线层6以及第二电极5，其中，正面导电件为正面栅线层2，硅片1可以包括硅基片11、正面第一类扩散层12、背面第二类扩散层15、侧面隔层13、以及背面隔层14，其中，侧面隔层13可以为与正面第一类扩散层12类型相同的侧面扩散层，背面隔层14可以为与正面第一类扩散层12类型相同的背面第一类扩散层。其中，背面第二类扩散层15包括沿垂直于第二电极5长度方向延伸的多条背面第二子栅线层61，也就是说，每个背面第二子栅线层61均垂直于第二电极5的长度方向。由此，可以缩短背面第二子栅线层61的电荷传输路径，提高电荷传输效率，提高电池片100的功率。
具体地，硅基片11的背光面包括第一区域和第二区域，第一区域和第二区域无交集且互不接触，也就是说，第一区域的轮廓线与第二区域的轮廓线不接触。
背面第一类扩散层仅设在第一区域上，即硅基片11的背光面上的除第一区域以外的其余表面上都不具有背面第一类扩散层，进一步地，背面第一类扩散层布满在第一区域上，这样，当第一区域为非离散的连续区域时，背面第一类扩散层可以非离散、即连续地布置在硅基片11上。由此，由于背面第一类扩散层连续、即非离散地布置在硅基片11上，而并不是离散地、即不连续地，例如呈现散点状、斑马条状等离散形式散布在硅基片11上，从而极大地降低了背面第一类扩散层的加工难度，提高了加工效率，降低了加工成本，且可以有效地提高电池片100的功率。
背面第二类扩散层15仅设在第二区域上，即硅基片11的背光面上的除第二区域以外的其余表面上都不具有背面第二类扩散层15。进一步地，背面第二类扩散层15布满在第二区域上，这样，当第二区域为非离散的连续区域时，背面第二类扩散层15可以非离散、即连续地布置在硅基片11上。由此，由于背面第二类扩散层15连续、即非离散地布置在硅基片11上，而并不是离散地、即不连续地，例如呈现散点状、斑马条状等离散形式散布在硅基片11上，从而极大地降低了背面第二类扩散层15的加工难度，提高了加工效率，降低了加工成本，且可以有效地提高电池片100的功率。
第一电极4设在背面第一类扩散层上，也就是说，第一电极4可以直接或者间接设在背面第一类扩散层上，此时，第一电极4设在硅片1的背光面上且与第一区域相对应，也就是说，沿硅片1的厚度方向投影，第一电极4不超出第一区域。硅片1还可以包括钝化层102，钝化层102可以设在背面第一类扩散层上。这样，当硅片1包括钝化层102时，第一电极4可以直接设在钝化层102上。在本公开的一些实施例中，而当硅片1不包括钝化层102时，第一电极4可以直接设在背面第一类扩散层上。
背面第二栅线层6和第二电极5均设在背面第二类扩散层15上，也就是说，背面第二栅线层6和第二电极5可以直接或者间接设在背面第二类扩散层15上，此时，背面第二栅线层6和第二电极5设在硅片1的背光面上且与第二区域相对，也就是说，沿硅片1的厚度方向投影，背面第二栅线层6和第二电极5不超出第二区域。其中，第一电极4既不与背面第二栅线层6接触、也不与第二电极5接触。
例如，硅片1还可以包括钝化层102，钝化层102可以设在背面第二类扩散层15上。这样，当硅片1包括钝化层102时，背面第二栅线层6和第二电极5可以直接设在钝化层102上。而当硅片1不包括钝化层102时，背面第二栅线层6和第二电极5可以直接设在背面第二类扩散层15上。
另外，需要说明的是，在本公开的一些实施例中，背面第二栅线层6和第二电极5可以互不叠置且接触相连，此时，背面第二栅线层6和第二电极5分别完全设在硅片1的背光面上且边缘直接接触电连接，从而可以充分地利用空间，提高电池片100的功率；在本公开的另外一些实施例中，背面第二栅线层6和第二电极5还可以相互叠置，此时，背面第二栅线层6和第二电极5以其两者叠置后的并集表面设在硅片1的背光面上。
其中，由于第一区域和第二区域无交集且互不接触，从而可以加工面积较大的第一电极4、从而可以加工面积较大的背面第二栅线层6和第二电极5，可选地，沿硅片1的厚度方向投影、第一电极4的外边缘落在第一区域的轮廓线上、背面第二栅线层6和第二电极5整体的外边缘均落在第二区域的轮廓线上。由此，可以最大化地利用第一区域和第二区域，提高电池片100的功率。
这里，需要说明的是，本文中所述的“第一类扩散层”和“第二类扩散层”为两个不同种类的扩散层，当将导电介质设在(例如直接设在或通过本文所述的减反层或钝化层间接设在)第一类扩散层和第二类扩散层上时可以收集不同种类的电荷。另外，需要说明的是，本文所述的减反层和钝化层的概念为本领域技术人员所熟知，其两者主要起减少反射、加强电荷收集的作用。
由此，“第一类扩散层”中的正面第一类扩散层、背面第一类扩散层、以及本文所述的侧面第一类扩散层为同一种类的扩散层，当将导电介质设在第一类扩散层上时，可以收集 第一种类的电荷；而“第二类扩散层”中的背面第二类扩散层为另一个种类的扩散层，当将导电介质设在第二类扩散层上时，可以收集第二种类的电荷。这里，需要说明的是，导电介质在硅片上收集电荷的原理应为本领域技术人员所熟知，这里不再详述。
例如，当硅基片11为P型硅时，第一类扩散层可以为磷扩散层，此时设置在磷扩散层上的导电介质可以收集负电荷，而第二类扩散层可以为硼扩散层，设置在硼扩散层上的导电介质可以收集正电荷。又例如，当硅基片11为N型硅时，“第一类扩散层”可以为硼扩散层，“第二类扩散层”可以为磷扩散层，这里不再赘述。
这样，由于正面栅线层2设在(例如直接设在或通过减反层101间接设在)第一类扩散层上，从而正面栅线层2可以收集第一种类的电荷(例如负电荷)。而背面第二栅线层6设在(例如直接设在或通过钝化层102间接设在)第二类扩散层上，从而背面第二栅线层6可以收集第二种类的电荷(例如正电荷)。
具体地，第一电极4通过侧面导电件3电连接至正面栅线层2，从而正面栅线层2收集的第一种类电荷(例如负电荷)可以传递给第一电极4(例如负电极)；第二电极5电连接至背面第二栅线层6，从而背面第二栅线层6收集的第二种类电荷(例如正电荷)可以传递给第二电极5(例如正电极)。由此，第一电极4和第二电极5可以作为电池片100的正负两极输出电能。
这样，由于第一电极4可以通过位于硅片1受光侧的正面栅线层2收集第一种类电荷，第二电极5可以通过为硅片1背光侧的背面第二栅线层6收集第二种类电荷，从而有效地提高了空间利用率，进一步提高电池片100的功率，使得电池片100可以成为美观、高效的双面电池。
具体而言，本实施例2中的电池片100的制备方法与实施例1中的电池片1的制备方法大体相同，不同之处在于，在制备本实施例2中的硅片1时，对硅基片11进行双面不同类型的扩散、即使硅基片11的受光面和背光面分别扩散出类型不同的扩散层，且使受光面上的扩散层由硅基片11的一个侧表面延伸到硅基片11的背光面上，以得到正面第一类扩散层12、侧面第一类扩散层13和背面第一类扩散层14，然后再在背面第一类扩散层14和背面第二类扩散层15以及硅基片11上蒸镀与减反层101材料相同的钝化层102，接着再在钝化层102上丝网印刷背面第二栅线层6。
实施例3
参照图15-图19，本实施例3与实施例2的结构大致相同，其中相同的部件采用相同的附图标记，不同之处仅在于：实施例2中的第一区域和第二区域无交集且互不接触，而本实施例3中第一区域和第二区域无交集且互相接触，也就是说，第一区域的轮廓线与第二区域的轮廓线接触。
具体地，第一区域和第二区域无交集且互相接触，第一电极4设在第一区域上，也就是说，第一电极4可以直接或者间接设在第一区域上，此时，第一电极4设在硅片1的背光面上且与第一区域相对应，也就是说，沿硅片1的厚度方向投影，第一电极4不超出第一区域且位于第二区域之外。背面第二栅线层6和第二电极5均设在第二区域上且均与第一电极4不接触，也就是说，背面第二栅线层6和第二电极5可以直接或者间接设在第二区域上，且背面第二栅线层6不与第一电极4接触，第二电极5也不与第一电极4接触，此时，背面第二栅线层6和第二电极5设在硅片1的背光面上且与第二区域相对应，也就是说，沿硅片1的厚度方向投影，背面第二栅线层6和第二电极5不超出第二区域且位于第一区域之外。由此，可以有效地避免第一电极4与第二电极5应接触导致的短路。
实施例4
参照图20-图24，本实施例4与实施例3的结构大致相同，其中相同的部件采用相同的附图标记，不同之处仅在于：实施例3中的侧面隔层13为侧面第一类扩散层、背面隔层14为背面第一类扩散层，而本实施例4中的侧面隔层13和背面隔层14均为绝缘层。
具体而言，本实施例4中的电池片100的制备方法与实施例2中的电池片1的制备方法大体相同，不同之处在于，在制备本实施例4中的硅片1时，对硅基片11进行双面不同类型的扩散、即使硅基片11的受光面和背光面分别扩散出类型不同的扩散层，以得到正面第一类扩散层12和背面第二类扩散层15、且在硅基片11的背光面的一侧和与该侧相邻的侧表面上加工绝缘层，以得到背面隔层14和侧面隔层13。
实施例5
参照图25-图31，本实施例5与实施例3的结构大致相同，其中相同的部件采用相同的附图标记，不同之处仅在于：第一、实施例3中的背面第一类扩散层(即背面隔层14)上仅设有第一电极4，而本实施例5中的背面第一类扩散层(即背面隔层14)上还设有与第一电极4电连接的背面第一栅线层7。第二、本实施例5中的第一区域和第二区域成接触式指交叉分布。
背面第一栅线层7和第一电极4设在背面第一类扩散层上，也就是说，面第一栅线层和第一电极4可以直接或者间接设在背面第一类扩散层上，此时，背面第一栅线层7和第一电极4设在硅片1的背光面上且与第一区域相对应，也就是说，沿硅片1的厚度方向投影，背面第一栅线层7和第一电极4不超出第一区域且位于第二区域之外。
例如，硅片1还可以包括钝化层102，钝化层102可以设在背面第一类扩散层上。这样，当硅片1包括钝化层102时，背面第一栅线层7和第一电极4可以直接设在钝化层102上。而当硅片1不包括钝化层102时，背面第一栅线层7和第一电极4可以直接设在背面第一类扩散层上。
另外，需要说明的是，在本公开的一些实施例中，背面第一栅线层7和第一电极4可以互不叠置且接触相连，此时，背面第一栅线层7和第一电极4分别完全设在硅片1的背光面上且边缘直接接触电连接，从而可以充分地利用空间，提高电池片100的功率；在本公开的另外一些实施例中，背面第一栅线层7和第一电极4还可以相互叠置，此时，背面第一栅线层7和第一电极4以其两者叠置后的并集表面设在硅片1的背光面上。
由此，根据本实施例的电池片100，通过在硅片1的受光面和背光面分别加工与第一电极4相连的正面栅线层2和背面第一栅线层7，且通过在硅片1的背光面加工与第二电极5相连的背面第二栅线层6，从而使得电池片100可以为双面电池，功率更高。
第一区域和第二区域呈指接触式交叉形分布，也就是说，第一区域的轮廓线和第二区域的轮廓线接触，例如，第一区域和第二区域可以完全无缝隙对插，组成一个连续、完整、无孔的非离散区域。例如，可选地，第一区域和第二区域可以布满硅基片11的背光面。由此，可以充分地利用空间、提高电池片100的功率。这里，需要说明的是，“指交叉形”指的是类似左右两手手指相互交叉且无重叠的形状。
具体地，第一区域包括第一连通区域和多个第一分散区域，多个第一分散区域在第一连通区域的长度方向上间隔开且均与第一连通区域连通，第二区域包括第二连通区域和多个第二分散区域，多个第二分散区域在第二连通区域的长度方向上间隔开且均与第二连通区域连通。
其中，多个第一分散区域和多个第二分散区域的数量不限，而且，第一连通区域、多个第一分散区域、第二连通区域、多个第二分散区域的形状不限，例如多个第一分散区域和多个第二分散区域均可以形成为三角形、半圆形、矩形等等，多个第一分散区域和多个第二分散区域可以形成为矩形、波浪带形等等。
其中，第一连通区域与第二连通区域相对设置，例如，第一连通区域与第二连通区域平行或大体平行(有一较小夹角)设置，多个第一分散区域和多个第二分散区域在第一连通区域和第二连通区域之间一一交替，也就是说，沿着第一连通区域的长度方向、即沿着第二连通区域的长度方向，依次排置一个第一分散区域、一个第二分散区域、再一个第一分散区域、再一个第二分散区域，依此类推，多个第一分散区域和多个第二分散区域一一交替轮流交叉分布。
其中，第一连通区域的轮廓线与多个第二分散区域的轮廓线接触，第二连通区域的轮廓线与多个第一分散区域的轮廓线分别接触。由此，可以确保第一区域和第二区域呈接触式指交叉排布。
进一步地，第一电极4设在第一连通区域上，背面第一栅线层7设在多个第一分散区域上。换言之，第一电极4与第一连通区域相对应设置，背面第一栅线层7与多个第一分 散区域相对应设置。也就是说，沿硅片1的厚度方向投影，第一电极4不超出第一连通区域的轮廓线，背面第一栅线层7不超出多个第一分散区域的轮廓线且位于第二区域的轮廓线之外。由此，第一电极4和背面第一栅线层7的布局合理简单，便于在背面第一类扩散层上加工。
可选地，背面第一栅线层7包括沿垂直于第一连通区域长度方向延伸且在第一连通区域长度方向上间隔开的多个背面第一子栅线层71。由此，背面第一栅线层7可以以更短的路径将收集的电荷传递给第一电极4，从而提高了电荷传递效率，提高了电池片100的功率。
进一步地，第二电极5设在第二连通区域上，背面第二栅线层6设在多个第二分散区域上。换言之，第二电极5与第二连通区域相对应设置，背面第二栅线层6与多个第二分散区域相对应设置。也就是说，沿硅片1的厚度方向投影，第二电极5不超出第二连通区域的轮廓线，背面第二栅线层6不超出多个第二分散区域的轮廓线且位于第一区域的轮廓线之外。由此，第二电极5和背面第二栅线层6的布局合理简单，便于在背面第二类扩散层15上加工。
可选地，背面第二栅线层6包括沿垂直于第二连通区域长度方向延伸且在第二连通区域长度方向上间隔开的多个背面第二子栅线层61。由此，背面第二栅线层6可以以更短的路径将收集的电荷传递给第二电极5，从而提高了电荷传递效率，提高了电池片100的功率。
其中，每个背面第一子栅线层71的轮廓线与第二连通区域和多个第二分散区域均不接触，也就是说，每个背面第一子栅线层71与背面第二子栅线层61和第二电极5均不接触。其中，每个背面第二子栅线层61的轮廓线与第一连通区域和多个第一分散区域均不接触，也就是说，每个背面第二子栅线层61与背面第一子栅线层71和第一电极4均不接触。
具体而言，本实施例5中的电池片100的制备方法与实施例2中的电池片1的制备方法大体相同，不同之处在于，在制备完硅片1后，再在背面第二类扩散层15上加工背面第二子栅线层61。
实施例6
参照图32-图38，本实施例6与实施例5的结构大致相同，其中相同的部件采用相同的附图标记，不同之处仅在于：实施例5中的第一区域和第二区域成接触式指交叉分布，而本实施例6中的第一区域和第二区域成非接触式指交叉分布。
第一连通区域的轮廓线与第二连通区域的轮廓线和多个第二分散区域的轮廓线均不接触，第二连通区域的轮廓线与第一连通区域的轮廓线和多个第一分散区域的轮廓线均不接触。由此，可以确保第一区域和第二区域非呈接触式指交叉排布。其中，每个背面第一子 栅线层71的轮廓线与第二连通区域和第二分散区域均不接触，也就是说，每个背面第一子栅线层71与背面第二子栅线层61和第二电极5均不接触。其中，每个背面第二子栅线层61的轮廓线与第一连通区域和第一分散区域均不接触，也就是说，每个背面第二子栅线层61与背面第一子栅线层71和第一电极4均不接触。
实施例7
参照图39-图45，本实施例7与实施例5的结构大致相同，其中相同的部件采用相同的附图标记，不同之处仅在于：实施例5中的第二区域上布满背面第二类扩散层15，而本实施例7中的第二区域上不设有第二类扩散层。
第二电极5和背面第二栅线层6可以直接或者间接设在第二区域上。例如，第二区域上可以布满钝化层102，背面第二栅线层6和第二电极5可以直接设在钝化层102上。而当硅片1不包括钝化层102时，背面第二栅线层6和第二电极5可以直接设在第二区域上。
在本实用新型的描述中，需要理解的是，术语“上”、“下”、“前”、“后”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本实用新型和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本实用新型的限制。
在本实用新型中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本实用新型中的具体含义。在本实用新型中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本实用新型的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管已经示出和描述了本实用新型的实施例，本领域的普通技术人员可以理解：在不脱离本实用新型的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本实用新型的范围由权利要求及其等同物限定。

Claims (20)

  1. 一种电池片组件，其特征在于，包括：
    沿纵向依次排布的多个电池片，每个所述电池片均包括硅片、设在所述硅片受光面上的正面导电件、设在所述硅片背光面上的两个电极、以及设在所述硅片侧表面上且电连接在所述正面导电件和两个电极中的一个之间的侧面导电件，其中，两个所述电极均沿横向延伸且在所述纵向上间隔开分布；
    导电带，所述导电带与所述电极的延伸方向相同、且与彼此靠近且分别位于相邻两个所述电池片上的两个电极电连接以导通位于相邻两个所述电池片上的两个电极，使相邻的两个所述电池片串联或并联。
  2. 根据权利要求1所述的电池片组件，其特征在于，在所述导电带的延伸方向上，所述导电带的延伸长度大于等于由所述导电带导通的每个所述电极的延伸长度，且所述导电带的两端分别超出于或平齐于由所述导电带导通的每个所述电极的相应端。
  3. 根据权利要求1所述的电池片组件，其特征在于，在垂直于所述导电带延伸方向的方向上，所述导电带的跨度大于等于由所述导电带导通的两个所述电极的跨度之和，且所述导电带的两侧边分别超出于或平齐于由所述导电带导通的两个所述电极彼此远离的两侧边。
  4. 根据权利要求1所述的电池片组件，其特征在于，所述导电带包括结构相同且在垂直于所述导电带延伸方向上依次布置的两个半部，两个所述半部恰好分别覆盖由所述导电带导通的两个所述电极。
  5. 根据权利要求1所述的电池片组件，其特征在于，在垂直于所述导电带延伸方向的方向上，相邻的两个所述电池片之间的间隙小于等于0.1mm。
  6. 根据权利要求1所述的电池片组件，其特征在于，所述硅片在垂直于所述侧面导电件所在侧表面方向上的跨度为20mm-60mm。
  7. 根据权利要求6所述的电池片组件，其特征在于，所述硅片为长方形片体且由正方形常规硅片本体按照长度不变的规则分割而成。
  8. 根据权利要求6所述的电池片组件，其特征在于，所述硅片为长方形片体，每个所述电池片上的两个所述电极分别贴靠所述硅片的两条长边设置且均沿所述硅片的长度方向延伸，所述侧面导电件设在所述硅片的一个长边侧表面上。
  9. 根据权利要求1所述的电池片组件，其特征在于，每个所述电池片上的两个所述电极分别为与所述侧面导电件电连接的第一电极和非与所述侧面导电件电连接的第二电极，
    所述硅片包括：硅基片、正面第一类扩散层以及背面隔层，其中，所述硅基片的背光 面包括第一区域和第二区域，所述正面第一类扩散层设在所述硅基片的受光面上，所述正面导电件设在所述正面第一类扩散层上，所述背面隔层仅设在且布满在所述第一区域上，所述第一电极设在所述背面隔层上，所述第二电极设在所述第二区域上且与所述第一电极不接触，其中，所述背面隔层的至少部分为绝缘层或与所述正面第一类扩散层类型相同的扩散层。
  10. 根据权利要求9所述的电池片组件，其特征在于，所述硅片还包括：侧面隔层，所述侧面隔层设在所述硅基片的侧表面上，所述侧面导电件设在所述侧面隔层上，所述侧面隔层的至少部分为绝缘层或与所述正面第一类扩散层类型相同的扩散层。
  11. 根据权利要求9所述的电池片组件，其特征在于，每个所述电池片还包括：
    背电层，所述背电层设在所述第二区域上，所述第二电极设在所述背电层上且与所述背电层电连接。
  12. 根据权利要求9所述的电池片组件，其特征在于，每个所述电池片还包括：
    背面第二栅线层，所述背面第二栅线层和所述第二电极均设在所述第二区域上，且所述第二电极与所述背面第二栅线层电连接且互不叠置。
  13. 根据权利要求12所述的电池片组件，其特征在于，所述硅片还包括与所述正面第一类扩散层类型不同的背面第二类扩散层，所述背面第二类扩散层仅设在且布满在所述第二区域上，所述背面第二栅线层和所述第二电极均设在所述背面第二类扩散层上。
  14. 根据权利要求9所述的电池片组件，其特征在于，每个所述电池片还包括：
    背面第一栅线层，所述背面第一栅线层和所述第一电极均设在所述背面隔层上，且所述第一电极与所述背面第一栅线层电连接且互不叠置。
  15. 根据权利要求14所述的电池片组件，其特征在于，所述背面隔层为与所述正面第一类扩散层类型相同的背面第一类扩散层，所述背面第一类扩散层仅设在且布满在所述第一区域上，所述背面第一栅线层和所述第一电极均设在所述背面第一类扩散层上。
  16. 根据权利要求9所述的电池片组件，其特征在于，所述第一区域与所述第二区域均为非离散区域。
  17. 根据权利要求16所述的电池片组件，其特征在于，所述第一区域与所述第二区域呈指交叉形分布，其中，所述第一区域包括第一连通区域和多个第一分散区域，多个所述第一分散区域在所述第一连通区域的长度方向上间隔开且均与所述第一连通区域连通，所述第二区域包括第二连通区域和多个第二分散区域，多个所述第二分散区域在所述第二连通区域的长度方向上间隔开且均与所述第二连通区域连通，其中，所述第一连通区域与所述第二连通区域平行设置，多个所述第一分散区域和多个所述第二分散区域在所述第一连通区域和所述第二连通区域之间一一交替。
  18. 一种电池片矩阵，其特征在于，
    由多个电池片并联组件串联而成，
    其中，每个所述电池片并联组件由多个电池片串联组件并联而成，
    其中，每个所述电池片串联组件均为根据权利要求1-17中任一项所述电池片组件，每个所述电池片组件中的多个所述电池片由所述导电带依次串联。
  19. 根据权利要求18所述的电池片矩阵，其特征在于，所述电池片并联组件为两个，每个所述电池片并联组件包括三个所述电池片串联组件。
  20. 一种太阳能电池组件，其特征在于，包括：从受光侧到背光侧依次设置的第一面板、第一粘结层、电池、第二粘结层以及第二面板，其中，所述电池为根据权利要求1-17中任一项所述的电池片组件或根据权利要求18或19所述的电池片矩阵。
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