WO2017219918A1 - 中断处理方法及装置 - Google Patents

中断处理方法及装置 Download PDF

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Publication number
WO2017219918A1
WO2017219918A1 PCT/CN2017/088646 CN2017088646W WO2017219918A1 WO 2017219918 A1 WO2017219918 A1 WO 2017219918A1 CN 2017088646 W CN2017088646 W CN 2017088646W WO 2017219918 A1 WO2017219918 A1 WO 2017219918A1
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Prior art keywords
interrupt request
value
reported
count
preset
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PCT/CN2017/088646
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English (en)
French (fr)
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武八一
陈晓伟
刘强
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中兴通讯股份有限公司
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Publication of WO2017219918A1 publication Critical patent/WO2017219918A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of communication technologies, for example, to an interrupt processing method and apparatus.
  • GPIO General Purpose Input Output
  • the problem in the above level triggering mode is: if the CPU is in a high load state at a certain time point, since the CPU does not respond to the level-triggered interrupt request in time, although the external device only interrupts once, if the CPU does not clear the interrupt in time, The interrupt request status will continue to form a positive feedback of a vicious circle that can cause the system to crash.
  • An interrupt processing method and device solve the problem in the related art that the interrupt request is repeatedly reported due to the CPU not processing an interrupt request in time.
  • An interrupt processing method includes:
  • the timing is started, the time value is obtained, and the number of times of reporting the interrupt request is counted, and the count value reported by the interrupt request is obtained;
  • the interrupt request is masked.
  • the calculating the frequency of reporting the interrupt request includes:
  • calculating a reporting frequency value of the interrupt request includes:
  • the method further includes:
  • the timed time value and the counted number value are reset to zero.
  • the method further includes:
  • the interrupt request is re-enabled.
  • An interrupt processing device includes:
  • the obtaining module is configured to start timing, obtain a timing time value, and count the number of times of reporting the interrupt request, and obtain a count number of times reported by the interrupt request;
  • a calculating module configured to: when the time value obtained by the acquiring module reaches a preset time value, or when the value of the number of times obtained by the acquiring module exceeds a preset counting threshold, a reporting frequency value of the interrupt request, wherein the reporting frequency value is a ratio of the counting time value to the timing time value;
  • the first processing module is configured to mask the interrupt request when the reported frequency value calculated by the calculating module is greater than a preset frequency value.
  • the computing module includes:
  • Obtaining a unit configured to acquire a count number of times reported by the interrupt request when the timed value reaches a preset time value
  • the calculating unit is configured to determine a reporting frequency value of the interrupt request according to a ratio of the counting number value obtained by the first acquiring unit to the timing time value.
  • the computing module includes:
  • Obtaining a unit configured to acquire the timed time value if the number of times of counting exceeds a preset counting threshold
  • the calculating unit is configured to determine a reported frequency value of the interrupt request according to a ratio of the count number of times to the timed value obtained by the second acquiring unit.
  • the device further includes:
  • a second processing module configured to calculate a reported frequency value of the interrupt request, and if the reported frequency value of the interrupt request is less than a preset frequency value, reset the timed time value and the counted number value to zero .
  • the device further includes:
  • timing module configured to mask the interrupt request, start a timer
  • a determining module configured to determine whether the interrupt request is blocked after a timing time of the timer initiated by the timing module arrives
  • the second processing module is configured to re-enable the interrupt request if the determining module determines that the interrupt request has been masked.
  • a computer readable storage medium storing computer executable instructions arranged to perform the above method.
  • An electronic device comprising:
  • At least one processor At least one processor
  • the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method described above.
  • FIG. 1 is a flowchart showing an interrupt processing method provided by the first embodiment
  • Figure 2 shows a flow chart 1 of step 102 provided by the first embodiment
  • Figure 3 shows a flow chart 2 of the step 102 provided by the first embodiment
  • Figure 4 is a block diagram showing the structure of the interrupt processing apparatus provided in the second embodiment
  • FIG. 5 is a structural block diagram 2 of the interrupt processing apparatus provided by the second embodiment
  • FIG. 6 is a diagram showing the hardware configuration of an electronic device according to a third embodiment.
  • This embodiment provides an interrupt processing method, which is shown in FIG. 1.
  • step 101 when an interrupt request is detected, timing is started, a time value is obtained, and the number of times of reporting the interrupt request is counted, and the count value reported by the interrupt request is obtained.
  • the CPU When the CPU detects an interrupt request, it can call the interrupt handler function and count the interrupt request, and count the number of times the interrupt request is reported.
  • the time value is the time period between the start time and the current time.
  • the interrupt request mentioned in this embodiment may be a trigger type interrupt request, such as a level triggered interrupt request.
  • step 102 when the timed value reaches the preset time value, or when the count number exceeds the preset count threshold, the reported frequency value of the interrupt request is calculated.
  • the reported frequency value is a ratio of the count number of times to the timed value.
  • the reported frequency of the interrupt request is calculated to determine whether the number of times of the interrupt request is excessive; or when the interrupt is detected When the number of reported times exceeds the preset count threshold, the reported frequency of the interrupt request is calculated to determine whether the number of times the interrupt request is reported is excessive.
  • the preset timing time value and the preset counting threshold value may be selected according to actual needs.
  • step 103 if the calculated reported frequency value is greater than the preset frequency value, the interrupt request is masked.
  • the calculated reporting frequency value is greater than or equal to the preset frequency value, it indicates that the interrupt request is reported too many times, and the interrupt request may be masked, that is, the interrupt mask flag for controlling the interrupt request is disabled. Suppressing the interrupt request to continue to generate, in order to reduce the number of times the same interrupt request is reported in a short period of time, avoiding the excessive number of times the interrupt request is reported in the CPU in a short period of time, causing the system to crash, thereby improving the system's stability.
  • the reporting frequency value of the interrupt request is less than the preset frequency value
  • the frequency of the interrupt request reporting is within an acceptable range, and the interrupt processing function is called, and the timing of the interrupt request and the reported time are reported.
  • the value is reset to zero, the timing of the interrupt request is restarted, and the number of times of reporting is counted.
  • calculating the reporting frequency value of the interruption request includes the following steps.
  • step 201 when the timed value reaches the preset time value, the count number of times reported by the interrupt request is obtained.
  • step 202 the reported frequency value of the interrupt request is determined according to the ratio of the obtained count number of times to the timed value.
  • the ratio of the number of times the interrupt request is reported to the time value may be calculated, wherein the calculated ratio may be the upper frequency of the interrupt request.
  • Degree value reporting frequency
  • calculating the reported frequency value of the interrupt request includes the following steps.
  • step 301 when the count number of times of the interrupt request exceeds the preset count threshold, the time value of the time is obtained.
  • step 302 the reported frequency value of the interrupt request is determined according to the ratio of the count number of the interrupt request to the acquired time value.
  • the number of reports of an interrupt request is monitored in real time, and when the count number exceeds a preset count threshold, the reporting frequency of the interrupt request is calculated, and the reporting frequency may be a ratio of the count value to the time value, according to the calculation.
  • the obtained reporting frequency determines whether the interrupt request needs to be masked. In this way, the reporting of the interrupt request can be processed in time to prevent the same interrupt request from being reported multiple times in a short time.
  • a timer is started. When the timer time expires, it is determined whether the interrupt request is masked. If the interrupt request has been masked, the device is re-enabled. The interrupt request, that is, the interrupt mask flag that controls the interrupt request is enabled, the interrupt mask is released, and the number of times of reporting the interrupt request is restarted.
  • the interrupt processing method provided in this embodiment is described as an example.
  • the method in steps 301-302 is taken as an example.
  • TIME_INTERVAL 200 milliseconds
  • the interrupt processing function When an IRQ is detected, the interrupt processing function is called, and the number of times of reporting the IRQ is counted, and the statistical time of the count (corresponding to the timing value described above) is recorded.
  • the interrupt handling function can be called.
  • the interrupt request reporting frequency is considered to be in the normal range, and the number of times of reporting the IRQ and the statistical time are cleared to zero, and the new counting and timing are restarted.
  • the interrupt request is masked, and a timing with a timing duration of 3000 ms is created.
  • the timing of 3000 ms arrives, it is detected whether the IRQ has been masked. If it has been masked, the masking of the IRQ is cancelled, and the 3000 ms timer is deleted, and the number of times of reporting the IRQ and the statistical time are cleared, and the new one is restarted. Count of.
  • the embodiment provides an interrupt processing device.
  • the interrupt processing device includes an obtaining module 401, a calculating module 402, and a first processing module 403.
  • the obtaining module 401 is configured to start timing, obtain a timing time value, and count the number of times of reporting the interrupt request, and obtain the count number of times reported by the interrupt request.
  • the interrupt processing function may be called, and the interrupt request is started, and the number of times of reporting the interrupt request is counted, and the count of the interrupt request is obtained by the obtaining module 401. Number of times and time value.
  • the interrupt request mentioned in this embodiment may be a trigger type interrupt request, such as a level triggered interrupt request.
  • the calculation module 402 is configured to calculate the reported frequency value of the interrupt request when the time value obtained by the obtaining module 401 reaches the preset time value, or when the value of the number of times obtained by the acquiring module exceeds the preset counting threshold,
  • the reported frequency value is a ratio of the count number of times to the timed value.
  • the calculating module 402 calculates the reporting frequency of the interrupt request to determine whether the number of times of the interrupt request is excessive; or When the obtaining module 401 detects that the number of times of reporting the interrupt request exceeds the preset counting threshold, the calculating module 402 calculates the reporting frequency value of the interrupt request to determine whether the number of times of reporting the interrupt request is excessive.
  • the preset timing time value and the preset counting threshold value may be selected according to actual needs.
  • the first processing module 403 is configured to mask the interrupt request when the reported frequency value calculated by the calculation module 402 is greater than the preset frequency value.
  • the number of times the interrupt request is reported is too large, and the interrupt request may be masked by the first processing module 403, that is, the control is performed.
  • the interrupt mask flag of the interrupt request is disabled, and the interrupt request is suppressed from being generated to reduce the number of times the same interrupt request is reported in a short time, and the number of times of large number of reports is avoided. In a very short time, the CPU usage is too high and the system crashes, which improves the stability of the system.
  • the calculation module 402 includes: a first obtaining unit 4021 and a first calculating unit 4022.
  • the first obtaining unit 4021 is configured to acquire the count number of times reported by the interrupt request when the timed value reaches the preset time value.
  • the first calculating unit 4022 is configured to determine the reported frequency value of the interrupt request according to the ratio of the count number value acquired by the first obtaining unit 4021 to the timed time value.
  • the first obtaining unit 4021 can obtain the count number of times that the interrupt request has been reported at this time, and calculate the time in the time by the first calculating unit 4022.
  • the ratio of the number of times the interrupt request is reported to the time value of the timeout, wherein the calculated ratio may be the reported frequency of the interrupt request.
  • the calculation module 402 includes: a second obtaining unit 4023 and a second calculating unit 4024.
  • the second obtaining unit 4023 is configured to acquire the timing time value when the count number of times exceeds the preset count threshold.
  • the second calculating unit 4024 is configured to determine the reported frequency value of the interrupt request according to the ratio of the count number value to the timed time value acquired by the second acquiring unit 4023.
  • the obtaining module 401 monitors the number of times of the report of the interrupt request in real time.
  • the second acquiring unit 4023 obtains the time value corresponding to the interrupt request, and calculates the time value by the second calculating unit 4024.
  • the reporting frequency of the interrupt request may be a ratio of the counting number value to the timing time value, determining whether the interrupt request needs to be masked according to the reporting frequency calculated by the second calculating unit 4024, and timely reporting the interrupt request Processing is performed to avoid the same interrupt request being reported in a large number of times in a short time.
  • the interrupt processing apparatus further includes: a second processing module 404.
  • the second processing module 404 is configured to reset the timing time value and the count number value to zero when the reported frequency value of the interrupt request is less than the preset frequency value.
  • the interrupt processing function may be invoked, and the timing corresponding to the interrupt request is simultaneously The time and the counted count value of the report are reset to zero, and the timing of the interrupt request is restarted, and the number of times of reporting is counted.
  • the interrupt processing apparatus further includes: a timing module 405, and a determining module. 406 and a third processing module 407.
  • Timing module 405 is set to initiate a timer.
  • the determining module 406 is configured to determine whether the interrupt request is masked after the timing time of the timer activated by the timing module 405 is reached.
  • the third processing module 407 is configured to re-enable the interrupt request when the interrupt request has been masked.
  • a timer is started by the timing module 405. After the timing time of the timer arrives, the second determining module 406 determines whether the interrupt request is blocked. If the second determining module 406 If it is determined that the interrupt request has been masked, the interrupt request is re-enabled by the third processing module 407, that is, the interrupt mask flag for controlling the interrupt request is enabled, the interrupt mask is released, and the interrupt request is restarted. The number of times is counted.
  • the interrupt processing device obtained in this embodiment obtains the number of times an interrupt request is reported and the corresponding time in time through the obtaining module 401, and calculates the reporting frequency of the terminal under certain conditions through the calculating module 402, and the calculated report is obtained.
  • the first processing module 403 masks the interrupt request, and reduces the probability of a system crash caused by the repeated request of the interrupt request due to the CPU not processing an interrupt request in time.
  • the interrupt processing device is a device corresponding to the interrupt processing method in the first embodiment described above, and all of the embodiments in the first embodiment described above are applicable to the embodiment of the device.
  • the present embodiment provides a computer readable storage medium storing computer executable instructions arranged to perform the method of any of the above embodiments.
  • the electronic device includes:
  • At least one processor 60 is exemplified by a processor 60 in FIG. 6; a memory 61; and a communication interface 62 and a bus 63.
  • the processor 60, the memory 61, and the communication interface 62 can complete communication with each other through the bus 63.
  • Communication interface 62 can transmit data and signals.
  • Processor 60 may invoke logic instructions in memory 61 to perform the methods of the above-described embodiments.
  • logic instructions in the memory 61 described above may be implemented in the form of a software functional unit and sold or used as a stand-alone product, and may be stored in a computer readable storage medium.
  • the memory 61 is used as a computer readable storage medium for storing software programs, computer executable programs, and program instructions or modules corresponding to the methods in the above embodiments.
  • the processor 60 executes the functional application and the data processing by executing a software program, an instruction or a module stored in the memory 61, that is, the method in the above embodiment is implemented.
  • the memory 61 may include a storage program area and an storage data area, wherein the storage program area may store an operating system, an application required for at least one function; the storage data area may store data created according to usage of the terminal device, and the like. Further, the memory 61 may include a high speed random access memory, and may also include a nonvolatile memory.
  • the above technical solution may be embodied in the form of a software product stored in a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute All or part of the steps of the method described in the above embodiments.
  • the foregoing storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • the interrupt processing method and device solve the problem in the related art that the interrupt request is repeatedly reported due to the CPU not processing an interrupt request in time.

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Abstract

一种中断处理方法及装置，其中，该中断处理方法包括：当检测到一中断请求时，开始计时，获得计时时间值，对所述中断请求的上报次数进行计数，获得所述中断请求上报的计数次数值（101）；当所述计时时间值到达预设计时时间值时，或当所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值，其中，所述上报频度值为所述计数次数值与所述计时时间值的比值（102）；以及若计算得到的上报频度值大于预设频度值，则屏蔽所述中断请求（103）。

Description

中断处理方法及装置 技术领域
本公开涉及通信技术领域，例如，涉及一种中断处理方法及装置。
背景技术
在高可靠的电信级系统中，外部通用输入/输出(General Purpose Input Output，GPIO)中断有两种触发选择：电平触发和边沿触发。其中，电平触发的处理过程中，当中央处理器(Central Processing Unit，CPU)处理该中断后，CPU才会主动去清除此中断，保证中断的可靠性。
上述电平触发方式中存在的问题是：若CPU在一个时间点处于高负荷状态，由于CPU没有及时响应电平触发的中断请求，虽然外部设备只发生一次中断，如果CPU没有及时清除该中断，中断请求状态会一直持续下去，形成一种恶性循环的正反馈，可能会导致系统崩溃。
发明内容
一种中断处理方法及装置，解决了相关技术中因CPU未及时处理一中断请求而导致该中断请求重复持续上报的问题。
一种中断处理方法，包括：
当检测到一中断请求时，开始计时，获得计时时间值，同时对所述中断请求的上报次数进行计数，获得所述中断请求上报的计数次数值；
当所述计时时间值到达预设计时时间值时，或当所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值，其中，所述上报频度值为所述计数次数值与所述计时时间值的比值；以及
若计算得到的上报频度值大于预设频度值，则屏蔽所述中断请求。
可选的，所述当所述计时时间值到达预设计时时间值时，计算所述中断请求的上报频度值包括：
当所述计时时间值到达预设计时时间值时，获取所述中断请求上报的计数 次数值；以及
根据所述计数次数值与所述计时时间值的比值，确定所述中断请求的上报频度值。
可选的，所述当所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值包括：
所述计数次数值超过预设计数阈值时，获取所述计时时间值；以及
根据所述计数次数值与所述计时时间值的比值，确定所述中断请求的上报频度值。
可选的，在所述计算所述中断请求的上报频度值之后，所述方法还包括：
若所述中断请求的上报频度值小于预设频度值，则将所述计时时间值和所述计数次数值归零。
可选的，所述屏蔽所述中断请求之后，所述方法还包括：
启动一定时器；
当所述定时器的定时时间到达后，判断所述中断请求是否被屏蔽；以及
若所述中断请求已被屏蔽，则重新使能所述中断请求。
一种中断处理装置，包括：
获取模块，设置为当检测到一中断请求时，开始计时，获得计时时间值，同时对所述中断请求的上报次数进行计数，获得所述中断请求上报的计数次数值；
计算模块，设置为当所述获取模块所获得的所述计时时间值到达预设计时时间值时，或当所述获取模块所获得的所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值，其中，所述上报频度值为所述计数次数值与所述计时时间值的比值；以及
第一处理模块，设置为当所述计算模块所计算得到的上报频度值大于预设频度值时，屏蔽所述中断请求。
可选的，所述计算模块包括：
获取单元，设置为当所述计时时间值到达预设计时时间值时，获取所述中断请求上报的计数次数值；以及
计算单元，设置为根据所述第一获取单元所获取的所述计数次数值与所述计时时间值的比值，确定所述中断请求的上报频度值。
可选的，所述计算模块包括：
获取单元，设置为若所述计数次数值超过预设计数阈值时，获取所述计时时间值；
计算单元，设置为根据所述计数次数值与所述第二获取单元所获取的所述计时时间值的比值，确定所述中断请求的上报频度值。
可选的，所述的装置还包括：
第二处理模块，设置为计算所述中断请求的上报频度值之后，若所述中断请求的上报频度值小于预设频度值，将所述计时时间值和所述计数次数值归零。
可选的，所述的装置还包括：
定时模块，设置为屏蔽所述中断请求之后，启动一定时器；
判断模块，设置为当所述定时模块所启动的所述定时器的定时时间到达后，判断所述中断请求是否被屏蔽；以及
第二处理模块，设置为若所述判断模块确定所述中断请求已被屏蔽，则重新使能所述中断请求。
一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述方法。
一种电子设备，包括：
至少一个处理器；以及
与所述至少一个处理器通信连接的存储器；其中，
所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器执行上述的方法。
上述技术方案，通过检测一定条件下一中断请求的上报频度值，从而判断该中断请求是否上报次数过多，若上报次数过多，则屏蔽该中断请求，这样能 够降低因CPU未及时处理某一中断请求，而导致该中断请求重复持续上报所造成的系统崩溃的概率。
附图说明
图1表示第一实施例提供的中断处理方法的流程图；
图2表示第一实施例提供的步骤102的流程图一；
图3表示第一实施例提供的步骤102的流程图二；
图4表示第二实施例提供的中断处理装置的结构框图一；
图5表示第二实施例提供的中断处理装置的结构框图二；以及
图6表示第三实施例提供的电子设备的硬件结构图。
具体实施方式
下面将参照附图描述示例性实施例。在不冲突的情况下，以下实施例以及实施例中的技术特征可以相互任意组合。
第一实施例
本实施例提供了一种中断处理方法，所述方法如图1所示。
在步骤101中，当检测到一中断请求时，开始计时，获得计时时间值，对该中断请求的上报次数进行计数，获得该中断请求上报的计数次数值。
当CPU检测到一中断请求到来时，可以调用中断处理函数，并对应该中断请求开始计时，对该种类型的中断请求的上报次数进行计数。计时时间值是启动计时时刻与当前时刻之间的时间段值。
其中，本实施例中提到的中断请求可以为触发类中断请求，如电平触发的中断请求。
在步骤102中，当计时时间值到达预设计时时间值时，或当计数次数值超过预设计数阈值时，计算该中断请求的上报频度值。
其中，所述上报频度值为所述计数次数值与所述计时时间值的比值。
当检测到该中断请求的计时时间值到达预设计时时间值时，计算该中断请求的上报频度值，以确定该中断请求的上报次数是否过多；或当检测到该中断 请求的上报次数超过预设计数阈值时，计算该中断请求的上报频度值，以确定该中断请求的上报次数是否过多。
其中，所述的预设计时时间值和预设计数阈值的取值，可根据实际需求选择。
在步骤103中，若计算得到的上报频度值大于预设频度值，则屏蔽中断请求。
其中，若计算得到的上报频度值大于或等于预设频度值，则说明该中断请求上报的次数过多，可以屏蔽该中断请求，即控制该中断请求的中断屏蔽标志为禁止(disable)，抑制该中断请求继续产生，以减少同一中断请求在短时间内大量上报的次数，避免中断请求在短时间内大量上报的次数在CPU内的占用率过高而造成系统崩溃，提升了系统的稳定性。
可选的，若中断请求的上报频度值小于预设频度值，该中断请求上报的频度在可接受范围内，调用中断处理函数，将对应该中断请求的计时时间和上报的计数次数值归零，重新开始对该中断请求进行计时，以及上报次数进行计数。
可选地，如图2所示，步骤102中的当计时时间值到达预设计时时间值时，计算中断请求的上报频度值包括以下步骤。
在步骤201中，当计时时间值到达预设计时时间值时，获取该中断请求上报的计数次数值。
在步骤202中，根据获取的计数次数值与计时时间值的比值，确定该中断请求的上报频度值。
当该中断请求的计时时间值到达预设计时时间值时，可以计算该计时时间内该中断请求上报的次数与该计时时间值的比值，其中，计算得到的比值可以为该中断请求的上报频度值(上报频度)。
可选地，如图3所示，步骤102中的当计数次数值超过预设计数阈值时，计算中断请求的上报频度值包括以下步骤。
在步骤301中，当该中断请求的计数次数值超过预设计数阈值时，获取此时的计时时间值。
在步骤302中，根据该中断请求的计数次数值与获取的计时时间值的比值，确定该中断请求的上报频度值。
上述方法，通过实时监测一中断请求的上报次数，当计数次数值超过预设计数阈值时，计算该中断请求的上报频度，上报频度可以为计数次数值与计时时间值的比值，根据计算得到的上报频度确定是否需要屏蔽该中断请求，通过这样的方式能够及时对中断请求的上报进行处理，避免同一中断请求在短时间内多次上报。
可选地，本实施例中，在屏蔽中断请求之后，启动一定时器，当定时器的定时时间到达后，判断该中断请求是否被屏蔽，若该中断请求已被屏蔽，则重新使能该中断请求，即控制该中断请求的中断屏蔽标志为可用(enable)，解除中断屏蔽，重新开始对该中断请求的上报次数进行计数。
下面以一示例说明本实施例提供的中断处理方法，该示例中以步骤301～302所述方法为例。
在系统初始化时候，设置需要监控的中断请求(Interrupt Request，IRQ)为GPIO外部中断号，其中，监测过程中的相关参数和注册回调函数，举例应用如下：
参考时间间隔值：TIME_INTERVAL＝200毫秒；
上报次数门限值(对应上述的预设计数阈值)：THRESHOLD＝100次；
定时器的定时时间：TIMER＝3000毫秒。
当检测到一IRQ到来时，调用中断处理函数，并对该IRQ的上报次数进行计数，同时记录计数的统计时间(对应上述的计时时间值)。
若该IRQ上报次数小于或等于200次，则可以调用中断处理函数。
若该IRQ上报次数大于200次，但此时统计时间大于200ms，则认为该中断请求上报频度属于正常范围，将该IRQ的上报次数和统计时间清零，重新开始新的计数和计时。
若该IRQ上报次数大于200次，且统计时间小于或等于200ms，说明该中断请求的上报频度值过大(例如上报频度大于1)，则屏蔽该中断请求，创建定时时长为3000ms的定时器。在3000ms的定时时间到达时，检测该IRQ是否已被屏蔽，若已被屏蔽，则解除该IRQ的屏蔽，并删除3000ms定时器，同时将该IRQ的上报次数和统计时间清零，重新开始新的计数。
综上所述，本实施例通过检测一定条件下一中断请求的上报频度，从而判断该中断请求是否上报次数过多，若上报次数过多，则屏蔽该中断请求，能够 降低因CPU未及时处理一中断请求，而导致该中断请求重复持续上报所造成的系统崩溃的概率。
第二实施例
本实施例提供了一种中断处理装置，如图4所示，中断处理装置包括获取模块401、计算模块402和第一处理模块403。
获取模块401设置为当检测到一中断请求时，开始计时，获得计时时间值，同时对该中断请求的上报次数进行计数，获得该中断请求上报的计数次数值。
当CPU检测到一中断请求到来时，可以调用中断处理函数，并对应该中断请求开始计时，同时对该种类型的中断请求的上报次数进行计数，并通过获取模块401获得该中断请求上报的计数次数值和计时时间值。
其中，本实施例中提到的中断请求可以为触发类中断请求，如电平触发的中断请求。
计算模块402设置为当获取模块401所获得的计时时间值到达预设计时时间值时，或当获取模块所获得的计数次数值超过预设计数阈值时，计算该中断请求的上报频度值，其中，所述上报频度值为所述计数次数值与所述计时时间值的比值。
当获取模块401检测到对应该中断请求的计时时间值到达预设计时时间值时，通过计算模块402计算该中断请求的上报频度值，以确定该中断请求的上报次数是否过多；或当获取模块401检测到该中断请求的上报次数超过预设计数阈值时，通过计算模块402计算该中断请求的上报频度值，以确定该中断请求的上报次数是否过多。
其中，所述的预设计时时间值和预设计数阈值的取值，可根据实际需求选择。
第一处理模块403设置为当计算模块402所计算得到的上报频度值大于预设频度值时，屏蔽该中断请求。
可选的，若计算模块402计算得到的上报频度值大于或等于预设频度值，则说明该中断请求上报的次数过多，可以通过第一处理模块403屏蔽该中断请求，即控制该中断请求的中断屏蔽标志为禁止(disable)，抑制该中断请求继续产生，以减少同一中断请求在短时间内大量上报的次数，避免大量上报的次数 在极短时间内在CPU内占用率过高而造成系统崩溃，提升了系统的稳定性。
可选地，如图5所示，该计算模块402包括：第一获取单元4021和第一计算单元4022。
第一获取单元4021设置为当计时时间值到达预设计时时间值时，获取该中断请求上报的计数次数值。
第一计算单元4022设置为根据第一获取单元4021获取的计数次数值与计时时间值的比值，确定该中断请求的上报频度值。
当对应该中断请求的计时时间值到达预设计时时间值时，可以通过第一获取单元4021获取该中断请求此时已上报的计数次数值，并通过第一计算单元4022计算该计时时间内该中断请求上报的次数与该计时时间值的比值，其中，计算得到的比值可以为该中断请求的上报频度。
可选地，该计算模块402包括：第二获取单元4023和第二计算单元4024。
第二获取单元4023设置为当计数次数值超过预设计数阈值时，获取计时时间值。
第二计算单元4024设置为根据计数次数值与第二获取单元4023所获取的计时时间值的比值，确定中断请求的上报频度值。
通过获取模块401实时监测一中断请求的上报次数，当计数次数值超过预设计数阈值时，通过第二获取单元4023获取此时对应该中断请求的计时时间值，并通过第二计算单元4024计算该中断请求的上报频度，上报频度可以为计数次数值与计时时间值的比值，根据第二计算单元4024计算得到的上报频度确定是否需要屏蔽该中断请求，能够及时对中断请求的上报进行处理，避免同一中断请求在短时间内大量次数的上报。
可选地，如图5所示，该中断处理装置还包括：第二处理模块404。
第二处理模块404设置为当该中断请求的上报频度值小于预设频度值时，将计时时间值和计数次数值归零。
第二处理模块404确定该中断请求的上报频度值小于预设频度值时，说明该中断请求上报的频度在可接受范围内，可以调用中断处理函数，同时将对应该中断请求的计时时间和上报的计数次数值归零，重新开始对应该中断请求进行计时，以及上报次数进行计数。
可选地，如图5所示，该中断处理装置还包括：定时模块405、判断模块 406和第三处理模块407。
定时模块405设置为启动一定时器。
判断模块406设置为当所述定时模块405所启动的定时器的定时时间到达后，判断该中断请求是否被屏蔽。
第三处理模块407设置为当该中断请求已被屏蔽时，重新使能该中断请求。
本实施例中，在屏蔽上述中断请求时，通过定时模块405启动一定时器，当定时器的定时时间到达后，通过第二判断模块406判断该中断请求是否被屏蔽，若第二判断模块406确定该中断请求已被屏蔽，则通过第三处理模块407重新使能该中断请求，即控制该中断请求的中断屏蔽标志为可用(enable)，解除中断屏蔽，同时重新开始对该中断请求的上报次数进行计数。
本实施例提供的中断处理装置，通过获取模块401实时获取一中断请求上报的次数和对应的计时时间，并通过计算模块402计算该终端请求在一定条件下的上报频度，当计算得到的上报频度大于预设频度时，则由第一处理模块403屏蔽该中断请求，降低因CPU未及时处理一中断请求，而导致该中断请求重复持续上报所造成的系统崩溃的概率。
该中断处理装置是与上述第一实施例中的中断处理方法对应的装置，上述第一实施例中的所有实施例均适用于该装置的实施例。
本实施例提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述任一实施例中的方法。
第三实施例
本实施例提供了一种电子设备的硬件结构示意图。参见图6，该电子设备包括：
至少一个处理器(processor)60，图6中以一个处理器60为例；存储器(memory)61；还可以包括通信接口(Communications Interface)62和总线63。其中，处理器60、存储器61以及通信接口62可以通过总线63完成相互间的通信。通信接口62可以传输数据和信号。处理器60可以调用存储器61中的逻辑指令，以执行上述实施例的方法。
此外，上述的存储器61中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。
存储器61作为一种计算机可读存储介质，可用于存储软件程序、计算机可执行程序，如上述实施例中的方法对应的程序指令或模块。处理器60通过运行存储在存储器61中的软件程序、指令或模块，从而执行功能应用以及数据处理，即实现上述实施例中的方法。
存储器61可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端设备的使用所创建的数据等。此外，存储器61可以包括高速随机存取存储器，还可以包括非易失性存储器。
以上技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括一个或多个指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行上述实施例所述方法的全部或部分步骤。而前述的存储介质可以是非暂态存储介质，包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等多种可以存储程序代码的介质，也可以是暂态存储介质。
工业实用性
中断处理方法及装置解决了相关技术中因CPU未及时处理一中断请求而导致该中断请求重复持续上报的问题。

Claims (11)

  1. 一种中断处理方法，包括：
    当检测到一中断请求时，开始计时，获得计时时间值，同时对所述中断请求的上报次数进行计数，获得所述中断请求上报的计数次数值；
    当所述计时时间值到达预设计时时间值时，或当所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值，其中，所述上报频度值为所述计数次数值与所述计时时间值的比值；以及
    若计算得到的上报频度值大于预设频度值，则屏蔽所述中断请求。
  2. 根据权利要求1所述的方法，其中，所述当所述计时时间值到达预设计时时间值时，计算所述中断请求的上报频度值包括：
    当所述计时时间值到达预设计时时间值时，获取所述中断请求上报的计数次数值；以及
    根据所述计数次数值与所述计时时间值的比值，确定所述中断请求的上报频度值。
  3. 根据权利要求1所述的方法，其中，所述当所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值包括：
    所述计数次数值超过预设计数阈值时，获取所述计时时间值；以及
    根据所述计数次数值与所述计时时间值的比值，确定所述中断请求的上报频度值。
  4. 根据权利要求1所述的方法，在所述计算所述中断请求的上报频度值之后，所述方法还包括：
    若所述中断请求的上报频度值小于预设频度值，则将所述计时时间值和所述计数次数值归零。
  5. 根据权利要求1所述的方法，所述屏蔽所述中断请求之后，所述方法还包括：
    启动一定时器；
    当所述定时器的定时时间到达后，判断所述中断请求是否被屏蔽；以及
    若所述中断请求已被屏蔽，则重新使能所述中断请求。
  6. 一种中断处理装置，包括：
    获取模块，设置为当检测到一中断请求时，开始计时，获得计时时间值，同时对所述中断请求的上报次数进行计数，获得所述中断请求上报的计数次数值；
    计算模块，设置为当所述获取模块所获得的所述计时时间值到达预设计时时间值时，或当所述获取模块所获得的所述计数次数值超过预设计数阈值时，计算所述中断请求的上报频度值，其中，所述上报频度值为所述计数次数值与所述计时时间值的比值；以及
    第一处理模块，设置为当所述计算模块所计算得到的上报频度值大于预设频度值时，屏蔽所述中断请求。
  7. 根据权利要求6所述的装置，其中，所述计算模块包括：
    获取单元，设置为当所述计时时间值到达预设计时时间值时，获取所述中断请求上报的计数次数值；以及
    计算单元，设置为根据所述第一获取单元所获取的所述计数次数值与所述计时时间值的比值，确定所述中断请求的上报频度值。
  8. 根据权利要求6所述的装置，其中，所述计算模块包括：
    获取单元，设置为若所述计数次数值超过预设计数阈值时，获取所述计时 时间值；以及
    计算单元，设置为根据所述计数次数值与所述第二获取单元所获取的所述计时时间值的比值，确定所述中断请求的上报频度值。
  9. 根据权利要求6所述的装置，还包括：
    第二处理模块，设置为计算所述中断请求的上报频度值之后，若所述中断请求的上报频度值小于预设频度值，将所述计时时间值和所述计数次数值归零。
  10. 根据权利要求6所述的装置，还包括：
    定时模块，设置为屏蔽所述中断请求之后，启动一定时器；
    判断模块，设置为当所述定时模块所启动的所述定时器的定时时间到达后，判断所述中断请求是否被屏蔽；以及
    第二处理模块，设置为若所述判断模块确定所述中断请求已被屏蔽，则重新使能所述中断请求。
  11. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行权利要求1-5中任一项的方法。
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