WO2017210958A1 - 半色调掩模板及tft基板的制作方法 - Google Patents

半色调掩模板及tft基板的制作方法 Download PDF

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WO2017210958A1
WO2017210958A1 PCT/CN2016/089958 CN2016089958W WO2017210958A1 WO 2017210958 A1 WO2017210958 A1 WO 2017210958A1 CN 2016089958 W CN2016089958 W CN 2016089958W WO 2017210958 A1 WO2017210958 A1 WO 2017210958A1
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region
semi
transmissive
layer
photoresist
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French (fr)
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莫超德
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a halftone mask and a method of fabricating a TFT substrate.
  • Liquid crystal displays are widely used in various daily necessities and office supplies, such as computers, mobile phones, and bulletin display boards, because of their low energy consumption, small radiation, light weight, and thinness.
  • the liquid crystal display includes a thin film transistor (TFT) array substrate, a color filter substrate, and a liquid crystal layer injected between the two plates.
  • TFT thin film transistor
  • a color filter substrate In the fabrication of a thin film transistor substrate, it is usually produced by a 4 to 6-round mask process through thin film deposition, mask exposure, development, etching, and the like.
  • halftone masks With the development of science and technology, the emergence of halftone masks has reduced the manufacturing process of liquid crystal panels to 4Mask process technology.
  • the existing method for fabricating a TFT substrate by using a 5Mask process includes the following steps:
  • Step 1 as shown in FIG. 1, a substrate 10 is provided, a gate metal layer is deposited on the substrate 10, and the gate metal layer is patterned by a mask process using a mask to obtain a gate 25 ;
  • Step 2 As shown in FIG. 2-3, a gate insulating layer 30 and a semiconductor layer 40 are sequentially deposited on the gate electrode 25 and the substrate 10, and the semiconductor layer 40 is subjected to ion doping treatment to make the semiconductor layer.
  • the upper surface portion of 40 is formed with an ohmic contact layer 41, the semiconductor layer 40 is patterned using a mask process using a mask process to obtain an active layer 45;
  • Step 3 depositing a source/drain metal layer on both ends of the gate insulating layer 30 and the active layer 45, and using a mask to cover the source and drain using a mask process
  • the metal layer is patterned to obtain the source and drain electrodes 51 and 52.
  • the source and drain electrodes 51 and 52 are used as the shielding layer, and the active layer 45 is etched to prevent the source layer 45 from being sourced or drained.
  • the ion-treated surface covered by the poles 51, 52 is etched away to obtain a channel region 46 on the active layer 45, and corresponding to the source and drain contact regions 47 under the source and drain electrodes 51, 52, respectively. 48;
  • Step 4 depositing a passivation layer 70 on the source 51, the drain 52, the active layer 45, and the gate insulating layer 30, using a mask using a mask process for the blunt
  • the layer 70 is patterned to obtain a first via 71 corresponding to the upper surface of the drain 52;
  • Step 5 depositing a transparent electrode layer on the passivation layer 70 layer, using one The mask is patterned by a mask process to obtain a pixel electrode 81.
  • the 4Mask process is compared with the above-mentioned 5Mask process, after the semiconductor layer is ion-doped, it is not patterned, and the source and drain metal layers are directly deposited thereon, and then only a half-tone mask is used.
  • Half Tone Mask uses a halftone mask process to complete the pattern created by the two mask processes used in steps 2 and 3 of the 5Mask process.
  • the halftone mask 90 used in the conventional 4Mask process includes first and second opaque regions 91, 92 corresponding to the source and drain positions of the thin film transistor, respectively, and the film.
  • U-shaped semi-transmissive region 93 corresponding to the U-shaped channel region of the active layer of the transistor, and a remaining fully transparent region 94, and a semi-transparent halftone mask on the halftone mask 90 for forming a U-shaped channel region
  • the light region 93 is located in a gap between the first and second opaque regions 91, 92 and has a U-shape.
  • the U-shaped semi-transmissive region 93 is directly connected to the fully transparent region 94, and thus is used in the 4Mask process.
  • portions corresponding to the first and second opaque regions 91, 92 are unexposed regions
  • portions corresponding to the semi-transmissive regions 93 are semi-exposed regions, and other portions.
  • a portion of the photoresist material that has been fully exposed consumes a large amount of developer in the region for a short period of time, while a portion of the semi-exposed portion consumes only a portion of the developer, so that part of the developer penetrates from the half-exposure region.
  • Another object of the present invention is to provide a method for fabricating a TFT substrate.
  • the present invention first provides a halftone mask comprising first and second opaque regions corresponding to source and drain positions of a thin film transistor, respectively, for use with the thin film transistor a U-shaped semi-transmissive region corresponding to the position of the U-shaped channel region of the active layer, two semi-transparent extending regions extending outside the opening of the U-shaped semi-transmissive region, and remaining remaining Light area
  • the first opaque region includes a strip portion
  • the second opaque region includes a U shape a portion of the strip portion of the first opaque region extends into the opening of the U-shaped portion of the second opaque region and is not in contact therewith, thereby forming a U-shaped gap
  • the semi-transmissive region is located and fills a U-shaped gap between the first opaque region and the second opaque region, and the semi-transmissive region includes a vertical strip portion and is respectively connected to the vertical strip Two horizontal strip portions at both ends to form a U-shaped structure;
  • the semi-transmissive extending region is perpendicular to a strip portion of the first opaque region and extends outwardly of the U-shaped structure of the semi-transmissive region, and is in contact with the semi-transmissive region and blocks the first portion An opening of a U-shaped gap between the opaque region and the second opaque region;
  • the length of the semi-transmissive extension region is greater than the width of the horizontal strip portion of the semi-transmissive region.
  • the length of the semi-transmissive extension region is larger than the width of the horizontal strip portion in the semi-transmissive region by 1 to 3 ⁇ m.
  • the width of the vertical strip portion and the width of the horizontal strip portion in the semi-transmissive region are both greater than 1 ⁇ m.
  • the width of the vertical strip portion in the semi-transmissive region is equal to the width of the horizontal strip portion.
  • the two semi-transmissive extension regions are obtained by providing a semi-permeable membrane at the opening of the U-shaped semi-transmissive region, and the semi-permeable membrane is a chromium oxide film or a molybdenum silicon film.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a gate metal layer on the substrate, using a mask to pattern the gate metal layer by using a mask process to obtain a gate;
  • Step 2 sequentially depositing a gate insulating layer and a semiconductor layer on the gate and the substrate, and performing ion doping treatment on the semiconductor layer to form an ohmic contact layer on an upper surface portion of the semiconductor layer;
  • Step 3 depositing a source and drain metal layer on the semiconductor layer, coating a photoresist material on the source and drain metal layer, and exposing the photoresist layer using a halftone mask;
  • the halftone mask includes first and second opaque regions, a U-shaped semi-transmissive region located between the first opaque region and the second opaque region, and located in the U-shape a semi-transmissive extension region extending at an opening of the semi-transmissive region and extending outwardly of the opening, and a remaining fully transparent region; the first opaque region comprising a strip portion, the second opaque region comprising a U-shaped portion, one end of the strip portion of the first opaque region extends into the opening of the U-shaped portion of the second opaque region and is not in contact therewith, thereby forming a U-shaped gap;
  • the semi-transmissive region is located at the U-shaped gap between the first opaque region and the second opaque region, and includes a vertical strip portion and two horizontal strip portions respectively connected to the two ends of the vertical strip portion Forming a U-shaped structure, the semi-transmissive extending region is perpendicular to a strip portion of the first opaque region and extends outwardly from the U-shaped structure of the semi-trans
  • the photoresist layer including a first photoresist segment formed corresponding to the first opaque region, corresponding to the first a second photoresist segment formed by the two opaque regions, and a U-shaped third photoresist segment formed between the first photoresist segment and the second photoresist segment corresponding to the semi-transmissive region, The thickness of the first photoresist segment and the second photoresist segment is greater than the thickness of the third photoresist segment;
  • Step 4 etching the source/drain metal layer to obtain a source corresponding to the first photoresist segment pattern and a drain corresponding to the second photoresist segment pattern, and engraving the semiconductor layer Etching, an active layer corresponding to the photoresist layer pattern is obtained, and a portion of the ohmic contact layer on the upper surface of the semiconductor layer corresponding to the third photoresist segment is etched away to obtain a channel region on the active layer And obtaining source and drain contact regions respectively located under the source and the drain;
  • Step 5 depositing a passivation layer on the source, the drain, the active layer, and the gate insulating layer, and patterning the passivation layer by using a mask process using a mask process to obtain a corresponding a first via above the drain;
  • Step 6 Depositing a transparent electrode layer on the passivation layer, and patterning the transparent electrode layer by using a mask process using a mask process to obtain a pixel electrode.
  • the step 4 specifically includes the following steps:
  • Step 41 dry etching the source and drain metal layers with the photoresist layer as a shielding layer to obtain a transition source and drain metal layer corresponding to the photoresist layer pattern, and performing wet etching on the semiconductor layer. Etching, obtaining an active layer corresponding to the photoresist layer pattern;
  • Step 42 Perform ashing treatment on the photoresist layer, thin the first and second photoresist segments and remove the third photoresist segment; and use a dry etching process to remove uncovered portions of the transition source drain metal layer.
  • the step 4 specifically includes the following steps:
  • Step 41' dry etching the source and drain metal layers with the photoresist layer as a shielding layer to obtain a transition source and drain metal layer corresponding to the photoresist layer pattern;
  • Step 42 ′ performing a wet etching on the photoresist layer, the semiconductor layer, and the transition source drain metal layer, so that the uncovered portion of the semiconductor layer is etched away to obtain an active layer corresponding to the photoresist layer pattern. Thinning the first and second photoresist segments and causing the third photoresist segment to be etched away, such that a portion of the transition source drain metal layer corresponding to the third photoresist segment is etched away, resulting in the corresponding a source of the first photoresist segment pattern and a drain corresponding to the second photoresist segment pattern, such that the upper surface of the active layer is a portion of the contact layer corresponding to the third photoresist segment is etched away to obtain a channel region on the active layer, and corresponding source and drain contact regions respectively located under the source and drain are removed, and the remaining portion is removed. Photoresist material.
  • the length of the semi-transmissive extending region is larger than the width of the horizontal strip portion in the semi-transmissive region by 1 to 3 ⁇ m; and the width of the vertical strip portion and the width of the horizontal strip portion in the semi-transmissive region are both greater than 1 ⁇ m.
  • the width of the vertical strip portion in the semi-transmissive region is equal to the width of the horizontal strip portion.
  • the present invention also provides a halftone mask comprising first and second opaque regions respectively corresponding to source and drain positions of the thin film transistor, U-shaped for active layer with the thin film transistor a U-shaped semi-transmissive region corresponding to the position of the channel region, two semi-transmissive extending regions extending outside the opening of the U-shaped semi-transmissive region, and remaining remaining light-transmissive regions;
  • the first opaque region includes a strip portion, and the second opaque region includes a U-shaped portion, and one end of the strip portion of the first opaque region extends into the second opaque portion a U-shaped portion of the region is not in contact with the opening of the U-shaped portion, thereby forming a U-shaped gap;
  • the semi-transmissive region is located and fills a U-shaped gap between the first opaque region and the second opaque region, and the semi-transmissive region includes a vertical strip portion and is respectively connected to the vertical strip Two horizontal strip portions at both ends to form a U-shaped structure;
  • the semi-transmissive extending region is perpendicular to a strip portion of the first opaque region and extends outwardly of the U-shaped structure of the semi-transmissive region, and is in contact with the semi-transmissive region and blocks the first portion An opening of a U-shaped gap between the opaque region and the second opaque region;
  • the length of the semi-transmissive extending region is greater than the width of the horizontal strip portion of the semi-transmissive region
  • the length of the semi-transmissive extension region is larger than the width of the horizontal strip portion in the semi-transmissive region by 1 to 3 ⁇ m;
  • the halftone mask provided by the present invention includes first and second opaque regions for respectively corresponding to source and drain positions of the thin film transistor, and active for the thin film transistor a U-shaped semi-transmissive region corresponding to the position of the U-shaped channel region of the layer, two semi-transmissive extending regions extending outside the opening of the U-shaped semi-transmissive region, and the remaining fully transparent region
  • the semi-transmissive extension region can avoid over-expanding and over-etching when edge-effects are formed when patterning the source and drain electrodes and the channel region, thereby eliminating the problem of insufficient yield and low yield in the prior art.
  • the method for fabricating the TFT substrate provided by the present invention adopts the above-mentioned halftone mask to avoid the occurrence of edge effects when patterning the channel region is formed, thereby causing excessive and excessive engraving, thereby eliminating the shortage of yield and the yield in the prior art. Low problem.
  • FIG. 1 is a schematic view of a conventional step 1 of fabricating a TFT substrate using a 5Mask process
  • 2-3 is a schematic diagram of a conventional step 2 of fabricating a TFT substrate by using a 5Mask process
  • 4-5 is a schematic diagram of a conventional step 3 of fabricating a TFT substrate by using a 5Mask process
  • FIG. 6 is a schematic diagram of a conventional step 4 of fabricating a TFT substrate using a 5Mask process
  • FIG. 7 is a schematic diagram of a conventional step 5 of fabricating a TFT substrate using a 5Mask process
  • FIG. 8 is a schematic structural view of a conventional halftone mask for fabricating a TFT substrate in a 4Mask process
  • Figure 9 is a schematic structural view of a halftone mask of the present invention.
  • FIG. 10 is a schematic flow chart of a method of fabricating a TFT substrate of the present invention.
  • FIG. 11 is a schematic view showing a step 1 of a method of fabricating a TFT substrate of the present invention.
  • step 2 is a schematic diagram of step 2 of a method of fabricating a TFT substrate of the present invention.
  • Figure 13 is a schematic view showing the third step of the method for fabricating the TFT substrate of the present invention.
  • FIGS. 14-16 are schematic views showing a step 4 of a method of fabricating a TFT substrate of the present invention.
  • 17 is a schematic view showing a step 5 of a method of fabricating a TFT substrate of the present invention.
  • Figure 18 is a schematic view showing the sixth step of the method of fabricating the TFT substrate of the present invention.
  • the present invention firstly provides a halftone mask comprising first and second opaque regions 910, 920 for respectively corresponding to source and drain positions of a thin film transistor, for use with the film.
  • a U-shaped semi-transmissive region 930 corresponding to the U-shaped channel region of the active layer of the transistor, two semi-transmissive extension regions 940 located at the opening of the U-shaped semi-transmissive region 930 and extending outwardly of the opening, And the remaining fully transparent region 950.
  • the first opaque region 910 includes a strip portion 911
  • the second opaque region 920 includes a U-shaped portion 921, and one end of the strip portion 911 of the first opaque region 910
  • the U-shaped portion 921 of the second opaque region 920 extends into and is not in contact with the opening of the U-shaped portion 920 to form a U-shaped gap.
  • the semi-transmissive region 930 is located and fills a U-shaped gap between the first opaque region 910 and the second opaque region 920, and the semi-transmissive region 930 includes a vertical strip portion. 931, and two horizontal strip portions 932 respectively connected to both ends of the vertical strip portion 931, thereby forming a U-shaped structure.
  • the semi-transmissive extending region 940 is perpendicular to the strip portion 911 of the first opaque region 910 and extends outwardly from the U-shaped structure of the semi-transmissive region 930, and the semi-transmissive region 930 meets and blocks an opening of the U-shaped gap between the first opaque region 910 and the second opaque region 920.
  • the length L of the semi-transmissive extending region 940 is greater than the width D of the horizontal strip portion 932 of the semi-transmissive region 930.
  • the length L of the semi-transmissive extending region 940 is larger than the width D of the horizontal strip portion 932 in the semi-transmissive region 930 by 1 to 3 ⁇ m.
  • the width of the vertical strip portion 931 and the width D of the horizontal strip portion 932 in the semi-transmissive region 930 are both greater than 1 ⁇ m.
  • the width of the vertical strip portion 931 in the semi-transmissive region 930 is equal to the width D of the horizontal strip portion 932.
  • the two semi-transmissive extending regions 940 are obtained by providing a semipermeable membrane at the opening of the U-shaped semi-transmissive region 930, and the semipermeable membrane is a chromium oxide film or a molybdenum silicon film.
  • the halftone mask of the present invention has a two-half transparent extending region 940 disposed at the opening of the U-shaped semi-transmissive region 930 such that the contact edge of the fully transparent region 950 and the semi-transmissive region 930 on the halftone mask Extending the exposure display of the photoresist material using the halftone mask corresponds to enlarging the flow area of the developer on the photoresist material from the semi-exposed area to the full exposure area, thereby avoiding the occurrence of edge effects and causing over-exposure And over-etching, thereby eliminating the problem of insufficient yield and low yield in the prior art.
  • the present invention further provides a method for fabricating a TFT substrate using the above-described halftone mask, comprising the following steps:
  • Step 1 as shown in FIG. 11, a substrate 100 is provided, a gate metal layer 200 is deposited on the substrate 100, and the gate metal layer 200 is patterned by a mask process using a mask to obtain a gate. Extreme 250.
  • Step 2 As shown in FIG. 12, a gate insulating layer 300 and a semiconductor layer 400 are sequentially deposited on the gate 250 and the substrate 100, and the semiconductor layer 400 is subjected to ion doping treatment to make the semiconductor layer 400 The upper surface portion forms an ohmic contact layer 410.
  • Step 3 depositing a source/drain metal layer 500 on the semiconductor layer 400, applying a photoresist material on the source/drain metal layer 500, using a halftone mask 900 The layer of photoresist is exposed.
  • the halftone mask 900 includes first and second opaque regions 910 and 920 between the first opaque region 910 and the second opaque region 920 .
  • the exposed photoresist material is developed with a developing solution to obtain a photoresist layer 600 having a patterned structure, the photoresist layer 600 including a first photoresist segment 610 formed corresponding to the first opaque region 910, a second photoresist segment 620 formed corresponding to the second opaque region 920 and a U-shaped portion formed between the first photoresist segment 610 and the second photoresist segment 620 corresponding to the semi-transmissive region 930
  • the third photoresist segment 630 has a thickness greater than a thickness of the third photoresist segment 630 and the second photoresist segment 630.
  • the first opaque region 910 includes a strip portion 911
  • the second opaque region 920 includes a U-shaped portion 921, and one end of the strip portion 911 of the first opaque region 910
  • the U-shaped portion 921 of the second opaque region 920 extends into and is not in contact with the opening of the U-shaped portion 920 to form a U-shaped gap.
  • the semi-transmissive region 930 is located and fills a U-shaped gap between the first opaque region 910 and the second opaque region 920, and the semi-transmissive region 930 includes a vertical strip portion. 931, and two horizontal strip portions 932 respectively connected to both ends of the vertical strip portion 931, thereby forming a U-shaped structure.
  • the semi-transmissive extending region 940 is perpendicular to the strip portion 911 of the first opaque region 910 and extends outwardly from the U-shaped structure of the semi-transmissive region 930, and the semi-transmissive region
  • the opening 930 meets and blocks the opening of the U-shaped gap between the first opaque region 910 and the second opaque region 920; the length L of the semi-transmissive extending region 940 is greater than the semi-transmissive region 930 The width D of the horizontal strip portion 932.
  • the length L of the semi-transmissive extending region 940 is larger than the width D of the horizontal strip portion 932 in the semi-transmissive region 930 by 1 to 3 ⁇ m.
  • the width of the vertical strip portion 931 and the width D of the horizontal strip portion 932 in the semi-transmissive region 930 are both greater than 1 ⁇ m.
  • the width of the vertical strip portion 931 in the semi-transmissive region 930 is equal to the width D of the horizontal strip portion 932.
  • the two semi-transmissive extending regions 940 are obtained by providing a semipermeable membrane at the opening of the U-shaped semi-transmissive region 930, and the semipermeable membrane is a chromium oxide film or a molybdenum silicon film.
  • two semi-transmissive extension regions 940 are disposed at the opening of the U-shaped semi-transmissive region 930 corresponding to the channel region, such that the halftone
  • the contact edge of the all-transmissive region 950 and the semi-transmissive region 930 on the mask 900 is extended, and when the photoresist is exposed and displayed using the halftone mask 900, it is equivalent to enlargement.
  • the flow area of the developer on the photoresist material from the half-exposure region to the full-exposure region avoids the generation of edge effects, thereby preventing the first photoresist segment 610 from being excessively opened at the opening of the U-shaped third photoresist segment 630.
  • the development avoids the occurrence of source breakage caused by excessive etching of the source and drain metal layer 500 during subsequent etching to form the source.
  • Step 4 etching the source/drain metal layer 500 to obtain a source 510 corresponding to the pattern of the first photoresist segment 610 and corresponding to the second photoresist segment 620.
  • a drain 520 of the pattern the semiconductor layer 400 is etched to obtain an active layer 450 corresponding to the pattern of the photoresist layer 600, and the ohmic contact layer 410 on the upper surface of the semiconductor layer 400 corresponds to the third layer
  • a portion of the photoresist segment 630 is etched away to obtain a channel region 453 on the active layer 450, and source and drain contact regions 451, 452 corresponding to the source and drain electrodes 510, 520, respectively, are obtained.
  • the step 4 can be implemented by two dry etching and two wet etching, and specifically includes the following steps:
  • Step 41 dry etching the source/drain metal layer 500 with the photoresist layer 600 as a shielding layer to obtain a transition source/drain metal layer 500 ′ corresponding to the photoresist layer 600 pattern, and the semiconductor The layer 400 is wet etched to obtain an active layer 450 corresponding to the pattern of the photoresist layer 600.
  • Step 42 Perform ashing treatment on the photoresist layer 600, thin the first and second photoresist segments 610 and 620 and remove the third photoresist segment 630; and remove the transition source drain metal layer 500' by a dry etching process.
  • the uncovered portion obtains the source 510 corresponding to the pattern of the first photoresist segment 610 and the drain 520 corresponding to the pattern of the second photoresist segment 620; removing the active layer 450 by a wet etching process a portion of the upper surface of the ohmic contact layer 410 that is not covered, a channel region 453 on the active layer 450 is obtained, and source and drain contact regions 451 respectively located under the source and drain electrodes 510 and 520 are obtained. 452, removing the remaining photoresist material.
  • the step 4 can also be implemented by one dry etching and one wet etching, and specifically includes the following steps:
  • Step 41' dry etching the source and drain metal layer 500 with the photoresist layer 600 as a shielding layer, to obtain a transition source and drain metal layer 500' corresponding to the pattern of the photoresist layer 600;
  • Step 42 ′ wet etching the photoresist layer 600 , the semiconductor layer 400 , and the transition source/drain metal layer 500 ′, so that the uncovered portion of the semiconductor layer 400 is etched away, and the photoresist corresponding to the photoresist is obtained.
  • the active layer 450 of the layer 600 pattern is such that the first and second photoresist segments 610, 620 are thinned and the third photoresist segment 630 is etched away, so that the third source of light on the transition source drain metal layer 500' A portion of the resistive segment 630 is etched away to obtain a source 510 corresponding to the pattern of the first photoresist segment 610 and a drain 520 corresponding to the pattern of the second photoresist segment 620 such that the upper surface of the active layer 450 A portion of the ohmic contact layer 410 corresponding to the third photoresist segment 630 is etched away to obtain a channel region 453 on the active layer 450, and corresponding sources and drains respectively located under the source and drain electrodes 510 and 520 are obtained. Extremely connected The touch regions 451, 452 remove the remaining photoresist material.
  • Step 5 depositing a passivation layer 700 on the source 510, the drain 520, the active layer 450, and the gate insulating layer 300, using a mask using a mask process for the blunt
  • the layer 700 is patterned to obtain a first via 710 corresponding to the upper surface of the drain 520;
  • Step 6 As shown in FIG. 18, a transparent electrode layer is deposited on the passivation layer 700, and the transparent electrode layer is patterned by using a mask process using a mask process to obtain a pixel electrode 810.
  • the present invention provides a halftone mask comprising first and second opaque regions respectively corresponding to source and drain positions of a thin film transistor, for active with the thin film transistor a U-shaped semi-transmissive region corresponding to the position of the U-shaped channel region of the layer, two semi-transmissive extending regions extending outside the opening of the U-shaped semi-transmissive region, and the remaining fully transparent region
  • the semi-transmissive extension region can avoid over-expanding and over-etching when edge-effects are formed when patterning the source and drain electrodes and the channel region, thereby eliminating the problem of insufficient yield and low yield in the prior art.
  • the method for fabricating the TFT substrate provided by the present invention adopts the above-mentioned halftone mask to avoid the occurrence of edge effects when patterning the channel region is formed, thereby causing excessive and excessive engraving, thereby eliminating the shortage of yield and the yield in the prior art. Low problem.

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Abstract

一种半色调掩模板及TFT基板的制作方法，半色调掩模板包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域（910，920）、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域（930）、位于该U形的半透光区域（930）开口处并向该开口外延伸的两半透光延伸区域（940）、以及剩余的全透光区域（950）；该半透光延伸区域（940）可以避免在构图形成源漏极、及沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。TFT基板的制作方法，采用上述半色调掩模板，可以避免在构图形成沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。

Description

半色调掩模板及TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种半色调掩模板及TFT基板的制作方法。
背景技术
液晶显示器，因具有能耗低、辐射小、轻、薄等优点，被广泛地应用于各种生活用品、办公用品中，如电脑、手机、公告显示板等。
液晶显示器包括薄膜晶体管(Thin Film Transist，TFT)阵列基板、彩膜基板以及注入两板之间的液晶层。在制作薄膜晶体管基板时通常通过4～6轮掩模(Mask)工艺，经过薄膜沉积、掩模板曝光、显影、刻蚀等工艺而制得。随着科学技术的发展，半色调掩模板的出现已经将液晶面板的制作工艺减少到了4Mask工艺技术。
如图1-7所示，现有采用5Mask工艺制作TFT基板的方法，包括如下步骤：
步骤1、如图1所示，提供一基板10，在所述基板10上沉积栅极金属层，使用一掩模板采用一道光罩制程对该栅极金属层进行图形化处理，得到栅极25；
步骤2、如图2-3所示，在所述栅极25、及基板10上依次沉积栅极绝缘层30、半导体层40，对该半导体层40进行离子掺杂处理，使所述半导体层40的上表面部分形成欧姆接触层41，使用一掩模板采用一道光罩制程对该半导体层40进行图形化处理，得到有源层45；
步骤3、如图4-5所示，在所述栅极绝缘层30、及有源层45的两端上沉积源漏极金属层，使用一掩模板采用一道光罩制程对该源漏极金属层进行图形化处理，得到源、漏极51、52；以源、漏极51、52为遮蔽层，对有源层45进行刻蚀，将所述有源层45上未被源、漏极51、52覆盖的经离子处理的表面刻蚀掉，得到有源层45上的沟道区46，及分别对应位于所述源、漏极51、52下方的源、漏极接触区47、48；
步骤4、如图6所示，在所述源极51、漏极52、有源层45、及栅极绝缘层30上沉积钝化层70，使用一掩模板采用一道光罩制程对该钝化层70进行图形化处理，得到对应于所述漏极52上方的第一过孔71；
步骤5、如图7所示，在所述钝化层70层上沉积透明电极层，使用一 掩模板采用一道光罩制程对该透明电极层进行图形化处理，得到像素电极81。
而4Mask工艺与上述的5Mask工艺相比，在对该半导体层进行离子掺杂处理后，不对其进行图形化，而在其上直接沉积源漏极金属层，然后只需使用一半色调掩模板(Half Tone Mask)采用一道半色调光罩制程即可完成上述5Mask工艺中步骤2和步骤3所使用的两道光罩制程所形成的图案。其中，如图8所示，现有4Mask工艺所使用的半色调掩模板90包括分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域91、92、与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域93、及剩余的全透光区域94，半色调掩模板90上的用于形成U形沟道区的半透光区域93位于第一、第二不透光区域91、92之间的间隙而呈U形，该U形的半透光区域93开口处直接连接全透光区域94，因此在4Mask工艺中使用该半色调掩模板90对光阻材料进行曝光显影时，对应第一、第二不透光区域91、92的部分为不曝光区，对应半透光区域93的部分为半曝光区，其他部分为全曝光区，光阻材料上经过全曝光的部分短时间内在该区域内消耗了大量的显影液，而经过半曝光的部分仅消耗了部分显影液，因此有部分显影液从半曝光区渗透到全曝光区，显影液流动过程中增加了交界处的显影，从而在形成源极时在对应U形的沟道区的开口处容易过显及过刻，增加了源极在该处断裂的风险，该种现象将造成后续工艺的不稳定性，降低产能，也降低了产品的品质。
发明内容
本发明的目的在于提供一种半色调掩模板，可以避免在构图形成源漏极、及沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。
本发明的目的还在于提供一种TFT基板的制作方法，采用上述半色调掩模板，可以避免在构图形成沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。
为实现上述目的，本发明首先提供了一种半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；
所述第一不透光区域包括一条形部，所述第二不透光区域包括一U形 部，所述第一不透光区域的条形部的一端伸入所述第二不透光区域的U形部的开口内并与其不相接，从而形成一U形间隙；
所述半透光区域位于并填满所述第一不透光区域与第二不透光区域之间的U形间隙，所述半透光区域包括一竖条部、及分别连接于竖条部两端的两横条部，从而形成U形结构；
所述半透光延伸区域垂直于所述第一不透光区域的条形部并向所述半透光区域的U形结构外延伸，与所述半透光区域相接并挡住所述第一不透光区域与第二不透光区域之间的U形间隙的开口；
所述半透光延伸区域的长度大于所述半透光区域的横条部的宽度。
所述半透光延伸区域的长度比所述半透光区域中横条部的宽度大1～3μm。
所述半透光区域中竖条部的宽度与横条部的宽度均大于1μm。
所述半透光区域中竖条部的宽度与横条部的宽度相等。
所述两半透光延伸区域通过在所述U形的半透光区域开口处设置一层半透膜得到，所述半透膜为氧化铬薄膜、或钼硅薄膜。
本发明还提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积栅极金属层，使用一掩模板采用一道光罩制程对该栅极金属层进行图形化处理，得到栅极；
步骤2、在所述栅极、及基板上依次沉积栅极绝缘层、及半导体层，对该半导体层进行离子掺杂处理，使所述半导体层的上表面部分形成欧姆接触层；
步骤3、在所述半导体层上沉积源漏极金属层，在所述源漏极金属层上涂覆一层光阻材料，使用一半色调掩模板对该层光阻材料进行曝光；
所述半色调掩模板包括第一、第二不透光区域、位于所述第一不透光区域与第二不透光区域之间间隙的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；所述第一不透光区域包括一条形部，所述第二不透光区域包括一U形部，所述第一不透光区域的条形部的一端伸入所述第二不透光区域的U形部的开口内并与其不相接，从而形成一U形间隙；所述半透光区域位于并填满所述第一不透光区域与第二不透光区域之间的U形间隙，包括一竖条部、及分别连接于竖条部两端的两横条部，从而形成U形结构，所述半透光延伸区域垂直于所述第一不透光区域的条形部并向所述半透光区域的U形结构外延伸，与所述半透光区域相接并挡住所述第一不透光区域与第二不透光区域之间的U形间隙的开口；所述半透光延伸区域的长度大于所 述半透光区域的横条部的宽度；
然后用显影液对经曝光后的光阻材料进行显影，得到具有图形结构的光阻层，该光阻层包括对应所述第一不透光区域形成的第一光阻段、对应所述第二不透光区域形成的第二光阻段、及对应所述半透光区域形成的位于第一光阻段与第二光阻段之间的U形的第三光阻段，所述第一光阻段与第二光阻段的厚度大于第三光阻段的厚度；
步骤4、对所述源漏极金属层进行刻蚀，得到对应于所述第一光阻段图形的源极、及对应于第二光阻段图形的漏极，对所述半导体层进行刻蚀，得到对应于所述光阻层图形的有源层，将所述半导体层上表面的欧姆接触层上对应于第三光阻段的部分刻蚀掉，得到有源层上的沟道区，并得到分别对应位于所述源、漏极下方的源、漏极接触区；
步骤5、在所述源极、漏极、有源层、及栅极绝缘层上沉积钝化层，使用一掩模板采用一道光罩制程对该钝化层进行图形化处理，得到对应于所述漏极上方的第一过孔；
步骤6、在所述钝化层上沉积透明电极层，使用一掩模板采用一道光罩制程对该透明电极层进行图形化处理，得到像素电极。
可选地，所述步骤4具体包括以下步骤：
步骤41、以光阻层为遮蔽层对所述源漏极金属层进行干法刻蚀，得到对应于所述光阻层图形的过渡源漏极金属层，对所述半导体层进行湿法刻蚀，得到对应于所述光阻层图形的有源层；
步骤42、对光阻层进行灰化处理，薄化第一、第二光阻段并去除第三光阻段；采用干法刻蚀工艺去除过渡源漏极金属层上未被覆盖的部分，得到对应于所述第一光阻段图形的源极、及对应于第二光阻段图形的漏极；采用湿法刻蚀工艺去除有源层上表面的欧姆接触层上未被覆盖的部分，得到有源层上的沟道区，并得到分别对应位于所述源、漏极下方的源、漏极接触区，去除剩余的光阻材料。
可选地，所述步骤4具体包括以下步骤：
步骤41’、以光阻层为遮蔽层对所述源漏极金属层进行干法刻蚀，得到对应于所述光阻层图形的过渡源漏极金属层；
步骤42’、对光阻层、半导体层、及过渡源漏极金属层进行湿法刻蚀，使得半导体层未被覆盖的部分刻蚀掉，得到对应于所述光阻层图形的有源层，使得第一、第二光阻段变薄并使得第三光阻段被刻蚀掉，使得过渡源漏极金属层上对应第三光阻段的部分被刻蚀掉，得到对应于所述第一光阻段图形的源极、及对应于第二光阻段图形的漏极，使得有源层上表面的欧 姆接触层上对应第三光阻段的部分被刻蚀掉，得到有源层上的沟道区，并得到分别对应位于所述源、漏极下方的源、漏极接触区，去除剩余的光阻材料。
所述半透光延伸区域的长度比所述半透光区域中横条部的宽度大1～3μm；所述半透光区域中竖条部的宽度与横条部的宽度均大于1μm。
所述半透光区域中竖条部的宽度与横条部的宽度相等。
本发明还提供一种半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；
所述第一不透光区域包括一条形部，所述第二不透光区域包括一U形部，所述第一不透光区域的条形部的一端伸入所述第二不透光区域的U形部的开口内并与其不相接，从而形成一U形间隙；
所述半透光区域位于并填满所述第一不透光区域与第二不透光区域之间的U形间隙，所述半透光区域包括一竖条部、及分别连接于竖条部两端的两横条部，从而形成U形结构；
所述半透光延伸区域垂直于所述第一不透光区域的条形部并向所述半透光区域的U形结构外延伸，与所述半透光区域相接并挡住所述第一不透光区域与第二不透光区域之间的U形间隙的开口；
所述半透光延伸区域的长度大于所述半透光区域的横条部的宽度；
其中，所述半透光延伸区域的长度比所述半透光区域中横条部的宽度大1～3μm；
其中，所述半透光区域中竖条部的宽度与横条部的宽度均大于1μm。本发明的有益效果：本发明提供的半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；该半透光延伸区域可以避免在构图形成源漏极、及沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。本发明提供的TFT基板的制作方法，采用上述半色调掩模板，可以避免在构图形成沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的采用5Mask工艺制作TFT基板的步骤1的示意图；
图2-3为现有的采用5Mask工艺制作TFT基板的步骤2的示意图；
图4-5为现有的采用5Mask工艺制作TFT基板的步骤3的示意图；
图6为现有的采用5Mask工艺制作TFT基板的步骤4的示意图；
图7为现有的采用5Mask工艺制作TFT基板的步骤5的示意图；
图8为现有的一种用于4Mask工艺制作TFT基板的半色调掩模板的结构示意图；
图9为本发明的半色调掩模板的结构示意图；
图10为本发明的TFT基板的制作方法的流程示意图；
图11为本发明的TFT基板的制作方法的步骤1的示意图；
图12为本发明的TFT基板的制作方法的步骤2的示意图；
图13为本发明的TFT基板的制作方法的步骤3的示意图；
图14-16为本发明的TFT基板的制作方法的步骤4的示意图；
图17为本发明的TFT基板的制作方法的步骤5的示意图；
图18为本发明的TFT基板的制作方法的步骤6的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图9，本发明首先提供一种半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域910、920、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域930、位于该U形的半透光区域930开口处并向该开口外延伸的两半透光延伸区域940、以及剩余的全透光区域950。
具体地，所述第一不透光区域910包括一条形部911，所述第二不透光区域920包括一U形部921，所述第一不透光区域910的条形部911的一端伸入所述第二不透光区域920的U形部921的开口内并与其不相接，从而形成一U形间隙。
具体地，所述半透光区域930位于并填满所述第一不透光区域910与第二不透光区域920之间的U形间隙，所述半透光区域930包括一竖条部931、及分别连接于竖条部931两端的两横条部932，从而形成U形结构。
具体地，所述半透光延伸区域940垂直于所述第一不透光区域910的条形部911并向所述半透光区域930的U形结构外延伸，与所述半透光区域930相接并挡住所述第一不透光区域910与第二不透光区域920之间的U形间隙的开口。
具体地，所述半透光延伸区域940的长度L大于所述半透光区域930的横条部932的宽度D。
具体地，所述半透光延伸区域940的长度L比所述半透光区域930中横条部932的宽度D大1～3μm。
具体地，所述半透光区域930中竖条部931的宽度与横条部932的宽度D均大于1μm。
具体地，所述半透光区域930中竖条部931的宽度与横条部932的宽度D相等。
具体地，所述两半透光延伸区域940通过在所述U形的半透光区域930开口处设置一层半透膜得到，所述半透膜为氧化铬薄膜、或钼硅薄膜。
本发明的半色调掩模板，通过在U形的半透光区域930的开口处设置两半透光延伸区域940，使得半色调掩模板上全透光区域950与半透光区域930的接触边缘延长，使用该半色调掩模板对光阻材料进行曝光显示时，相当于放大了光阻材料上的显影液从半曝光区域向全曝光区域的流向面积，避免了边缘效应的产生而造成过显及过刻，从而消除现有技术中良品率不足、及产率过低的问题。
请参阅图10，本发明还提供一种使用上述半色调掩模板的TFT基板的制作方法，包括如下步骤：
步骤1、如图11所示，提供一基板100，在所述基板100上沉积栅极金属层200，使用一掩模板采用一道光罩制程对该栅极金属层200进行图形化处理，得到栅极250。
步骤2、如图12所示，在所述栅极250、及基板100上依次沉积栅极绝缘层300、及半导体层400，对该半导体层400进行离子掺杂处理，使所述半导体层400的上表面部分形成欧姆接触层410。
步骤3、如图13所示，在所述半导体层400上沉积源漏极金属层500，在所述源漏极金属层500上涂覆一层光阻材料，使用一半色调掩模板900对该层光阻材料进行曝光。
具体地，如图9所示，所述半色调掩模板900包括第一、第二不透光区域910、920、位于所述第一不透光区域910与第二不透光区域920之间间隙的U形的半透光区域930、位于该U形的半透光区域930开口处并向该开口外延伸的两半透光延伸区域940、以及剩余的全透光区域950。
然后用显影液对经曝光后的光阻材料进行显影，得到具有图形结构的光阻层600，该光阻层600包括对应所述第一不透光区域910形成的第一光阻段610、对应所述第二不透光区域920形成的第二光阻段620、及对应所述半透光区域930形成的位于第一光阻段610与第二光阻段620之间的U形的第三光阻段630，所述第一光阻段610与第二光阻段620的厚度大于第三光阻段630的厚度。
具体地，所述第一不透光区域910包括一条形部911，所述第二不透光区域920包括一U形部921，所述第一不透光区域910的条形部911的一端伸入所述第二不透光区域920的U形部921的开口内并与其不相接，从而形成一U形间隙。
具体地，所述半透光区域930位于并填满所述第一不透光区域910与第二不透光区域920之间的U形间隙，所述半透光区域930包括一竖条部931、及分别连接于竖条部931两端的两横条部932，从而形成U形结构。
具体地，所述半透光延伸区域940垂直于所述第一不透光区域910的条形部911并向所述半透光区域930的U形结构外延伸，与所述半透光区域930相接并挡住所述第一不透光区域910与第二不透光区域920之间的U形间隙的开口；所述半透光延伸区域940的长度L大于所述半透光区域930的横条部932的宽度D。
具体地，所述半透光延伸区域940的长度L比所述半透光区域930中横条部932的宽度D大1～3μm。
具体地，所述半透光区域930中竖条部931的宽度与横条部932的宽度D均大于1μm。
具体地，所述半透光区域930中竖条部931的宽度与横条部932的宽度D相等。
具体地，所述两半透光延伸区域940通过在所述U形的半透光区域930开口处设置一层半透膜得到，所述半透膜为氧化铬薄膜、或钼硅薄膜。
需要说明的是，由于该步骤3中所使用的半色调掩模板900，在对应沟道区的U形的半透光区域930的开口处设置有两半透光延伸区域940，使得该半色调掩模板900上全透光区域950与半透光区域930的接触边缘延长，使用该半色调掩模板900对光阻材料进行曝光显示时，相当于放大了 光阻材料上的显影液从半曝光区域向全曝光区域的流向面积，避免了边缘效应的产生，从而避免了第一光阻段610在U形的第三光阻段630的开口处被过量显影，进而避免了在后续刻蚀形成源极时源漏极金属层500被过量刻蚀而导致源极断裂的发生。
步骤4、如图14-16所示，对所述源漏极金属层500进行刻蚀，得到对应于所述第一光阻段610图形的源极510、及对应于第二光阻段620图形的漏极520，对所述半导体层400进行刻蚀，得到对应于所述光阻层600图形的有源层450，将所述半导体层400上表面的欧姆接触层410上对应于第三光阻段630的部分刻蚀掉，得到有源层450上的沟道区453，并得到分别对应位于所述源、漏极510、520下方的源、漏极接触区451、452。
具体的，所述步骤4可以通过两次干法刻蚀加两次湿法刻蚀实现，具体包括以下步骤：
步骤41、以光阻层600为遮蔽层对所述源漏极金属层500进行干法刻蚀，得到对应于所述光阻层600图形的过渡源漏极金属层500’，对所述半导体层400进行湿法刻蚀，得到对应于所述光阻层600图形的有源层450。
步骤42、对光阻层600进行灰化处理，薄化第一、第二光阻段610、620并去除第三光阻段630；采用干法刻蚀工艺去除过渡源漏极金属层500’上未被覆盖的部分，得到对应于所述第一光阻段610图形的源极510、及对应于第二光阻段620图形的漏极520；采用湿法刻蚀工艺去除有源层450上表面的欧姆接触层410上未被覆盖的部分，得到有源层450上的沟道区453，并得到分别对应位于所述源、漏极510、520下方的源、漏极接触区451、452，去除剩余的光阻材料。
或者，所述步骤4也可以通过一次干法刻蚀加一次湿法刻蚀实现，具体包括以下步骤：
步骤41’、以光阻层600为遮蔽层对所述源漏极金属层500进行干法刻蚀，得到对应于所述光阻层600图形的过渡源漏极金属层500’；
步骤42’、对光阻层600、半导体层400、及过渡源漏极金属层500’进行湿法刻蚀，使得半导体层400上未被覆盖的部分刻蚀掉，得到对应于所述光阻层600图形的有源层450，使得第一、第二光阻段610、620变薄并使得第三光阻段630被刻蚀掉，使得过渡源漏极金属层500’上对应第三光阻段630的部分被刻蚀掉，得到对应于所述第一光阻段610图形的源极510、及对应于第二光阻段620图形的漏极520，使得有源层450上表面的欧姆接触层410上对应第三光阻段630的部分被刻蚀掉，得到有源层450上的沟道区453，并得到分别对应位于所述源、漏极510、520下方的源、漏极接 触区451、452，去除剩余的光阻材料。
步骤5、如图17所示，在所述源极510、漏极520、有源层450、及栅极绝缘层300上沉积钝化层700，使用一掩模板采用一道光罩制程对该钝化层700进行图形化处理，得到对应于所述漏极520上方的第一过孔710；
步骤6、如图18所示，在所述钝化层700上沉积透明电极层，使用一掩模板采用一道光罩制程对该透明电极层进行图形化处理，得到像素电极810。
综上所述，本发明提供一种半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；该半透光延伸区域可以避免在构图形成源漏极、及沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。本发明提供的TFT基板的制作方法，采用上述半色调掩模板，可以避免在构图形成沟道区时产生边缘效应而造成过显及过刻，从而消除现有技术中良品率不足、产率过低的问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；
    所述第一不透光区域包括一条形部，所述第二不透光区域包括一U形部，所述第一不透光区域的条形部的一端伸入所述第二不透光区域的U形部的开口内并与其不相接，从而形成一U形间隙；
    所述半透光区域位于并填满所述第一不透光区域与第二不透光区域之间的U形间隙，所述半透光区域包括一竖条部、及分别连接于竖条部两端的两横条部，从而形成U形结构；
    所述半透光延伸区域垂直于所述第一不透光区域的条形部并向所述半透光区域的U形结构外延伸，与所述半透光区域相接并挡住所述第一不透光区域与第二不透光区域之间的U形间隙的开口；
    所述半透光延伸区域的长度大于所述半透光区域的横条部的宽度。
  2. 如权利要求1所述的半色调掩模板，其中，所述半透光延伸区域的长度比所述半透光区域中横条部的宽度大1～3μm。
  3. 如权利要求1所述的半色调掩模板，其中，所述半透光区域中竖条部的宽度与横条部的宽度均大于1μm。
  4. 如权利要求1所述的半色调掩模板，其中，所述半透光区域中竖条部的宽度与横条部的宽度相等。
  5. 如权利要求1所述的半色调掩模板，其中，所述两半透光延伸区域通过在所述U形的半透光区域开口处设置一层半透膜得到，所述半透膜为氧化铬薄膜、或钼硅薄膜。
  6. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积栅极金属层，使用一掩模板采用一道光罩制程对该栅极金属层进行图形化处理，得到栅极；
    步骤2、在所述栅极、及基板上依次沉积栅极绝缘层、及半导体层，对该半导体层进行离子掺杂处理，使所述半导体层的上表面部分形成欧姆接触层；
    步骤3、在所述半导体层上沉积源漏极金属层，在所述源漏极金属层上涂覆一层光阻材料，使用一半色调掩模板对该层光阻材料进行曝光；
    所述半色调掩模板包括第一、第二不透光区域、位于所述第一不透光区域与第二不透光区域之间间隙的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；所述第一不透光区域包括一条形部，所述第二不透光区域包括一U形部，所述第一不透光区域的条形部的一端伸入所述第二不透光区域的U形部的开口内并与其不相接，从而形成一U形间隙；所述半透光区域位于并填满所述第一不透光区域与第二不透光区域之间的U形间隙，包括一竖条部、及分别连接于竖条部两端的两横条部，从而形成U形结构，所述半透光延伸区域垂直于所述第一不透光区域的条形部并向所述半透光区域的U形结构外延伸，与所述半透光区域相接并挡住所述第一不透光区域与第二不透光区域之间的U形间隙的开口；所述半透光延伸区域的长度大于所述半透光区域的横条部的宽度；
    然后用显影液对经曝光后的光阻材料进行显影，得到具有图形结构的光阻层，该光阻层包括对应所述第一不透光区域形成的第一光阻段、对应所述第二不透光区域形成的第二光阻段、及对应所述半透光区域形成的位于第一光阻段与第二光阻段之间的U形的第三光阻段，所述第一光阻段与第二光阻段的厚度大于第三光阻段的厚度；
    步骤4、对所述源漏极金属层进行刻蚀，得到对应于所述第一光阻段图形的源极、及对应于第二光阻段图形的漏极，对所述半导体层进行刻蚀，得到对应于所述光阻层图形的有源层，将所述半导体层上表面的欧姆接触层上对应于第三光阻段的部分刻蚀掉，得到有源层上的沟道区，并得到分别对应位于所述源、漏极下方的源、漏极接触区；
    步骤5、在所述源极、漏极、有源层、及栅极绝缘层上沉积钝化层，使用一掩模板采用一道光罩制程对该钝化层进行图形化处理，得到对应于所述漏极上方的第一过孔；
    步骤6、在所述钝化层上沉积透明电极层，使用一掩模板采用一道光罩制程对该透明电极层进行图形化处理，得到像素电极。
  7. 如权利要求6所述的TFT基板的制作方法，其中，所述步骤4具体包括以下步骤：
    步骤41、以光阻层为遮蔽层对所述源漏极金属层进行干法刻蚀，得到对应于所述光阻层图形的过渡源漏极金属层，对所述半导体层进行湿法刻蚀，得到对应于所述光阻层图形的有源层；
    步骤42、对光阻层进行灰化处理，薄化第一、第二光阻段并去除第三光阻段；采用干法刻蚀工艺去除过渡源漏极金属层上未被覆盖的部分，得 到对应于所述第一光阻段图形的源极、及对应于第二光阻段图形的漏极；采用湿法刻蚀工艺去除有源层上表面的欧姆接触层上未被覆盖的部分，得到有源层上的沟道区，并得到分别对应位于所述源、漏极下方的源、漏极接触区，去除剩余的光阻材料。
  8. 如权利要求6所述的TFT基板的制作方法，其中，所述步骤4具体包括以下步骤：
    步骤41’、以光阻层为遮蔽层对所述源漏极金属层进行干法刻蚀，得到对应于所述光阻层图形的过渡源漏极金属层；
    步骤42’、对光阻层、半导体层、及过渡源漏极金属层进行湿法刻蚀，使得半导体层上未被覆盖的部分刻蚀掉，得到对应于所述光阻层图形的有源层，使得第一、第二光阻段变薄并使得第三光阻段被刻蚀掉，使得过渡源漏极金属层上对应第三光阻段的部分被刻蚀掉，得到对应于所述第一光阻段图形的源极、及对应于第二光阻段图形的漏极，使得有源层上表面的欧姆接触层上对应第三光阻段的部分被刻蚀掉，得到有源层上的沟道区，并得到分别对应位于所述源、漏极下方的源、漏极接触区，去除剩余的光阻材料。
  9. 如权利要求6所述的TFT基板的制作方法，其中，所述半透光延伸区域的长度比所述半透光区域中横条部的宽度大1～3μm；所述半透光区域中竖条部的宽度与横条部的宽度均大于1μm。
  10. 如权利要求6所述的TFT基板的制作方法，其中，所述半透光区域中竖条部的宽度与横条部的宽度相等。
  11. 一种半色调掩模板，包括用于分别与薄膜晶体管的源、漏极位置对应的第一、第二不透光区域、用于与所述薄膜晶体管的有源层的U形沟道区位置对应的U形的半透光区域、位于该U形的半透光区域开口处并向该开口外延伸的两半透光延伸区域、以及剩余的全透光区域；
    所述第一不透光区域包括一条形部，所述第二不透光区域包括一U形部，所述第一不透光区域的条形部的一端伸入所述第二不透光区域的U形部的开口内并与其不相接，从而形成一U形间隙；
    所述半透光区域位于并填满所述第一不透光区域与第二不透光区域之间的U形间隙，所述半透光区域包括一竖条部、及分别连接于竖条部两端的两横条部，从而形成U形结构；
    所述半透光延伸区域垂直于所述第一不透光区域的条形部并向所述半透光区域的U形结构外延伸，与所述半透光区域相接并挡住所述第一不透光区域与第二不透光区域之间的U形间隙的开口；
    所述半透光延伸区域的长度大于所述半透光区域的横条部的宽度；
    其中，所述半透光延伸区域的长度比所述半透光区域中横条部的宽度大1～3μm；
    其中，所述半透光区域中竖条部的宽度与横条部的宽度均大于1μm。
  12. 如权利要求11所述的半色调掩模板，其中，所述半透光区域中竖条部的宽度与横条部的宽度相等。
  13. 如权利要求11所述的半色调掩模板，其中，所述两半透光延伸区域通过在所述U形的半透光区域开口处设置一层半透膜得到，所述半透膜为氧化铬薄膜、或钼硅薄膜。
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