WO2017206208A1 - 阵列基板、显示器及阵列基板的制备方法 - Google Patents

阵列基板、显示器及阵列基板的制备方法 Download PDF

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WO2017206208A1
WO2017206208A1 PCT/CN2016/086637 CN2016086637W WO2017206208A1 WO 2017206208 A1 WO2017206208 A1 WO 2017206208A1 CN 2016086637 W CN2016086637 W CN 2016086637W WO 2017206208 A1 WO2017206208 A1 WO 2017206208A1
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substrate
layer
isolation layer
array substrate
display
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French (fr)
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秦芳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/113,410 priority Critical patent/US10141351B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of flexible display technologies, and in particular, to an array substrate, a display, and a method for preparing an array substrate.
  • the main flexible display devices are prepared on an organic material substrate, and the organic material substrate is required to be water-proof, oxygen-insulating, and heat-resistant, and is required to produce a low temperature poly-silicon (LTPS) flexible display.
  • LTPS low temperature poly-silicon
  • high-temperature processes such as eximer laser annealing (ELA)
  • ELA eximer laser annealing
  • nitride or oxide buffer layer is typically deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • the low-temperature deposition of the buffer layer is loose, water-insulating, and oxygen-insulating, and when deposited at a higher temperature, the organic dust generated by the direct bombardment of the organic material substrate during the deposition process may contaminate the equipment cavity and the pipeline.
  • the technical problem to be solved by the present invention is to provide an array substrate which can avoid the problem that the plasma directly bombards the substrate made of the organic material during the high temperature plasma enhanced chemical vapor deposition process.
  • the present invention also provides a display to which the array substrate is applied.
  • the present invention also provides a method of preparing an array substrate to prepare the array substrate.
  • an array substrate comprising:
  • the substrate is made of an organic material
  • the isolation layer is made of a metal material, and the isolation layer is formed on the substrate;
  • a buffer layer formed on a side of the isolation layer facing away from the substrate.
  • the array substrate further includes a plurality of thin film transistors formed on a side of the buffer layer facing away from the isolation layer, and the plurality of thin film transistors comprise a low temperature polysilicon layer.
  • the isolation layer is made of titanium material.
  • the isolation layer is made of aluminum material, copper material or nickel material.
  • a display comprising an organic light emitting diode and the array substrate of any of the above, the organic light emitting diode being formed on a side of the buffer layer facing away from the isolation layer.
  • a method for preparing an array substrate including:
  • the isolation layer is made of a metal material
  • a plurality of thin film transistors are formed on a side of the buffer layer facing away from the isolation layer.
  • the "forming an isolation layer on the substrate” comprises depositing a titanium material on the substrate to form the isolation layer.
  • the "depositing titanium material on the substrate” comprises: depositing a titanium material on the substrate at a process temperature of 250 or less.
  • depositing a titanium material on the substrate comprises depositing a titanium material on the substrate by magnetron sputtering.
  • the “forming an isolation layer on the substrate” comprises depositing an aluminum material, a copper material or a nickel material on the substrate to form the isolation layer.
  • the present invention has the following beneficial effects:
  • An isolation layer is disposed between the substrate of the array substrate and the buffer layer according to the embodiment of the invention, and the isolation layer is made of a metal material, so the buffer layer is subjected to high temperature plasma enhanced chemical vapor deposition (Plasma Enhanced).
  • Plasma Enhanced high temperature plasma enhanced chemical vapor deposition
  • the isolation layer prevents the plasma from directly bombarding the organic matter generated by the substrate from contaminating the device chamber and the pipe.
  • the spacer layer can also reduce external heat transfer to the substrate to protect the substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a display according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an organic light emitting diode according to an embodiment of the present invention.
  • the fixed connection may also be detachably connected or integrally connected; it may be a mechanical connection; it may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • an embodiment of the present invention provides an array substrate 1 including a substrate 11 , an isolation layer 12 , and a buffer layer 13 which are sequentially stacked.
  • the substrate 11 is made of an organic material.
  • the isolation layer 12 is made of a metal material and is formed on the substrate 11.
  • the buffer layer 13 is formed on a side of the isolation layer 12 facing away from the substrate 11.
  • the isolation layer 12 is disposed between the substrate 11 and the buffer layer 13 of the array substrate 1, the isolation layer 12 is made of a metal material, so that the buffer layer 13 passes the high temperature plasma.
  • the isolation layer 12 prevents the plasma from directly bombarding the organic matter generated by the substrate 11 from contaminating the device cavity and the pipe.
  • the spacer layer 12 can also reduce external heat conduction to the substrate 11 to protect the substrate 11.
  • the isolation layer 12 can reduce the conduction of heat from the outside of the substrate 11 to the inside of the substrate 11.
  • the array substrate 1 further includes a plurality of thin film transistors 10 (TFTs), and the plurality of thin film transistors 10 are formed on the buffer layer 13 facing away from the isolation layer 12 .
  • TFTs thin film transistors
  • the plurality of thin film transistors 10 are arranged in an array on the buffer layer 13.
  • the plurality of thin film transistors 10 include a low temperature polysilicon layer 14 , that is, the active layers of the plurality of thin film transistors 10 are formed by a low temperature poly-silicon (LTPS) process.
  • the low temperature polysilicon process includes an eximer laser annealing (ELA) process.
  • ELA eximer laser annealing
  • the isolation layer 12 can effectively reduce external heat conduction to the substrate 11 and function to protect the substrate 11.
  • the isolation layer 12 may be made of a titanium (Ti) material. Because titanium has good toughness, corrosion resistance, high melting point, low thermal conductivity, low stress under extremely cold and extreme heat conditions, and can be obtained by physical vapor deposition (PVD) under low temperature conditions, The isolation layer 12 can better protect the substrate 11 use. In particular, since the toughness of the titanium material is good, the isolation layer 12 is highly resistant to plasma bombardment, and the isolation layer 12 can well protect the substrate 11 during the formation of the buffer layer 13. At the same time, since the thermal conductivity of the titanium material is low, the isolation layer 12 can effectively reduce the external heat conduction to the substrate 11 during the excimer laser crystallization, thereby protecting the substrate 11.
  • Ti titanium
  • the isolation layer 12 may also be made of an aluminum (Al) material, a copper (Cu) material, or a nickel (Ni) material.
  • Al aluminum
  • Cu copper
  • Ni nickel
  • the isolation layer 12 of the present embodiment can absorb a large amount of thermal energy, so that the external heat conduction to the substrate 11 can be effectively reduced, thereby protecting the substrate 11.
  • the plurality of thin film transistors 10 further include a gate insulating layer 15 , a gate electrode 16 , a dielectric layer 17 , a source region 192 , a drain region 191 , and a planarization layer 18 .
  • the gate insulating layer 15 covers the low temperature polysilicon layer 14 and the buffer layer 13.
  • the low temperature polysilicon layer 14 is P-type doping and channel doped to form a first portion 141, a second portion 142, and a third portion 143 that are sequentially connected.
  • the gate electrode 16 is formed on a side of the gate insulating layer 15 that faces away from the low temperature polysilicon layer 14, and the gate electrode 16 faces the second portion 142.
  • the dielectric layer 17 covers the gate electrode 16 and the gate insulating layer 15.
  • the gate insulating layer 15 and the dielectric layer 17 are jointly provided with a first hole and a second hole.
  • the first hole For exposing a portion of the first portion 141
  • the second aperture is for exposing the second portion 143.
  • the drain region 191 and the source region 192 are both formed on a surface of the dielectric layer 17 facing away from the gate insulating layer 15, and the drain region 191 is connected to the first portion 141 through the first hole.
  • the source region 192 is coupled to the second portion 142 by the second aperture.
  • the flat layer 18 covers the dielectric layer 17, the source region 192, and the drain region 191.
  • the flat layer 18 defines a third hole 110 for exposing a portion of the source region. 192, such that the source region 192 can be connected to other components.
  • the buffer layer 13 includes an oxide (for example, silicon oxide, SiOx) or/and a nitride (for example, silicon nitride, SiNx).
  • the buffer layer 13 includes a first sub-buffer layer and a second sub-buffer layer which are disposed in a stack.
  • the first sub-buffer layer is adjacent to the isolation layer 12
  • the first sub-buffer layer is a silicon nitride (SiNx) material
  • the second sub-buffer layer is silicon oxide. (SiOx) material.
  • the arrangement of the first sub-buffer layer and the second sub-buffer layer can better buffer the damage of the substrate 11 during the preparation process of the array substrate 1.
  • the first sub-buffer layer With the silicon nitride material, a hydrogen (H) element can be generated for repairing the low temperature polysilicon layer 14 when the silicon nitride material is prepared, and the electrical properties of the low temperature polysilicon layer 14 are improved.
  • the second sub-buffer layer is made of a silicon oxide material for improving stress of the second sub-buffer layer and preventing the second sub-buffer layer from falling off.
  • the organic material is Polyimide (PI).
  • the substrate 11 may also be made of other organic materials (materials composed of elements such as carbon, hydrogen, oxygen, nitrogen, etc. are collectively referred to as organic materials).
  • the flexible material is preferred such that the substrate 11 is a flexible substrate.
  • an embodiment of the present invention further provides a display 100 including an organic light emitting diode 2 and the array substrate 1 according to any of the above embodiments, that is, the display 100 is an organic light emitting diode. monitor.
  • the organic light emitting diode 2 is formed on a side of the buffer layer 13 facing away from the isolation layer 12.
  • the organic light emitting diode 2 is formed on a side of the plurality of thin film transistors 10 facing away from the buffer layer 13.
  • the display 100 is a flexible display.
  • the array substrate 1 used in the display 100 includes an isolation layer 12 disposed between the substrate 11 and the buffer layer 13, and the isolation layer 12 is made of metal.
  • the isolation layer 12 can prevent the plasma from directly bombarding the organic material contamination device generated by the substrate 11 Cavity and pipe.
  • the isolation layer 12 can also reduce the external heat conduction to the substrate 11 and function to protect the substrate 11.
  • the isolation layer 12 since the isolation layer 12 has a certain conductivity, it can also function as an electrostatic shield, which improves the antistatic interference capability of the display 100.
  • the isolation layer 12 is made of a titanium material, an aluminum material, a copper material or a nickel material.
  • the organic light emitting diode 2 includes an anode 21, a light emitting layer 24, and a cathode 27.
  • the light emitting layer 24 is located at the anode 21 and the Between the cathodes 27.
  • the anode 21 is a transparent electrode
  • the cathode 27 is a transparent electrode or a translucent electrode. Since the isolation layer 12 is made of a metal material such as titanium, the transmittance to light is low, and thus the isolation layer 12 can serve as a reflective layer of the organic light emitting diode 2.
  • the isolation layer 12 reflects the light emitted by the light-emitting layer 24, and the organic light-emitting diode 2 realizes top emission. Due to the anode 21 And the cathodes 27 are all made of transparent electrodes, and the same material can be used, thereby reducing the production cost of the organic light emitting diode 2, that is, reducing the cost of the display 100.
  • the isolation layer 12 forms a resonant microcavity with the translucent cathode 27, which increases the total optical path of the microcavity and prevents the microcavity from being adjusted to the organic light emitting diode 2.
  • the organic film layer (for example, the light-emitting layer 24) is excessively dependent, thereby improving the adjustability of the organic light-emitting diode 2, so that the organic light-emitting diode 2 has higher luminous efficiency, so that the display 100 has better performance. Display effect and low energy consumption.
  • the transparent electrode may be made of indium tin oxide (ITO) to reduce the cost of the organic light emitting diode 2, that is, to reduce the manufacturing cost of the display 100.
  • ITO indium tin oxide
  • the hole injecting ability can be improved and the hole injecting energy barrier can be lowered.
  • the anode 21 may also be selected from other transparent conductive materials having a high work function.
  • the cathode 27 may be made of a magnesium-silver (Mg/Ag) alloy to form a translucent electrode. Among them, the ratio of magnesium to silver is 1:9. It should be understood that in other embodiments, the cathode 27 may also utilize other translucent conductive materials having a low work function.
  • Mg/Ag magnesium-silver
  • the OLED 2 further includes a Hole Inject Layer (HIL) 22, a Hole Transport Layer (HTL) 23, An electron transport layer (ETL) 25 and an electron injecting layer (EIL) 26 are used to increase the transmission and balance of electrons or holes, thereby improving the luminous efficiency of the organic light emitting diode 2.
  • the hole injection layer 22 is formed on a side of the anode 21 facing the light-emitting layer 24.
  • the hole transport layer 23 is formed between the hole injection layer 22 and the light emitting layer 24.
  • the electron transport layer 25 is formed on a side of the light emitting layer 24 facing away from the hole transport layer 23.
  • the electron injection layer 26 is formed between the electron transport layer 25 and the cathode 27.
  • the anode 21 can be connected to the source region 192 through the third hole 110 to implement the organic light emitting diode 2 and the array substrate. 1 electrical connection.
  • an embodiment of the present invention further provides a method for preparing an array substrate 1 for preparing the array substrate 1 of the above embodiment.
  • the preparation method comprises:
  • Step 1 providing a substrate 11 using an organic material
  • Step 2 forming an isolation layer 12 on the substrate 11, the isolation layer 12 is made of a metal material;
  • Step 3 forming a buffer layer 13 on a side of the isolation layer 12 facing away from the substrate 11;
  • Step 4 forming a plurality of thin film transistors 10 on a side of the buffer layer 13 facing away from the isolation layer 12.
  • the isolation layer 12 is disposed on the substrate 11, the isolation layer 12 is made of a metal material, so when the buffer layer 13 is subjected to plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, The PECVD process is formed on the side of the isolation layer 12 facing away from the substrate 11, which prevents the plasma from directly bombarding the organic matter generated by the substrate 11 from contaminating the device cavity and the conduit. At the same time, the isolation layer 12 can also reduce the external heat conduction to the substrate 11 and function to protect the substrate 11.
  • plasma enhanced chemical vapor deposition Plasma enhanced chemical vapor deposition
  • the PECVD process is formed on the side of the isolation layer 12 facing away from the substrate 11, which prevents the plasma from directly bombarding the organic matter generated by the substrate 11 from contaminating the device cavity and the conduit.
  • the isolation layer 12 can also reduce the external heat conduction to the substrate 11 and function to protect the substrate 11.
  • step Step 2 includes depositing a titanium material on the substrate to form the isolation layer 12. Since the titanium material has characteristics of good toughness, corrosion resistance, high melting point, low thermal conductivity, and low stress under extremely cold and extreme heat conditions, the isolation layer 12 can better protect the substrate 11. In particular, since the toughness of the titanium material is good, the isolation layer 12 is highly resistant to plasma bombardment, and the isolation layer 12 can well protect the substrate 11 during the formation of the buffer layer 13. At the same time, since the thermal conductivity of the titanium material is low, the isolation layer 12 can effectively reduce the external heat conduction to the substrate 11 during the excimer laser crystallization, thereby protecting the substrate 11.
  • the “depositing titanium material on the substrate” includes: depositing a titanium material on the substrate at a process temperature of 250° or less, that is, the titanium material may be deposited by low temperature deposition to form a The isolation layer 12 is less difficult to form.
  • the "depositing a titanium material on the substrate” includes depositing a titanium material on the buffer layer 13 by magnetron sputtering.
  • the magnetron sputtering is one of physical Vapor Deposition (PVD). Magnetron sputtering increases the plasma density by introducing a magnetic field on the surface of the target cathode and utilizing the constraints of the magnetic field on the charged particles to increase the sputtering rate.
  • the titanium material may also be deposited by other physical vapor deposition methods.
  • step Step 2 includes depositing an aluminum material, a copper material or a nickel material on the substrate to form the isolation layer 12.
  • the isolation layer 12 of the embodiment can Since a large amount of heat energy can be absorbed, the external heat conduction to the substrate 11 can be effectively reduced, and the substrate 11 can be protected.
  • step Step 4 includes:
  • Step 41 forming an amorphous silicon layer on a side of the buffer layer 13 facing away from the isolation layer 12;
  • Step 42 converting the amorphous silicon layer into a polysilicon layer by an eximer laser annealing (ELA) process;
  • Step 43 patterning the polysilicon layer by a photolithography process
  • Step 44 P-type doping and channel doping, the polysilicon layer is formed into an active layer of the plurality of thin film transistors 10 (ie, low-temperature polysilicon layer 14);
  • Step 45 sequentially forming a gate insulating layer 15, a gate electrode 16, a dielectric layer 17, a source region 192, a drain region 191, and a flat layer 18 on the active layer and the buffer layer 13 to form the plurality of Thin film transistor 10.
  • the spacer layer 12 can reduce the external heat conduction to the substrate 11 during the process of excimer laser crystallization, thereby protecting the substrate 11.
  • the amorphous silicon layer may be pre-cleaned by dehydrogenation and excimer laser crystallization.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种阵列基板（1），包括：基板（11），采用有机材料；隔离层（12），采用金属材质，隔离层（12）形成在基板（11）上；及缓冲层（13），缓冲层（13）形成在隔离层（12）背离基板（11）的一侧。阵列基板（1）在高温等离子体增强化学气相沉积过程中，可避免等离子直接轰击由有机材料制成的基板（11）而产生污染问题。还提供一种应用阵列基板（1）的显示器（100）以及一种阵列基板（1）的制备方法。

Description

阵列基板、显示器及阵列基板的制备方法
本发明要求2016年5月31日递交的发明名称为“阵列基板、显示器及阵列基板的制备方法”的申请号201610375303.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及柔性显示器技术领域，尤其涉及一种阵列基板、一种显示器以及一种阵列基板的制备方法。
背景技术
目前主要的柔性显示器件是基于有机材料基板上制备的，而由于有机材料基板隔水、隔氧、耐热能力较差，且在制作低温多晶硅(Low temperature poly-silicon，LTPS)柔性显示器时需经过准分子镭射结晶(Eximer laser annealing，ELA)等高温制程，因此需要在基板上制备一层较厚的氮化物或氧化物作为缓冲层，避免有机材料基板受到损伤。氮化物或氧化物缓冲层一般是通过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积。通过低温沉积的缓冲层膜层疏松、隔水、隔氧效果较差，而采用较高温度沉积时，沉积过程中等离子直接轰击有机材料基板产生的有机物尘埃会污染设备腔体和管道等。
发明内容
本发明所要解决的技术问题在于提供一种阵列基板，所述阵列基板在高温等离子体增强化学气相沉积过程中，可避免等离子直接轰击由有机材料制成的基板而产生污染问题。
另外，本发明还提供一种应用所述阵列基板的显示器。
此外，本发明还提供一种阵列基板的制备方法，以制备所述阵列基板。
为了实现上述目的，本发明实施方式采用如下技术方案：
一方面，提供一种阵列基板，包括：
基板，采用有机材料；
隔离层，采用金属材质，所述隔离层形成在所述基板上；及
缓冲层，所述缓冲层形成在所述隔离层背离所述基板的一侧。
其中，所述阵列基板还包括多个薄膜晶体管，所述多个薄膜晶体管形成在所述缓冲层背离所述隔离层的一侧，所述多个薄膜晶体管包括低温多晶硅层。
其中，所述隔离层采用钛材料。
其中，所述隔离层采用铝材料、铜材料或镍材料。
另一方面，还提供一种显示器，包括有机发光二极管和如上述任一项所述的阵列基板，所述有机发光二极管形成在所述缓冲层背离所述隔离层的一侧。
再另一方面，还提供一种阵列基板的制备方法，包括：
提供基板，所述基板采用有机材料；
在所述基板上形成隔离层，所述隔离层采用金属材质；
在所述隔离层背离所述基板的一侧上形成缓冲层；及
在所述缓冲层背离所述隔离层的一侧上形成多个薄膜晶体管。
其中，所述“在所述基板上形成隔离层”包括：在所述基板上沉积钛材料，以形成所述隔离层。
其中，所述“在所述基板上沉积钛材料”包括：在所述基板上沉积钛材料的工艺温度小于等于250°。
其中，所述“在所述基板上沉积钛材料”包括：通过磁控溅射在所述基板上沉积钛材料。
其中，所述“在所述基板上形成隔离层”包括：在所述基板上沉积铝材料、铜材料或镍材料，以形成所述隔离层。
相较于现有技术，本发明具有以下有益效果：
由于本发明实施例所述阵列基板的所述基板与所述缓冲层之间设置有隔离层，所述隔离层采用金属材质，故而在所述缓冲层通过高温等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)的过程中，所述隔离层可防止等离子体直接轰击所述基板产生的有机物污染设备腔体和管道。同时，在后续的其他高温工艺中，例如准分子镭射结晶过程，所述隔离层也能够降低外部对所述基板的热传导，起到保护所述基板的作用。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本发明实施例提供的一种阵列基板的结构示意图。
图2是本发明实施例提供的一种显示器的结构示意图。
图3是本发明实施例提供的一种有机发光二极管的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“设置在……上”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现该工序所预期的作用则也包括在本用语中。另外， 本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
请参阅图1，本发明实施例提供了一种阵列基板1，包括依次层叠设置的基板11、隔离层12以及缓冲层13。其中，所述基板11采用有机材料制成。所述隔离层12采用金属材质制成，并且形成在所述基板11上。所述缓冲层13形成在所述隔离层12背离所述基板11的一侧。
在本实施例中，由于所述阵列基板1的所述基板11与所述缓冲层13之间设置有隔离层12，所述隔离层12采用金属材质，故而在所述缓冲层13通过高温等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)的过程中，所述隔离层12可防止等离子体直接轰击所述基板11产生的有机物污染设备腔体和管道。同时，在后续的其他高温工艺中，例如准分子镭射结晶过程，所述隔离层12也能够降低外部对所述基板11的热传导，起到保护所述基板11的作用。
应当理解的，所述“外部”指所述基板11的外部，也即所述隔离层12能够降低热量自所述基板11的外部向所述基板11的内部的传导。
进一步地，请参阅图1，所述阵列基板1还包括多个薄膜晶体管10(Thin-film transistor，TFT)，所述多个薄膜晶体管10形成在所述缓冲层13背离所述隔离层12的一侧。所述多个薄膜晶体管10呈阵列排布在所述缓冲层13上。
进一步地，请参阅图1，所述多个薄膜晶体管10包括低温多晶硅层14，也即所述多个薄膜晶体管10的有源层采用低温多晶硅(Low temperature poly-silicon，LTPS)工艺制成。所述低温多晶硅工艺包括准分子镭射结晶过程(Eximer laser annealing，ELA)。在准分子镭射结晶过程中，所述隔离层12能够有效降低外部对所述基板11的热传导，起到保护所述基板11的作用。
进一步地，作为一种优选实施例，所述隔离层12可采用钛(Ti)材料。由于钛材料具有韧性好、耐腐蚀、熔点高、热导系数低、在极冷极热条件下应力小，且能够在低温条件下通过物理气相沉积(Physical Vapor Deposition，PVD)得到等特点，故而所述隔离层12能够更好地起到保护所述基板11的作 用。特别的，由于钛材料的韧性好，故而所述隔离层12抗等离子体轰击能力强，在所述缓冲层13的形成过程中，所述隔离层12能够很好地保护所述基板11。同时，由于所述钛材料的导热系数低，在准分子镭射结晶过程中，所述隔离层12亦能够有效降低外部对所述基板11的热传导，起到保护所述基板11的作用。
进一步地，作为另一种优选实施例，所述隔离层12也可采用铝(Al)材料、铜(Cu)材料或者镍(Ni)材料。在准分子镭射结晶过程中，本实施例所述隔离层12能够吸收大量热能，故而能够有效降低外部对所述基板11的热传导，起到保护所述基板11的作用。
进一步地，请参阅图1，可选的，所述多个薄膜晶体管10还包括栅极绝缘层15、栅极16、介质层17、源区192、漏区191以及平坦层18。具体而言：所述栅极绝缘层15覆盖所述低温多晶硅层14和所述缓冲层13。所述低温多晶硅层14经过P型掺杂(P-type doping)和沟道掺杂，形成依次连接的第一部分141、第二部分142以及第三部分143。所述栅极16形成在所述栅极绝缘层15背离所述低温多晶硅层14的一侧，且所述栅极16正对所述第二部分142。所述介质层17覆盖所述栅极16以及所述栅极绝缘层15，所述栅极绝缘层15与所述介质层17上共同开设有第一孔和第二孔，所述第一孔用于显露部分所述第一部分141，所述第二孔用于暴露所述第二部分143。所述漏区191和所述源区192均形成在所述介质层17背离所述栅极绝缘层15的表面上，所述漏区191通过所述第一孔连接至所述第一部分141，所述源区192通过所述第二孔连接至所述第二部分142。所述平坦层18覆盖所述介质层17、所述源区192以及所述漏区191，所述平坦层18开设有第三孔110，所述第三孔110用于暴露部分所述源区192，使得所述源区192可与其他部件实现连接。
进一步地，所述缓冲层13包括氧化物(例如氧化硅，SiOx)或/和氮化物(例如氮化硅，SiNx)。优选的，所述缓冲层13包括层叠设置的第一子缓冲层及第二子缓冲层。所述第一子缓冲层相较于所述第二子缓冲层邻近所述隔离层12，所述第一子缓冲层为氮化硅(SiNx)材料，所述第二子缓冲层为氧化硅(SiOx)材料。所述第一子缓冲层及所述第二子缓冲层的设置能够更好地缓冲所述阵列基板1在制备过程中对所述基板11的损伤。且，所述第一子缓冲层 采用氮化硅材料，在制备氮化硅材料的时候能够产生氢(H)元素用于修补所述低温多晶硅层14，提高所述低温多晶硅层14的电性能。所述第二子缓冲层采用氧化硅材料，用于改善所述第二子缓冲层的应力，防止所述第二子缓冲层脱落。
进一步地，所述有机材料为聚酰亚胺(Polyimide，PI)。当然，所述基板11也可采用其他有机材料(由碳、氢、氧、氮等元素组成的材料统称为有机材料)。优选柔性材料，使得所述基板11为柔性基板。
请一并参阅图1至图3，本发明实施例还提供一种显示器100，包括有机发光二极管2和如上述任一实施例所述的阵列基板1，也即所述显示器100为有机发光二极管显示器。所述有机发光二极管2形成在所述缓冲层13背离所述隔离层12的一侧。具体而言，所述有机发光二极管2形成在所述多个薄膜晶体管10背离所述缓冲层13的一侧。特别的，当所述阵列基板1的所述基板11采用柔性材料时，所述显示器100为柔性显示器。
在本实施例中，由于所述显示器100采用的所述阵列基板1包括隔离层12，所述隔离层12设置在所述基板11与所述缓冲层13之间，所述隔离层12采用金属材质，故而在所述缓冲层13通过高温等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)的过程中，所述隔离层12可防止等离子体直接轰击所述基板11产生的有机物污染设备腔体和管道。同时，所述隔离层12也能够降低外部对所述基板11的热传导，起到保护所述基板11的作用。再者，由于所述隔离层12具有一定的导电性，因此也能起到静电屏蔽作用，提高了所述显示器100的抗静电干扰能力。
优选的，所述隔离层12采用钛材料、铝材料、铜材料或镍材料。
进一步地，请一并参阅图1至图3，作为一种可选实施例，所述有机发光二极管2包括阳极21、发光层24以及阴极27，所述发光层24位于所述阳极21与所述阴极27之间。所述阳极21采用透明电极，所述阴极27采用透明电极或半透明电极。由于所述隔离层12采用金属材质，例如钛，对光的穿透率低，因此所述隔离层12可作为所述有机发光二极管2的反射层。
在本实施例中，当所述阴极27采用透明电极时，所述隔离层12反射所述发光层24发出的光线，所述有机发光二极管2实现顶发射。由于所述阳极21 以及所述阴极27均采用透明电极，可采用相同材质，因此降低了所述有机发光二极管2的生产成本，也即降低了所述显示器100的成本。
当所述阴极27采用半透明电极时，所述隔离层12与半透明的所述阴极27形成共振微腔，增加了微腔的总光程，避免微腔调整对所述有机发光二极管2的有机膜层(例如所述发光层24)过度依赖，进而提高所述有机发光二极管2的可调节性能，使得所述有机发光二极管2具有更高的发光效率，使得所述显示器100具有更佳的显示效果、能耗低。
进一步地，所述透明电极可采用氧化铟锡(indium tin oxide，ITO)材质，以降低所述有机发光二极管2的成本，也即降低所述显示器100的制作成本。同时，当所述阳极21采用氧化铟锡材质时，可提高空穴注入能力、降低空穴注入能垒。应当理解的是，在其他实施例中，所述阳极21也可以选用其他透明的具有高功函数的导电材料。
进一步地，所述阴极27可采用采用镁银(Mg/Ag)合金制作半透明电极。其中，镁与银的比例为1：9。应当理解的是，在其他实施例中，所述阴极27也可以选用其他半透明的具有低功函数的导电材料。
进一步地，作为一种可选实施例，请参阅图3，所述有机发光二极管2还包括空穴注入层(Hole Inject Layer，HIL)22、空穴传输层(Hole Transport Layer，HTL)23、电子传输层(Electron Transport Layer，ETL)25以及电子注入层(Electron Inject Layer，EIL)26，用以增加电子或空穴的传输及平衡，从而提高所述有机发光二极管2的发光效率。其中，所述空穴注入层22形成在所述阳极21朝向所述发光层24的一侧。所述空穴传输层23形成在所述空穴注入层22与所述发光层24之间。所述电子传输层25形成在所述发光层24背离所述空穴传输层23的一侧。所述电子注入层26形成在所述电子传输层25与所述阴极27之间。
请一并参阅图1至图3，在本实施例中，所述阳极21可通过所述第三孔110连接至所述源区192，用以实现所述有机发光二极管2与所述阵列基板1的电性连接。
请参阅图1，本发明实施例还提供一种阵列基板1的制备方法，用以制备上述实施例的所述阵列基板1。所述制备方法包括：
Step1：提供基板11，所述基板11采用有机材料；
Step2：在所述基板11上形成隔离层12，所述隔离层12采用金属材质；
Step3：在所述隔离层12背离所述基板11的一侧上形成缓冲层13；及
Step4：在所述缓冲层13背离所述隔离层12的一侧上形成多个薄膜晶体管10。
在本实施例中，由于所述基板11上设置有隔离层12，所述隔离层12采用金属材质，，故而当所述缓冲层13通过高温等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺形成在所述隔离层12背离所述基板11的一侧时，所述隔离层12可防止等离子体直接轰击所述基板11产生的有机物污染设备腔体和管道。同时，所述隔离层12也能够降低外部对所述基板11的热传导，起到保护所述基板11的作用。
进一步地，步骤Step2包括：在所述基板上沉积钛材料，以形成所述隔离层12。由于钛材料具有韧性好、耐腐蚀、熔点高、热导系数低、在极冷极热条件下应力小等特点，故而所述隔离层12能够更好地起到保护所述基板11的作用。特别的，由于钛材料的韧性好，故而所述隔离层12抗等离子体轰击能力强，在所述缓冲层13的形成过程中，所述隔离层12能够很好地保护所述基板11。同时，由于所述钛材料的导热系数低，在准分子镭射结晶过程中，所述隔离层12亦能够有效降低外部对所述基板11的热传导，起到保护所述基板11的作用。
进一步地，所述“在所述基板上沉积钛材料”包括：在所述基板上沉积钛材料的工艺温度小于等于250°，也即所述钛材料可采用低温沉积方式进行沉积，以形成所述隔离层12，所述隔离层12成形难度较低。
进一步地，所述“在所述基板上沉积钛材料”包括：通过磁控溅射在所述缓冲层13上沉积钛材料。所述磁控溅射是物理气相沉积(Physical Vapor Deposition，PVD)的一种。磁控溅射通过在靶阴极表面引入磁场，利用磁场对带电粒子的约束来提高等离子体密度以增加溅射率。在其他实施中，也可以采用其他物理气相沉积方式沉积所述钛材料。
进一步地，步骤Step2包括：在所述基板上沉积铝材料、铜材料或镍材料，以形成所述隔离层12。在准分子镭射结晶过程中，本实施例所述隔离层12能 够吸收大量热能，故而能够有效降低外部对所述基板11的热传导，起到保护所述基板11的作用。
进一步地，请参阅图1，步骤Step4包括：
Step41：在所述缓冲层13背离所述隔离层12的一侧上形成非晶硅层；
Step42：通过准分子镭射结晶(Eximer laser annealing，ELA)工艺，将所述非晶硅层转化为多晶硅层；
Step43：通过光刻工艺图案化所述多晶硅层；
Step44：经过P型掺杂(P-type doping)和沟道掺杂，使所述多晶硅层形成所述多个薄膜晶体管10的有源层(也即低温多晶硅层14)；
Step45：在所述有源层和所述缓冲层13上，依次形成栅极绝缘层15、栅极16、介质层17、源区192、漏区191以及平坦层18，以形成所述多个薄膜晶体管10。
本实施例中，在通过准分子镭射结晶过程中，所述隔离层12能够降低外部对所述基板11的热传导，起到保护所述基板11的作用。
可选的，在步骤Step42进行前，可先对所述非晶硅层进行去氢和准分子镭射结晶的预先清洗。
以上对本发明实施例进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (18)

  1. 一种阵列基板，其中，包括：
    基板，采用有机材料；
    隔离层，采用金属材质，所述隔离层形成在所述基板上；及
    缓冲层，所述缓冲层形成在所述隔离层背离所述基板的一侧。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括多个薄膜晶体管，所述多个薄膜晶体管形成在所述缓冲层背离所述隔离层的一侧，所述多个薄膜晶体管包括低温多晶硅层。
  3. 如权利要求1所述的阵列基板，其中，所述隔离层采用钛材料。
  4. 如权利要求2所述的阵列基板，其中，所述隔离层采用钛材料。
  5. 如权利要求1所述的阵列基板，其中，所述隔离层采用铝材料、铜材料或镍材料。
  6. 如权利要求2所述的阵列基板，其中，所述隔离层采用铝材料、铜材料或镍材料。
  7. 一种显示器，其中，包括有机发光二极管和如权利要求1所述的阵列基板，所述有机发光二极管形成在所述缓冲层背离所述隔离层的一侧。
  8. 如权利要求7所述的显示器，其中，所述阵列基板还包括多个薄膜晶体管，所述多个薄膜晶体管形成在所述缓冲层背离所述隔离层的一侧，所述多个薄膜晶体管包括低温多晶硅层。
  9. 如权利要求7所述的显示器，其中，所述隔离层采用钛材料。
  10. 如权利要求8所述的显示器，其中，所述隔离层采用钛材料。
  11. 如权利要求7所述的显示器，其中，所述隔离层采用铝材料、铜材料或镍材料。
  12. 如权利要求8所述的显示器，其中，所述隔离层采用铝材料、铜材料或镍材料。
  13. 一种阵列基板的制备方法，其中，包括：
    提供基板，所述基板采用有机材料；
    在所述基板上形成隔离层，所述隔离层采用金属材质；
    在所述隔离层背离所述基板的一侧上形成缓冲层；及
    在所述缓冲层背离所述隔离层的一侧上形成多个薄膜晶体管。
  14. 如权利要求13所述的阵列基板的制备方法，其中，所述“在所述基板上形成隔离层”包括：
    在所述基板上沉积钛材料，以形成所述隔离层。
  15. 如权利要求14所述的阵列基板的制备方法，其中，所述“在所述基板上沉积钛材料”包括：
    在所述基板上沉积钛材料的工艺温度小于等于250°。
  16. 如权利要求14所述的阵列基板的制备方法，其中，所述“在所述基板上沉积钛材料”包括：
    通过磁控溅射在所述基板上沉积钛材料。
  17. 如权利要求15所述的阵列基板的制备方法，其中，所述“在所述基板上沉积钛材料”包括：
    通过磁控溅射在所述基板上沉积钛材料。
  18. 如权利要求13所述的阵列基板的制备方法，其中，所述“在所述基板上形成隔离层”包括：
    在所述基板上沉积铝材料、铜材料或镍材料，以形成所述隔离层。
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