WO2017201786A1 - 直流电压转换电路及液晶显示装置 - Google Patents

直流电压转换电路及液晶显示装置 Download PDF

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Publication number
WO2017201786A1
WO2017201786A1 PCT/CN2016/086785 CN2016086785W WO2017201786A1 WO 2017201786 A1 WO2017201786 A1 WO 2017201786A1 CN 2016086785 W CN2016086785 W CN 2016086785W WO 2017201786 A1 WO2017201786 A1 WO 2017201786A1
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Prior art keywords
voltage
circuit
thin film
film transistor
adjustment
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PCT/CN2016/086785
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English (en)
French (fr)
Inventor
曹丹
Original Assignee
深圳市华星光电技术有限公司
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Priority to US15/128,987 priority Critical patent/US9960590B1/en
Publication of WO2017201786A1 publication Critical patent/WO2017201786A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/44—Testing lamps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to the field of display, and in particular, to a DC voltage conversion circuit and a liquid crystal display device.
  • a liquid crystal display device generally includes a circuit board, a backlight module, and a liquid crystal display panel.
  • the circuit board is used to drive the backlight module and the liquid crystal display panel.
  • the backlight module is used to provide light to the liquid crystal display panel, and the liquid crystal display panel is used to display information such as text and images.
  • Circuit boards typically include a DC voltage conversion circuit.
  • the DC voltage conversion circuit generally converts the first voltage into a second voltage and outputs the second voltage to a VGH line of a WOA (Wire On Array) in the liquid crystal display device.
  • EOS Electrical Over Stress
  • the present invention provides a DC voltage conversion circuit, the DC voltage conversion circuit is applied to a liquid crystal display device, the DC voltage conversion circuit includes a voltage doubler circuit and a protection circuit, and the voltage doubler circuit includes a voltage doubler input terminal and a voltage doubler An output terminal, the voltage doubler input terminal is configured to receive a first voltage, the voltage doubler circuit is configured to convert the first voltage into a second voltage, and the second voltage is outputted through the voltage doubler output terminal
  • the protection circuit includes a detection circuit, a first feedback circuit, a first adjustment circuit, a second adjustment circuit, and a second feedback circuit, wherein an input end of the first feedback circuit is electrically connected to the voltage doubler output, the first An output end of the feedback circuit is electrically connected to the VGH line in the liquid crystal display device, and one end of the second feedback circuit is electrically connected to the voltage doubler output end, and the other end is grounded.
  • the detecting circuit detects the voltage of the VGH line, and obtains a first detecting voltage according to the voltage of the VGH line, where the first detecting voltage passes through the Outputting an output of the detection circuit, the first adjustment circuit compares the first detection voltage with a reference voltage, and generates a first signal according to a comparison result between the first detection voltage and the reference voltage The first signal is used to adjust an equivalent resistance of the first feedback circuit to be a first equivalent resistance, and the second adjustment circuit generates a second signal according to the first detection voltage, where the second signal is used for Adjusting an equivalent resistance of the second feedback circuit to a second equivalent resistance,
  • the voltage doubler circuit When the voltage doubler circuit performs an EOS test, the voltage doubler output terminal loads a test signal, and the detecting circuit detects a voltage of the VGH line, and obtains a second detection voltage according to the voltage of the VGH line.
  • the second detection voltage is outputted through an output end of the detection circuit, and the first adjustment circuit compares the second detection voltage with the reference voltage, and according to the second detection voltage
  • the comparison result of the reference voltage generates a third signal
  • the third signal is used to adjust an equivalent resistance of the first feedback circuit to a third equivalent resistance
  • the second adjustment circuit is configured according to the second detection
  • the voltage generates a fourth signal, the fourth signal is used to adjust an equivalent resistance of the second feedback circuit to a fourth equivalent resistance, when an equivalent resistance of the first feedback branch is adjusted to the third
  • the equivalent resistance and the equivalent resistance of the second feedback branch are adjusted to the fourth equivalent resistance, the voltage of the VGH line becomes the first detection voltage.
  • the first feedback circuit includes a first feedback branch, a second feedback branch, and a third feedback branch
  • the first adjustment circuit includes a first adjustment branch, a second adjustment branch, and a third Adjusting a branch
  • the first adjusting branch is configured to compare a voltage outputted from an output end of the detecting circuit with a first reference voltage, and output a voltage according to an output end of the detecting circuit and the first
  • the comparison result of the reference voltage generates a first adjustment signal for adjusting the resistance of the first feedback branch
  • the second adjustment branch is for outputting from the output of the detection circuit Comparing the voltage with the second reference voltage, and generating a second adjustment signal according to a comparison result between the voltage outputted by the output end of the detecting circuit and the second reference voltage, wherein the second adjustment signal is used to adjust the a resistor of the second feedback branch
  • the third adjustment branch is configured to compare a voltage outputted from an output end of the detecting circuit with a third reference voltage, and output according to an output end of the detecting circuit Voltage and
  • the first feedback branch includes a first thin film transistor and a first resistor, and a source of the first thin film transistor is electrically connected to the voltage doubler output terminal, and a gate of the first thin film transistor is used for receiving a first adjustment signal, a drain of the first thin film transistor is electrically connected to the first resistor to the VGH line, and the first adjustment signal is used to adjust an on or off of the first thin film transistor;
  • the second feedback branch includes a second thin film transistor and a second resistor, a source of the second thin film transistor is electrically connected to the voltage doubler output terminal, and a gate of the second thin film transistor is configured to receive the first And adjusting the signal, the drain of the second thin film transistor is electrically connected to the second resistor to the VGH line, and the second adjustment signal is used for adjusting on or off of the second thin film transistor.
  • the third feedback branch includes a third thin film transistor and a third resistor, a source of the third thin film transistor is electrically connected to the voltage doubler output terminal, and a gate of the second thin film transistor is configured to receive the first And adjusting the signal, the drain of the third thin film transistor electrically connecting the third resistor to the VGH line, and the third adjusting signal is used for adjusting on or off of the third thin film transistor.
  • the first adjustment branch includes a first comparator, and the non-inverting input end of the first comparator is electrically connected to an output end of the detecting circuit to receive a voltage outputted by an output end of the detecting circuit.
  • the inverting input terminal of the first comparator loads the first reference voltage, and when the voltage received by the non-inverting input terminal of the first comparator is greater than or equal to the first reference voltage, the first adjustment branch
  • the first thin film transistor is turned off, and when the voltage received by the receiving end of the first adjusting branch is less than the first reference voltage, the first adjusting branch controls the first thin film transistor to be turned on. ;
  • the second adjustment branch includes a second comparator, and the non-inverting input end of the second comparator is electrically connected to the output end of the detecting circuit to receive a voltage outputted by the output end of the detecting circuit,
  • the inverting input terminal of the second comparator loads the second reference voltage, and when the voltage received by the non-inverting input terminal of the second comparator is greater than or equal to the second reference voltage, the second adjustment branch control
  • the second thin film transistor is turned off, and when the voltage received by the receiving end of the second adjusting branch is less than the second reference voltage, the second adjusting branch controls the second thin film transistor to be turned on;
  • the third adjustment branch includes a third comparator, and the non-inverting input end of the third comparator is electrically connected to the output end of the detecting circuit to receive a voltage outputted by the output end of the detecting circuit,
  • the inverting input terminal of the third comparator loads the third reference voltage, and when the voltage received by the non-inverting input terminal of the third comparator is greater than or equal to the third reference voltage, the third adjusting branch controls the Third film
  • the transistor is turned off, and when the voltage received by the receiving end of the third adjusting branch is less than the third reference voltage, the third adjusting branch controls the third thin film transistor to be turned on.
  • the detecting circuit includes a fourth resistor, a fifth resistor, and a photocoupler
  • the photocoupler includes a first coupling input terminal, a second coupling input terminal, a first coupling output terminal, and a second coupling output terminal.
  • One end of the fourth resistor is electrically connected to the VGH line as an input end of the detecting circuit, and the other end of the fourth resistor is electrically connected to the first coupling output end, and the first coupling input end is electrically connected
  • the VGH line, the second coupling input terminal is electrically connected to the voltage doubler circuit, and the second coupling output terminal is electrically connected to the fifth resistor to ground, the second coupling output end and the fifth resistor The node between them serves as the output of the detection circuit.
  • the second feedback circuit includes a fourth feedback branch, a fifth feedback branch, and a sixth feedback branch connected in parallel, and the second adjustment circuit is configured to obtain a voltage according to an output of the detection circuit.
  • a fourth adjustment signal, a fifth adjustment signal, and a sixth adjustment signal wherein the fourth adjustment signal is used to adjust a resistance of the fourth feedback branch, and the fifth adjustment signal is used to adjust the fifth feedback branch
  • the sixth adjustment signal is used to adjust the resistance of the sixth feedback branch, and the fourth adjustment signal, the fifth adjustment signal, and the sixth adjustment signal cooperate to adjust the second feedback The resistance of the circuit.
  • the second adjustment circuit includes a multiplier and a controller
  • the multiplier includes a first multiplication input terminal, a second multiplication input terminal, and a multiplication output terminal
  • the first multiplication input terminal is electrically connected to the detection circuit
  • the output end receives the voltage outputted by the output of the detecting circuit
  • the second multiplication input terminal loads a preset coefficient
  • the multiplier is used to multiply the voltage outputted by the output end of the detecting circuit by Determining a coefficient to obtain a control signal, and outputting the control signal
  • the controller includes a control signal receiving end, a first output end, a second output end, and a third output end, wherein the control signal receiving end is used Receiving the control signal, the controller generates the fourth adjustment signal, the fifth adjustment signal, and the sixth adjustment signal according to the control signal, wherein the fourth adjustment signal is sent by the first The output terminal outputs, the fifth adjustment signal is output via the second output terminal, and the sixth adjustment signal is output via the third output terminal.
  • the fourth feedback branch includes a fourth thin film transistor and a sixth resistor
  • the fifth feedback branch includes a fifth thin film transistor and a seventh resistor
  • the sixth feedback branch includes a sixth thin film transistor and a
  • the eighth feedback circuit further includes a seventh feedback branch
  • the seventh feedback branch includes a ninth resistor and a tenth resistor, and one end of the ninth resistor is electrically connected to the voltage doubler output terminal Ninth The other end of the resistor electrically connects the tenth resistor to the ground;
  • a gate of the fourth thin film transistor is configured to receive the fourth adjustment signal, the fourth adjustment signal is used to control on or off of the fourth thin film transistor, and a drain of the fourth thin film transistor passes
  • the sixth resistor is electrically connected to a node between the ninth resistor and the tenth resistor, and a source of the fourth thin film transistor is grounded;
  • a gate of the fifth thin film transistor is configured to receive the fifth adjustment signal, the fifth adjustment signal is used to control on or off of the fifth thin film transistor, and a drain of the fifth thin film transistor passes
  • the seventh resistor is electrically connected to a node between the ninth resistor and the tenth resistor, and a source of the fifth thin film transistor is grounded;
  • a gate of the sixth thin film transistor is configured to receive the sixth adjustment signal, the sixth adjustment signal is used to control on or off of the sixth thin film transistor, and a drain of the sixth thin film transistor passes
  • the eighth resistor is electrically connected to a node between the ninth resistor and the tenth resistor, and a source of the sixth thin film transistor is grounded.
  • the voltage doubler circuit further includes a capacitor, and one end of the capacitor is electrically connected to the voltage doubler output end, and the other end is grounded.
  • the DC voltage conversion circuit of the present invention loads the test signal at the voltage doubler output when the voltage doubler circuit performs the EOS test, and the detection circuit obtains the second detection voltage according to the voltage of the VGH line.
  • An adjusting circuit generates a third signal according to a comparison result between the second detecting voltage and the reference voltage, and the second adjusting circuit generates a fourth signal according to a comparison result of the second detecting voltage and the reference voltage.
  • the third signal adjusts the equivalent resistance of the first feedback branch to be a third equivalent resistance
  • the fourth adjustment signal adjusts the equivalent resistance of the second feedback branch to a fourth resistance, thereby passing the first feedback branch and the second
  • the adjustment of the equivalent resistance of the feedback branch causes the voltage of the VGH line to return to the voltage at which the test signal is not loaded. Therefore, it is possible to avoid damage to the components in the VGH line or the DC voltage conversion circuit or other components of the liquid crystal display device red when the voltage doubling circuit performs the EOS test.
  • the present invention also provides a liquid crystal display device comprising the DC voltage conversion circuit of any of the foregoing embodiments.
  • FIG. 1 is a circuit block diagram of a DC voltage conversion circuit according to a preferred embodiment of the present invention.
  • FIG. 2 is a circuit configuration diagram of a DC voltage conversion circuit according to a preferred embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a liquid crystal display device according to a preferred embodiment of the present invention.
  • FIG. 1 is a circuit block diagram of a DC voltage conversion circuit according to a preferred embodiment of the present invention
  • FIG. 2 is a circuit configuration diagram of a DC voltage conversion circuit according to a preferred embodiment of the present invention.
  • the DC voltage conversion circuit 10 includes a voltage doubling circuit 100 and a protection circuit 300.
  • the voltage doubler circuit 100 includes a voltage doubler output terminal 110 and a voltage doubler output terminal 120.
  • the voltage doubler input terminal 110 is configured to receive a first voltage
  • the voltage doubler circuit 100 is configured to convert the first voltage into a second voltage
  • the second voltage is outputted through the voltage doubler output terminal 120.
  • the protection circuit 300 includes a detection circuit 310, a first feedback circuit 320, a first adjustment circuit 330, a second adjustment circuit 340, and a second feedback circuit 350.
  • An input end of the first feedback circuit 320 is electrically connected to the voltage doubler output terminal 120, and an output end of the first feedback circuit 320 is electrically connected to a VGH line in the liquid crystal display device.
  • One end of the second feedback circuit 350 is electrically connected to the voltage doubler output terminal 120, and the other end is grounded.
  • the detecting circuit 310 detects the voltage of the VGH line, and obtains a first detecting voltage according to the voltage of the VGH line, the first detecting voltage. Outputted through the output of the detection circuit 310.
  • the first adjustment circuit 330 compares the first detection voltage with a reference voltage, and generates a first signal according to a comparison result between the first detection voltage and the reference voltage, where the first signal is used for
  • the equivalent resistance of the first feedback circuit 320 is adjusted to be a first equivalent resistance.
  • the second adjustment circuit 340 generates a second signal according to the first detection voltage, and the second signal is used to adjust an equivalent resistance of the second feedback circuit to a second equivalent resistance.
  • the voltage doubler circuit When the voltage doubler circuit performs the EOS test, the voltage doubler output terminal 120 loads a test signal, and the detecting circuit 310 detects the voltage of the VGH line, and obtains the second detection according to the voltage of the VGH line.
  • the second detection voltage is output via the output of the detection circuit 310.
  • the first adjustment circuit 330 compares the second detection voltage with the reference voltage, and generates a third signal according to a comparison result between the second detection voltage and the reference voltage, the third signal
  • the equivalent resistance of the first feedback circuit 320 is adjusted to be a third equivalent resistance.
  • the second adjustment circuit 340 generates a fourth signal according to the second detection voltage, and the fourth signal is used to adjust an equivalent resistance of the second feedback circuit 350 to a fourth equivalent resistance.
  • EOS test usually refers to the test of the performance of the device to be tested when the voltage to be tested is higher than the rated operating voltage of the device to be tested, or when the current to be tested exceeds the rated operating current of the device to be tested.
  • the first feedback circuit 320 includes a first feedback branch 321 , a second feedback branch 322 , and a third feedback branch 323 connected in parallel.
  • the first adjustment circuit 310 includes a first adjustment branch 331 , a second adjustment branch 332 , and a third adjustment branch 333 .
  • the first adjustment branch 331 is configured to compare the voltage outputted from the output end of the detecting circuit 310 with the first reference voltage, and output the voltage according to the output end of the detecting circuit 310 and the first A comparison result of a reference voltage produces a first adjustment signal for adjusting the resistance of the first feedback branch 321 .
  • the second adjustment branch 332 is configured to compare the voltage outputted from the output end of the detecting circuit 310 with the second reference voltage, and output the voltage according to the output end of the detecting circuit 310 and the first The comparison result of the two reference voltages produces a second adjustment signal for adjusting the resistance of the second feedback branch 322.
  • the third adjustment branch 333 is configured to compare the voltage outputted from the output end of the detecting circuit 310 with a third reference voltage, and output the voltage according to the output end of the detecting circuit 310 and the first The comparison result of the three reference voltages generates a third adjustment signal, where the third adjustment signal is used to adjust the resistance of the third feedback branch 323, wherein the first reference voltage is smaller than the second reference voltage, and The second reference voltage is less than the third reference voltage.
  • the first feedback branch 321 includes a first thin film transistor Q1 and a first resistor R1.
  • the source of the first thin film transistor Q1 is electrically connected to the voltage doubler output terminal 120, and the first thin film transistor Q1 a gate for receiving the first adjustment signal, a drain of the first thin film transistor Q1 is electrically connected to the first resistor R1 to the VGH line, and the first adjustment signal is used to adjust the first
  • the thin film transistor Q1 is turned on or off.
  • the second feedback branch 322 includes a second thin film transistor Q2 and a second resistor R2.
  • the third feedback branch 323 includes a third thin film transistor Q3 and a third resistor R3.
  • a source of the third thin film transistor Q3 is electrically connected to the voltage doubler output terminal 120, and a gate of the second thin film transistor Q3 is configured to receive the third adjustment signal, and a drain of the third thin film transistor Q3
  • the third resistor R3 is electrically connected to the VGH line, and the third adjustment signal is used to adjust the on or off of the third thin film transistor Q3.
  • the first thin film transistor Q1, the second thin film transistor Q2, and the third thin film transistor Q3 are all P-type thin film transistors (P-Metal Oxide Semiconductors, PMOS).
  • the first adjustment signal is a low level signal
  • the first thin film transistor Q1 is turned on, and when the first adjustment signal is a high level signal, the first thin film transistor Q1 is turned off.
  • the second adjustment signal is a low level signal
  • the second thin film transistor Q2 is turned on, and when the second adjustment signal is a high level signal, the second thin film transistor Q2 is turned off.
  • the third adjustment signal is a low level signal
  • the third thin film transistor Q3 is turned on, and when the third adjustment signal is a high level signal, the third thin film transistor Q3 is turned off.
  • the first adjustment branch 331 includes a first comparator OP1.
  • the non-inverting input end of the first comparator OP1 is electrically connected to the output end of the detecting circuit 310 to receive the voltage outputted by the output end of the detecting circuit 310, and the inverting input end of the first comparator OP1 is loaded.
  • the first reference voltage The first adjustment branch 331 controls the first thin film transistor Q1 to be turned off when the voltage received by the non-inverting input terminal of the first comparator OP1 is greater than or equal to the first reference voltage, when the first When the voltage received by the receiving end of the adjusting branch 331 is smaller than the first reference voltage, the first adjusting branch 331 controls the first thin film transistor Q1 to be turned on.
  • the second adjustment branch 332 includes a second comparator OP2.
  • the non-inverting input end of the second comparator OP2 is electrically connected to the output end of the detecting circuit 310 to receive the voltage outputted by the output end of the detecting circuit 310, and the inverting input end of the second comparator OP2 is loaded.
  • the second reference voltage when When the voltage received by the non-inverting input terminal of the second comparator OP2 is greater than or equal to the second reference voltage, the second adjusting branch 332 controls the second thin film transistor Q2 to be turned off when the second adjustment When the voltage received by the receiving end of the branch 332 is less than the second reference voltage, the second adjusting branch 332 controls the second thin film transistor Q2 to be turned on.
  • the third adjustment branch 333 includes a third comparator OP3.
  • the non-inverting input end of the third comparator OP3 is electrically connected to the output end of the detecting circuit 310 to receive the voltage outputted by the output end of the detecting circuit 310, and the inverting input end of the third comparator OP2 is loaded.
  • the third reference voltage When the voltage received by the non-inverting input terminal of the third comparator OP3 is greater than or equal to the third reference voltage, the third adjusting branch 333 controls the third thin film transistor Q3 to be turned off, when the third adjusting branch When the voltage received by the receiving end of the path 333 is less than the third reference voltage, the third adjusting branch 333 controls the third thin film transistor Q3 to be turned on.
  • the detecting circuit 310 includes a fourth resistor R4, a fifth resistor R5, and a photocoupler 311.
  • the photocoupler 311 includes a first coupling input terminal 311a, a second coupling input terminal 311b, a first coupling output terminal 311c, and a second coupling output terminal 311d.
  • One end of the fourth resistor R4 is electrically connected to the VGH line as an input end of the detecting circuit 310, and the other end of the fourth resistor R4 is electrically connected to the first coupling output end 311c, the first coupling The input terminal 311a is electrically connected to the VGH line, the second coupling input terminal 311b is electrically connected to the voltage doubler circuit 100, and the second coupling output terminal 311d is electrically connected to the fifth resistor R5 to the ground, the second A node A between the coupled output terminal 311d and the fifth resistor R5 serves as an output terminal of the detecting circuit 310.
  • the photocoupler 311 receives the electrical signals of the first coupling input terminal 311a and the second coupling input terminal 311b, and receives the signals received by the first coupling input terminal 311a and the second coupling input terminal 311b.
  • the signal is converted into an optical signal, and the optical signal is converted into an electrical signal and outputted through the first coupled output terminal 311c and the second coupled output terminal 311d.
  • the signals output from the first coupled output terminal 311c and the second coupled output terminal 311d are N times the signals input from the first coupling input terminal 311a and the second coupling input terminal 311b (where N Is a positive number).
  • the optocoupler 311 is configured to prevent an electronic component pair connected to the first coupling input end 311a and the second coupling input end 311b from the first coupling output end 311c and the second coupling output end 311d
  • the mutual interference of the connected electronic components improves the protection accuracy of the overcurrent protection of the entire protection circuit 300 when performing the EOS test.
  • the second feedback circuit 350 includes a fourth feedback branch 351, a fifth feedback branch 352, and a sixth feedback branch 353 connected in parallel.
  • the second adjustment circuit 340 is configured to obtain a fourth adjustment signal, a fifth adjustment signal, and a sixth adjustment signal according to the voltage outputted by the output end of the detection circuit 310.
  • the fourth adjustment signal is used to adjust the resistance of the fourth feedback branch 351
  • the fifth adjustment signal is used to adjust the resistance of the fifth feedback branch 352
  • the sixth adjustment signal is used to adjust the The resistance of the sixth feedback branch 353 is described.
  • the fourth adjustment signal, the fifth adjustment signal, and the sixth adjustment signal cooperate to adjust a resistance of the second feedback circuit 350.
  • the second adjustment circuit 340 includes a multiplier 341 and a controller 342.
  • the multiplier 341 includes a first multiplication input terminal 341a, a second multiplication input terminal 341b, and a multiplication output terminal 341c.
  • the first multiplication input terminal 341a is electrically connected to the output end of the detection circuit 310 to receive the voltage outputted by the output end of the detection circuit 310.
  • the second multiplication input terminal 341b loads a preset coefficient, and the multiplier 341 is configured to multiply the voltage outputted by the output end of the detection circuit 310 by the preset coefficient to obtain a control signal, and the A control signal is output via the multiplying output terminal 341c.
  • the controller 342 includes a control signal receiving end 342a, a first output end 342b, a second output end 342c, and a third output end 342d.
  • the control signal receiving end 342a is configured to receive the control signal, and the controller 342 generates the fourth adjustment signal, the fifth adjustment signal, and the sixth adjustment signal according to the control signal.
  • the fourth adjustment signal is output via the first output terminal 342b
  • the fifth adjustment signal is output via the second output terminal 342c
  • the sixth adjustment signal is output via the third output terminal 342d.
  • the fourth feedback branch 351 includes a fourth thin film transistor Q4 and a sixth resistor R6.
  • the fifth feedback branch 352 includes a fifth thin film transistor Q5 and a seventh resistor R7.
  • the sixth feedback branch 353 includes a sixth thin film transistor Q6 and an eighth resistor R8.
  • the second feedback circuit 350 also includes a seventh feedback branch 354.
  • the seventh feedback branch 354 includes a ninth resistor R9 and a tenth resistor R10. One end of the ninth resistor R9 is electrically connected to the voltage doubler output terminal 120, and the other end of the ninth resistor R9 is electrically connected to the tenth resistor R10 to ground.
  • a gate of the fourth thin film transistor Q4 is configured to receive the fourth adjustment signal, and the fourth adjustment signal is used to control on or off of the fourth thin film transistor Q4, where the fourth thin film transistor Q4 is The drain is electrically connected to the node FB between the ninth resistor R9 and the tenth resistor R10 through the sixth resistor R6, and the source of the fourth thin film transistor Q4 is grounded.
  • a gate of the fifth thin film transistor Q5 for receiving the fifth adjustment signal, the fifth adjustment signal for controlling on or off of the fifth thin film transistor Q5, the fifth thin film transistor Q5
  • the drain is electrically connected to a node between the ninth resistor R9 and the tenth resistor R10 through the seventh resistor R7, and a source of the fifth thin film transistor Q5 is grounded.
  • a gate of the sixth thin film transistor Q6 for receiving the sixth adjustment signal, the sixth adjustment signal for controlling conduction or deactivation between the sixth thin film transistors Q6, the sixth thin film transistor
  • the drain of Q6 is electrically connected to a node between the ninth resistor R9 and the tenth resistor R10 through the eighth resistor R8, and the source of the sixth thin film transistor Q6 is grounded.
  • the fourth thin film transistor Q4, the fifth thin film transistor Q5, and the sixth thin film transistor Q6 are all N-type thin film transistors (N-Metal Oxide Semiconductors, NMOS).
  • the fourth adjustment signal is a high level signal
  • the fourth thin film transistor Q4 is turned on
  • the fourth adjustment signal is a low level signal
  • the fourth thin film transistor Q4 is turned off.
  • the fifth adjustment signal is a high level signal
  • the fifth thin film transistor Q5 is turned on.
  • the fifth thin film transistor Q5 is turned off.
  • the sixth adjustment signal is a high level signal
  • the sixth thin film transistor Q6 is turned on.
  • the sixth adjustment signal is a low level signal
  • the sixth thin film transistor Q6 is turned off.
  • the voltage doubler circuit 100 further includes a capacitor C123.
  • One end of the capacitor C123 is electrically connected to the voltage doubler output terminal 120, and the other end is grounded.
  • the capacitor C123 is configured to filter the second voltage output by the voltage doubler output terminal 120 such that the waveform of the second voltage outputted through the voltage doubler output terminal 120 is smoother.
  • the VGH pin flowing through the power management IC (PMIC) of the voltage multiplying circuit 100 and the current flowing through the VGH line are small.
  • the voltage flowing through the node A between the second coupled output terminal 311d and the fifth resistor R5 is represented by VA
  • the first reference voltage is represented by Vref1
  • the second reference voltage is represented by Vref2
  • the third reference voltage is represented by Vref3.
  • the first comparator OP1 generates a low level signal according to the result of the comparison of the VA with the first reference voltage Vref1
  • the second comparator OP2 is based on the VA and
  • the result of the comparison of the second reference voltage Vref2 produces a low level signal
  • the third comparator generates a low level signal based on the result of the comparison of VA with the third reference voltage.
  • the first thin film transistor Q1, the second thin film transistor Q2, and the third thin film transistor Q3 are both turned on.
  • the equivalent resistance of the first feedback circuit 320 that is, the first equivalent resistance Req1 is equal to the parallel connection of R1, R2, and R3 (represented by the symbol "//" in parallel, then R1, R2, and R3 are represented in parallel as R1. / / R2 / / R3) after the resistance.
  • the current of the first feedback circuit 320 is defined as I1.
  • the voltage drop of the first feedback circuit 320 is equal to I1*Req1.
  • the voltage of the node FB between the ninth resistor R9 and the tenth resistor R10 is represented by VFB.
  • the voltage of the voltage doubler output terminal 120 of the voltage multiplying circuit 100 is represented by VGHF, and the voltage of the VGH line is represented by V GH .
  • VGHF VFB*(1+R9/R10)
  • the current flowing into the power management chip VGH pin of the voltage multiplying circuit 100 increases with the path of the VGH line.
  • the first comparator OP1 generates a high level signal according to a comparison result of the VA and the first reference voltage Vref1
  • the second comparator OP2 generates a high level signal according to a comparison result of the VA and the second reference voltage Vref2
  • the third comparator OP3 generates a low level signal based on the comparison result of VA and Vref3.
  • the first thin film transistor Q1 is turned off, the second thin film transistor Q2 is turned off, and the third thin film transistor Q3 is turned on.
  • the equivalent resistance of the first feedback circuit 320 that is, the third equivalent resistance Req3 is equal to R3.
  • the voltage drop of the first feedback circuit 320 is equal to I1*R3.
  • the fourth adjustment signal outputted in the second adjustment circuit 340 is a high level signal, and the fifth resistance signal is high. a flat signal, the sixth adjustment signal being a low level signal.
  • VGHF VFB*[1+R9/(R10//R6//R7)]
  • I1*R3 VFB*(1+R9/R10)-I1*(R1//R2/ /R3). It can be seen that the voltage of the VGH line when performing the EOS test is equal to the voltage of the VGH line when the test is not performed.
  • the DC voltage conversion circuit 10 of the present invention loads the test signal at the voltage doubler output terminal 120 when the voltage doubler circuit 100 performs the EOS test, and the detection circuit 310 obtains the second detection according to the voltage of the VGH line.
  • the first adjustment circuit 330 generates a third signal according to the comparison result of the second detection voltage and the reference voltage
  • the second adjustment circuit 340 generates a fourth signal according to the comparison result of the second detection voltage and the reference voltage.
  • the third signal adjusts the equivalent resistance of the first feedback branch 320 to be a third equivalent resistance
  • the fourth adjustment signal adjusts the equivalent resistance of the second feedback branch 350 to a fourth resistance, thereby passing
  • the adjustment of the equivalent resistance of the first feedback branch 320 and the second feedback branch 350 causes the voltage of the VGH line to return to the voltage at which the test signal is not loaded. This makes it possible to avoid damage to the components in the VGH line or the DC voltage conversion circuit or other components of the liquid crystal display device red when the voltage doubling circuit 100 performs the EOS test.
  • FIG. 3 is a schematic structural diagram of a liquid crystal display device according to a preferred embodiment of the present invention.
  • the liquid crystal display device 1 includes the DC voltage conversion circuit described above, and details are not described herein again.
  • the liquid crystal display device 1 includes but is not limited to, but not limited to, a smart phone, a mobile Internet device (MID), an e-book, a tablet computer, and a portable play station (Play Station Portable).
  • Portable devices such as PSP) or Personal Digital Assistant (PDA).

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Abstract

一种直流电压转换电路（10）及液晶显示装置（1），该直流电压转换电路（10）包括倍压电路（100）及保护电路（300），在倍压电路（100）在进行EOS测试时，侦测电路（310）根据VGH线的电压得到第二侦测电压，第一调整电路（330）根据第二侦测电压与参考电压的比较结果产生第三信号，第二调整电路（340）根据第二侦测电压与参考电压的比较结果产生第四信号，第三信号调整第一反馈支路（320）的等效电阻为第三等效电阻，第四信号调整第二反馈支路（350）的等效电阻为第四电阻，从而通过对第一反馈支路（320）及第二反馈支路（350）的等效电阻的调整使得VGH线的电压恢复到未加载测试信号时的电压。

Description

直流电压转换电路及液晶显示装置
本发明要求2016年5月26日递交的发明名称为“直流电压转换电路及液晶显示装置”的申请号201610365302.8的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种直流电压转换电路及液晶显示装置。
背景技术
随着显示技术的发展，液晶显示装置由于具有体积小、功耗低等优点而得到广大用户的青睐。液晶显示装置通常包括电路板、背光模组及液晶显示面板。电路板用于驱动背光模组及液晶显示面板。背光模组用于为液晶显示面板提供光线，液晶显示面板用于显示文字、图像等信息。电路板中通常包括用于直流电压转换电路。所述直流电压转换电路通常将第一电压转换为第二电压，并将所述第二电压输出至液晶显示装置中WOA(Wire On Array，阵列外布线)的VGH线。在所述直流电压转换电路进行过度电性应力(Electrical Over Stress，EOS)测试时，常常会因为直流电压转换电路中没有保护措施进而将VGH线或者直流电压转换电路中的元件或者液晶显示装置中的其他元件烧毁。
发明内容
本发明提供一种直流电压转换电路，所述直流电压转换电路应用于液晶显示装置中，所述直流电压转换电路包括倍压电路及保护电路，所述倍压电路包括倍压输入端及倍压输出端，所述倍压输入端用于接收第一电压，所述倍压电路用于将所述第一电压转换为第二电压，所述第二电压经由所述倍压输出端输出，所述保护电路包括侦测电路、第一反馈电路、第一调整电路、第二调整电路及第二反馈电路，所述第一反馈电路的输入端电连接所述倍压输出端，所述第一反馈电路的输出端电连接所述液晶显示装置中的VGH线，所述第二反馈电路的一端电连接所述倍压输出端，另一端接地，
当所述倍压电路未进行EOS测试时，所述侦测电路侦测所述VGH线的电压，并根据所述VGH线的电压得到第一侦测电压，所述第一侦测电压经由所述侦测电路的输出端输出，所述第一调整电路将所述第一侦测电压与参考电压进行比较，并根据所述第一侦测电压与所述参考电压的比较结果产生第一信号，所述第一信号用于调整第一反馈电路的等效电阻为第一等效电阻，所述第二调整电路根据所述第一侦测电压产生第二信号，所述第二信号用于调整所述第二反馈电路的等效电阻为第二等效电阻，
当所述倍压电路进行EOS测试时，所述倍压输出端加载测试信号，所述侦测电路侦测所述VGH线的电压，并根据所述VGH线的电压得到第二侦测电压，所述第二侦测电压经由所述侦测电路的输出端输出，所述第一调整电路将所述第二侦测电压与所述参考电压进行比较，并根据所述第二侦测电压与所述参考电压的比较结果产生第三信号，所述第三信号用于调整所述第一反馈电路的等效电阻为第三等效电阻，所述第二调整电路根据所述第二侦测电压产生第四信号，所述第四信号用于调整所述第二反馈电路的等效电阻为第四等效电阻，当所述第一反馈支路的等效电阻被调整为所述第三等效电阻且所述第二反馈支路的等效电阻被调整为所述第四等效电阻时，所述VGH线的电压变为第一侦测电压。
其中，所述第一反馈电路包括并联的第一反馈支路、第二反馈支路及第三反馈支路，所述第一调整电路包括第一调整支路、第二调整支路及第三调整支路，所述第一调整支路用于将自所述侦测电路的输出端输出的电压与第一参考电压进行比较，并根据所述侦测电路的输出端输出的电压与第一参考电压的比较结果产生第一调整信号，所述第一调整信号用于调整所述第一反馈支路的电阻，所述第二调整支路用于将自所述侦测电路的输出端输出的电压与第二参考电压进行比较，并根据所述侦测电路的输出端输出的电压与所述第二参考电压的比较结果产生第二调整信号，所述第二调整信号用于调整所述第二反馈支路的电阻，所述第三调整支路用于将自所述侦测电路的输出端输出的电压与第三参考电压进行比较，并根据所述侦测电路的输出端输出的电压与所述第三参考电压的比较结果产生第三调整信号，所述第三调整信号用于调整所述第三反馈支路的电阻，其中，所述第一参考电压小于所述第二参考电压，且所述第二参 考电压小于所述第三参考电压。
其中，所述第一反馈支路包括第一薄膜晶体管及第一电阻，所述第一薄膜晶体管的源极电连接所述倍压输出端，所述第一薄膜晶体管的栅极用于接收所述第一调整信号，所述第一薄膜晶体管的漏极电连接所述第一电阻至所述VGH线，所述第一调整信号用于调整所述第一薄膜晶体管的导通或者截止；
所述第二反馈支路包括第二薄膜晶体管及第二电阻，所述第二薄膜晶体管的源极电连接所述倍压输出端，所述第二薄膜晶体管的栅极用于接收所述第二调整信号，所述第二薄膜晶体管的漏极电连接所述第二电阻至所述VGH线，所述第二调整信号用于调整所述第二薄膜晶体管的导通或者截止，
所述第三反馈支路包括第三薄膜晶体管与第三电阻，所述第三薄膜晶体管的源极电连接所述倍压输出端，所述第二薄膜晶体管的栅极用于接收所述第三调整信号，所述第三薄膜晶体管的漏极电连接所述第三电阻至所述VGH线，所述第三调整信号用于调整所述第三薄膜晶体管的导通或者截止。
其中，所述第一调整支路包括第一比较器，所述第一比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第一比较器的反相输入端加载所述第一参考电压，当所述第一比较器的同相输入端接收到的电压大于或等于所述第一参考电压时，所述第一调整支路控制所述第一薄膜晶体管截止，当所述第一调整支路的接收端接收到的电压小于所述第一参考电压时，所述第一调整支路控制所述第一薄膜晶体管导通；
所述第二调整支路包括第二比较器，所述第二比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第二比较器的反相输入端加载所述第二参考电压，当所述第二比较器的同相输入端接收到的电压大于或等于所述第二参考电压时，所述第二调整支路控制所述第二薄膜晶体管截止，当所述第二调整支路的接收端接收到的电压小于所述第二参考电压时，所述第二调整支路控制所述第二薄膜晶体管导通；
所述第三调整支路包括第三比较器，所述第三比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第三比较器的反相输入端加载所述第三参考电压，当第三比较器的同相输入端接收到的电压大于或等于所述第三参考电压时，所述第三调整支路控制所述第三薄膜 晶体管截止，当所述第三调整支路的接收端接收到的电压小于所述第三参考电压时，所述第三调整支路控制所述第三薄膜晶体管导通。
其中，所述侦测电路包括第四电阻、第五电阻及光电耦合器，所述光电耦合器包括第一耦合输入端、第二耦合输入端、第一耦合输出端及第二耦合输出端，所述第四电阻的一端作为所述侦测电路的输入端电连接所述VGH线，所述第四电阻的另一端电连接所述第一耦合输出端，所述第一耦合输入端电连接所述VGH线，所述第二耦合输入端电连接所述倍压电路，所述第二耦合输出端电连接所述第五电阻至地，所述第二耦合输出端及所述第五电阻之间的节点作为所述侦测电路的输出端。
其中，所述第二反馈电路包括并联的第四反馈支路、第五反馈支路及第六反馈支路，所述第二调整电路用于根据所述侦测电路的输出端输出的电压得到第四调整信号、第五调整信号及第六调整信号，所述第四调整信号用于调整所述第四反馈支路的电阻，所述第五调整信号用于调整所述第五反馈支路的电阻，所述第六调整信号用于调整所述第六反馈支路的电阻，所述第四调整信号、所述第五调整信号及所述第六调整信号配合以调整所述第二反馈电路的电阻。
其中，所述第二调整电路包括乘法器及控制器，所述乘法器包括第一乘法输入端、第二乘法输入端及乘法输出端，所述第一乘法输入端电连接所述侦测电路的输出端，以接收所述侦测电路的输出端输出的电压，所述第二乘法输入端加载预设系数，所述乘法器用于将所述侦测电路的输出端输出的电压乘以所述预设系数，以得到控制信号，并将所述控制信号输出，所述控制器包括控制信号接收端、第一输出端、第二输出端及第三输出端，所述控制信号接收端用于接收所述控制信号，所述控制器根据所述控制信号产生所述第四调整信号、所述第五调整信号及所述第六调整信号，其中所述第四调整信号经由所述第一输出端输出，所述第五调整信号经由所述第二输出端输出，所述第六调整信号经由所述第三输出端输出。
其中，所述第四反馈支路包括第四薄膜晶体管及第六电阻，所述第五反馈支路包括第五薄膜晶体管及第七电阻，所述第六反馈支路包括第六薄膜晶体管及第八电阻，所述第二反馈电路还包括第七反馈支路，所述第七反馈支路包括第九电阻及第十电阻，所述第九电阻的一端电连接所述倍压输出端，所述第九 电阻的另一端电连接所述第十电阻至地；
所述第四薄膜晶体管的栅极用于接收所述第四调整信号，所述第四调整信号用于控制所述第四薄膜晶体管的导通或者截止，所述第四薄膜晶体管的漏极通过所述第六电阻电连接所述第九电阻与所述第十电阻之间的节点，所述第四薄膜晶体管的源极接地；
所述第五薄膜晶体管的栅极用于接收所述第五调整信号，所述第五调整信号用于控制所述第五薄膜晶体管的导通或者截止，所述第五薄膜晶体管的漏极通过所述第七电阻电连接所述第九电阻与所述第十电阻之间的节点，所述第五薄膜晶体管的源极接地；
所述第六薄膜晶体管的栅极用于接收所述第六调整信号，所述第六调整信号用于控制所述第六薄膜晶体管的导通或者截止，所述第六薄膜晶体管的漏极通过所述第八电阻电连接至所述第九电阻与所述第十电阻之间的节点，所述第六薄膜晶体管的源极接地。
其中，所述倍压电路还包括电容，所述电容一端电连接所述倍压输出端，另一端接地。
相较于现有技术，本发明的直流电压转换电路在所述倍压电路在进行EOS测试时，倍压输出端加载测试信号，侦测电路根据VGH线的电压得到第二侦测电压，第一调整电路根据第二侦测电压与参考电压的比较结果产生第三信号，第二调整电路根据第二侦测电压与参考电压的比较结果产生第四信号。第三信号调整第一反馈支路的等效电阻为第三等效电阻，第四调整信号调整第二反馈支路的等效电阻为第四电阻，从而通过对第一反馈支路及第二反馈支路的等效电阻的调整使得所述VGH线的电压恢复到未加载测试信号时的电压。由此可以避免在倍压电路进行EOS测试时，加载测试信号对VGH线或者直流电压转换电路中的元件或者液晶显示装置红的其他元件造成的损坏。
本发明还提供了一种液晶显示装置，所述液晶显示装置包括前述任意实施方式所述的直流电压转换电路。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的直流电压转换电路的电路框图。
图2为本发明一较佳实施方式的直流电压转换电路的电路结构图。
图3为本发明一较佳实施方式的液晶显示装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1和图2，图1为本发明一较佳实施方式的直流电压转换电路的电路框图；图2为本发明一较佳实施方式的直流电压转换电路的电路结构图。所述直流电压转换电路10包括倍压电路100和保护电路300。所述倍压电路100包括倍压输出端110及倍压输出端120。所述倍压输入端110用于接收第一电压，所述倍压电路100用于将所述第一电压转换为第二电压，所述第二电压经由所述倍压输出端120输出。所述保护电路300包括侦测电路310、第一反馈电路320、第一调整电路330、第二调整电路340及第二反馈电路350。所述第一反馈电路320的输入端电连接所述倍压输出端120，所述第一反馈电路320的输出端电连接所述液晶显示装置中的VGH线。所述第二反馈电路350的一端电连接所述倍压输出端120，另一端接地。当所述倍压电路100未进行EOS测试时，所述侦测电路310侦测所述VGH线的电压，并根据所述VGH线的电压得到第一侦测电压，所述第一侦测电压经由所述侦测电路310的输出端输出。所述第一调整电路330将所述第一侦测电压与参考电压进行比较，并根据所述第一侦测电压与所述参考电压的比较结果产生第一信号，所述第一信号用于调整所述第一反馈电路320的等效电阻为第一等效电阻。所述第二调整电路340根据所述第一侦测电压产生第二信号，所述第二信号用于调整所述第二反馈电路的等效电阻为第二等效电阻。
当所述倍压电路进行EOS测试时，所述倍压输出端120加载测试信号，所述侦测电路310侦测所述VGH线的电压，并根据所述VGH线的电压得到第二侦测电压，所述第二侦测电压经由所述侦测电路310的输出端输出。所述第一调整电路330将所述第二侦测电压与所述参考电压进行比较，并根据所述第二侦测电压与所述参考电压的比较结果产生第三信号，所述第三信号用于调整所述第一反馈电路320的等效电阻为第三等效电阻。所述第二调整电路340根据所述第二侦测电压产生第四信号，所述第四信号用于调整所述第二反馈电路350的等效电阻为第四等效电阻。当所述第一反馈电路320的等效电阻被调整为所述第三等效电阻且所述等效电阻被调整为所述第四等效电阻时，所述VGH线的电压为第一侦测电压。
所谓EOS测试，通常是指对待测试的器件加载的电压超过待测试器件的额定工作电压，或者是对待测试的器件加载的电流超过待测试器件的额定工作电流时，对待测试器件性能的测试。
所述第一反馈电路320包括并联的第一反馈支路321、第二反馈支路322及第三反馈支路323。所述第一调整电路310包括第一调整支路331、第二调整支路332及第三调整支路333。所述第一调整支路331用于将自所述侦测电路310的输出端输出的电压与第一参考电压进行比较，并根据所述侦测电路310的输出端输出的电压与所述第一参考电压的比较结果产生第一调整信号，所述第一调整信号用于调整所述第一反馈支路321的电阻。所述第二调整支路332用于将自所述侦测电路310的输出端输出的电压与第二参考电压进行比较，并根据所述侦测电路310的输出端输出的电压与所述第二参考电压的比较结果产生第二调整信号，所述第二调整信号用于调整所述第二反馈支路322的电阻。所述第三调整支路333用于将自所述侦测电路310的输出端输出的电压与第三参考电压进行比较，并根据所述侦测电路310的输出端输出的电压与所述第三参考电压的比较结果产生第三调整信号，所述第三调整信号用于调整所述第三反馈支路323的电阻，其中，所述第一参考电压小于所述第二参考电压，且所述第二参考电压小于所述第三参考电压。
所述第一反馈支路321包括第一薄膜晶体管Q1及第一电阻R1。所述第一薄膜晶体管Q1的源极电连接所述倍压输出端120，所述第一薄膜晶体管Q1 的栅极用于接收所述第一调整信号，所述第一薄膜晶体管Q1的漏极电连接所述第一电阻R1至所述VGH线，所述第一调整信号用于调整所述第一薄膜晶体管Q1的导通或者截止。所述第二反馈支路322包括第二薄膜晶体管Q2及第二电阻R2。所述第二薄膜晶体管Q2的源极电连接所述倍压输出端120，所述第二薄膜晶体管Q2的栅极用于接收所述第二调整信号，所述第二薄膜晶体管Q2的漏极电连接所述第二电阻R2至所述VGH线，所述第二调整信号用于调整所述第二薄膜晶体管Q2的导通或者截止。所述第三反馈支路323包括第三薄膜晶体管Q3与第三电阻R3。所述第三薄膜晶体管Q3的源极电连接所述倍压输出端120，所述第二薄膜晶体管Q3的栅极用于接收所述第三调整信号，所述第三薄膜晶体管Q3的漏极电连接所述第三电阻R3至所述VGH线，所述第三调整信号用于调整所述第三薄膜晶体管Q3的导通或者截止。
在本实施方式中，所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2及所述第三薄膜晶体管Q3均为P型薄膜晶体管(P-Metal Oxide Semiconductor，PMOS)。当所述第一调整信号为低电平信号时，所述第一薄膜晶体管Q1导通，当所述第一调整信号为高电平信号时，所述第一薄膜晶体管Q1截止。当所述第二调整信号为低电平信号时，所述第二薄膜晶体管Q2导通，当所述第二调整信号为高电平信号时，所述第二薄膜晶体管Q2截止。当所述第三调整信号为低电平信号时，所述第三薄膜晶体管Q3导通，当所述第三调整信号为高电平信号时，所述第三薄膜晶体管Q3截止。
所述第一调整支路331包括第一比较器OP1。所述第一比较器OP1的同相输入端电连接所述侦测电路310的输出端以接收所述侦测电路310的输出端输出的电压，所述第一比较器OP1的反相输入端加载所述第一参考电压。当所述第一比较器OP1的同相输入端接收到的电压大于或等于所述第一参考电压时，所述第一调整支路331控制所述第一薄膜晶体管Q1截止，当所述第一调整支路331的接收端接收到的电压小于所述第一参考电压时，所述第一调整支路331控制所述第一薄膜晶体管Q1导通。
所述第二调整支路332包括第二比较器OP2。所述第二比较器OP2的同相输入端电连接所述侦测电路310的输出端以接收所述侦测电路310的输出端输出的电压，所述第二比较器OP2的反相输入端加载所述第二参考电压。当 所述第二比较器OP2的同相输入端接收到的电压大于或等于所述第二参考电压时，所述第二调整支路332控制所述第二薄膜晶体管Q2截止，当所述第二调整支路332的接收端接收到的电压小于所述第二参考电压时，所述第二调整支路332控制所述第二薄膜晶体管Q2导通。
所述第三调整支路333包括第三比较器OP3。所述第三比较器OP3的同相输入端电连接所述侦测电路310的输出端以接收所述侦测电路310的输出端输出的电压，所述第三比较器OP2的反相输入端加载所述第三参考电压。当第三比较器OP3的同相输入端接收到的电压大于或等于所述第三参考电压时，所述第三调整支路333控制所述第三薄膜晶体管Q3截止，当所述第三调整支路333的接收端接收到的电压小于所述第三参考电压时，所述第三调整支路333控制所述第三薄膜晶体管Q3导通。
所述侦测电路310包括第四电阻R4、第五电阻R5及光电耦合器311。所述光电耦合器311包括第一耦合输入端311a、第二耦合输入端311b、第一耦合输出端311c及第二耦合输出端311d。所述第四电阻R4的一端作为所述侦测电路310的输入端电连接所述VGH线，所述第四电阻R4的另一端电连接所述第一耦合输出端311c，所述第一耦合输入端311a电连接所述VGH线，所述第二耦合输入端311b电连接所述倍压电路100，所述第二耦合输出端311d电连接所述第五电阻R5至地，所述第二耦合输出端311d及所述第五电阻R5之间的节点A作为所述侦测电路310的输出端。
所述光电耦合器311接收所述第一耦合输入端311a及所述第二耦合输入端311b的电信号，将所述第一耦合输入端311a及所述第二耦合输入端311b接收到的信号转换为光信号，再将光信号转换为电信号经由所述第一耦合输出端311c及第二耦合输出端311d输出。自所述第一耦合输出端311c及所述第二耦合输出端311d输出的信号是自所述第一耦合输入端311a及所述第二耦合输入端311b输入的信号的N倍(其中，N为正数)。所述光电耦合器311用于防止与所述第一耦合输入端311a及所述第二耦合输入端311b连接的电子元件对与所述第一耦合输出端311c及所述第二耦合输出端311d连接的电子元件的相互干扰，以提高在进行EOS测试时，整个保护电路300的过流保护时的保护精度。
所述第二反馈电路350包括并联的第四反馈支路351、第五反馈支路352及第六反馈支路353。所述第二调整电路340用于根据所述侦测电路310的输出端输出的电压得到第四调整信号、第五调整信号及第六调整信号。所述第四调整信号用于调整所述第四反馈支路351的电阻，所述第五调整信号用于调整所述第五反馈支路352的电阻，所述第六调整信号用于调整所述第六反馈支路353的电阻。所述第四调整信号、所述第五调整信号及所述第六调整信号配合以调整所述第二反馈电路350的电阻。
所述第二调整电路340包括乘法器341及控制器342。所述乘法器341包括第一乘法输入端341a、第二乘法输入端341b及乘法输出端341c。所述第一乘法输入端341a电连接所述侦测电路310的输出端，以接收所述侦测电路310的输出端输出的电压。所述第二乘法输入端341b加载预设系数，所述乘法器341用于将所述侦测电路310的输出端输出的电压乘以所述预设系数，以得到控制信号，并将所述控制信号经由所述乘法输出端341c输出。所述控制器342包括控制信号接收端342a、第一输出端342b、第二输出端342c及第三输出端342d。所述控制信号接收端342a用于接收所述控制信号，所述控制器342根据所述控制信号产生所述第四调整信号、所述第五调整信号及所述第六调整信号。其中所述第四调整信号经由所述第一输出端342b输出，所述第五调整信号经由所述第二输出端342c输出，所述第六调整信号经由所述第三输出端342d输出。
所述第四反馈支路351包括第四薄膜晶体管Q4及第六电阻R6。所述第五反馈支路352包括第五薄膜晶体管Q5及第七电阻R7。所述第六反馈支路353包括第六薄膜晶体管Q6及第八电阻R8。所述第二反馈电路350还包括第七反馈支路354。所述第七反馈支路354包括第九电阻R9及第十电阻R10。所述第九电阻R9的一端电连接所述倍压输出端120，所述第九电阻R9的另一端电连接所述第十电阻R10至地。
所述第四薄膜晶体管Q4的栅极用于接收所述第四调整信号，所述第四调整信号用于控制所述第四薄膜晶体管Q4的导通或者截止，所述第四薄膜晶体管Q4的漏极通过所述第六电阻R6电连接所述第九电阻R9与所述第十电阻R10之间的节点FB，所述第四薄膜晶体管Q4的源极接地。
所述第五薄膜晶体管Q5的栅极用于接收所述第五调整信号，所述第五调整信号用于控制所述第五薄膜晶体管Q5的导通或者截止，所述第五薄膜晶体管Q5的漏极通过所述第七电阻R7电连接所述第九电阻R9与所述第十电阻R10之间的节点，所述第五薄膜晶体管Q5的源极接地。
所述第六薄膜晶体管Q6的栅极用于接收所述第六调整信号，所述第六调整信号用于控制所述第六薄膜晶体管Q6的之间导通或者截止，所述第六薄膜晶体管Q6的漏极通过所述第八电阻R8电连接至所述第九电阻R9与所述第十电阻R10之间的节点，所述第六薄膜晶体管Q6的源极接地。
在本实施方式中，所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5及所述第六薄膜晶体管Q6均为N型薄膜晶体管(N-Metal Oxide Semiconductor，NMOS)。当所述第四调整信号为高电平信号时，所述第四薄膜晶体管Q4导通，当所述第四调整信号为低电平信号时，所述第四薄膜晶体管Q4截止。当所述第五调整信号为高电平信号时，所述第五薄膜晶体管Q5导通。当所述第五调整信号为低电平信号时，所述第五薄膜晶体管Q5截止。当所述第六调整信号为高电平信号时，所述第六薄膜晶体管Q6导通。当所述第六调整信号为低电平信号时，所述第六薄膜晶体管Q6截止。
所述倍压电路100还包括电容C123，所述电容C123一端电连接所述倍压输出端120，另一端接地。所述电容C123用于对所述倍压输出端120输出的第二电压进行滤波，以使得经由所述倍压输出端120输出的第二电压的波形更加平滑。
下面对本发明的直流电压转换电路的工作原理进行介绍。当所述倍压电路100未进行EOS测试时，流过所述倍压电路100中电源管理芯片(Power ManagementIC PMIC)的VGH引脚及流经所述VGH线的电流都很小。流经所述第二耦合输出端311d及所述第五电阻R5之间的节点A的电压用VA表示，所述第一参考电压用Vref1表示，所述第二参考电压用Vref2表示，所述第三参考电压用Vref3表示。则，此时，VA＜Vref1＜Vref2＜Vref3，此时，所述第一比较器OP1根据VA与第一参考电压Vref1比较的结果产生低电平信号，所述第二比较器OP2根据VA与第二参考电压Vref2比较的结果产生低电平信号，所述第三比较器根据VA与所述第三参考电压比较的结果产生低电平 信号。所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2及所述第三薄膜晶体管Q3均导通。此时，所述第一反馈电路320的等效电阻即第一等效电阻Req1等于R1、R2及R3的并联(用符号“//”表示并联，则，R1、R2和R3并联表示为R1//R2//R3)之后的电阻。所述第一反馈电路320的电流定义为I1。此时，所述第以反馈电路320的电压降等于I1*Req1。所述第九电阻R9与所述第十电阻R10之间的节点FB的电压用VFB表示。所述倍压电路100的倍压输出端120的电压用VGHF表示，VGH线的电压用VGH表示。则，此时VGHF＝VFB*(1+R9/R10)，VGH＝VGHF-I1*Req1＝VFB*(1+R9/R10)-I1*(R1//R2//R3)。
当所述倍压电路100进行EOS测试时，流入所述倍压电路100中电源管理芯片VGH引脚以路径所述VGH线的电流增大。假设此时，Vref1＜Vref2＜VA＜Vref3。所述第一比较器OP1根据VA与第一参考电压Vref1的比较结果产生高电平信号，所述第二比较器OP2根据VA与第二参考电压Vref2的比较结果产生高电平信号，所述第三比较器OP3根据VA与Vref3的比较结果产生低电平信号。此时，所述第一薄膜晶体管Q1截止，所述第二薄膜晶体管Q2截止，所述第三薄膜晶体管Q3导通。此时，所述第一反馈电路320的等效电阻即第三等效电阻Req3等于R3。此时，所述第一反馈电路320的电压降等于I1*R3，此时，所述第二调整电路340中输出的第四调整信号为高电平信号、所述第五电阻信号为高电平信号，所述第六调整信号为低电平信号。则，此时，VGHF＝VFB*[1+R9/(R10//R6//R7)]，由此可见，进行EOS测试时的VGHF相较于未进行EOS测试时的VGHF电压值增加。而VGH＝VGHF-I1*R3＝VFB*[1+R9/(R10//R6//R7)]-I1*R3＝VFB*(1+R9/R10)-I1*(R1//R2//R3)。由此可见，进行EOS测试时所述VGH线的电压等于未进行测试时VGH线的电压。
相较于现有技术，本发明的直流电压转换电路10在所述倍压电路100在进行EOS测试时，倍压输出端120加载测试信号，侦测电路310根据VGH线的电压得到第二侦测电压，第一调整电路330根据第二侦测电压与参考电压的比较结果产生第三信号，第二调整电路340根据第二侦测电压与参考电压的比较结果产生第四信号。第三信号调整第一反馈支路320的等效电阻为第三等效电阻，第四调整信号调整第二反馈支路350的等效电阻为第四电阻，从而通过 对第一反馈支路320及第二反馈支路350的等效电阻的调整使得所述VGH线的电压恢复到未加载测试信号时的电压。由此可以避免在倍压电路100进行EOS测试时，加载测试信号对VGH线或者直流电压转换电路中的元件或者液晶显示装置红的其他元件造成的损坏。
本发明还提供了一种液晶显示装置1，请参阅图3，图3为本发明一较佳实施方式的液晶显示装置的结构示意图。所述液晶显示装置1包括前面所述的直流电压转换电路，在此不再赘述。在本实施方式中，所述液晶显示装置1包括但不仅限于包括但不仅限于智能手机(Smart Phone)、互联网设备(Mobile Internet Device，MID)、电子书、平板电脑、便携式播放站(Play Station Portable，PSP)或者个人数字助理(Personal Digital Assistant，PDA)等便携式设备。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种直流电压转换电路，所述直流电压转换电路应用于液晶显示装置中，其中，所述直流电压转换电路包括倍压电路及保护电路，所述倍压电路包括倍压输入端及倍压输出端，所述倍压输入端用于接收第一电压，所述倍压电路用于将所述第一电压转换为第二电压，所述第二电压经由所述倍压输出端输出，所述保护电路包括侦测电路、第一反馈电路、第一调整电路、第二调整电路及第二反馈电路，所述第一反馈电路的输入端电连接所述倍压输出端，所述第一反馈电路的输出端电连接所述液晶显示装置中的VGH线，所述第二反馈电路的一端电连接所述倍压输出端，另一端接地，
    当所述倍压电路未进行EOS测试时，所述侦测电路侦测所述VGH线的电压，并根据所述VGH线的电压得到第一侦测电压，所述第一侦测电压经由所述侦测电路的输出端输出，所述第一调整电路将所述第一侦测电压与参考电压进行比较，并根据所述第一侦测电压与所述参考电压的比较结果产生第一信号，所述第一信号用于调整第一反馈电路的等效电阻为第一等效电阻，所述第二调整电路根据所述第一侦测电压产生第二信号，所述第二信号用于调整所述第二反馈电路的等效电阻为第二等效电阻，
    当所述倍压电路进行EOS测试时，所述倍压输出端加载测试信号，所述侦测电路侦测所述VGH线的电压，并根据所述VGH线的电压得到第二侦测电压，所述第二侦测电压经由所述侦测电路的输出端输出，所述第一调整电路将所述第二侦测电压与所述参考电压进行比较，并根据所述第二侦测电压与所述参考电压的比较结果产生第三信号，所述第三信号用于调整所述第一反馈电路的等效电阻为第三等效电阻，所述第二调整电路根据所述第二侦测电压产生第四信号，所述第四信号用于调整所述第二反馈电路的等效电阻为第四等效电阻，当所述第一反馈支路的等效电阻被调整为所述第三等效电阻且所述第二反馈支路的等效电阻被调整为所述第四等效电阻时，所述VGH线的电压变为第一侦测电压。
  2. 如权利要求1所述的直流电压转换电路，其中，所述第一反馈电路包括 并联的第一反馈支路、第二反馈支路及第三反馈支路，所述第一调整电路包括第一调整支路、第二调整支路及第三调整支路，所述第一调整支路用于将自所述侦测电路的输出端输出的电压与第一参考电压进行比较，并根据所述侦测电路的输出端输出的电压与第一参考电压的比较结果产生第一调整信号，所述第一调整信号用于调整所述第一反馈支路的电阻，所述第二调整支路用于将自所述侦测电路的输出端输出的电压与第二参考电压进行比较，并根据所述侦测电路的输出端输出的电压与所述第二参考电压的比较结果产生第二调整信号，所述第二调整信号用于调整所述第二反馈支路的电阻，所述第三调整支路用于将自所述侦测电路的输出端输出的电压与第三参考电压进行比较，并根据所述侦测电路的输出端输出的电压与所述第三参考电压的比较结果产生第三调整信号，所述第三调整信号用于调整所述第三反馈支路的电阻，其中，所述第一参考电压小于所述第二参考电压，且所述第二参考电压小于所述第三参考电压。
  3. 如权利要求2所述的直流电压转换电路，其中，所述第一反馈支路包括第一薄膜晶体管及第一电阻，所述第一薄膜晶体管的源极电连接所述倍压输出端，所述第一薄膜晶体管的栅极用于接收所述第一调整信号，所述第一薄膜晶体管的漏极电连接所述第一电阻至所述VGH线，所述第一调整信号用于调整所述第一薄膜晶体管的导通或者截止；
    所述第二反馈支路包括第二薄膜晶体管及第二电阻，所述第二薄膜晶体管的源极电连接所述倍压输出端，所述第二薄膜晶体管的栅极用于接收所述第二调整信号，所述第二薄膜晶体管的漏极电连接所述第二电阻至所述VGH线，所述第二调整信号用于调整所述第二薄膜晶体管的导通或者截止，
    所述第三反馈支路包括第三薄膜晶体管与第三电阻，所述第三薄膜晶体管的源极电连接所述倍压输出端，所述第二薄膜晶体管的栅极用于接收所述第三调整信号，所述第三薄膜晶体管的漏极电连接所述第三电阻至所述VGH线，所述第三调整信号用于调整所述第三薄膜晶体管的导通或者截止。
  4. 如权利要求3所述的直流电压转换电路，其中，所述第一调整支路包括第一比较器，所述第一比较器的同相输入端电连接所述侦测电路的输出端以接 收所述侦测电路的输出端输出的电压，所述第一比较器的反相输入端加载所述第一参考电压，当所述第一比较器的同相输入端接收到的电压大于或等于所述第一参考电压时，所述第一调整支路控制所述第一薄膜晶体管截止，当所述第一调整支路的接收端接收到的电压小于所述第一参考电压时，所述第一调整支路控制所述第一薄膜晶体管导通；
    所述第二调整支路包括第二比较器，所述第二比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第二比较器的反相输入端加载所述第二参考电压，当所述第二比较器的同相输入端接收到的电压大于或等于所述第二参考电压时，所述第二调整支路控制所述第二薄膜晶体管截止，当所述第二调整支路的接收端接收到的电压小于所述第二参考电压时，所述第二调整支路控制所述第二薄膜晶体管导通；
    所述第三调整支路包括第三比较器，所述第三比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第三比较器的反相输入端加载所述第三参考电压，当第三比较器的同相输入端接收到的电压大于或等于所述第三参考电压时，所述第三调整支路控制所述第三薄膜晶体管截止，当所述第三调整支路的接收端接收到的电压小于所述第三参考电压时，所述第三调整支路控制所述第三薄膜晶体管导通。
  5. 如权利要求1所述的直流电压转换电路，其中，所述侦测电路包括第四电阻、第五电阻及光电耦合器，所述光电耦合器包括第一耦合输入端、第二耦合输入端、第一耦合输出端及第二耦合输出端，所述第四电阻的一端作为所述侦测电路的输入端电连接所述VGH线，所述第四电阻的另一端电连接所述第一耦合输出端，所述第一耦合输入端电连接所述VGH线，所述第二耦合输入端电连接所述倍压电路，所述第二耦合输出端电连接所述第五电阻至地，所述第二耦合输出端及所述第五电阻之间的节点作为所述侦测电路的输出端。
  6. 如权利要求1所述的直流电压转换电路，其中，所述第二反馈电路包括并联的第四反馈支路、第五反馈支路及第六反馈支路，所述第二调整电路用于根据所述侦测电路的输出端输出的电压得到第四调整信号、第五调整信号及第 六调整信号，所述第四调整信号用于调整所述第四反馈支路的电阻，所述第五调整信号用于调整所述第五反馈支路的电阻，所述第六调整信号用于调整所述第六反馈支路的电阻，所述第四调整信号、所述第五调整信号及所述第六调整信号配合以调整所述第二反馈电路的电阻。
  7. 如权利要求6所述的直流电压转换电路，其中，所述第二调整电路包括乘法器及控制器，所述乘法器包括第一乘法输入端、第二乘法输入端及乘法输出端，所述第一乘法输入端电连接所述侦测电路的输出端，以接收所述侦测电路的输出端输出的电压，所述第二乘法输入端加载预设系数，所述乘法器用于将所述侦测电路的输出端输出的电压乘以所述预设系数，以得到控制信号，并将所述控制信号输出，所述控制器包括控制信号接收端、第一输出端、第二输出端及第三输出端，所述控制信号接收端用于接收所述控制信号，所述控制器根据所述控制信号产生所述第四调整信号、所述第五调整信号及所述第六调整信号，其中所述第四调整信号经由所述第一输出端输出，所述第五调整信号经由所述第二输出端输出，所述第六调整信号经由所述第三输出端输出。
  8. 如权利要求6所述的直流电压转换电路，其中，所述第四反馈支路包括第四薄膜晶体管及第六电阻，所述第五反馈支路包括第五薄膜晶体管及第七电阻，所述第六反馈支路包括第六薄膜晶体管及第八电阻，所述第二反馈电路还包括第七反馈支路，所述第七反馈支路包括第九电阻及第十电阻，所述第九电阻的一端电连接所述倍压输出端，所述第九电阻的另一端电连接所述第十电阻至地；
    所述第四薄膜晶体管的栅极用于接收所述第四调整信号，所述第四调整信号用于控制所述第四薄膜晶体管的导通或者截止，所述第四薄膜晶体管的漏极通过所述第六电阻电连接所述第九电阻与所述第十电阻之间的节点，所述第四薄膜晶体管的源极接地；
    所述第五薄膜晶体管的栅极用于接收所述第五调整信号，所述第五调整信号用于控制所述第五薄膜晶体管的导通或者截止，所述第五薄膜晶体管的漏极通过所述第七电阻电连接所述第九电阻与所述第十电阻之间的节点，所述第五 薄膜晶体管的源极接地；
    所述第六薄膜晶体管的栅极用于接收所述第六调整信号，所述第六调整信号用于控制所述第六薄膜晶体管的导通或者截止，所述第六薄膜晶体管的漏极通过所述第八电阻电连接至所述第九电阻与所述第十电阻之间的节点，所述第六薄膜晶体管的源极接地。
  9. 如权利要求8所述的直流电压转换电路，其中，所述倍压电路还包括电容，所述电容一端电连接所述倍压输出端，另一端接地。
  10. 一种液晶显示装置，其中，所述液晶显示装置包括直流电压转换电路，所述直流电压转换电路包括倍压电路及保护电路，所述倍压电路包括倍压输入端及倍压输出端，所述倍压输入端用于接收第一电压，所述倍压电路用于将所述第一电压转换为第二电压，所述第二电压经由所述倍压输出端输出，所述保护电路包括侦测电路、第一反馈电路、第一调整电路、第二调整电路及第二反馈电路，所述第一反馈电路的输入端电连接所述倍压输出端，所述第一反馈电路的输出端电连接所述液晶显示装置中的VGH线，所述第二反馈电路的一端电连接所述倍压输出端，另一端接地，
    当所述倍压电路未进行EOS测试时，所述侦测电路侦测所述VGH线的电压，并根据所述VGH线的电压得到第一侦测电压，所述第一侦测电压经由所述侦测电路的输出端输出，所述第一调整电路将所述第一侦测电压与参考电压进行比较，并根据所述第一侦测电压与所述参考电压的比较结果产生第一信号，所述第一信号用于调整第一反馈电路的等效电阻为第一等效电阻，所述第二调整电路根据所述第一侦测电压产生第二信号，所述第二信号用于调整所述第二反馈电路的等效电阻为第二等效电阻，
    当所述倍压电路进行EOS测试时，所述倍压输出端加载测试信号，所述侦测电路侦测所述VGH线的电压，并根据所述VGH线的电压得到第二侦测电压，所述第二侦测电压经由所述侦测电路的输出端输出，所述第一调整电路将所述第二侦测电压与所述参考电压进行比较，并根据所述第二侦测电压与所述参考电压的比较结果产生第三信号，所述第三信号用于调整所述第一反馈电 路的等效电阻为第三等效电阻，所述第二调整电路根据所述第二侦测电压产生第四信号，所述第四信号用于调整所述第二反馈电路的等效电阻为第四等效电阻，当所述第一反馈支路的等效电阻被调整为所述第三等效电阻且所述第二反馈支路的等效电阻被调整为所述第四等效电阻时，所述VGH线的电压变为第一侦测电压。
  11. 如权利要求10所述的液晶显示装置，其中，所述第一反馈电路包括并联的第一反馈支路、第二反馈支路及第三反馈支路，所述第一调整电路包括第一调整支路、第二调整支路及第三调整支路，所述第一调整支路用于将自所述侦测电路的输出端输出的电压与第一参考电压进行比较，并根据所述侦测电路的输出端输出的电压与第一参考电压的比较结果产生第一调整信号，所述第一调整信号用于调整所述第一反馈支路的电阻，所述第二调整支路用于将自所述侦测电路的输出端输出的电压与第二参考电压进行比较，并根据所述侦测电路的输出端输出的电压与所述第二参考电压的比较结果产生第二调整信号，所述第二调整信号用于调整所述第二反馈支路的电阻，所述第三调整支路用于将自所述侦测电路的输出端输出的电压与第三参考电压进行比较，并根据所述侦测电路的输出端输出的电压与所述第三参考电压的比较结果产生第三调整信号，所述第三调整信号用于调整所述第三反馈支路的电阻，其中，所述第一参考电压小于所述第二参考电压，且所述第二参考电压小于所述第三参考电压。
  12. 如权利要求11所述的液晶显示装置，其中，所述第一反馈支路包括第一薄膜晶体管及第一电阻，所述第一薄膜晶体管的源极电连接所述倍压输出端，所述第一薄膜晶体管的栅极用于接收所述第一调整信号，所述第一薄膜晶体管的漏极电连接所述第一电阻至所述VGH线，所述第一调整信号用于调整所述第一薄膜晶体管的导通或者截止；
    所述第二反馈支路包括第二薄膜晶体管及第二电阻，所述第二薄膜晶体管的源极电连接所述倍压输出端，所述第二薄膜晶体管的栅极用于接收所述第二调整信号，所述第二薄膜晶体管的漏极电连接所述第二电阻至所述VGH线，所述第二调整信号用于调整所述第二薄膜晶体管的导通或者截止，
    所述第三反馈支路包括第三薄膜晶体管与第三电阻，所述第三薄膜晶体管的源极电连接所述倍压输出端，所述第二薄膜晶体管的栅极用于接收所述第三调整信号，所述第三薄膜晶体管的漏极电连接所述第三电阻至所述VGH线，所述第三调整信号用于调整所述第三薄膜晶体管的导通或者截止。
  13. 如权利要求12所述的液晶显示装置，其中，所述第一调整支路包括第一比较器，所述第一比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第一比较器的反相输入端加载所述第一参考电压，当所述第一比较器的同相输入端接收到的电压大于或等于所述第一参考电压时，所述第一调整支路控制所述第一薄膜晶体管截止，当所述第一调整支路的接收端接收到的电压小于所述第一参考电压时，所述第一调整支路控制所述第一薄膜晶体管导通；
    所述第二调整支路包括第二比较器，所述第二比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第二比较器的反相输入端加载所述第二参考电压，当所述第二比较器的同相输入端接收到的电压大于或等于所述第二参考电压时，所述第二调整支路控制所述第二薄膜晶体管截止，当所述第二调整支路的接收端接收到的电压小于所述第二参考电压时，所述第二调整支路控制所述第二薄膜晶体管导通；
    所述第三调整支路包括第三比较器，所述第三比较器的同相输入端电连接所述侦测电路的输出端以接收所述侦测电路的输出端输出的电压，所述第三比较器的反相输入端加载所述第三参考电压，当第三比较器的同相输入端接收到的电压大于或等于所述第三参考电压时，所述第三调整支路控制所述第三薄膜晶体管截止，当所述第三调整支路的接收端接收到的电压小于所述第三参考电压时，所述第三调整支路控制所述第三薄膜晶体管导通。
  14. 如权利要求10所述的液晶显示装置，其中，所述侦测电路包括第四电阻、第五电阻及光电耦合器，所述光电耦合器包括第一耦合输入端、第二耦合输入端、第一耦合输出端及第二耦合输出端，所述第四电阻的一端作为所述侦测电路的输入端电连接所述VGH线，所述第四电阻的另一端电连接所述第一 耦合输出端，所述第一耦合输入端电连接所述VGH线，所述第二耦合输入端电连接所述倍压电路，所述第二耦合输出端电连接所述第五电阻至地，所述第二耦合输出端及所述第五电阻之间的节点作为所述侦测电路的输出端。
  15. 如权利要求10所述的液晶显示装置，其中，所述第二反馈电路包括并联的第四反馈支路、第五反馈支路及第六反馈支路，所述第二调整电路用于根据所述侦测电路的输出端输出的电压得到第四调整信号、第五调整信号及第六调整信号，所述第四调整信号用于调整所述第四反馈支路的电阻，所述第五调整信号用于调整所述第五反馈支路的电阻，所述第六调整信号用于调整所述第六反馈支路的电阻，所述第四调整信号、所述第五调整信号及所述第六调整信号配合以调整所述第二反馈电路的电阻。
  16. 如权利要求15所述的液晶显示装置，其中，所述第二调整电路包括乘法器及控制器，所述乘法器包括第一乘法输入端、第二乘法输入端及乘法输出端，所述第一乘法输入端电连接所述侦测电路的输出端，以接收所述侦测电路的输出端输出的电压，所述第二乘法输入端加载预设系数，所述乘法器用于将所述侦测电路的输出端输出的电压乘以所述预设系数，以得到控制信号，并将所述控制信号输出，所述控制器包括控制信号接收端、第一输出端、第二输出端及第三输出端，所述控制信号接收端用于接收所述控制信号，所述控制器根据所述控制信号产生所述第四调整信号、所述第五调整信号及所述第六调整信号，其中所述第四调整信号经由所述第一输出端输出，所述第五调整信号经由所述第二输出端输出，所述第六调整信号经由所述第三输出端输出。
  17. 如权利要求15所述的液晶显示装置，其中，所述第四反馈支路包括第四薄膜晶体管及第六电阻，所述第五反馈支路包括第五薄膜晶体管及第七电阻，所述第六反馈支路包括第六薄膜晶体管及第八电阻，所述第二反馈电路还包括第七反馈支路，所述第七反馈支路包括第九电阻及第十电阻，所述第九电阻的一端电连接所述倍压输出端，所述第九电阻的另一端电连接所述第十电阻至地；
    所述第四薄膜晶体管的栅极用于接收所述第四调整信号，所述第四调整信号用于控制所述第四薄膜晶体管的导通或者截止，所述第四薄膜晶体管的漏极通过所述第六电阻电连接所述第九电阻与所述第十电阻之间的节点，所述第四薄膜晶体管的源极接地；
    所述第五薄膜晶体管的栅极用于接收所述第五调整信号，所述第五调整信号用于控制所述第五薄膜晶体管的导通或者截止，所述第五薄膜晶体管的漏极通过所述第七电阻电连接所述第九电阻与所述第十电阻之间的节点，所述第五薄膜晶体管的源极接地；
    所述第六薄膜晶体管的栅极用于接收所述第六调整信号，所述第六调整信号用于控制所述第六薄膜晶体管的导通或者截止，所述第六薄膜晶体管的漏极通过所述第八电阻电连接至所述第九电阻与所述第十电阻之间的节点，所述第六薄膜晶体管的源极接地。
  18. 如权利要求17所述的液晶显示装置，其中，所述倍压电路还包括电容，所述电容一端电连接所述倍压输出端，另一端接地。
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