WO2017201703A1 - 一种功率半导体芯片背面金属结构及其制备方法 - Google Patents

一种功率半导体芯片背面金属结构及其制备方法 Download PDF

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WO2017201703A1
WO2017201703A1 PCT/CN2016/083433 CN2016083433W WO2017201703A1 WO 2017201703 A1 WO2017201703 A1 WO 2017201703A1 CN 2016083433 W CN2016083433 W CN 2016083433W WO 2017201703 A1 WO2017201703 A1 WO 2017201703A1
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layer
nickel
thickness
silicon
chip
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PCT/CN2016/083433
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English (en)
French (fr)
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艾哈迈德伊夫蒂哈尔
舒小平
徐远梅
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中山港科半导体科技有限公司
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Priority to PCT/CN2016/083433 priority Critical patent/WO2017201703A1/zh
Publication of WO2017201703A1 publication Critical patent/WO2017201703A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries

Definitions

  • the present invention pertains to the structure and manufacturing technology of a semiconductor chip, and more particularly to a metal structure of a power semiconductor chip back surface and a method of fabricating the same.
  • VDMOS vertical double-diffused metal oxide semiconductor field effect transistors
  • FPD fast recovery diodes
  • VDMOS vertical double-diffused metal oxide semiconductor field effect transistors
  • FPD fast recovery diodes
  • Conduction loss, the parasitic resistance on the back of the chip should be as small as possible. Therefore, in the latter part of the manufacturing process of the chip, the entire wafer is thinned from the back side to about 200 um, and then the metal layer is deposited on the back side.
  • the back metal structure commonly used in the power semiconductor chip industry is a titanium/nickel/silver combination.
  • titanium (Ti) acts as an adhesion layer to maintain a close physical contact between the back metal and silicon
  • nickel (Ni) acts as a barrier to prevent silver from diffusing to the silicon surface during packaging
  • Silver (Ag) acts as a conductive layer, and the connection resistance between the chip and the solder is as small as possible in the package.
  • the above back metal structure can be deposited on the back surface of the wafer by evaporation, sputtering, etc., and the main component of the parasitic resistance is the contact resistance between titanium and silicon.
  • Figure 2 shows the band structure of titanium after contact with silicon.
  • the silicon in the figure is N-type heavily doped, which is the substrate material used in most VDMOS and FRD, as shown, titanium and silicon.
  • the barrier between them is a tunneling barrier.
  • the probability of electron tunneling into the silicon in the silicon conduction band (EC) depends on the height and width of the barrier. Therefore, the height and width of the barrier determine the titanium and silicon.
  • the width of the barrier depends on the barrier height and the concentration of N-type impurities (phosphorus or arsenic) in silicon. Generally, the barrier width is reduced as much as possible.
  • the concentration of N-type impurities in silicon is saturated or nearly saturated, and it is impossible to further increase.
  • the height of the barrier depends on the difference in work function between silicon and titanium.
  • the electrons are transferred until the Fermi level (Ef) of both sides is the same.
  • the work function of titanium depends on the material itself and is an amount that cannot be changed.
  • the work function of heavily doped N-type silicon cannot be significantly changed. Therefore, there is a minimum value of the parasitic resistance of the currently used titanium/nickel/silver structure, and this value cannot be lowered by optimizing the process conditions.
  • the present invention provides a new chip back metal structure, and an object of the present invention is to provide a back metal structure of a power semiconductor chip having a smaller parasitic resistance, and the manufacture of the metal structure. method.
  • the technical solution of the present invention is as follows:
  • a power semiconductor chip back metal structure the metal structure from the back of the chip in order is: Ni x Si y layer, where x: y is (1-2):
  • x:y can be 1:2, 1:1 or 2:1, x:y can also be any value between 1:2 ⁇ 1: 1, or between 1: 1 ⁇ Any value between 1:2; since the role of nickel silicide is only to adjust the height and width of the barrier, the thickness of the nickel silicide need not be too thick, generally between 2 nm and 20 nm; the titanium layer, the titanium layer The thickness is 50nm - 150nm, and the underlying nickel silicide is titanium, which is the same as the conventional structure, where the role of titanium is to enhance the adhesion between the nickel silicide and other metal layers; the nickel layer, the thickness of the nickel layer is 100n m -300nm, the lower nickel titanium, where nickel is to prevent the effect of the process of packaging the silver diffused into the silicon surface; silver layer, the thickness of the silver layer is 500nm -2000 nm, under the effect of nickel is silver, silver It is a conductive layer, and the connection resistance between the chip and the solder is as small as possible in the package;
  • a method for preparing a metal structure of a back surface of a power semiconductor chip comprising the following steps:
  • the first layer is nickel, and the nickel has a thickness of 2 n m-20nm, which is then reacted with silicon to form nickel silicide, adjusting the barrier height, so this layer of nickel
  • the thickness of the second layer is not too thick;
  • the second layer is titanium, the thickness of titanium is about 100 nm, preferably 50 nm to 150 nm;
  • the third layer is nickel, the thickness of the second layer of nickel is about 200 nm, preferably the thickness is from 100 nm to 300 nm;
  • the four layers are silver, and the thickness of silver is about 100 nm, preferably 500 nm to 2000 nm ;
  • the deposition method may be evaporation, sputtering or electroplating, wherein evaporation is a preferred deposition method because different metals may be disposed in the cavity of the device. ⁇ , evaporating the required metal materials in order, and the evaporation device can process a large amount of one time Wafer.
  • the silicon wafer is subjected to a superalloy to react the first layer of nickel with silicon: the chip deposited in step 1 is heated to 280-800 degrees Celsius, heated while introducing nitrogen or a combination of nitrogen and hydrogen, A layer of nickel reacts with silicon for 5 min-lh to form Ni x Si y .
  • step 3 is: heating the chip deposited in step 3 to 400 degrees Celsius, using the same nitrogen or a combination of nitrogen and hydrogen, and the ratio of the first layer of nickel deposited to silicon is 1: 1, the reaction 5min-lh
  • step 3 is: heating the chip deposited in step 1 to 280 degrees Celsius, heating while introducing nitrogen or a combination of nitrogen and hydrogen, and the ratio of the first layer of nickel deposited to silicon is 2: 1. React 5mi n-lh to form Ni 2 Si.
  • step 3 is: heating the chip deposited in step 1 to 800 degrees Celsius, heating while introducing nitrogen or a combination of nitrogen and hydrogen.
  • the first layer of deposited nickel and silicon reacted at a ratio of 1:2, and the reaction was carried out for 5 min-lh to form NiSi 2 .
  • the beneficial effects of the present invention are that the back metal structure of the power semiconductor chip provided by the present invention has smaller parasitic resistance than the conventional titanium/nickel/silver back metal structure, which is advantageous for reducing the conductivity of the power semiconductor chip. Through loss.
  • 1 is a back metal structure of a conventional power semiconductor chip
  • FIG. 2 is an energy band diagram of a contact position corresponding to a back metal structure of a conventional power semiconductor chip
  • FIG. 3 is a back metal structure of a power semiconductor chip according to the present invention.
  • the metal structure is in order from the back surface of the chip to the silicon: Ni x Si y layer, titanium layer, nickel layer, silver layer;
  • FIG. 4 is an energy band diagram of a contact position corresponding to a back metal structure of a power semiconductor chip according to the present invention.
  • the present invention provides a back metal structure of a new power semiconductor chip, which is in order from the back surface (Si) of the chip: Ni x Si y layer (thickness: 15 nm). Titanium layer (thickness: 100 nm), nickel layer (thickness: 200 nm), silver layer (thickness: 100 nm); nickel silicide (Ni x Si y ) acts to reduce the contact resistance between metal and silicon, nickel silicide (NkSiy) The atomic ratio (x:y) of nickel to silicon may be 1:2, 1:1 or 2:1. Compared with titanium, nickel silicide has a relatively low work function.
  • the barrier height formed is relatively low, and the barrier width is relatively narrow, as shown in FIG.
  • the barrier characteristics, the contact resistance of nickel silicide and silicon contact is lower than that of the conventional structure, so that the power semiconductor chip can have lower conduction loss.
  • nickel silicide Since the role of nickel silicide is only to adjust the barrier height and width, the thickness of nickel silicide need not be too thick, generally between 2 nm and 20 nm; below the nickel silicide is titanium, like the conventional structure, where the role of titanium It is to enhance the adhesion between nickel silicide and other metal layers; below the titanium is nickel, where the role of nickel is to prevent silver from diffusing to the silicon surface during the packaging process; under the nickel is silver, silver acts as a conductive layer, The connection resistance between the chip and the solder is made as small as possible during packaging.
  • the present invention also provides a method for preparing a metal structure of a back surface of a power semiconductor chip, comprising the following steps:
  • the first layer is nickel, the thickness of nickel is lOnm;
  • the second layer is titanium, the thickness of the titanium is 100 nm;
  • the third layer Nickel the thickness of nickel is 200nm;
  • the fourth layer is silver, the thickness of the silver is 1000om;
  • step 3 the silicon wafer is subjected to a superalloy, so that the first layer of nickel reacts with the silicon: the chip deposited in step 1 is placed in an evaporation device, heated to 400 degrees Celsius, and nitrogen gas is introduced and reacted for 1 hour to generate NiSi.
  • the finally obtained metal structure is: NiSi layer, lOnm or so; titanium layer, the thickness of the titanium layer is 100 nm; nickel layer, the thickness of the nickel layer is 200 nm; silver layer, the silver The thickness of the layer is lOOOnm
  • Embodiment 3 also provides a method for preparing a metal structure of a back surface of a power semiconductor chip, comprising the following steps:
  • the first layer is nickel, the thickness of the nickel is 20 nm ;
  • the second layer is titanium, the thickness of the titanium is 90 nm ;
  • the third layer is nickel, the nickel has a thickness of 210 nm;
  • the fourth layer is silver, and the silver has a thickness of 900 nm ;
  • step 3 The silicon wafer is subjected to a superalloy such that the first layer of nickel reacts with the silicon: the chip deposited in step 1 is heated to 280 degrees Celsius in a sputtering system, and the combination of nitrogen and hydrogen is heated by heating the same layer. The reaction was carried out for 40 min to form N i 2 Si.
  • the present invention also provides a method for fabricating a metal structure on the back side of a power semiconductor chip, comprising the following steps: [0033] 1) thinning the wafer to a specified thickness (eg, 200 um) to remove an oxide layer on the silicon surface of the back side of the chip
  • ⁇ electroplating method is deposited on the back side of the chip four layers: the first layer is nickel, the thickness of nickel is 5nm; the second layer is titanium, the thickness of the titanium is l lOnm; The third layer is nickel, the nickel has a thickness of 190 nm; the fourth layer is silver, and the silver has a thickness of l lOOnm;
  • step 3 The silicon wafer is subjected to a superalloy to react the first layer of nickel with silicon:
  • the chip deposited in step 1 is heated to 800 degrees Celsius, and the same layer of nitrogen or nitrogen is reacted with hydrogen for 1 hour to form NiSi. 2 .
  • the back metal structure provided by the invention can reduce the contact resistance of the conventional structure by 10 mQ-mm ⁇
  • x:y in the nickel silicide is not limited to the three cases listed above depending on the alloy temperature and time.
  • x:y in the resulting nickel silicide can be between 1:2 and 1:1.
  • the resulting nickel silicide may have a ratio of x:y between 1:1 and 1:2.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

提供了一种功率半导体芯片背面金属结构及其制备方法，该金属结构自芯片背面与硅接触的位置开始依次为：Ni xSi y层，所述Ni xSi y层的厚度为2nm-20nm，其中x∶y为(1-2)∶(1-2)；钛层，钛层的厚度为50nm-150nm；镍层，镍层的厚度为100nm-300nm；银层，银层的厚度为500nm-2000nm。所提供的功率半导体芯片的背面金属结构，其寄生电阻更小，有利于降低功率半导体芯片的导通损耗。

Description

发明名称:一种功率半导体芯片背面金属结构及其制备方法 技术领域
[0001] 本发明属于半导体芯片的结构和制造技术， 具体地， 属一种功率半导体芯片背 面金属结构及其制备方法。
背景技术
[0002] 功率半导体芯片如垂直双扩散金属氧化物半导体场效应晶体管 （VDMOS) 和 快恢复二极管 （FRD) 被大量应用于幵关电源、 马达驱动等电力电子系统中， 为 降低这一类芯片的导通损耗， 芯片背面的寄生电阻需尽可能小。 因此， 在芯片 的制造过程后段， 整个晶圆会从背面被减薄到大约 200um左右， 之后在背面淀积 金属层， 目前， 功率半导体芯片业界常用的背面金属结构是钛 /镍 /银组合， 如图 1所示， 钛 （Ti) 的作用是粘附层， 使背金属和硅之间保持紧密的物理接触； 镍 (Ni) 的作用是阻挡层， 防止封装过程中银扩散到硅表面； 银 （Ag) 的作用是 导电层， 在封装吋使芯片和焊料之间的连接电阻尽可能地小。 上述背金属结构 可以用蒸发、 溅射等方法淀积到晶圆背面， 其寄生电阻的主要成分是钛与硅之 间的接触电阻。 图 2示出了钛与硅形成接触后的能带结构， 图中的硅是 N型重掺 杂的， 这是绝大部分 VDMOS和 FRD采用的衬底材料， 如图所示， 钛与硅之间的 势垒是一个隧穿势垒， 硅导带 （EC) 中电子隧穿到钛中的几率取决于势垒高度 和宽度， 因此势垒的高度和宽度也就决定了钛与硅之间接触电阻的大小， 势垒 越低 /窄， 接触电阻越小。 该势垒的宽度取决于势垒高度和硅中 N型杂质 （磷或 砷） 的浓度， 通常为尽可能降低势垒宽度， 硅中 N型杂质的浓度已饱和或接近饱 和， 不可能进一步提高； 另一方面， 该势垒的高度取决于硅和钛的功函数之差 , 二者接触时， 电子发生转移直至双方的费米能级 （Ef) 相同。 但是， 钛的功函 数取决于材料本身， 是一个不能改变的量， 重掺杂的 N型硅的功函数也不能明显 改变。 因此， 目前常用的钛 /镍 /银结构的寄生电阻存在一个最小值， 且该值不能 够通过优化工艺条件而降低。
技术问题 问题的解决方案
技术解决方案
[0003] 为解决上述提到的问题， 本发明提供一种新的芯片背面金属结构， 本发明的目 的是提供一种寄生电阻更小的功率半导体芯片的背面金属结构， 以及该金属结 构的制造方法。 本发明的技术方案如下：
[0004] 一种功率半导体芯片背面金属结构， 所述的金属结构自芯片背面开始依次为： Ni xSi y层， 其中 x:y为（1-2):
(1-2)， x:y可以是 1:2、 1 : 1或 2: 1 , x:y也可以是介于 1 :2~1: 1之间任何值， 或介于 1 : 1 ~1:2之间任何值； 由于硅化镍的作用仅仅是调整势垒高度和宽度， 硅化镍的厚度 不需要太厚， 大致在 2nm到 20nm之间即可； 钛层， 所述的钛层的厚度为 50nm - 150nm, 硅化镍的下方是钛， 与常规结构一样， 此处钛的作用是增强硅化镍和 其他金属层之间的粘附性； 镍层， 所述的镍层的厚度为 100nm -300nm， 钛的下 方是镍， 此处镍的作用是防止封装过程中银扩散到硅表面； 银层， 所述的银层 的厚度为 500nm -2000nm， 镍的下方是银， 银的作用是导电层， 在封装吋使芯片 和焊料之间的连接电阻尽可能地小； 较之于钛， Ni xSi y具有相对较低的功函数， 因此， 硅化镍与硅接触后， 形成的势垒高度相对较低， 且势垒宽度相对较窄， 由于这样的势垒特性， 硅化镍与硅接触得到的接触电阻较之于常规结构更低， 因此能够使功率半导体芯片具有更低的导通损耗。
[0005] 一种功率半导体芯片背面金属结构的制备方法， 包括如下步骤：
[0006] 1 ) 将晶圆减薄至指定厚度 （例如 200um) ， 除去芯片背面的硅表面的氧化层
2) 在芯片背面依次沉积四层： 第一层为镍， 所述的镍的厚度为 2nm-20nm, 其 作用是随后与硅反应生成硅化镍， 调整势垒高度， 因此这一层镍的厚度不需要 太厚； 第二层为钛， 钛的厚度为 lOOnm左右， 优选为 50nm -150nm; 第三层为镍 , 第二层镍的厚度为 200nm左右， 优选厚度为 lOOnm -300nm; 第四层为银， 银的 厚度为 lOOOnm左右， 优选 500nm -2000nm; 沉积方法可以是蒸发、 溅射或电镀， 其中， 蒸发是优选的淀积方法， 因为可以在设备的腔体内设置不同金属对应的 坩埚， 按照顺序依次蒸发所需的金属材料， 并且蒸发设备可以一次处理大量的 晶圆。
[0008] 3) 将硅片进行高温合金，使得第一层镍与硅反应： 将步骤 1中淀积好的芯片加热 到 280-800摄氏度， 加热同时通入氮气或者氮气与氢气的组合， 第一层镍与硅反 应 5min-lh， 生成 Ni xSi y。
[0009] 进一步的， 步骤 3为： 将步骤 3中淀积好的芯片加热到 400摄氏度， 同吋通入氮 气或者氮气与氢气的组合， 沉积的第一层镍与硅的反应比例为 1:1， 反应 5min-lh
, 生成 NiSi。
[0010] 进一步的， 步骤 3为： 将步骤 1中淀积好的芯片加热到 280摄氏度， 加热同时通 入氮气或者氮气与氢气的组合， 沉积的第一层镍与硅的反应比例为 2:1 , 反应 5mi n-lh, 生成 Ni 2Si。
[0011] 进一步的， 步骤 3为： 将步骤 1中淀积好的芯片加热到 800摄氏度， 加热同时通 入氮气或者氮气与氢气的组合
, 沉积的第一层镍与硅的反应比例为 1:2, 反应 5min-lh, 生成 NiSi 2。
发明的有益效果
有益效果
[0012] 本发明的有益效果在于， 本发明提供的功率半导体芯片的背面金属结构， 较之 于常规的钛 /镍 /银背金属结构， 其寄生电阻更小， 有利于降低功率半导体芯片的 导通损耗。
对附图的简要说明
附图说明
[0013] 图 1为常规的功率半导体芯片的背金属结构；
[0014] 图 2为常规的功率半导体芯片的背金属结构对应的接触位置的能带图；
[0015] 图 3为本发明提供的功率半导体芯片的背面金属结构， 所述的金属结构自芯片 背面与硅接触的位置开始依次为： Ni xSi y层， 钛层， 镍层， 银层；
[0016] 图 4为本发明提供的功率半导体芯片的背面金属结构对应的接触位置的能带图 发明实施例 本发明的实施方式
[0017] 实施例 1
[0018] 如图 3所示， 本发明提供一种新的功率半导体芯片的背面金属结构， 所述的金 属结构自芯片背面 （Si) 开始依次为： Ni xSi y层 （厚度为 15nm) ， 钛层 （厚度 为 lOOnm) ， 镍层 （厚度为 200nm) , 银层 （厚度为 lOOOnm) ； 硅化镍 （Ni xSi y ) 的作用是降低金属与硅之间的接触电阻， 硅化镍 （NkSiy) 中， 镍与硅的原子 比例 (x:y)可以为 1:2、 1: 1或 2: 1。 较之于钛， 硅化镍具有相对较低的功函数， 因此 ， 硅化镍与硅接触后， 形成的势垒高度相对较低， 且势垒宽度相对较窄， 如图 4 所示， 由于这样的势垒特性， 硅化镍与硅接触得到的接触电阻较之于常规结构 更低， 因此能够使功率半导体芯片具有更低的导通损耗。 由于硅化镍的作用仅 仅是调整势垒高度和宽度， 硅化镍的厚度不需要太厚， 大致在 2nm到 20nm之间 即可； 硅化镍的下方是钛， 与常规结构一样， 此处钛的作用是增强硅化镍和其 他金属层之间的粘附性； 钛的下方是镍， 此处镍的作用是防止封装过程中银扩 散到硅表面； 镍的下方是银， 银的作用是导电层， 在封装时使芯片和焊料之间 的连接电阻尽可能地小。
[0019] 实施例 2
[0020] 本发明还提供一种功率半导体芯片背面金属结构的制备方法， 包括如下步骤：
[0021] 1 ) 将晶圆减薄 200um, 除去芯片背面的硅表面的氧化层；
[0022] 2) 在芯片背面采用蒸发的方式依次沉积四层： 第一层为镍， 所述的镍的厚度 为 lOnm; 第二层为钛， 所述的钛的厚度为 lOOnm; 第三层为镍， 所述的镍的厚 度为 200nm; 第四层为银， 所述的银的厚度为 lOOOnm;
[0023] 3) 将硅片进行高温合金， 使得第一层镍与硅反应： 将步骤 1中淀积好的芯片放 入蒸发设备中， 加热到 400摄氏度， 同时通入氮气， 反应 lh , 生成 NiSi。
[0024] 最终得到的金属结构依次为： NiSi层， lOnm左右； 钛层， 所述的钛层的厚度为 lOOnm; 镍层， 所述的镍层的厚度为 200nm; 银层， 所述的银层的厚度为 lOOOnm
, 经实验验证， 在 cy=l:l的条件下 本发明所提供的背金属结构比常规结构接 触电阻可以降低 12 mQ，mm 2。
[0025] 实施例 3 [0026] 本发明还提供一种功率半导体芯片背面金属结构的制备方法， 包括如下步骤:
[0027] 1 ) 将晶圆减薄至 200um， 除去芯片背面的硅表面的氧化层；
[0028] 2) 釆用溅射的方法在芯片背面依次沉积四层： 第一层为镍， 所述的镍的厚度 为 20nm; 第二层为钛， 所述的钛的厚度为 90nm; 第三层为镍， 所述的镍的厚度 为 210nm; 第四层为银， 所述的银的厚度为 900mn;
[0029] 3) 将硅片进行高温合金，使得第一层镍与硅反应： 将步骤 1中淀积好的芯片于溅 射系统中加热至 280摄氏度， 加热同吋通入氮气与氢气的组合反应 40min， 生成 N i 2Si。
[0030] 最终得到的金属结构依次为： Ni 2Si层， 20nm左右； 钛层， 所述的钛层的厚度 为 90nm; 镍层， 所述的镍层的厚度为 210nm; 银层， 所述的银层的厚度为 900nm , 经实验验证， 在 y=2:l的条件下 本发明所提供的背金属结构比常规结构接 触电阻可以降低 11 mQ*mm 2。
[0031] 实施例 4
[0032] 本发明还提供一种功率半导体芯片背面金属结构的制备方法， 包括如下步骤： [0033] 1 ) 将晶圆减薄至指定厚度 （例如 200um) ， 除去芯片背面的硅表面的氧化层
[0034] 2) 釆用电镀的方法在芯片背面依次沉积四层： 第一层为镍， 所述的镍的厚度 为 5nm; 第二层为钛， 所述的钛的厚度为 l lOnm; 第三层为镍， 所述的镍的厚度 为 190nm; 第四层为银， 所述的银的厚度为 l lOOnm;
[0035] 3) 将硅片进行高温合金，使得第一层镍与硅反应： 将步骤 1中淀积好的芯片加热 到 800摄氏度， 加热同吋通入氮气或者氮气与氢气反应 lh， 生成 NiSi 2。
[0036] 最终得到的金属结构依次为： NiSi 2
层， 5nm左右； 钛层， 所述的钛层的厚度为 l lOnm; 镍层， 所述的镍层的厚度为 190nm; 银层， 所述的银层的厚度为 1100nm， 经实验验证， 在 x:y=l:2的条件下 , 本发明所提供的背金属结构比常规结构接触电阻可以降低 10 mQ-mm ^
[0037] 需要说明的是， 取决于合金温度和时间， 硅化镍中 x:y的值并不限于以上列举 的三种情况。 例如， 在 350摄氏度下进行合金， 生成的硅化镍中 x:y可以介于 1:2 和 1:1之间。 例如， 在 700摄氏度下进行合金， 生成的硅化镍中 x:y可以介于 1:1和 1:2之间。

Claims

[权利要求 1] 一种功率半导体芯片背面金属结构， 其特征在于， 所述的金属结构自 芯片背面与硅接触的位置开始依次为： Ni xSi y层， 所述的 Ni xSi y的厚 度为 2nm-20nm， 其中 x:y为（1-2):
(1-2)； 钛层， 所述的钛层的厚度为 50nm - 150nm; 镍层， 所述的镍层 的厚度为 100nm -300nm; 银层， 所述的银层的厚度为 500nm -2000nm
[权利要求 2] —种功率半导体芯片背面金属结构的制备方法， 其特征在于， 包括如 下步骤：
1) 除去芯片背面的硅表面的氧化层；
2) 在芯片背面依次沉积四层： 第一层为镍， 所述的镍的厚度为 2nm- 20nm; 第二层为钛， 所述的钛的厚度为 50nm -150nm; 第三层为镍， 所述的镍的厚度为 lOOnm
-300nm; 第四层为银， 所述的银的厚度为 500nm -2000nm;
3) 第一层镍与硅反应： 将步骤 1中淀积好的芯片加热到 280-800摄氏 度, 同吋通入氮气或者氮气与氢气的组合， 第一层镍与硅反应 5min-l h， 生成 Ni xSi y。
[权利要求 3] 如权利要求 2所述的制备方法， 其特征在于， 步骤 3为： 将步骤 1中淀 积好的芯片加热到 400摄氏度， 同时通入氮气或者氮气与氢气的组合 , 沉积的第一层镍与硅的反应比例为 1:1 , 反应 5min-lh, 生成 NiSi。
[权利要求 4] 如权利要求 2所述的制备方法， 其特征在于， 步骤 3为： 将步骤 1中淀 积好的芯片加热到 280摄氏度， 同时通入氮气或者氮气与氢气的组合 ， 沉积的第一层镍与硅的反应比例为 2:1， 反应 5min-lh, 生成 Ni 2Si。
[权利要求 5] 如权利要求 2所述的制备方法， 其特征在于， 步骤 3为： 将步骤 1中淀 积好的芯片加热到 800摄氏度， 同时通入氮气或者氮气与氢气的组合 ， 沉积的第一层镍与硅的反应比例为 1:2， 反应 5min-lh， 生成 NiSi 2。
[权利要求 6] 如权利要求 2所述的制备方法， 其特征在于， 步骤 1) 沉积方法为蒸发
、 溅射或电镀。
PCT/CN2016/083433 2016-05-26 2016-05-26 一种功率半导体芯片背面金属结构及其制备方法 WO2017201703A1 (zh)

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