WO2017194013A1 - 纠错编码方法及装置 - Google Patents

纠错编码方法及装置 Download PDF

Info

Publication number
WO2017194013A1
WO2017194013A1 PCT/CN2017/084221 CN2017084221W WO2017194013A1 WO 2017194013 A1 WO2017194013 A1 WO 2017194013A1 CN 2017084221 W CN2017084221 W CN 2017084221W WO 2017194013 A1 WO2017194013 A1 WO 2017194013A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit sequence
coding
error
check
code
Prior art date
Application number
PCT/CN2017/084221
Other languages
English (en)
French (fr)
Inventor
许进
徐俊
李立广
陈泽为
徐晓梅
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2017194013A1 publication Critical patent/WO2017194013A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Definitions

  • the present invention relates to the field of communications, and in particular to an error correction coding method and apparatus.
  • the digital communication system usually includes a source, a source encoder, a channel coder and a modulator, and the receiving end usually includes a demodulator, a channel decoder, a source decoder and a sink, as shown in FIG. Shown is a schematic diagram of a digital communication system according to the related art.
  • the channel coder is used to introduce information bits into the information bits according to certain rules so that the receiving channel decoder can correct the errors occurring when the information is transmitted on the channel to some extent.
  • Common channel coding methods include bit-OR coding, block code, BCH code (multi-level, cyclic, error correction, variable length digital coding for correcting multiple random error modes), Reed-Solomon code (RS code), fountain code, low density parity check code, turbo (Turbo) code, polarization code, convolutional code, etc.; unwanted channel coding methods usually have different application scenarios, and also have different coding performance. Sometimes, in order to improve the performance of the channel coding and decoding, special optimization processing is required for these channel coding methods.
  • Ultra-reliable applications generally include application scenarios such as vehicle networking and industrial control that require high reliability for data transmission.
  • Ultra-reliable applications generally have two characteristics: 1) the error rate of data blocks for ultra-reliable data transmission must be 4 to 5 orders of magnitude lower than the data block error rate for normal data transmission; 2) the length of the normal data block is not long, generally Below 1000 bits, it is difficult to obtain sufficient coding gain by the conventional channel coding method.
  • the Low Density Parity Check Code (LDPC) code is a linear block code based on a sparse check matrix. It is the sparsity of its check matrix that can achieve low complexity code. Thereby, the LDPC code is put into practical use.
  • the aforementioned Gallager code is a regular LDPC code (regular ldpcc), and Luby And the Mitzenmacher et al. promoted the Gallager code and proposed a non-regular LDPC code (irregular ldpcc).
  • LDPC codes have many decoding algorithms. Among them, Message Passing algorithm or Belief Propagation algorithm (BP algorithm) is the mainstream and basic algorithm of LDPC codes. At present, there are many improved effective decoding algorithms. .
  • the graphical representation of the LDPC parity check matrix is a bipartite graph.
  • An M*N parity check matrix H defines a constraint that each codeword having N bits satisfies M parity sets.
  • a bipartite graph includes N variable nodes and M parity nodes.
  • the bipartite graph there is no connection between any nodes of the same class, and the total number of edges in the bipartite graph is equal to the number of non-zero elements in the check matrix.
  • the parity check matrix H of this LDPC code be a (M ⁇ z) ⁇ (N ⁇ z) matrix, which is composed of M ⁇ N block matrices, each of which is a basic permutation of z ⁇ z.
  • the matrix is different powers and the basic permutation matrix is a unit matrix, they are cyclic shifting matrices of the unit array (the default is right shift).
  • the power of the unit matrix can be represented by 0, and the matrix is generally represented by -1.
  • an M ⁇ N power matrix H b is obtained .
  • H b is the basic matrix of H
  • H is called the extension matrix of H b .
  • z code length / number of columns N of the basic matrix, called the spreading factor.
  • the encoder of the LDPC code is uniquely generated by the base matrix H b , the spreading factor z and the selected basic permutation matrix.
  • the basic check matrix of the LDPC code can also be written as follows:
  • Kb is a positive integer
  • the system bit and the check bit portion of the basic check matrix may have the same or different column weights.
  • Column weight refers to the number of non-zero elements (or non-1 elements) in the column.
  • the embodiment of the invention provides an error correction coding method and device, so as to at least solve the problem of insufficient error correction capability of the error correction coding scheme in the related art.
  • an error correction coding method including: segmenting a first bit error-correction-coded bit sequence; and performing error checking on each of the segmented partial or all bit-sequence segments Encoding, each bit sequence segment encoded by the error check is formed into a second bit sequence to be error-correction-coded, and the second error-correction-coded bit sequence is subjected to forward error correction coding to generate a bit sequence to be transmitted; The bit sequence to be transmitted.
  • the first error correction coded bit sequence includes at least one of the following: an information bit sequence; and a bit sequence after the error check coding is performed on the information bit sequence as a whole.
  • the error check coding includes at least one of the following: a cyclic redundancy check code, a BCH code code, an RS code code, and a parity code.
  • segmenting the bit sequence to be error-correction-coded includes: uniformly or non-uniformly dividing the bit sequence to be encoded according to a preset number of bit sequence segments or a length of the bit sequence segment. segment.
  • each bit sequence segment encoded by the error check is formed into a second bit sequence to be error-correction-coded, and the second error-correction-coded bit sequence is forward-corrected and encoded to generate a to-be-sent.
  • the bit sequence includes: performing forward error correction coding on each information bit sequence consisting of bits in corresponding positions in each bit sequence segment after error check coding, to obtain respective check bit sequences; using each check bit sequence The bits in the corresponding position constitute a new bit sequence segment; each bit sequence segment encoded by the original error check is combined with the new bit sequence segment into a third bit sequence to be error-correction encoded, and the third bit is The error correction coded bit sequence is subjected to forward error correction coding to generate a bit sequence to be transmitted.
  • the forward error correction coding includes at least one of the following: bit exclusive OR coding, block code coding, BCH code coding, RS code coding, fountain code coding, and low density parity check.
  • Code coding Turbo code coding, polarization code coding, convolutional code coding.
  • the forward error correction coding method is low-density parity check code coding
  • respectively performing error check coding on the segmented partial bit sequence segments includes: after segmentation In the bit sequence segment, the systematic bit portion of the basic check matrix of the low density parity check code is selected to be a bit sequence segment that is larger than a preset threshold; and the selected bit sequence segment is subjected to error check coding.
  • an error correction encoding apparatus comprising: a segmentation module configured to segment a first bit sequence to be error-correction encoded; and an error check coding module set to be The segmented partial or all bit sequence segments are respectively subjected to error check coding; the forward error correction coding module is configured to form each bit sequence segment encoded by the error check into a second bit sequence to be error-correction coded, and And performing a forward error correction coding on the second error correction coded bit sequence to generate a bit sequence to be transmitted; and sending, configured to send the to-be-transmitted bit sequence.
  • the segmentation module is further configured to perform uniform or non-uniform segmentation on the bit sequence to be encoded according to the preset number of bit sequence segments or the length of the bit sequence segment.
  • the forward error correction coding module is further configured to: perform forward error correction coding on each information bit sequence consisting of bits in corresponding positions in each bit sequence segment after error check coding, Obtaining respective check bit sequences; forming new bit sequence segments by using bits in corresponding positions in each check bit sequence; synthesizing the bit sequence fragments encoded by the original error check with the new bit sequence segments The bit sequence to be error-corrected, and The third error correction coded bit sequence is subjected to forward error correction coding to generate a bit sequence to be transmitted.
  • the error check coding module when the forward error correction coding method is low density parity check code coding, includes: a selection unit, which is set to be selected in the segmented bit sequence segment.
  • the systematic bit portion of the basic check matrix of the low density parity check code lists a bit sequence segment that is larger than a preset threshold; the error check coding unit is configured to perform error check coding on the selected bit sequence segment.
  • a storage medium is also provided.
  • the storage medium is configured to store program code for performing the following steps: segmenting the first bit error-correction-coded bit sequence; performing error-correction coding on the segmented partial or all bit-sequence segments respectively; And verifying the encoded bit sequence segments to form a second bit error correction coded bit sequence, and performing forward error correction coding on the second error correction coded bit sequence to generate a to-be-transmitted bit sequence; Bit sequence.
  • a storage medium comprising a stored program, wherein the program is executed to perform the method of any of the above.
  • a processor for running a program wherein the program is executed to perform the method of any of the above.
  • the error correction coded bit sequence segment is forward-corrected.
  • the decoder can determine, according to the error check code of each bit sequence segment, that the current bit sequence segment is in the decoding process No is correct, if it is correct, the decoder regards the current bit sequence segment as a sure bit, and does not need to continue decoding the current bit sequence, which is equivalent to shortening the code decoding and reducing the original code word.
  • the code rate can improve the decoding performance and solve the problem of insufficient error correction capability of the error correction coding scheme in the related art.
  • FIG. 1 is a schematic diagram of a digital communication system according to the related art
  • FIG. 2 is a flowchart of an error correction encoding method according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing the structure of an error correction encoding apparatus according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an error correction encoding process according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram of an error correction coding process according to Embodiment 2 of the present invention.
  • the embodiment of the present invention proposes a new error correction coding method, which increases the manner of segment coding of the bit sequence to be encoded, further enhances the error correction capability of the codeword, and improves the method.
  • the gain of the code is a new error correction coding method, which increases the manner of segment coding of the bit sequence to be encoded, further enhances the error correction capability of the codeword, and improves the method. The gain of the code.
  • FIG. 2 is a flowchart of an error correction coding method according to an embodiment of the present invention. As shown in FIG. 2, the method includes the following steps:
  • Step S202 segmenting the first bit sequence to be error-correction encoded
  • Step S204 performing error check coding on the segmented partial or all bit sequence segments respectively;
  • Step S206 the bit sequence segments encoded by the error check are combined into a second bit sequence to be error-correction-coded, and the second error-correction-coded bit sequence is subjected to forward error correction coding to generate a bit sequence to be transmitted.
  • Step S208 transmitting the bit sequence to be transmitted.
  • the bit sequence to be error-corrected encoded is segmented by the above steps, and the segmented bit sequence segments are respectively subjected to error check coding, and then the error-coded bit sequence segment is forwarded.
  • Error correction coding and generating a bit sequence to be transmitted so that the decoder can judge whether the current bit sequence segment is correct according to the error check code of each bit sequence segment in the decoding process, and if correct, the decoder
  • the current bit sequence segment is regarded as a sure bit, and there is no need to continue decoding the current bit sequence, which is equivalent to shortening the code decoding, reducing the code rate of the original code word, improving the decoding performance, and solving the related technology.
  • the error correction capability of the error correction coding scheme is insufficient.
  • the error correction coded bit sequence includes a sequence of information bits or a bit sequence after performing overall error check coding on the information bit sequence; wherein the error check code may be Any code having an error check function includes, but is not limited to, cyclic redundancy check code, BCH code code, Reed-Solomon code (RS code) code, and parity code.
  • the error check coding in step S204 may also be any code having an error check function, including but not limited to cyclic redundancy check code, BCH code code, Reed-Solomon code (RS code) coding, Parity encoding.
  • the step of performing error correction coding on the bit sequence may be: performing the bit sequence to be coded according to the preset number of bit sequence segments or the length of the bit sequence segment. Uniform segmentation or non-uniform segmentation.
  • the method may further include:
  • Step S2062 Perform forward error correction coding on each information bit sequence composed of bits in the corresponding position in each bit sequence segment after the error check coding, to obtain respective check bits.
  • the forward error correction coding refers to an code having an error correction function, including but not limited to bit-OR coding, block code coding, BCH code coding, Reed-Solomon code (RS code) coding, fountain code Coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding;
  • Step S2064 the bits in the corresponding positions in each check bit sequence constitute a new bit sequence segment
  • Step S2066 the bit sequence segment encoded by the original error check is combined with the new bit sequence segment in step S2064 to form a new bit sequence to be error-correction-coded, and the new bit-code to be error-corrected is forwarded.
  • Error correction coding generating a sequence of bits to be transmitted.
  • the forward error correction coding may refer to an encoding with an error correction function, including but not limited to bit-OR coding, block code coding, BCH code coding, Reed-Solomon Code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding.
  • error correction function including but not limited to bit-OR coding, block code coding, BCH code coding, Reed-Solomon Code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding.
  • the segmented partial bit sequence segments may be separately subjected to error check coding, for example, according to low density.
  • the systematic bit portion of the parity check matrix of the parity check is selected to select a partial bit sequence segment for error check coding.
  • the system bit portion of the basic check matrix of the low density parity check code may be selected to be a bit sequence segment that is greater than a preset threshold; and the selected bit sequence segment is selected. Error check code.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
  • an error correction coding apparatus is further provided, which is used to implement the foregoing embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 3 is a structural block diagram of an error correction encoding apparatus according to an embodiment of the present invention.
  • the apparatus includes: a segmentation module 32 configured to segment a bit sequence of the first error correction coded;
  • the verification coding module 34 is configured to perform error check coding on some or all of the bit sequence segments segmented by the segmentation module 32.
  • the forward error correction coding module 36 is configured to perform error correction on the error check coding module 34.
  • the encoded bit sequence segments constitute a second bit error correction coded bit sequence, and the second error correction coded bit sequence is subjected to forward error correction coding to generate a to-be-transmitted bit sequence;
  • the sending module 38 is configured to The to-be-transmitted bit sequence generated by the forward error correction coding module 36 is transmitted.
  • the segmentation module 32 may be further configured to perform uniform segmentation or non-uniform segmentation on the bit sequence to be encoded according to the preset number of bit sequence segments or the length of the bit sequence segment.
  • the forward error correction coding module 36 may be further configured to perform forward error correction on each information bit sequence consisting of bits in corresponding positions in each bit sequence segment encoded by the error check. Encoding to obtain respective check bit sequences; using each check bit The bits in the corresponding positions in the sequence constitute a new bit sequence segment; each bit sequence segment encoded by the original error check and the new bit sequence segment are combined into a third bit sequence to be error-correction encoded, and the The three-in-one error correction coded bit sequence performs forward error correction coding to generate a bit sequence to be transmitted.
  • the error check coding module may include: a selection unit, configured to be in the segmented bit sequence segment, The system bit portion of the basic check matrix of the low density parity check code is selected to be a bit sequence segment that is larger than a preset threshold; and the error check coding unit is configured to perform error check coding on the selected bit sequence segment.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are in any combination.
  • the forms are located in different processors.
  • a method for error correction coding in a data transmission process comprising:
  • the sender side segments the error correction coded bit sequence
  • bit sequence segment of the error check coding is formed into a new bit sequence to be error-corrected coded, and the new error correction coded bit sequence is forward error-correction coded to generate a bit sequence to be transmitted;
  • the transmitting end sends the to-be-transmitted bit sequence.
  • the bit error correction coded bit sequence includes an information bit sequence or a bit sequence after performing overall error check coding on the information bit sequence; wherein the error check code refers to any error correction Encoding of the function, including but not limited to cyclic redundancy check coding, BCH code coding, Reed-Solomon code (RS code) coding, parity coding;
  • the error check code refers to any error correction Encoding of the function, including but not limited to cyclic redundancy check coding, BCH code coding, Reed-Solomon code (RS code) coding, parity coding;
  • the segmentation of the bit sequence to be error-corrected refers to uniformly segmenting the bit sequence to be encoded according to the number of preset bit sequence segments or the length of the bit sequence segment or Non-uniform segmentation;
  • the error check coding refers to any code having an error check function, including but not limited to cyclic redundancy check code, BCH code code, Reed-Solomon code (RS code) coding. , parity coding;
  • the method may further include:
  • Step c1 Perform forward error correction coding on each information bit sequence composed of bits in corresponding positions in each bit sequence segment after error check coding, to obtain respective check bit sequences; wherein the forward error correction is performed.
  • Encoding refers to an encoding with error correction function, including but not limited to bit XOR coding, block code coding, BCH code coding, Reed-Solomon code (RS code) coding, fountain code coding, low density parity check code coding. , Turbo code coding, Polar code coding, convolutional code coding;
  • Step c2 the bits in the corresponding positions in each check bit sequence form a new bit sequence segment
  • Step c3 Combining each bit sequence segment encoded by the original error check with the new bit sequence segment in step c2 to form a new bit sequence to be error-correction-coded, and forwarding the new bit-code to be error-corrected Error correction coding, generating a bit sequence to be transmitted;
  • the forward error correction coding refers to an encoding with an error correction function, including but not limited to bit XOR coding, block code coding, BCH code coding, Reed-Solomon code (RS code). Coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding;
  • Kb is a positive integer
  • Kb Nb-Mb
  • Nb is the basic check of the low-density parity check code
  • Mb is the number of rows of the basic matrix of the low density parity check code
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the error check coding includes but is not limited to cyclic redundancy check coding, BCH code coding, Reed-Solomon code (RS code) coding, parity coding
  • RS code Reed-Solomon code
  • the error check coding mode is a Cyclic Redundancy Check (CRC) code.
  • FIG. 4 is a schematic diagram of an error correction encoding process according to Embodiment 1 of the present invention. As shown in FIG. 4, the transmitting end processes the encoded bit sequence as follows:
  • the transmitting end segments the coded bit sequence according to the number of preset bit sequence segments or the length of the bit sequence segment.
  • the number of segments is C segment
  • the K-bit bit sequence to be encoded is evenly divided.
  • C bit sequence segments each bit sequence segment length is Bit. If K cannot be divisible by C, add it to one of the bit sequence fragments.
  • Known bits at both ends of the transceiver Indicates an up rounding operation.
  • the transmitting end performs error check coding on each bit sequence segment respectively, and K3 is a check bit generated after each bit sequence segment is subjected to error check coding, and the length of each bit sequence after error check coding is Bits;
  • the error check coding includes, but is not limited to, cyclic redundancy check coding, BCH code coding, Reed-Solomon code (RS code) coding, parity coding; in this example, each bit sequence segment is assumed
  • the error check coding mode is cyclic redundancy check (CRC) coding.
  • the transmitting end performs forward error correction coding on the encoded bit sequence to generate a bit sequence to be transmitted.
  • the forward error correction coding includes but is not limited to bit XOR coding, block code coding, BCH code coding, Reed-Solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding. , polarization code coding, convolutional code coding; in this example, it is assumed that the forward error correction coding mode of the new bit sequence to be coded is low density parity check code (LDPC) coding.
  • LDPC low density parity check code
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the error check coding includes but is not limited to cyclic redundancy check coding, BCH code coding, Reed-Solomon code (RS code) coding, parity coding
  • RS code Reed-Solomon code
  • the error check coding mode is Cyclic Redundancy Check (CRC) coding.
  • FIG. 5 is a schematic diagram of an error correction encoding process according to Embodiment 2 of the present invention. As shown in FIG. 5, the transmitting end processes the encoded bit sequence as follows:
  • the transmitting end segments the coded bit sequence according to the number of preset bit sequence segments or the length of the bit sequence segment.
  • the number of segments is C segment
  • the K-bit bit sequence to be encoded is evenly divided.
  • C bit sequence segments each bit sequence segment length is Bit. If K cannot be divisible by C, add it to one of the bit sequence fragments.
  • Known bits at both ends of the transceiver Indicates an up rounding operation.
  • the transmitting end performs error check coding on each bit sequence segment respectively, and K3 is a check bit generated after each bit sequence segment is subjected to error check coding, and the length of each bit sequence after error check coding is Bits;
  • the error check coding includes, but is not limited to, cyclic redundancy check coding, BCH code coding, Reed-Solomon code (RS code) coding, parity coding; in this example, each bit sequence segment is assumed
  • the error check coding mode is a cyclic redundancy check (CRC) check code.
  • the transmitting end performs forward error correction coding on each information bit sequence composed of bits in corresponding positions in the C bit sequence segments after the error check coding, to obtain respective check bit sequences.
  • the ith information consisting of a total of C bits
  • forward error correction coding on the bit sequence to obtain an i-th parity bit sequence wherein the length of the parity bit sequence is T bits, where i is a positive integer, and And so on, there are
  • the information sequence of length C bits is subjected to forward error correction coding, respectively.
  • the forward error correction coding includes, but is not limited to, bit exclusive OR coding, block code coding, BCH code coding, Reed-Solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, and convolutional code coding.
  • bit exclusive OR coding block code coding
  • BCH code coding Reed-Solomon code (RS code) coding
  • fountain code coding coding
  • low density parity check code coding Turbo code coding
  • Turbo code coding polarization code coding
  • convolutional code coding convolutional code coding
  • the bits at corresponding positions in each check bit sequence constitute a new bit sequence segment; for example, the jth bit of the first check bit sequence and the j th bit of the second check bit sequence, ...,
  • the jth bit of the bit sequence segment constitutes a new bit sequence segment, wherein the length of the new bit sequence is Bit, where j is a positive integer and 1 ⁇ j ⁇ T; and so on, there are a total of T new bit sequence segments.
  • the transmitting end combines the C bit sequence segments encoded by the original error check with the T new bit sequence segments to form a new error correction coded bit sequence, and the length of the new error correction coded bit sequence is Bit.
  • the transmitting end performs forward error correction coding on the new error correction coded bit sequence.
  • the forward error correction coding includes but is not limited to bit XOR coding, block code coding, BCH code coding, Reed-Solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code. Coding, Polar code coding, convolutional code coding. In this example, it is assumed to be a Polar code.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • CRC cyclic redundancy check
  • the sender treats the encoded bit sequence as follows:
  • the transmitting end segments the coded bit sequence according to the number of preset bit sequence segments or the length of the bit sequence segment.
  • the number of segments is Kb segment, where Kb is a low density parity check code (LDPC).
  • LDPC low density parity check code
  • the number of columns in the basic matrix H b minus the number of rows, the K-bit bit sequence to be encoded is evenly divided into Kb bit sequence segments, and the length of each bit sequence segment is Bit. If K cannot be divisible by Kb, add it to one of the bit sequence fragments.
  • Known bits at both ends of the transceiver Indicates an up rounding operation.
  • the transmitting end performs error check coding on each bit sequence segment respectively, and K3 is a check bit generated after each bit sequence segment is subjected to error check coding, and the length of each bit sequence after error check coding is Bit; in this example, it is assumed that the error check coding mode of each bit sequence segment is cyclic redundancy check (CRC) coding.
  • CRC cyclic redundancy check
  • the transmitting end performs forward error correction coding on the encoded bit sequence to generate a bit sequence to be transmitted.
  • the forward error correction coding mode of the new bit sequence to be encoded is Low Density Parity Check (LDPC) coding.
  • LDPC Low Density Parity Check
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • CRC cyclic redundancy check
  • the sender treats the encoded bit sequence as follows:
  • the transmitting end segments the coded bit sequence according to the number of preset bit sequence segments or the length of the bit sequence segment.
  • E is a positive integer
  • E z-K3
  • K3 is the redundant bit length after the error check encoding of each bit sequence segment is intended.
  • the transmitting end performs error check coding on each bit sequence segment respectively, and K3 is a check bit generated after each bit sequence segment is subjected to error check coding, and the length of each bit sequence after error check coding is z bits;
  • the error check coding mode of each bit sequence segment is cyclic redundancy check (CRC) coding.
  • the transmitting end performs forward error correction coding on the coded bit sequence to generate a bit sequence to be transmitted.
  • the forward error correction coding mode of the new bit sequence to be encoded is Low Density Parity Check (LDPC) coding.
  • LDPC Low Density Parity Check
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • CRC cyclic redundancy check
  • the sender treats the encoded bit sequence as follows:
  • the transmitting end segments the coded bit sequence according to the number of preset bit sequence segments or the length of the bit sequence segment.
  • the number of segments is Kb segment, where Kb is a low density parity check code (LDPC).
  • LDPC low density parity check code
  • the number of columns in the basic matrix H b minus the number of rows, the K-bit bit sequence to be encoded is non-uniformly divided into Kb bit sequence segments, and only the partial bit sequence segments therein are subjected to error check coding;
  • each bit sequence segment has a length of z bits
  • W2 second class bit sequence segments wherein the second type bit sequence segment
  • Kb W1+W2;
  • the W2 second type bit sequence segments correspond to a column with a heavier system bit portion of a base check matrix of the low density parity check code.
  • the column weight of the W2 column is greater than or equal to a preset threshold;
  • the second type of bit sequence segment corresponds to W2 bit sequence segments referenced as I in the Kb bit sequence segments; the remaining bit sequence segments are the W1 first class bit sequence segments;
  • Each bit sequence segment of the W2 second type bit sequence segments is separately subjected to error check coding, and K3 error check bits are added after each second type bit sequence segment.
  • the error check coding mode of each bit sequence segment is cyclic redundancy check (CRC) coding.
  • the transmitting end forms the bit sequence segment of the error check coding into a new bit sequence to be encoded, and the length of the new band coded bit sequence is z*Kb bits.
  • the transmitting end performs forward error correction coding on the coded bit sequence to generate a bit sequence to be transmitted.
  • the forward error correction coding mode of the new bit sequence to be encoded is Low Density Parity Check (LDPC) coding.
  • LDPC Low Density Parity Check
  • the beneficial effects of the solution provided by this embodiment are mainly represented by: when the channel decoder of the receiving end decodes the codeword that performs error correction coding in this embodiment, the decoder can be based on each bit in the decoding process.
  • the error check code of the sequence segment is used to determine whether the current bit sequence segment is correct. If it is correct, the decoder regards the current bit sequence segment as a sure bit and does not need to continue decoding the current bit sequence. Equivalent to shortening code decoding, reducing the original code word The code rate can improve the decoding performance.
  • the present embodiment also proposes a forward error correction for the corresponding position bits between the bit sequence segments, which is equivalent to adding a first-level inner code protection, thereby improving the The performance of the final decoding.
  • the present embodiment specifically proposes parameters for the number of bit sequence segments and the basic matrix of the low density parity check code for the low density parity check code, or the length of the bit sequence segment and the low density parity check.
  • the size of the spreading factor of the code is matched, so that the segmentation error check and the low-density parity check coding proposed in the embodiment can be perfectly combined, and the efficiency and performance of the coding and decoding can be improved.
  • the present embodiment also specifically proposes a non-uniform segmentation and partial error check method for the low-density parity check code. Only the column with the heavier column weight of the base check matrix system of the low-density parity check code is error-checked.
  • the beneficial effect is that the error check of the bit sequence segment with strong error correction capability can confirm whether the bit sequence segment has been correctly decoded as soon as possible, and the bit sequence segment that has been correctly decoded can be regarded as a sure bit, and There is no need to continue decoding the current bit sequence, which is equivalent to shortening the code decoding, reducing the code rate of the original code word, and improving the decoding performance. At the same time, since only the error check bits are added to the partial bit sequence segments, the reduction is also reduced. The overhead.
  • Embodiments of the present invention also provide a storage medium including a stored program, wherein the program described above executes the method of any of the above.
  • the foregoing storage medium may be configured to store program code for performing the following steps:
  • Step S1 segmenting the first bit sequence to be error-correction encoded
  • Step S2 performing error check coding on the segmented partial or all bit sequence segments respectively;
  • Step S3 the bit sequence segments encoded by the error check are combined into a second bit sequence to be error-correction-coded, and the second error-correction-coded bit sequence is subjected to forward error correction coding to generate a bit sequence to be transmitted.
  • step S4 the bit sequence to be transmitted is transmitted.
  • the foregoing storage medium may include, but is not limited to: a USB flash drive, only A medium that can store program code, such as a read-only memory (ROM), a random access memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • removable hard disk such as a hard disk, a magnetic disk, or an optical disk.
  • Embodiments of the present invention also provide a processor for running a program, wherein the program is executed to perform the steps of any of the above methods.
  • the foregoing program is used to perform the following steps:
  • Step S1 segmenting the first bit sequence to be error-correction encoded
  • Step S2 performing error check coding on the segmented partial or all bit sequence segments respectively;
  • Step S3 the bit sequence segments encoded by the error check are combined into a second bit sequence to be error-correction-coded, and the second error-correction-coded bit sequence is subjected to forward error correction coding to generate a bit sequence to be transmitted.
  • step S4 the bit sequence to be transmitted is transmitted.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the bit sequence to be error-corrected coded is segmented, and the segmented bit sequence segment is separately subjected to error check coding, and then the bit after the error check is encoded.
  • the sequence segment performs forward error correction coding and generates a bit sequence to be transmitted, so that the decoder can determine whether the current bit sequence segment is correct according to the error check code of each bit sequence segment in the decoding process, if it is correct.
  • the decoder regards the current bit sequence segment as a sure bit, and does not need to continue decoding the current bit sequence, which is equivalent to shortening the code decoding, reducing the code rate of the original code word, and improving the decoding performance.
  • the problem of insufficient error correction capability of the error correction coding scheme in the related art is solved.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

一种纠错编码方法及装置，其中，该方法包括：对第一待纠错编码的比特序列进行分段（S202）；对分段后的部分或全部比特序列片段，分别进行差错校验编码（S204）；将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列（S206）；发送所述待发送比特序列（S208）。该方法解决了相关技术中的纠错编码方案纠错能力不足的问题，降低了原码字的码率，可以提高译码性能。

Description

纠错编码方法及装置 技术领域
本发明涉及通信领域，具体而言，涉及一种纠错编码方法及装置。
背景技术
数字通信系统通常发射端通常包括信源、信源编码器、信道编码器和调制器等部分，接收端通常包括解调器、信道译码器、信源译码器和信宿，如图1所示，为根据相关技术的数字通信系统的示意图。信道编码器用于给信息比特按照一定的规则引入冗余信息以便接收端信道译码器能够在一定程度上纠正信息在信道上传输时发生的误码。
常见的信道编码方法包括比特异或编码、分组码、BCH码(该BCH码是用于校正多个随机错误模式的多级、循环、错误校正、变长数字编码)、里德-所罗门码(RS码)、喷泉码、低密度奇偶校验码、涡轮(Turbo)码、极化码、卷积码等；不要的信道编码方法通常有不同的适用场景，也有不同的编译码性能。有时为了提高信道编译码的性能需要对这些信道编码方法进行特殊的优化处理。
一个比较典型的需要提升信道编译码性能的应用场景是移动通信中的超可靠应用。超可靠应用一般包括车联网，工业控制等对数据传输可靠性要求较高的应用场景。超可靠应用一般有两个特点：1)超可靠数据传输的数据块的错误比率必须比普通数据传输的数据块错误率低4到5个数量级；2)通常数据块的长度都不长，一般在1000比特以下，传统的信道编码方法很难获得足够的编码增益。
低密度奇偶校验(Low Density Parity Check Code，简称LDPC)码是一种基于稀疏校验矩阵的线性分组码，正是利用它的校验矩阵的稀疏性，才能实现低复杂度的编译码，从而使得LDPC码走向实用化。前面提到的加拉格尔(Gallager)码是一种正则的LDPC码(regular ldpcc)，而Luby 和Mitzenmacher等人对Gallager码进行了推广，提出非正则的LDPC码(irregular ldpcc)。LDPC码具有很多译码算法，其中，信息传递算法(Message Passing algorithm)或者置信度传播算法(Belief Propagation algorithm，BP算法)是LDPC码的主流和基础算法，目前出现了很多改进的有效译码算法。
LDPC奇偶校验矩阵的图形表示形式是二分图。二分图和校验矩阵之间具有一一对应的关系，一个M*N的奇偶校验矩阵H定义了每个具有N比特的码字满足M个奇偶校验集的约束。一个二分图包括N个变量节点和M个奇偶校验节点。当第m个校验涉及到第n个比特位，即H中第m行第n列的元素Hm，n＝1时，将有一根连线连接校验节点m和变量节点n。二分图中，任何同一类的节点之间都不会有连接，并且二分图中的总边数和校验矩阵中非零元素的个数相等。
一类特殊LDPC码由于具有结构化的特征，逐渐成为主流应用。设这种LDPC码的奇偶校验矩阵H为(M×z)×(N×z)矩阵，它是由M×N个分块矩阵构成，每个分块矩阵都是z×z的基本置换矩阵的不同幂次，基本置换矩阵为单位阵时，它们都是单位阵的循环移位矩阵(文中默认为右移)。具有如下的形式：
Figure PCTCN2017084221-appb-000001
如果
Figure PCTCN2017084221-appb-000002
有
Figure PCTCN2017084221-appb-000003
如果
Figure PCTCN2017084221-appb-000004
是大于或者等于0的整数，定义
Figure PCTCN2017084221-appb-000005
在这里P是一个z×z的标准置换矩阵，如下所示：
Figure PCTCN2017084221-appb-000006
通过这样的幂次
Figure PCTCN2017084221-appb-000007
就可以唯一标识每一个分块矩阵，单位矩阵的幂次可用0表示，矩阵一般用-1来表示。这样，如果将H的每个分块矩阵都用它的幂次代替，就得到一个M×N的幂次矩阵Hb。这里，定义Hb是H的基础矩阵，H称为Hb的扩展矩阵。在实际编码时，z＝码长/基础矩阵的列数N，称为扩展因子。
例如，矩阵
Figure PCTCN2017084221-appb-000008
可以用下面的参数z和一个2×4的基础矩阵Hb扩展得到：
z＝3和
Figure PCTCN2017084221-appb-000009
因此，也可以说LDPC码的编码器是由基础矩阵Hb，扩展因子z及所选择的基本置换矩阵唯一生成的。
LDPC码的基础校验矩阵还可以写成如下形式：
Figure PCTCN2017084221-appb-000010
其中，
Figure PCTCN2017084221-appb-000011
是基础校验矩阵的系统位部分，
Figure PCTCN2017084221-appb-000012
有Kb列，
Figure PCTCN2017084221-appb-000013
是基础校验矩阵的校验位部分，
Figure PCTCN2017084221-appb-000014
有Mb列。其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；其中，在基础校验矩阵的系统位和校验位部分，各列的列重量可以相同也可以不同。列重量是指该列中非零元素(或者非-1元素)的个数。
针对相关技术中的纠错编码方案纠错能力不足的问题，目前尚未给出 解决方案。
发明内容
本发明实施例提供了一种纠错编码方法及装置，以至少解决相关技术中的纠错编码方案纠错能力不足的问题。
根据本发明的一个实施例，提供了一种纠错编码方法，包括：对第一待纠错编码的比特序列进行分段；对分段后的部分或全部比特序列片段，分别进行差错校验编码；将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；发送所述待发送比特序列。
本发明实施例中，所述第一待纠错编码比特序列包括以下至少之一：信息比特序列；对所述信息比特序列整体进行差错校验编码后的比特序列。
本发明实施例中，所述差错校验编码包括以下至少之一：循环冗余校验编码、BCH码编码、RS码编码、奇偶校验编码。
本发明实施例中，对第一待纠错编码的比特序列进行分段包括：根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀或非均匀分段。
本发明实施例中，将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列包括：先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列；使用各校验比特序列中对应位置上的比特组成新的比特序列片段；将原差错校验编码后的各比特序列片段与所述新的比特序列片段合成第三待纠错编码的比特序列，并对所述第三待纠错编码比特序列进行前向纠错编码，生成待发送比特序列。
本发明实施例中，所述前向纠错编码包括以下至少之一：比特异或编码、分组码编码、BCH码编码、RS码编码、喷泉码编码、低密度奇偶校 验码编码、Turbo码编码、极化码编码、卷积码编码。
本发明实施例中，在所述前向纠错编码方法为低密度奇偶校验码编码的情况下，对第一待纠错编码的比特序列进行分段包括：对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；或者，按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是对所述分段后的部分或全部比特序列片段，分别进行差错校验编码后的冗余比特长度。
本发明实施例中，在所述前向纠错编码方法为低密度奇偶校验码编码的情况下，对分段后的部分比特序列片段，分别进行差错校验编码包括：在分段后的比特序列片段中，选出低密度奇偶校验码的基础校验矩阵的系统位部分列重大于预设阈值的比特序列片段；对选出的比特序列片段进行差错校验编码。
根据本发明的另一实施例，还提供了一种纠错编码装置，包括：分段模块，设置为对第一待纠错编码的比特序列进行分段；差错校验编码模块，设置为对分段后的部分或全部比特序列片段，分别进行差错校验编码；前向纠错编码模块，设置为将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；发送模块，设置为发送所述待发送比特序列。
本发明实施例中，所述分段模块还设置为：根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀或非均匀分段。
本发明实施例中，所述前向纠错编码模块还设置为：先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列；使用各校验比特序列中对应位置上的比特组成新的比特序列片段；将原差错校验编码后的各比特序列片段与所述新的比特序列片段合成第三待纠错编码的比特序列，并对所 述第三待纠错编码比特序列进行前向纠错编码，生成待发送比特序列。
本发明实施例中，当所述前向纠错编码方法为低密度奇偶校验码编码时，所述分段模块还设置为：对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；或者，按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是对所述分段后的部分或全部比特序列片段，分别进行差错校验编码后的冗余比特长度。
本发明实施例中，当所述前向纠错编码方法为低密度奇偶校验码编码时，所述差错校验编码模块包括：选择单元，设置为在分段后的比特序列片段中，选出低密度奇偶校验码的基础校验矩阵的系统位部分列重大于预设阈值的比特序列片段；差错校验编码单元，设置为对选出的比特序列片段进行差错校验编码。
根据本发明的又一个实施例，还提供了一种存储介质。该存储介质设置为存储用于执行以下步骤的程序代码：对第一待纠错编码的比特序列进行分段；对分段后的部分或全部比特序列片段，分别进行差错校验编码；将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；发送所述待发送比特序列。
根据本发明的又一个实施例，还提供了一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述任一项所述的方法。
根据本发明的又一个实施例，还提供了一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述任一项所述的方法。
通过本发明，由于将待纠错编码的比特序列进行了分段，并对分段后的比特序列片段分别进行差错校验编码，再对差错校验编码后的比特序列片段进行前向纠错编码并生成待发送比特序列，从而使得译码器在译码过程中可以根据各比特序列片段的差错校验码来判断当前比特序列片段是 否是正确的，如果是正确的，译码器则将当前比特序列片段看成是确知比特，并且无需对当前比特序列继续译码，这相当于缩短码译码，降低了原码字的码率，可以提高译码性能，解决了相关技术中的纠错编码方案纠错能力不足的问题。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据相关技术的数字通信系统的示意图；
图2是根据本发明实施例的纠错编码方法的流程图；
图3是根据本发明实施例的纠错编码装置的结构框图；
图4是根据本发明实施例一的纠错编码过程的示意图；
图5是根据本发明实施例二的纠错编码过程的示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
针对超可靠应用的特点，本发明实施例提出了一种新的纠错编码方法，该方法增加了对待编码的比特序列进行分段编码的方式，进一步增强了码字的纠错能力，提高了编码的增益。
在本实施例中，提供了一种纠错编码方法，图2是根据本发明实施例的纠错编码方法的流程图，如图2所示，该方法包括如下步骤：
步骤S202，对第一待纠错编码的比特序列进行分段；
步骤S204，对分段后的部分或全部比特序列片段，分别进行差错校验编码；
步骤S206，将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
步骤S208，发送所述待发送比特序列。
本实施例通过上述步骤，将待纠错编码的比特序列进行了分段，并对分段后的比特序列片段分别进行差错校验编码，再对差错校验编码后的比特序列片段进行前向纠错编码并生成待发送比特序列，从而使得译码器在译码过程中可以根据各比特序列片段的差错校验码来判断当前比特序列片段是否是正确的，如果是正确的，译码器则将当前比特序列片段看成是确知比特，并且无需对当前比特序列继续译码，这相当于缩短码译码，降低了原码字的码率，可以提高译码性能，解决了相关技术中的纠错编码方案纠错能力不足的问题。
作为一种优选实施方式，对于步骤S202，所述待纠错编码比特序列包括信息比特序列或者对所述信息比特序列进行整体差错校验编码后的比特序列；其中所述差错校验编码可以是任何具有差错校验功能的编码，包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码。同样地，步骤S204中的差错校验编码也可以是任何具有差错校验功能的编码，包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码。
作为一种优选实施方式，对于步骤S202，所述对待纠错编码的比特序列进行分段可以是：根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀分段或者非均匀分段。
作为一种优选实施方式，对于步骤S206，所述方法还可以包括：
步骤S2062：先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特 序列；其中所述前向纠错编码是指具有纠错功能的编码，包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码编码、卷积码编码；
步骤S2064：各校验比特序列中对应位置上的比特组成新的比特序列片段；
步骤S2066：将原差错校验编码后的各比特序列片段与步骤S2064中的新的比特序列片段一起组成新的待纠错编码的比特序列，并对新的待纠错编码比特序列进行前向纠错编码，生成待发送比特序列。
作为一种优选实施方式，对于步骤S206，所述前向纠错编码可以是指具有纠错功能的编码，包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码编码、卷积码编码。
本发明实施例中，如果前向纠错编码方法为低密度奇偶校验码编码，则在步骤a中，发送端对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；或者，
如果前向纠错编码方法为低密度奇偶校验码编码，则在步骤a中，发送端按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是步骤b中各比特序列片段进行差错校验编码后的冗余比特长度。
本发明实施例中，在所述前向纠错编码方法为低密度奇偶校验码编码的情况下，可以对分段后的部分比特序列片段分别进行差错校验编码，例如，可以依据低密度奇偶校验码的基础校验矩阵的系统位部分列重来选出进行差错校验编码的部分比特序列片段。具体地，可以在分段后的比特序列片段中，选出低密度奇偶校验码的基础校验矩阵的系统位部分列重大于预设阈值的比特序列片段；对选出的比特序列片段进行差错校验编码。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明各个实施例所述的方法。
在本实施例中，还提供了一种纠错编码装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图3是根据本发明实施例的纠错编码装置的结构框图，如图3所示，该装置包括：分段模块32，设置为对第一待纠错编码的比特序列进行分段；差错校验编码模块34，设置为对分段模块32分段后的部分或全部比特序列片段，分别进行差错校验编码；前向纠错编码模块36，设置为将差错校验编码模块34执行差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；发送模块38，设置为发送前向纠错编码模块36生成的所述待发送比特序列。
本发明实施例中，所述分段模块32还可以设置为根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀分段或者非均匀分段。
本发明实施例中，所述前向纠错编码模块36还可以设置为：先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列；使用各校验比特 序列中对应位置上的比特组成新的比特序列片段；将原差错校验编码后的各比特序列片段与所述新的比特序列片段合成第三待纠错编码的比特序列，并对所述第三待纠错编码比特序列进行前向纠错编码，生成待发送比特序列。
本发明实施例中，当所述前向纠错编码方法为低密度奇偶校验码编码时，所述分段模块32还可以设置为：对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；或者，按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是对所述分段后的部分或全部比特序列片段，分别进行差错校验编码后的冗余比特长度。
本发明实施例中，当所述前向纠错编码方法为低密度奇偶校验码编码时，所述差错校验编码模块可以包括：选择单元，设置为在分段后的比特序列片段中，选出低密度奇偶校验码的基础校验矩阵的系统位部分列重大于预设阈值的比特序列片段；差错校验编码单元，设置为对选出的比特序列片段进行差错校验编码。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
下面结合优选实施例进行说明，以下优选实施例结合了上述实施例及其优选实施方式。在以下优选实施例中，提供了一种数据发送过程中的纠错编码的方法，该方法包括：
a，发送端对待纠错编码的比特序列进行分段；
b，对分段后的各比特序列片段，分别进行差错校验编码；
c，将差错校验编码后的各比特序列片段组成新的待纠错编码的比特序列，并对新的待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
d，发送端发送所述待发送比特序列。
进一步地，对于步骤a，所述待纠错编码比特序列包括信息比特序列或者对所述信息比特序列进行整体差错校验编码后的比特序列；其中所述差错校验编码是指任何具有差错校验功能的编码，包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码；
进一步地，对于步骤a，所述对待纠错编码的比特序列进行分段是指，根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀分段或者非均匀分段；
进一步地，对于步骤b，所述差错校验编码是指任何具有差错校验功能的编码，包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码；
进一步地，对于步骤c，所述方法还可以包括：
步骤c1：先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列；其中所述前向纠错编码是指具有纠错功能的编码，包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码(Polar code)编码、卷积码编码；
步骤c2：各校验比特序列中对应位置上的比特组成新的比特序列片段；
步骤c3：将原差错校验编码后的各比特序列片段与步骤c2中的新的比特序列片段一起组成新的待纠错编码的比特序列，并对新的待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
进一步地，对于步骤c，所述前向纠错编码是指具有纠错功能的编码，包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码(Polar code)编码、卷积码编码；
进一步地，对于步骤a到步骤c，如果前向纠错编码方法为低密度奇 偶校验码编码，则在步骤a中，发送端对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；或者，
如果前向纠错编码方法为低密度奇偶校验码编码，则在步骤a中，发送端按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是步骤b中各比特序列片段进行差错校验编码后的冗余比特长度。
进一步，对于预先给定的阈值，当分段后的比特序列片段中，有一部分比特序列片段对应的低密度奇偶校验码的基础校验矩阵的系统位部分列重大于该阈值时，则可以对这部分比特序列片段进行前向差错校验编码。
下面以几个具体的实施例来对上述提出的纠错编码方案加以说明：
实施例一：
发送端向接收端发送待编码比特序列，其中待编码比特序列的长度为K比特，其中K1比特为信息比特，K2比特为信息比特经过差错校验编码后生成的校验比特，K，K1，K2都是非负整数，且K＝K1+K2；所述差错校验编码包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码；在本例中假设差错校验编码方式为循环冗余校验(Cyclic Redundancy Check，简称CRC)编码。
图4是根据本发明实施例一的纠错编码过程的示意图，如图4所示，发送端对待编码比特序列进行如下处理：
发送端根据预先设置的比特序列片段的数目或者比特序列片段的长度对待编码比特序列进行分段，在本例中，假设分段数目为C段，则将K比特的待编码比特序列均匀分为C个比特序列片段，每个比特序列片段的长度为
Figure PCTCN2017084221-appb-000015
比特。如果K不能被C整除，则在其中一个比特序列片段中添加
Figure PCTCN2017084221-appb-000016
个收发两端的已知比特；其中
Figure PCTCN2017084221-appb-000017
表示向上取整运算。
发送端对各比特序列片段分别进行差错校验编码，K3为各比特序列 片段经过差错校验编码后生成的校验比特，则经过差错校验编码后各比特序列的长度为
Figure PCTCN2017084221-appb-000018
比特；所述差错校验编码包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码；在本例中假设各比特序列片段的差错校验编码方式为循环冗余校验(CRC)编码。
发送端将所述经过差错校验编码的各比特序列片段组成新的待编码比特序列，所述新的带编码比特序列的长度为K+C*K3比特，或者
Figure PCTCN2017084221-appb-000019
比特。发送端对带编码比特序列进行前向纠错编码，生成待发送比特序列。其中前向纠错编码包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码编码、卷积码编码；在本例中假设新的待编码比特序列的前向纠错编码方式为低密度奇偶校验码(LDPC)编码。
实施例二：
发送端向接收端发送待编码比特序列，其中待编码比特序列的长度为K比特，其中K1比特为信息比特，K2比特为信息比特经过差错校验编码后生成的校验比特，K，K1，K2都是非负整数，且K＝K1+K2；所述差错校验编码包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码；在本例中假设差错校验编码方式为循环冗余校验(CRC)编码。
图5是根据本发明实施例二的纠错编码过程的示意图，如图5所示，发送端对待编码比特序列进行如下处理：
发送端根据预先设置的比特序列片段的数目或者比特序列片段的长度对待编码比特序列进行分段，在本例中，假设分段数目为C段，则将K比特的待编码比特序列均匀分为C个比特序列片段，每个比特序列片段的长度为
Figure PCTCN2017084221-appb-000020
比特。如果K不能被C整除，则在其中一个比特序列片段中添加
Figure PCTCN2017084221-appb-000021
个收发两端的已知比特；其中
Figure PCTCN2017084221-appb-000022
表示向上取整运算。
发送端对各比特序列片段分别进行差错校验编码，K3为各比特序列片段经过差错校验编码后生成的校验比特，则经过差错校验编码后各比特序列的长度为
Figure PCTCN2017084221-appb-000023
比特；所述差错校验编码包括但不限定于循环冗余校验编码、BCH码编码，里德-所罗门码(RS码)编码、奇偶校验编码；在本例中假设各比特序列片段的差错校验编码方式为循环冗余校验(CRC)校验编码。
发送端对差错校验编码后的C个比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列。例如，对第一个比特序列片段的第i个比特和第二个比特序列片段的第i个比特，…第C个比特序列片段的第i个比特，共C个比特组成的第i个信息比特序列进行前向纠错编码，得到第i个校验比特序列，其中校验比特序列的长度为T比特，其中i是正整数，且
Figure PCTCN2017084221-appb-000024
依此类推，一共有
Figure PCTCN2017084221-appb-000025
个长度为C比特的信息序列分别进行前向纠错编码，得到
Figure PCTCN2017084221-appb-000026
个长度为T比特的校验比特序列。其中，所述前向纠错编码包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码编码、卷积码编码。在本例中假设为比特异或编码。
各校验比特序列中对应位置上的比特组成新的比特序列片段；例如第一个校验比特序列的第j个比特和第二个校验比特序列的第j个比特，…，第
Figure PCTCN2017084221-appb-000027
个比特序列片段的第j个比特组成一个新的比特序列片段，其中所述新的比特序列的长度为
Figure PCTCN2017084221-appb-000028
比特，其中j是正整数，且1≤j≤T；依此类推，一共有T个新的比特序列片段。
发送端将原差错校验编码后的C个比特序列片段和上述T个新的比特序列片段一起组成新的待纠错编码比特序列，所述新的待纠错编码比特序列的长度为
Figure PCTCN2017084221-appb-000029
比特。发送端对所述新的待纠错编码比特序列进行前向纠错编码。所述前向纠错编码包括但不限定于比特异或编码、分组码编码、BCH码编码、里德-所罗门码(RS码)编码、喷泉码编码、低 密度奇偶校验码编码、Turbo码编码、极化码(Polar code)编码、卷积码编码。在本例中假设为极化码(Polar code)编码。
实施例三：
发送端向接收端发送待编码比特序列，其中待编码比特序列的长度为K比特，其中K1比特为信息比特，K2比特为信息比特经过差错校验编码后生成的校验比特，K，K1，K2都是非负整数，且K＝K1+K2；在本例中假设差错校验编码方式为循环冗余校验(CRC)编码。
发送端对待编码比特序列进行如下处理：
发送端根据预先设置的比特序列片段的数目或者比特序列片段的长度对待编码比特序列进行分段，在本例中，假设分段数目为Kb段，其中，Kb为低密度奇偶校验码(LDPC)的基础矩阵Hb中列数减去行数，则将K比特的待编码比特序列均匀分为Kb个比特序列片段，每个比特序列片段的长度为
Figure PCTCN2017084221-appb-000030
比特。如果K不能被Kb整除，则在其中一个比特序列片段中添加
Figure PCTCN2017084221-appb-000031
个收发两端的已知比特；其中
Figure PCTCN2017084221-appb-000032
表示向上取整运算。
发送端对各比特序列片段分别进行差错校验编码，K3为各比特序列片段经过差错校验编码后生成的校验比特，则经过差错校验编码后各比特序列的长度为
Figure PCTCN2017084221-appb-000033
比特；在本例中假设各比特序列片段的差错校验编码方式为循环冗余校验(CRC)编码。
发送端将所述经过差错校验编码的各比特序列片段组成新的待编码比特序列，所述新的待编码比特序列的长度为K+Kb*K3比特，或者
Figure PCTCN2017084221-appb-000034
比特。发送端对带编码比特序列进行前向纠错编码，生成待发送比特序列。在本例中假设新的待编码比特序列的前向纠错编码方式为低密度奇偶校验码(LDPC)编码。
实施例四：
发送端向接收端发送待编码比特序列，其中待编码比特序列的长度为K比特，其中K1比特为信息比特，K2比特为信息比特经过差错校验编码后生成的校验比特，K，K1，K2都是非负整数，且K＝K1+K2；在本例中 假设差错校验编码方式为循环冗余校验(CRC)编码。
发送端对待编码比特序列进行如下处理：
发送端根据预先设置的的比特序列片段的数目或者比特序列片段的长度对待编码比特序列进行分段，在本例中，假设比特序列片段的长度为E比特，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是拟对各比特序列片段进行差错校验编码后的冗余比特长度。则将K比特的待编码比特序列均匀分为
Figure PCTCN2017084221-appb-000035
个比特序列片段，每个比特序列片段的长度为E比特。如果K不能被E整除，则在其中一个比特序列片段中添加
Figure PCTCN2017084221-appb-000036
个收发两端的已知比特；其中
Figure PCTCN2017084221-appb-000037
表示向上取整运算。
发送端对各比特序列片段分别进行差错校验编码，K3为各比特序列片段经过差错校验编码后生成的校验比特，则经过差错校验编码后各比特序列的长度为z比特；在本例中假设各比特序列片段的差错校验编码方式为循环冗余校验(CRC)编码。
发送端将所述经过差错校验编码的各比特序列片段组成新的待编码比特序列，所述新的带编码比特序列的长度为
Figure PCTCN2017084221-appb-000038
比特。发送端对待编码比特序列进行前向纠错编码，生成待发送比特序列。在本例中假设新的待编码比特序列的前向纠错编码方式为低密度奇偶校验码(LDPC)编码。
实施例五：
发送端向接收端发送待编码比特序列，其中待编码比特序列的长度为K比特，其中K1比特为信息比特，K2比特为信息比特经过差错校验编码后生成的校验比特，K，K1，K2都是非负整数，且K＝K1+K2；在本例中假设差错校验编码方式为循环冗余校验(CRC)编码。
发送端对待编码比特序列进行如下处理：
发送端根据预先设置的比特序列片段的数目或者比特序列片段的长度对待编码比特序列进行分段，在本例中，假设分段数目为Kb段，其中， Kb为低密度奇偶校验码(LDPC)的基础矩阵Hb中列数减去行数，则将K比特的待编码比特序列非均匀地分为Kb个比特序列片段，并且仅对其中的部分比特序列片段进行差错校验编码；
其中，在Kb个比特序列片段中，有W1个第一类比特序列片段，其中每个比特序列片段的长度为z比特，有W2个第二类比特序列片段，其中第二类比特序列片段的的长度为E比特，其中E为正整数，并且E＝z-K3，K3是拟对所述第二类比特序列片段进行差错校验编码后的冗余比特长度。Kb＝W1+W2；
所述W2个第二类比特序列片段对应于所述低密度奇偶校验码的基础校验矩阵的系统位部分列重较重的列。例如，在所述基础教育矩阵的系统位部分
Figure PCTCN2017084221-appb-000039
中，有W2列的列重量大于或等于预先设定的阈值；这W2列的索引分别为I＝[I1,I2,I3,...,Iw2],则所述W2个第二类比特序列片段对应于Kb个比特序列片段中所引为I的W2个比特序列片段；其余的比特序列片段为所述W1个第一类比特序列片段；
对所述W2个第二类比特序列片段的每个比特序列片段分别进行差错校验编码，在每个第二类比特序列片段后添加K3个差错校验比特。在本例中假设各比特序列片段的差错校验编码方式为循环冗余校验(CRC)编码。
发送端将所述经过差错校验编码的各比特序列片段组成新的待编码比特序列，所述新的带编码比特序列的长度为z*Kb比特。发送端对待编码比特序列进行前向纠错编码，生成待发送比特序列。在本例中假设新的待编码比特序列的前向纠错编码方式为低密度奇偶校验码(LDPC)编码。
本实施例提供的方案的有益效果主要表现在，当接收端的信道译码器对采用本实施例的进行纠错编码的码字进行译码时，译码器在译码过程中可以根据各比特序列片段的差错校验码来判断当前比特序列片段是否是正确的，如果是正确的，译码器则将当前比特序列片段看成是确知比特，并且无需对当前比特序列继续译码，这相当于缩短码译码，降低了原码字 的码率，可以提高译码性能；同时，由于本实施例还提出了一种对各比特序列片段之间对应位置比特的前向纠错，相当于增加了一级内码保护，从而提高了最终译码的性能。
特别地，本实施例针对低密度奇偶校验码还专门提出了将比特序列片段的数目与低密度奇偶校验码的基础矩阵的参数，或者，将比特序列片段的长度与低密度奇偶校验码的扩展因子的大小匹配，从而使得本实施例提出的分段差错校验和低密度奇偶校验编码能完美结合，可以提高编码和译码的效率及性能。
特别地，由于低密度奇偶校验码对码字的不同部分有不同的纠错能力，本实施例还针对低密度奇偶校验码还专门提出了非均匀分段和部分差错校验的方法，仅对低密度奇偶校验码的基础校验矩阵系统位部分列重量较重的列进行差错校验。其有益效果是，对纠错能力较强的比特序列片段进行差错校验可以尽快确认该比特序列片段是否已经正确译码，对于已经正确译码的比特序列片段可以看成是确知比特，并且无需对当前比特序列继续译码，这相当于缩短码译码，降低了原码字的码率，可以提高译码性能；同时由于只需对部分比特序列片段添加差错校验比特，因此还降低了开销。
本发明的实施例还提供了一种存储介质，该存储介质包括存储的程序，其中，上述程序运行时执行上述任一项所述的方法。可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的程序代码：
步骤S1，对第一待纠错编码的比特序列进行分段；
步骤S2，对分段后的部分或全部比特序列片段，分别进行差错校验编码；
步骤S3，将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
步骤S4，发送所述待发送比特序列。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只 读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本发明的实施例还提供了一种处理器，该处理器用于运行程序，其中，该程序运行时执行上述任一项方法中的步骤。
可选地，在本实施例中，上述程序用于执行以下步骤：
步骤S1，对第一待纠错编码的比特序列进行分段；
步骤S2，对分段后的部分或全部比特序列片段，分别进行差错校验编码；
步骤S3，将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
步骤S4，发送所述待发送比特序列。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
基于本发明实施例提供的上述技术方案，由于将待纠错编码的比特序列进行了分段，并对分段后的比特序列片段分别进行差错校验编码，再对差错校验编码后的比特序列片段进行前向纠错编码并生成待发送比特序列，从而使得译码器在译码过程中可以根据各比特序列片段的差错校验码来判断当前比特序列片段是否是正确的，如果是正确的，译码器则将当前比特序列片段看成是确知比特，并且无需对当前比特序列继续译码，这相当于缩短码译码，降低了原码字的码率，可以提高译码性能，解决了相关技术中的纠错编码方案纠错能力不足的问题。

Claims (15)

  1. 一种纠错编码方法，包括：
    对第一待纠错编码的比特序列进行分段；
    对分段后的部分或全部比特序列片段，分别进行差错校验编码；
    将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
    发送所述待发送比特序列。
  2. 根据权利要求1所述的方法，其中，所述第一待纠错编码比特序列包括以下至少之一：
    信息比特序列；
    对所述信息比特序列整体进行差错校验编码后的比特序列。
  3. 根据权利要求1或2所述的方法，其中，所述差错校验编码包括以下至少之一：
    循环冗余校验编码、BCH码编码、RS码编码、奇偶校验编码。
  4. 根据权利要求1所述的方法，其中，对第一待纠错编码的比特序列进行分段包括：
    根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀或非均匀分段。
  5. 根据权利要求1所述的方法，其中，将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列包括：
    先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列；
    使用各校验比特序列中对应位置上的比特组成新的比特序列片段；
    将原差错校验编码后的各比特序列片段与所述新的比特序列片段合成第三待纠错编码的比特序列，并对所述第三待纠错编码比特序列进行前向纠错编码，生成待发送比特序列。
  6. 根据权利要求1至5中任一项所述的方法，其中，所述前向纠错编码包括以下至少之一：
    比特异或编码、分组码编码、BCH码编码、RS码编码、喷泉码编码、低密度奇偶校验码编码、Turbo码编码、极化码编码、卷积码编码。
  7. 根据权利要求6所述的方法，其中，在所述前向纠错编码方法为低密度奇偶校验码编码的情况下，对第一待纠错编码的比特序列进行分段包括：
    对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度奇偶校验码的基础矩阵的行数；或者，
    按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是对所述分段后的部分或全部比特序列片段，分别进行差错校验编码后的冗余比特长度。
  8. 根据权利要求6所述的方法，其中，在所述前向纠错编码方法为低密度奇偶校验码编码的情况下，对分段后的部分比特序列片段，分别进行差错校验编码包括：
    在分段后的比特序列片段中，选出低密度奇偶校验码的基础校验矩阵的系统位部分列重大于预设阈值的比特序列片段；
    对选出的比特序列片段进行差错校验编码。
  9. 一种纠错编码装置，包括：
    分段模块，设置为对第一待纠错编码的比特序列进行分段；
    差错校验编码模块，设置为对分段后的部分或全部比特序列片段，分别进行差错校验编码；
    前向纠错编码模块，设置为将差错校验编码后的各比特序列片段组成第二待纠错编码的比特序列，并对所述第二待纠错编码比特序列进行前向纠错编码，生成待发送比特序列；
    发送模块，设置为发送所述待发送比特序列。
  10. 根据权利要求9所述的装置，其中，所述分段模块还设置为：
    根据预先设定的比特序列片段的数目或者比特序列片段的长度对所述待编码比特序列进行均匀或非均匀分段。
  11. 根据权利要求9所述的装置，其中，所述前向纠错编码模块还设置为：
    先对差错校验编码后的各比特序列片段中对应位置上的比特组成的各信息比特序列分别进行前向纠错编码，得到各自的校验比特序列；
    使用各校验比特序列中对应位置上的比特组成新的比特序列片段；
    将原差错校验编码后的各比特序列片段与所述新的比特序列片段合成第三待纠错编码的比特序列，并对所述第三待纠错编码比特序列进行前向纠错编码，生成待发送比特序列。
  12. 根据权利要求9所述的装置，其中，当所述前向纠错编码方法为低密度奇偶校验码编码时，所述分段模块还设置为：
    对待编码比特序列分为Kb段，其中Kb为正整数，且Kb＝Nb-Mb，其中，Nb是低密度奇偶校验码的基础校验矩阵的列数，Mb是低密度 奇偶校验码的基础矩阵的行数；或者，
    按照E比特为单位进行分段，其中E为正整数，并且E＝z-K3，其中，z是低密度奇偶校验码的扩展因子，K3是对所述分段后的部分或全部比特序列片段，分别进行差错校验编码后的冗余比特长度。
  13. 根据权利要求9所述的装置，其中，当所述前向纠错编码方法为低密度奇偶校验码编码时，所述差错校验编码模块包括：
    选择单元，设置为在分段后的比特序列片段中，选出低密度奇偶校验码的基础校验矩阵的系统位部分列重大于预设阈值的比特序列片段；
    差错校验编码单元，设置为对选出的比特序列片段进行差错校验编码。
  14. 一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行权利要求1至8中任一项所述的方法。
  15. 一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行权利要求1至8中任一项所述的方法。
PCT/CN2017/084221 2016-05-13 2017-05-12 纠错编码方法及装置 WO2017194013A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610319307.7A CN107370488A (zh) 2016-05-13 2016-05-13 纠错编码方法及装置
CN201610319307.7 2016-05-13

Publications (1)

Publication Number Publication Date
WO2017194013A1 true WO2017194013A1 (zh) 2017-11-16

Family

ID=60266307

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/084221 WO2017194013A1 (zh) 2016-05-13 2017-05-12 纠错编码方法及装置

Country Status (2)

Country Link
CN (1) CN107370488A (zh)
WO (1) WO2017194013A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019201269A1 (zh) * 2018-04-19 2019-10-24 华为技术有限公司 极化码的编译码方法和装置
CN112688693A (zh) * 2020-12-14 2021-04-20 海光信息技术股份有限公司 一种内存多矩阵编码方法、纠错方法及相关装置
CN113727339A (zh) * 2021-07-13 2021-11-30 国能浙江宁海发电有限公司 无线密钥协商方法、装置、计算机设备及存储介质
CN114448448A (zh) * 2022-01-24 2022-05-06 电子科技大学 一种基于ca-scl的极化码编译码方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI602188B (zh) * 2017-01-03 2017-10-11 慧榮科技股份有限公司 用來於記憶裝置中進行資料管理之方法以及記憶裝置及其控制器
CN110417507A (zh) * 2018-04-26 2019-11-05 成都盛拓源科技有限公司 单向通信中的面向整数据包出错的纠错编码调用方法
CN111988044B (zh) * 2019-07-01 2022-07-19 中南大学 一种凿孔Polar码的码字构造方法
CN112398483A (zh) * 2019-08-15 2021-02-23 中兴通讯股份有限公司 一种ldpc编码方法、装置、基站及可读存储介质
CN114079534B (zh) 2020-08-20 2023-03-28 腾讯科技（深圳）有限公司 编码、解码方法、装置、介质和电子设备
CN114696953B (zh) * 2022-03-01 2023-12-12 重庆理工大学 一种自由空间光通信的信道编码和译码方法
CN115037415B (zh) * 2022-05-31 2024-02-09 江苏屹信航天科技有限公司 基于crc的纠错编码的方法、装置、终端

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1638286A (zh) * 2004-03-05 2005-07-13 上海交通大学 在Turbo乘积码编码之前添加循环校验位的方法
CN101159514A (zh) * 2007-10-31 2008-04-09 中兴通讯股份有限公司 一种传输块循环冗余码的添加方法
CN101383618A (zh) * 2007-09-05 2009-03-11 中兴通讯股份有限公司 一种传输块的循环冗余校验码的编码方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1638286A (zh) * 2004-03-05 2005-07-13 上海交通大学 在Turbo乘积码编码之前添加循环校验位的方法
CN101383618A (zh) * 2007-09-05 2009-03-11 中兴通讯股份有限公司 一种传输块的循环冗余校验码的编码方法
CN101159514A (zh) * 2007-10-31 2008-04-09 中兴通讯股份有限公司 一种传输块循环冗余码的添加方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019201269A1 (zh) * 2018-04-19 2019-10-24 华为技术有限公司 极化码的编译码方法和装置
CN112688693A (zh) * 2020-12-14 2021-04-20 海光信息技术股份有限公司 一种内存多矩阵编码方法、纠错方法及相关装置
CN112688693B (zh) * 2020-12-14 2023-12-05 海光信息技术股份有限公司 一种内存多矩阵编码方法、纠错方法及相关装置
CN113727339A (zh) * 2021-07-13 2021-11-30 国能浙江宁海发电有限公司 无线密钥协商方法、装置、计算机设备及存储介质
CN114448448A (zh) * 2022-01-24 2022-05-06 电子科技大学 一种基于ca-scl的极化码编译码方法

Also Published As

Publication number Publication date
CN107370488A (zh) 2017-11-21

Similar Documents

Publication Publication Date Title
WO2017194013A1 (zh) 纠错编码方法及装置
US10673468B2 (en) Concatenated and sliding-window polar coding
CN111628785B (zh) 使用硬选取硬译码模式下的译码器产生软信息的方法
US6948109B2 (en) Low-density parity check forward error correction
US8413008B2 (en) Method for recovery of lost and/or corrupted data
EP3119004B1 (en) Method, device, and computer storage medium supporting low bit rate encoding
WO2018059548A1 (zh) 数据发送方法、装置及信源
US9654147B2 (en) Concatenated error correction device
EP3032748A1 (en) Coding and decoding with staggered parity
US9473173B2 (en) Method for early terminating decoding processes of serial concatenated coding and decoder using the same
WO2015120719A1 (zh) 信息处理方法及装置
EP3713096B1 (en) Method and device for decoding staircase code, and storage medium
US9548761B2 (en) Coding and decoding of error correcting codes
US20160049962A1 (en) Method and apparatus of ldpc encoder in 10gbase-t system
US11303305B2 (en) Sparse graph creation device and sparse graph creation method
US11316534B2 (en) Encoding method and device, decoding method and device, and storage medium
US11050440B2 (en) Encoder, decoder, encoding method and decoding method based on low-density parity-check code
WO2011144161A1 (zh) 前向纠错方法、装置及系统
JP5523064B2 (ja) 復号装置及び方法
Dong et al. Towards high performance short polar codes: concatenated with the spinal codes
EP1643653A1 (en) Iterative decoding of low-density parity-check (LDPC) codes
CN114124108A (zh) 基于低密度奇偶校验的编码方法、译码方法和相关装置
WO2018126914A1 (zh) 准循环低密度奇偶校验码的编码方法及装置、存储介质
WO2020139234A1 (en) Performance enhancement of polar codes for short frame lengths considering error propagation effects
WO2018149304A1 (zh) 数据处理方法和装置、数据处理设备及存储介质

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17795631

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17795631

Country of ref document: EP

Kind code of ref document: A1