WO2017193877A1 - 脉冲密度调制转换电路及方法、存储介质 - Google Patents

脉冲密度调制转换电路及方法、存储介质 Download PDF

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WO2017193877A1
WO2017193877A1 PCT/CN2017/083273 CN2017083273W WO2017193877A1 WO 2017193877 A1 WO2017193877 A1 WO 2017193877A1 CN 2017083273 W CN2017083273 W CN 2017083273W WO 2017193877 A1 WO2017193877 A1 WO 2017193877A1
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audio signal
pdm
comb filter
downsampling
decimator
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French (fr)
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赵恒正
李安
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Sanechips Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K7/00Modulating pulses with a continuously-variable modulating signal
    • H03K7/08Duration or width modulation ; Duty cycle modulation

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  • the present invention relates to signal processing technologies, and in particular, to a pulse density modulation conversion circuit and method, and a storage medium.
  • Digital microphone is a new type of processing device that converts analog audio signals into digital signals. Compared with analog microphones, it has the advantages of strong anti-interference ability, high signal-to-noise ratio and low distortion.
  • the output signal of a digital microphone is typically in the form of pulse density modulation (PDM).
  • PDM pulse density modulation
  • PCM pulse code modulation
  • FIG. 1 is a schematic diagram of a conventional cascaded comb (CIC) filter structure, as shown in FIG.
  • Integral comb (CIC) filtering consists of a cascade integrator n-1, a cascade comb filter nD, and a downsampled decimation R.
  • 2 is an equivalent structure diagram of a conventional comb filter portion. As shown in FIG. 2, the cascade comb filter nD can be equivalent to a plurality of delay units Z (in FIG. 2, 32 delay units are taken as an example for illustration. ).
  • CIC Cascaded Integral Comb
  • the cascaded comb filter in the existing cascaded comb-like (CIC) filter has a large order and a large resource occupation.
  • embodiments of the present invention are expected to provide a pulse density modulation conversion circuit and method, and a storage medium, which are used to simplify the filter structure, facilitate hardware circuit implementation, and reduce resource occupation.
  • Embodiments of the present invention provide a pulse density modulation conversion circuit, the circuit including: a cascade integrator, a downsampling extractor, and a cascade comb filter;
  • the cascade integrator is configured to receive a pulse density modulated PDM audio signal, and perform an accumulating process on the PDM audio signal, and output the PDM audio signal accumulated by the integrators of each stage to the downsampler extractor;
  • the downsampling decimator is configured to extract the accumulated PDM audio signal every preset interval
  • the cascaded comb filter is configured to receive the PDM audio signal extracted by the downsampling decimator, and perform subtraction on the extracted PDM audio signal to obtain a pulse code modulated PCM audio signal.
  • the delay of the cascaded comb filter is the ratio of the original delay of the cascaded comb filter to the downsampled rate of the downsampler decimator.
  • the output of the PDM audio signal accumulated by the level integrators after being extracted by the downsampling extractor is:
  • the output is the PDM audio signal accumulated by the nth stage integrator, otherwise, when n is not equal to N*R, the output is 0; wherein N is the clock of the cascaded comb filter Frequency, R represents R times downsampling, and n is the number of stages in which the integrator is located.
  • the clock frequency of the cascaded integrator is the product of the clock frequency of the cascade comb filter and the downsampling rate.
  • the cascade comb filter includes an M-stage delayer and an M-stage subtractor; wherein the M is a positive integer;
  • the Mth stage delayer is configured to save an operation result of the M-1th stage subtractor; when the M is equal to 1, the 1st stage delayer is configured to save the Extracted PDM audio signal;
  • the Mth stage subtractor is configured to subtract the extracted Mth PDM audio signal and the M-1th audio signal.
  • the embodiment of the invention further provides a pulse density modulation conversion method, the method comprising:
  • the cascade integrator receives the pulse density modulated PDM audio signal, performs an accumulating process on the PDM audio signal, and outputs the PDM audio signal accumulated by the integrators of each stage to the downsampling extractor;
  • the downsampling decimator receives the accumulated PDM audio signal, and extracts the accumulated PDM audio signal every preset interval;
  • the cascaded comb filter receives the PDM audio signal extracted by the downsampled decimator, and performs subtraction on the extracted PDM audio signal to obtain a pulse code modulated PCM audio signal.
  • the delay of the cascaded comb filter is the ratio of the original delay of the cascaded comb filter to the downsampled rate of the downsampler decimator.
  • the downsampling decimator receives the accumulated PDM audio signal, and extracts the accumulated PDM audio signal at a preset interval, specifically:
  • the downsampling decimator When n is equal to N*R, the downsampling decimator extracts the PDM audio signal accumulated by the nth stage integrator as the output of the downsampled decimator, otherwise, when n is not equal to N*R, the downsampling The output of the decimator is 0; where N is the clock frequency of the cascaded comb filter, R table Show R times downsampling, where n is the number of stages in which the integrator is located.
  • the clock frequency of the cascaded integrator is the product of the clock frequency of the cascade comb filter and the downsampling rate.
  • the cascade comb filter includes an M-stage delayer and an M-stage subtractor; wherein the M is a positive integer;
  • the cascaded comb filter receives the PDM audio signal extracted by the downsampled decimator, and performs subtraction on the extracted PDM audio signal to obtain a pulse code modulated PCM audio signal:
  • the Mth stage subtractor subtracts the extracted Mth PDM audio signal and the extracted M-1th audio signal to obtain a pulse code modulated PCM audio signal, and the The operation result of the M-1 level subtractor is stored in the Mth stage delayer;
  • the PDM audio signal extracted by the downsampling decimator is saved in the first stage delayer.
  • Embodiments of the present invention provide a pulse density modulation conversion circuit and method, and a storage medium, including a cascade integrator, a downsampling extractor, and a cascade comb filter;
  • the cascade integrator is configured to receive pulse density modulated PDM audio Signal, and accumulate the PDM audio signal, output the PDM audio signal accumulated by the integrators of each stage to the downsampler decimator;
  • the downsampler decimator is configured to extract the accumulated PDM audio signal at every preset interval, cascading comb filter
  • the device is configured as a PDM audio signal extracted by the downsampling decimator, and performs subtraction on the extracted PDM audio signal to obtain a pulse code modulated PCM audio signal.
  • the conversion circuit advances the downsampled extractor R to the middle of the cascaded integrator and the cascaded comb filter, so that the differential delay D of the cascaded comb filter is only 1/R of the original structure, which is greatly simplified.
  • the structural complexity of the original cascade comb filter facilitates hardware circuit implementation and reduces resource occupation.
  • FIG. 1 is a schematic diagram of a conventional cascaded comb (CIC) filter structure
  • FIG. 3 is a schematic diagram of a PDM audio signal conversion circuit according to an embodiment of the present invention.
  • FIG. 4 is a structural block diagram of components included in a PDM audio signal conversion circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an equivalent structure of a cascade comb filter according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a two-stage cascade process of converting a PDM audio signal into a PCM audio signal
  • FIG. 7 is a two-level cascade circuit diagram of converting a PDM audio signal into a PCM audio signal
  • FIG. 8 is a schematic flowchart diagram of a PDM audio signal conversion method according to an embodiment of the present invention.
  • the pulse density modulation conversion circuit of the embodiment of the present invention improves the downsampling extraction part in the existing cascaded integral comb filter from the last stage of the processing structure to the middle of the integral filtering and the comb filtering, so that After the improvement, the differential delay D of the comb filter is only 1/R of the original structure, which greatly simplifies the structural complexity of the comb filter.
  • FIG. 3 is a schematic diagram of a PDM audio signal conversion circuit according to an embodiment of the present invention
  • FIG. 4 is a structural block diagram of components included in a PDM audio signal conversion circuit according to an embodiment of the present invention, as shown in FIG. 3 and FIG. include:
  • the cascade integrator 11 is configured to receive a pulse density modulated PDM audio signal, and perform an accumulation process on the PDM audio signal, and output the PDM audio signal accumulated by the integrators of each stage to the downsampler extractor;
  • the downsampling decimator 12 is configured to extract the accumulated PDM audio signal every preset interval
  • the cascaded comb filter 13 is configured to receive PDM sounds extracted by the downsampling extractor The frequency signal is subtracted from the extracted PDM audio signal to obtain a pulse code modulated PCM audio signal.
  • 11 in FIG. 3 corresponds to the cascade integrator 11 in FIG. 4
  • 12 in FIG. 3 corresponds to the downsampling extractor 12 in FIG. 13 corresponds to the cascaded comb filter 13 in FIG.
  • the PDM audio signal is input from the cascade integrator, and is output from the cascade comb filter after the downsampler decimator. Specific steps are as follows:
  • the PDM audio signal is input from the cascade integrator, and the delay of the cascade integrator is 1, that is, the current output of each stage integrator is equal to the sum of the current input and the previous output. which is:
  • x(n) is the nth input of the cascaded integrator
  • y(n-1) is the (n-1)th output of the cascaded integrator
  • y(n) is the nth of the cascaded integrator Level output
  • 1 means that the cascaded integrator has a delay of 1
  • the number of data becomes 1/R of the original number, that is, the downsampled extractor is every The accumulated value is extracted at a preset interval, where the preset interval is N*R.
  • N is the clock frequency of the cascaded comb filter
  • R represents R times downsampling
  • n is the number of stages in which the integrator is located
  • n N*R
  • n' is the output result number of the downsampled decimator
  • n' 1, 2...
  • y(n) is the output of the nth stage integrator
  • y(n') is the nthth output of the downsampled decimator.
  • the formula indicates that the PDM audio signals accumulated by the integrators of each stage are pumped by the downsampling extractor.
  • the output after fetching is:
  • the output is the PDM audio signal accumulated by the nth stage integrator; otherwise, when n is not equal to N*R, the output is 0; where N is the clock frequency of the cascaded comb filter, R represents R times downsampling, and n is the number of stages in which the integrator is located.
  • step (3) After the PDM audio signal processed by step (2) is output from the downsampling decimator, it enters the cascade comb filter, and the delay of the cascade comb filter is greatly reduced due to the forward shift of the downsampler decimator. Small, for example, assuming that the delay of the improved pre-cascade comb filter is 32 and the downsampling rate is 32, then the input-output relationship is expressed as:
  • y(n') is the nth output of the downsampled decimator
  • y(n'-32) is the (n'-32)th output of the downsampled decimator
  • the delay of the improved cascaded comb filter is the ratio of the original delay to the downsampling rate of the downsampled decimator, that is, the input-output relationship is expressed as:
  • the delay of the cascade comb filter is reduced from 32 to 1, that is, only at least one data needs to be saved, and the improved cascade comb filter is compared with the need to save at least 32 data before the improvement.
  • the delay of the device is reduced a lot. In the actual circuit, it means that the number of data to be saved is greatly reduced, which simplifies the circuit structure and occupied resources.
  • the conversion circuit includes: a cascade integrator 11, a downsampling extractor 12, and cascade comb filtering. 13.
  • the cascade integrator 11 is configured to receive the PDM audio signal and perform an accumulation process on the PDM audio signal, and output the PDM audio signal accumulated by the integrators of each stage to the downsampler decimator 12; the downsampler decimator 12 is configured to pre-predict
  • the accumulated PDM audio signal is extracted at intervals, and the extracted PDM audio signal is output to the cascade comb filter 13 for processing, and the cascaded comb filter 13 performs subtraction on the extracted PDM audio signal to obtain PCM audio. signal.
  • the preset interval is set according to the system and user requirements, and is not described here.
  • the input end of the cascade integrator 11 receives the PDM audio signal
  • the output of the cascaded integrator 11 is connected to the input of the downsampler decimator 12, the output of the downsampler decimator 12 and the cascaded comb filter 13
  • the input terminal is connected, and the output of the cascade comb filter 13 outputs a PCM audio signal.
  • the pulse density modulation conversion circuit of the embodiment comprises a cascade integrator, a downsampling extractor and a cascade comb filter; the PDM audio signal is input before the cascade integrator, and sequentially passes through the cascade integrator and the downsampler extractor. After processing by the cascade comb filter, it is output from the cascade comb filter.
  • the cascaded comb filter is filtered by the downsampled decimator in the original cascaded comb filter from the last stage of the processing structure to the middle of the cascade integrator and the cascade comb filter.
  • the differential delay D of the device is only 1/R of the original cascaded comb filter structure, which reduces the number of cascaded comb filters, facilitates hardware implementation, simplifies the structure, and saves resources.
  • FIG. 5 is a schematic diagram of an equivalent structure of a cascaded comb filter according to an embodiment of the present invention. As shown in FIG. 5, comparing FIG. 2 and FIG. 4, it is assumed that the differential delay D and the downsampling multiple R are both 32.
  • the improved PDM audio signal conversion circuit requires 32 stages of delay units, and the improved PDM audio signal conversion circuit requires only one level of delay units.
  • the downsampler decimator 12 By verification, the downsampler decimator 12, the system function corresponding to the last stage of the processing structure, and the system function corresponding to the intermediate between the cascaded integrator 11 and the cascaded comb filter 13 are equal to the same moving average
  • the system function of the filter so by moving the downsampling decimator 12 forward, it simplifies the circuit structure and ensures that the processing effect is the same as that without advance.
  • the delay of the cascade comb filter is a ratio of an original delay of the cascade comb filter to a down sample rate of the downsampler decimator.
  • the output of the PDM audio signal accumulated by the level integrators after being extracted by the downsampling extractor is:
  • the output is the PDM audio signal accumulated by the nth stage integrator; otherwise, When n is not equal to N*R, the output is 0; where N is the clock frequency of the cascaded comb filter, R is R times downsampling, and n is the number of the integrator.
  • the clock frequency of the cascaded integrator is the product of the clock frequency of the cascaded comb filter and the downsampling rate.
  • the cascade comb filter includes an M-stage delayer and an M-stage subtractor; wherein the M is a positive integer;
  • the Mth stage delayer is configured to save an operation result of the M-1th stage subtractor; when the M is equal to 1, the 1st stage delayer is configured to save the Extracted PDM audio signal;
  • the Mth stage subtractor is configured to subtract the extracted Mth PDM audio signal and the M-1th audio signal.
  • FIG. 6 is a schematic diagram of a two-stage cascade process of converting a PDM audio signal into a PCM audio signal; as shown in FIG. 6, the PDM audio signal sequentially passes through a two-stage integrator I, a downsampling extractor R, and a two-stage comb filter C. , converted to PCM audio signal.
  • the integrator I is composed of an integrator and a delay
  • the comb filter C is composed of a delayer and a subtractor.
  • FIG. 8 is a schematic flowchart of a PDM audio signal conversion method according to an embodiment of the present invention. As shown in FIG. 8, the method includes:
  • Step 101 The cascade integrator receives the pulse density modulated PDM audio signal, accumulates the PDM audio signal, and outputs the PDM audio signal accumulated by the integrators of each stage to the downsampler extractor.
  • the PDM audio signal is input from the cascade integrator, and after receiving the PDM audio signal, the integrators of each stage sequentially perform the accumulation processing on the PDM audio signal. Specifically, after the PDM audio signal is input from the cascade integrator, the current output of each stage integrator is equal to the current input and The sum of the last output.
  • Step 102 The downsampler decimator receives the accumulated PDM audio signal, and extracts the accumulated PDM audio signal at preset intervals.
  • the downsampling decimator receives the accumulated PDM audio signal output by the cascaded integrator, and performs an R-time downsampling extraction process on the accumulated PDM audio signal, and extracts data by R times down sampling.
  • the number becomes 1/R of the original number and the extracted PDM audio signal is obtained.
  • Step 103 The cascading comb filter receives the PDM audio signal extracted by the downsampled decimator, and performs subtraction on the extracted PDM audio signal, and obtains a pulse code modulated PCM audio signal after conversion.
  • the delay of the cascaded comb filter is greatly reduced due to the forward shift of the downsampled decimator, and the delay of the cascaded comb filter is the original delay and drop.
  • the PDM audio signal is input from the cascade integrator, and sequentially processed by the cascade integrator, the downsampling extractor, and the cascade comb filter, after the cascade comb filter Output.
  • this method by dropping the original cascaded comb filter
  • the processing of the sample decimator, from the last stage of the processing structure, is advanced to the middle of the cascade integrator and the cascade comb filter, so that the differential delay D of the cascade comb filter is only the original cascaded comb
  • the 1/R of the filtering structure reduces the number of cascaded stages of the comb filter, facilitating hardware implementation, simplifying the structure, and saving resources.
  • the delay of the cascade comb filter is a ratio of an original delay of the cascade comb filter to a down sample rate of the downsampler decimator.
  • the downsampling decimator receives the accumulated PDM audio signal, and extracts the accumulated PDM audio signal at a preset interval, specifically:
  • the downsampling decimator When n is equal to N*R, the downsampling decimator extracts the PDM audio signal accumulated by the nth stage integrator as the output of the downsampled decimator, otherwise, when n is not equal to N*R, the downsampling The output of the decimator is 0; where N is the clock frequency of the cascaded comb filter, R is R times downsampling, and n is the number of stages in which the integrator is located.
  • the clock frequency of the cascaded integrator is the product of the clock frequency of the cascaded comb filter and the downsampling rate.
  • the cascade comb filter includes an M-stage delayer and an M-stage subtractor; wherein the M is a positive integer;
  • the cascaded comb filter receives the PDM audio signal extracted by the downsampled decimator, and performs subtraction on the extracted PDM audio signal to obtain a pulse code modulated PCM audio signal:
  • the Mth stage subtractor subtracts the extracted Mth PDM audio signal and the extracted M-1th audio signal, and converts to obtain a pulse code modulated PCM audio signal, and
  • the operation result of the M-1th class subtractor is stored in the Mth stage delayer;
  • the PDM audio signal extracted by the downsampling decimator is saved in the first stage delayer.
  • the embodiment of the invention further describes a computer storage medium, wherein the computer storage medium stores a computer program for performing the pulse density modulation conversion method shown in FIG. 8 in the embodiment of the invention.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the differential sampling delay D of the cascaded comb filter is only 1/R of the original structure by moving the downsampling extractor R forward to the middle of the cascade integrator and the cascade comb filter. It simplifies the structural complexity of the original cascade comb filter, facilitates hardware circuit implementation, and reduces resource occupation.

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Abstract

一种脉冲密度调制转换电路、脉冲密度调制转换方法和存储介质,所述电路包括:级联积分器(11),降采样抽取器(12)和级联梳状滤波器(13);所述级联积分器(11)配置为接收脉冲密度调制PDM音频信号,并对所述脉冲密度调制PDM音频信号进行累加处理,输出各级积分器累加的脉冲密度调制PDM音频信号给所述降采样抽取器(12);所述降采样抽取器(12)配置为每隔预设间隔抽取所述累加的脉冲密度调制PDM音频信号;所述级联梳状滤波器(13)配置为接收所述降采样抽取器(12)抽取的脉冲密度调制PDM音频信号,并对所述抽取的脉冲密度调制PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。该电路简化了原级联梳状滤波器的结构复杂性,便于硬件电路实现,减少了资源的占用。

Description

脉冲密度调制转换电路及方法、存储介质
相关申请的交叉引用
本申请基于申请号为201610305551.8、申请日为2016年05月10日的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及信号处理技术,尤其涉及一种脉冲密度调制转换电路及方法、存储介质。
背景技术
数字麦克风是一种新型的将模拟音频信号转换为数字信号的处理装置,和模拟麦克风相比,具有抗干扰能力强、高信噪比、低失真度的优点。数字麦克风的输出信号一般是脉冲密度调制(pulse density modulation,PDM)的形式。但由于PDM格式的推广时间晚于脉冲编码调制(Pulse code modulation,PCM),造成目前大多数音频处理和播放设备都只支持PCM,所以从数字麦克风得到的PDM音频信号需要转换为PCM音频信号,以便常规的处理或应用。
现有的PDM转PCM的方法有级联积分梳状(cascade integrator comb,CIC)滤波,图1为现有的级联积分梳状(CIC)滤波结构示意图,如图1所示,该级联积分梳状(CIC)滤波由级联积分器n-1、级联梳状滤波器n-D、以及降采样抽取R组成。图2为现有的梳状滤波部分等效结构图,如图2所示,级联梳状滤波器n-D可以等效为多个延迟单元Z(图2中以32个延迟单元为例进行说明)。级联积分梳状(CIC)滤波中降采样率R等于级联梳状滤波器的 差分延时D。PDM音频信号从级联积分器之前输入,经过级联梳状滤波器和降采样抽取过程,从降采样抽取输出后,就转换为PCM音频信号。
由图2可知,现有的级联积分梳状(CIC)滤波中的级联梳状滤波器阶数较大,资源占用大。
发明内容
为解决上述技术问题,本发明实施例期望提供一种脉冲密度调制转换电路及方法、存储介质,用以简化滤波器结构,便于硬件电路实现,减少资源的占用。
本发明的技术方案是这样实现的:
本发明实施例提供一种脉冲密度调制转换电路,所述电路包括:级联积分器,降采样抽取器和级联梳状滤波器;
所述级联积分器配置为接收脉冲密度调制PDM音频信号,并对所述PDM音频信号进行累加处理,输出各级积分器累加的PDM音频信号给所述降采样抽取器;
所述降采样抽取器配置为每隔预设间隔抽取所述累加的PDM音频信号;
所述级联梳状滤波器配置为接收所述降采样抽取器抽取的PDM音频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。
上述方案中,所述级联梳状滤波器的时延为级联梳状滤波器的原延时与所述降采样抽取器的降采样率的比值。
上述方案中,所述各级积分器累加的PDM音频信号经所述降采样抽取器进行抽取后的输出为:
当n等于N*R时,输出为第n级积分器累加的PDM音频信号,否则,当n不等于N*R时,输出为0;其中,N为所述级联梳状滤波器的时钟频率, R表示R倍降采样,n为积分器所在的级数。
上述方案中,所述级联积分器的时钟频率为所述级联梳状滤波器的时钟频率和所述降采样率的乘积。
上述方案中,所述级联梳状滤波器包括M级延时器和M级减法器;其中,所述M为正整数;
当所述M大于等于2时,所述第M级延时器配置为保存第M-1级减法器的运算结果;当所述M等于1时,第1级延时器配置为保存所述抽取的PDM音频信号;
所述第M级减法器配置为将抽取的第M个PDM音频信号和第M-1个音频信号进行减法运算。
本发明实施例还提供一种脉冲密度调制转换方法,所述方法包括:
级联积分器接收脉冲密度调制PDM音频信号,对所述PDM音频信号进行累加处理并输出各级积分器累加的PDM音频信号给所述降采样抽取器;
降采样抽取器接收所述累加的PDM音频信号,并每隔预设间隔抽取所述累加的PDM音频信号;
级联梳状滤波器接收所述降采样抽取器抽取的PDM音频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。
上述方案中,所述级联梳状滤波器的时延为级联梳状滤波器的原延时与所述降采样抽取器的降采样率的比值。
上述方案中,所述降采样抽取器接收所述累加的PDM音频信号,并每隔预设间隔抽取所述累加的PDM音频信号具体为:
当n等于N*R时,所述降采样抽取器抽取第n级积分器累加的PDM音频信号作为所述降采样抽取器的输出,否则,当n不等于N*R时,所述降采样抽取器的输出为0;其中,N为所述级联梳状滤波器的时钟频率,R表 示R倍降采样,n为积分器所在的级数。
上述方案中,所述级联积分器的时钟频率为所述级联梳状滤波器的时钟频率和所述降采样率的乘积。
上述方案中,所述级联梳状滤波器包括M级延时器和M级减法器;其中,所述M为正整数;
相应的,级联梳状滤波器接收所述降采样抽取器抽取的PDM音频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号为:
当所述M大于等于2时,第M级减法器将抽取的第M个PDM音频信号和抽取的第M-1个音频信号进行减法运算,得到脉冲编码调制PCM音频信号,并将所述第M-1级减法器的运算结果保存在第M级延时器中;
当所述M等于1时,将所述降采样抽取器抽取的PDM音频信号保存在第1级延时器中。
本发明实施例提供了一种脉冲密度调制转换电路及方法、存储介质,包括级联积分器,降采样抽取器和级联梳状滤波器;该级联积分器配置为接收脉冲密度调制PDM音频信号,并对PDM音频信号进行累加处理,输出各级积分器累加的PDM音频信号给降采样抽取器;降采样抽取器配置为每隔预设间隔抽取累加的PDM音频信号,级联梳状滤波器配置为所述降采样抽取器抽取的PDM音频信号,并对抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。该转换电路通过将降采样抽取器R,前移到级联积分器和级联梳状滤波器中间,使得级联梳状滤波器的差分延时D仅为原结构的1/R,大大简化了原级联梳状滤波器的结构复杂性,便于硬件电路实现,减少了资源的占用。
附图说明
图1为现有的级联积分梳状(CIC)滤波结构示意图;
图2为现有的梳状滤波部分等效结构图;
图3为本发明实施例提供的PDM音频信号转换电路的示意图;
图4为本发明实施例提供的PDM音频信号转换电路包含的各组件的结构框图;
图5为本发明实施例提供的级联梳状滤波器的等效结构示意图;
图6为PDM音频信号转为PCM音频信号的二级级联流程示意图;
图7为PDM音频信号转为PCM音频信号的二级级联电路图;
图8为本发明实施例提供的PDM音频信号转换方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例的脉冲密度调制转换电路,将现有的级联积分梳状滤波中的降采样抽取部分,从处理结构的最后一级,前移到积分滤波和梳状滤波中间进行改进,这样改进后,梳状滤波的差分延时D仅为原结构的1/R,大大简化了梳状滤波器的结构复杂性。
图3为本发明实施例提供的PDM音频信号转换电路的示意图,图4为本发明实施例提供的PDM音频信号转换电路包含的各组件的结构框图,如图3和图4所示,该电路包括:
级联积分器11,降采样抽取器12和级联梳状滤波器13;
所述级联积分器11配置为接收脉冲密度调制PDM音频信号,并对所述PDM音频信号进行累加处理,输出各级积分器累加的PDM音频信号给所述降采样抽取器;
所述降采样抽取器12配置为每隔预设间隔抽取所述累加的PDM音频信号;
所述级联梳状滤波器13配置为接收所述降采样抽取器抽取的PDM音 频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。
需要说明的是,结合图3和图4可以看出,图3中的11对应图4中的级联积分器11,图3中的12对应图4中的降采样抽取器12,图3中的13对应图4中的级联梳状滤波器13。
具体的,PDM音频信号从级联积分器之前输入,经过降采样抽取器,从级联梳状滤波器之后输出。具体步骤如下:
(1)PDM音频信号从级联积分器之前输入,设级联积分器的时延为1,即每一级积分器的当前输出等于当前输入与上一次输出之和。即:
y(n)=x(n)+y(n-1)
其中,x(n)为级联积分器的第n级输入,y(n-1)为级联积分器的第(n-1)级输出,y(n)为级联积分器的第n级输出,1表示级联积分器的时延为1,n表示各个积分器所在的级数,n=1,2,3,…。
(2)经过步骤(1)处理后的PDM音频信号从级联积分器输出后,经过R倍降采样抽取器,数据个数变为原来个数的1/R,即降采样抽取器每隔预设间隔抽取累加值,这里预设间隔为N*R。降采样抽取器可以通过时钟频率的变化来实现:设级联积分器所用的工作时钟频率为T,级联梳状滤波器所用的工作时钟频率为N,并且满足n=T=N*R,那么进入级联梳状滤波器的数据个数,就是从级联积分器输出的数据个数的1/R。用公式表示如下:
Figure PCTCN2017083273-appb-000001
其中,N为级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的级数,n=N*R,n′为降采样抽取器的输出结果编号,n′=1,2…,y(n)为第n级积分器的输出,y(n′)为降采样抽取器的第n′个输出。
该公式表示,各级积分器累加的PDM音频信号经降采样抽取器进行抽 取后的输出为:
当n等于N*R时,输出为第n级积分器累加的PDM音频信号,否则,当n不等于N*R时,输出为0;其中,N为级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的级数。
(3)经过步骤(2)处理后的PDM音频信号从降采样抽取器输出后,进入级联梳状滤波器,级联梳状滤波器的时延由于降采样抽取器的前移而大大减小,例如,假设改进前级联梳状滤波器的时延为32,降采样率为32,那么输入输出关系表示为:
z(n″)=y(n′)-y(n′-32)
其中,y(n′)为降采样抽取器的第n′个输出,y(n′-32)为降采样抽取器的第(n′-32)个输出,z(n″)为级联梳状滤波器的第n″个输出,n″=1,2,…。
改进后级联梳状滤波器的时延为原时延与降采样抽取器的降采样率的比值,也就是1,输入输出关系表示为:
z(n″)=y(n′)-y(n′-1)
由此可知,改进后,级联梳状滤波器的时延由32降为1,即只需要保存至少一个数据,与改进前的需要保存至少32个数据相比,改进后级联梳状滤波器的时延减小了很多,在实际电路中意味着所需要保存数据的个数大大减小,也就简化了电路结构和占用的资源。
图4为本发明实施例提供的PDM音频信号转换电路包含的各组件的结构框图,如图4所示,该转换电路包括:级联积分器11,降采样抽取器12和级联梳状滤波器13。级联积分器11配置为接收PDM音频信号,并对该PDM音频信号进行累加处理,将各级积分器累加的PDM音频信号输出给降采样抽取器12;降采样抽取器12配置为每隔预设间隔抽取累加的PDM音频信号,并将抽取的PDM音频信号输出给级联梳状滤波器13进行处理,级联梳状滤波器13对抽取的PDM音频信号进行减法运算,得到PCM音频 信号。上述预设间隔根据系统和用户需求进行设置,此处不再赘述。
其中,级联积分器11的输入端接收PDM音频信号,级联积分器11的输出端和降采样抽取器12的输入端连接,降采样抽取器12的输出端和级联梳状滤波器13的输入端连接,级联梳状滤波器13的输出端输出PCM音频信号。
本实施例的脉冲密度调制转换电路,包括级联积分器,降采样抽取器和级联梳状滤波器;PDM音频信号从级联积分器之前输入,依次经过级联积分器、降采样抽取器、级联梳状滤波器处理后,从级联梳状滤波器之后输出。该电路中,通过将原级联积分梳状滤波中的降采样抽取器,从处理结构的最后一级,前移到级联积分器和级联梳状滤波器中间,使得级联梳状滤波器的差分延时D仅为原级联积分梳状滤波结构的1/R,减少了梳状滤波器的级联级数,方便硬件实现,简化结构,节省资源。
图5为本发明实施例提供的级联梳状滤波器的等效结构示意图,如图5所示,对比图2和图4可知,假设差分延时D和降采样倍数R均为32,则改进前的PDM音频信号转换电路需要32级延迟单元,而改进后PDM音频信号转换电路仅需要1级延迟单元。
通过验证,降采样抽取器12,在处理结构的最后一级所对应的系统函数,和在级联积分器11与级联梳状滤波器13中间所对应的系统函数,均等与同一个滑动平均滤波器的系统函数,所以通过将降采样抽取器12前移,既简化了电路结构,又可以保证处理效果和没有前移的相同。
进一步的,所述级联梳状滤波器的时延为级联梳状滤波器的原延时与所述降采样抽取器的降采样率的比值。
进一步的,所述各级积分器累加的PDM音频信号经所述降采样抽取器进行抽取后的输出为:
当n等于N*R时,输出为第n级积分器累加的PDM音频信号,否则, 当n不等于N*R时,输出为0;其中,N为所述级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的编号。
进一步的,所述级联积分器的时钟频率为所述级联梳状滤波器的时钟频率和所述降采样率的乘积。
进一步的,所述级联梳状滤波器包括M级延时器和M级减法器;其中,所述M为正整数;
当所述M大于等于2时,所述第M级延时器配置为保存第M-1级减法器的运算结果;当所述M等于1时,第1级延时器配置为保存所述抽取的PDM音频信号;
所述第M级减法器配置为将抽取的第M个PDM音频信号和第M-1个音频信号进行减法运算。
图6为PDM音频信号转为PCM音频信号的二级级联流程示意图;如图6所示,PDM音频信号依次经过两级积分器I、降采样抽取器R和两级梳状滤波器C后,转换为PCM音频信号。
图7为PDM音频信号转为PCM音频信号的二级级联电路图,如图7所示,积分器I由积分器和延时器组成,梳状滤波器C由延时器和减法器组成。
图8为本发明实施例提供的PDM音频信号转换方法的流程示意图,如图8所示,所述方法包括:
步骤101:级联积分器接收脉冲密度调制PDM音频信号,对PDM音频信号进行累加处理并输出各级积分器累加的PDM音频信号给降采样抽取器。
在本步骤中,PDM音频信号从级联积分器之前输入,各级积分器接收到该PDM音频信号后,依次对PDM音频信号进行累加处理。具体的,PDM音频信号从级联积分器输入后,每一级积分器的当前输出等于当前输入与 上一次输出之和。用公式y(n)=x(n)+y(n-1)来表示,其中,x(n)为级联积分器的第n级输入,y(n-1)为级联积分器的第(n-1)级输出,y(n)为级联积分器的第n级输出,1表示级联积分器的时延为1,n表示各个积分器所在的级数,n=1,2,3,…。
步骤102:降采样抽取器接收累加的PDM音频信号,并每隔预设间隔抽取累加的PDM音频信号。
在本步骤中,降采样抽取器接收上述级联积分器处理后输出的累加的PDM音频信号,并对该累加的PDM音频信号进行R倍降采样抽取过程,经过R倍降采样抽取,数据个数变为原来个数的1/R,并得到抽取的PDM音频信号。具体的降采样处理过程及输出结果在上述实施例中已详细说明,此处不再赘述。
步骤103:级联梳状滤波器接收降采样抽取器抽取的PDM音频信号,并对抽取的PDM音频信号进行减法运算,转换后得到脉冲编码调制PCM音频信号。
在本步骤中,级联梳状滤波器接收步骤102降采样抽取器抽取的PDM音频信号,并对该抽取的PDM音频信号经梳状滤波器处理,具体的对抽取的PDM音频信号按照公式z(n″)=y(n′)-y(n′-1)进行减法运算,得到PCM音频信号。其中,N为级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的级数,n=N*R,n′为降采样抽取器的输出结果编号,n′=1,2…,y(n)为第n级积分器的输出,y(n′)为降采样抽取器的第n′个输出。级联梳状滤波器的时延由于降采样抽取器的前移而大大减小,级联梳状滤波器的时延为原时延与降采样抽取器的降采样率的比值。
本实施例的脉冲密度调制转换方法,PDM音频信号从级联积分器之前输入,依次经过级联积分器、降采样抽取器、级联梳状滤波器处理后,从级联梳状滤波器之后输出。该方法中,通过将原级联积分梳状滤波中的降 采样抽取器的处理过程,从处理结构的最后一级,前移到级联积分器和级联梳状滤波器中间,使得级联梳状滤波器的差分延时D仅为原级联积分梳状滤波结构的1/R,减少了梳状滤波器的级联级数,方便硬件实现,简化结构,节省资源。
进一步的,所述级联梳状滤波器的时延为级联梳状滤波器的原延时与所述降采样抽取器的降采样率的比值。
进一步的,所述降采样抽取器接收所述累加的PDM音频信号,并每隔预设间隔抽取所述累加的PDM音频信号具体为:
当n等于N*R时,所述降采样抽取器抽取第n级积分器累加的PDM音频信号作为所述降采样抽取器的输出,否则,当n不等于N*R时,所述降采样抽取器的输出为0;其中,N为所述级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的级数。
进一步的,所述级联积分器的时钟频率为所述级联梳状滤波器的时钟频率和所述降采样率的乘积。
进一步的,所述级联梳状滤波器包括M级延时器和M级减法器;其中,所述M为正整数;
相应的,级联梳状滤波器接收所述降采样抽取器抽取的PDM音频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号为:
当所述M大于等于2时,第M级减法器将抽取的第M个PDM音频信号和抽取的第M-1个音频信号进行减法运算,转换后得到脉冲编码调制PCM音频信号,并将所述第M-1级减法器的运算结果保存在第M级延时器中;
当所述M等于1时,将所述降采样抽取器抽取的PDM音频信号保存在第1级延时器中。
本发明实施例还记载了一种计算机存储介质,所述计算机存储介质中存储有计算机程序,所述计算机程序用于执行本发明实施例中图8所示的脉冲密度调制转换方法。
本领域内的技术人员应明白,本发明的实施例可提供为方法、系统、或计算机程序产品。因此,本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且,本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器,使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中,使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品,该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上,使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理,从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述,仅为本发明的较佳实施例而已,并非用于限定本发明的保护范围。
工业实用性
本发明实施例通过将降采样抽取器R,前移到级联积分器和级联梳状滤波器中间,使得级联梳状滤波器的差分延时D仅为原结构的1/R,大大简化了原级联梳状滤波器的结构复杂性,便于硬件电路实现,减少了资源的占用。

Claims (11)

  1. 一种脉冲密度调制转换电路,所述电路包括:级联积分器,降采样抽取器和级联梳状滤波器;
    所述级联积分器配置为接收脉冲密度调制PDM音频信号,并对所述PDM音频信号进行累加处理,输出各级积分器累加的PDM音频信号给所述降采样抽取器;
    所述降采样抽取器配置为每隔预设间隔抽取所述累加的PDM音频信号;
    所述级联梳状滤波器配置为接收所述降采样抽取器抽取的PDM音频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。
  2. 根据权利要求1所述的电路,其中,所述级联梳状滤波器的时延为级联梳状滤波器的原延时与所述降采样抽取器的降采样率的比值。
  3. 根据权利要求2所述的电路,其中,所述各级积分器累加的PDM音频信号经所述降采样抽取器进行抽取后的输出为:
    当n等于N*R时,输出为第n级积分器累加的PDM音频信号,否则,当n不等于N*R时,输出为0;其中,N为所述级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的级数。
  4. 根据权利要求1所述的电路,其中,所述级联积分器的时钟频率为所述级联梳状滤波器的时钟频率和所述降采样抽取器的降采样率的乘积。
  5. 根据权利要求1~4任一项所述的电路,其中,所述级联梳状滤波器包括M级延时器和M级减法器;其中,所述M为正整数;
    当所述M大于等于2时,所述第M级延时器配置为保存第M-1级减法器的运算结果;当所述M等于1时,第1级延时器配置为保存所述抽取 的PDM音频信号;
    所述第M级减法器配置为将抽取的第M个PDM音频信号和第M-1个音频信号进行减法运算。
  6. 一种脉冲密度调制转换方法,所述方法包括:
    级联积分器接收脉冲密度调制PDM音频信号,对所述PDM音频信号进行累加处理并输出各级积分器累加的PDM音频信号给所述降采样抽取器;
    降采样抽取器接收所述累加的PDM音频信号,并每隔预设间隔抽取所述累加的PDM音频信号;
    级联梳状滤波器接收所述降采样抽取器抽取的PDM音频信号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号。
  7. 根据权利要求6所述的方法,其中,所述级联梳状滤波器的时延为级联梳状滤波器的原延时与所述降采样抽取器的降采样率的比值。
  8. 根据权利要求7所述的方法,其中,所述降采样抽取器接收所述累加的PDM音频信号,并每隔预设间隔抽取所述累加的PDM音频信号具体为:
    当n等于N*R时,所述降采样抽取器抽取第n级积分器累加的PDM音频信号作为所述降采样抽取器的输出,否则,当n不等于N*R时,所述降采样抽取器的输出为0;其中,N为所述级联梳状滤波器的时钟频率,R表示R倍降采样,n为积分器所在的级数。
  9. 根据权利要求6所述的方法,其中,所述级联积分器的时钟频率为所述级联梳状滤波器的时钟频率和所述降采样抽取器的降采样率的乘积。
  10. 根据权利要求6~9任一项所述的方法,其中,所述级联梳状滤波器包括M级延时器和M级减法器;其中,所述M为正整数;
    相应的,级联梳状滤波器接收所述降采样抽取器抽取的PDM音频信 号,并对所述抽取的PDM音频信号进行减法运算,得到脉冲编码调制PCM音频信号为:
    当所述M大于等于2时,第M级减法器将抽取的第M个PDM音频信号和抽取的第M-1个音频信号进行减法运算,得到脉冲编码调制PCM音频信号,并将所述第M-1级减法器的运算结果保存在第M级延时器中;
    当所述M等于1时,将所述降采样抽取器抽取的PDM音频信号保存在第1级延时器中。
  11. 一种计算机存储介质,所述计算机存储介质中存储有计算机程序,所述计算机程序用于执行前述权利要求6至10任一项所述的脉冲密度调制转换方法。
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