WO2017190544A1 - 一种数据传输线缆和数据传输方法 - Google Patents

一种数据传输线缆和数据传输方法 Download PDF

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Publication number
WO2017190544A1
WO2017190544A1 PCT/CN2017/074601 CN2017074601W WO2017190544A1 WO 2017190544 A1 WO2017190544 A1 WO 2017190544A1 CN 2017074601 W CN2017074601 W CN 2017074601W WO 2017190544 A1 WO2017190544 A1 WO 2017190544A1
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Prior art keywords
data transmission
control unit
output
data
handshake
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PCT/CN2017/074601
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English (en)
French (fr)
Inventor
崔云锋
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中兴通讯股份有限公司
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Publication of WO2017190544A1 publication Critical patent/WO2017190544A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a data transmission cable and a data transmission method.
  • the data transmitted under this structure is a parallel port protocol, so when the JTAG interface is transmitted to the logic device, the four data cable virtual JTAG interfaces of the parallel port are required to write the data into the logic device, but this scheme is There is only one data cable for actually transmitting data. It can be seen that the rate of writing data to the logic device is currently low.
  • an embodiment of the present invention provides a data transmission cable, including: a parallel port connector, a control unit, and a JTAG interface, where:
  • a first end of the parallel port connector is connected to a first end of the control unit, a second end of the parallel port connector is configured to connect an electronic device, and the parallel port connector is configured to receive the electronic device according to a parallel port protocol Transmitting data and transmitting to the control unit in accordance with the parallel port protocol The data;
  • the second end of the control unit is connected to the first end of the JTAG interface, the control unit is configured to receive the data transmitted by the parallel port connector, and convert the data transmission protocol into a JTAG protocol, Transmitting the converted data to the JTAG interface according to the JTAG protocol;
  • the second end of the JTAG interface is configured to connect logic
  • the JTAG interface is configured to receive the data transmitted by the control unit, and write the data to the logic device according to the JTAG protocol.
  • the third end of the control unit is connected to the first output device, and the control unit is further configured to transmit, by the parallel port connector, the first handshake signal to the electronic device, if the first handshake signal When the transmission is successful, transmitting, to the first output device, a first output signal indicating that the handshake with the electronic device is successful, the first output device is configured to output the first output signal;
  • a second output signal indicating that the handshake with the electronic device fails is transmitted to the first output device, and the first output device is configured to output the second output signal.
  • the fourth end of the control unit is connected to the second output device, and the control unit is further configured to transmit a second handshake signal to the logic device by using the JTAG interface, if the second handshake signal is transmitted Successfully transmitting a third output signal indicating successful handshake with the logic device to the second output device, the second output device being configured to display the third output signal; if the second handshake When the signal transmission fails, a fourth output signal indicating that the handshake with the logic device fails is transmitted to the second output device, and the second output device is configured to output the fourth output signal.
  • the fifth end of the control unit is connected to the third output device, and the control unit outputs a fifth output signal of the power supply connection to the third output device when the power source is connected, the third output device Arranging to output the fifth output signal; and/or, the sixth end of the control unit is connected to the fourth output device, and the control unit writes the data to the logic device Thereafter, the written sixth output signal is output to the fourth output device, and the fourth output device is configured to output the sixth output signal.
  • At least two select ends of the control unit are respectively connected to at least two selection devices, wherein a selection signal transmitted by each selection device to the control unit is used to select a transmission timing, the control unit And further configured to receive a selection signal transmitted by the target selection device of the at least two selection devices, and transmit the selected timing of the selection signal transmitted by the target selector to the JTAG interface according to a JTAG protocol data.
  • the first end of the parallel port connector is connected to one end of the surge protection circuit, and the other end of the surge protection circuit is connected to the first end of the control unit.
  • the second end of the control unit is connected to one end of the data transmission isolation circuit, and the other end of the data transmission isolation circuit is connected to the first end of the JTAG interface; or the second end of the control unit The end is connected to one end of the slow start circuit, and the other end of the slow start circuit is connected to the first end of the JTAG interface; or the second end of the control unit is connected to one end of the data transmission isolation circuit, the data The other end of the transmission isolation circuit is connected to one end of the slow start circuit, and the other end of the slow start circuit is connected to the first end of the JTAG interface; or the second end of the control unit is connected to one end of the slow start circuit The other end of the slow start circuit is connected to one end of the data transmission isolation circuit, and the other end of the data transmission isolation circuit is connected to the first end of the JTAG interface.
  • the embodiment of the invention further provides a data transmission method, including:
  • the data transmission cable receives data transmitted by the electronic device through a parallel port protocol
  • the data transmission cable converts the data transmission protocol into a JTAG protocol
  • the data transmission cable writes the data to the logic device in accordance with the JTAG protocol.
  • the method further includes: the data transmission cable and the electronic device transmitting a first handshake signal, if the first When the handshake signal is successfully transmitted, the data transmission cable outputs a first output signal indicating that the handshake with the electronic device is successful; if the first handshake signal fails to be transmitted The data transmission cable outputs a second output signal indicating that the handshake with the electronic device fails.
  • the method further includes: the data transmission cable and the logic device transmitting a second handshake signal, if When the second handshake signal is successfully transmitted, the data transmission cable outputs a third output signal indicating that the handshake with the logic device is successful; if the second handshake signal fails to transmit, the data transmission cable An output is used to indicate a fourth output signal that failed to handshake with the logic device.
  • Another embodiment of the present invention provides a computer storage medium, where the computer storage medium stores execution instructions for performing one or a combination of the steps in the foregoing method embodiments.
  • the data transmission cable of the embodiment of the present invention includes a control unit, and the control unit is respectively connected to the parallel port connector and the JTAG interface, the parallel port receiving electronic device transmission can be implemented.
  • the data can be transferred to the logic device according to the JTAG protocol.
  • the data can be written to the logic device by using the four data cable virtual JTAG interfaces in the related art, and the embodiment of the present invention can improve writing to the logic device.
  • the rate of the data is a control unit, and the control unit is respectively connected to the parallel port connector and the JTAG interface.
  • FIG. 1 is a schematic structural diagram of a data transmission cable according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another data transmission cable according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another data transmission cable according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another data transmission cable according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart diagram of a data transmission method according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a data transmission cable according to an embodiment of the present invention.
  • the data transmission cable 100 includes a parallel port connector 101, a control unit 102, and a JTAG interface 103, where:
  • the first end of the parallel port connector 101 is connected to the first end of the control unit 102, the second end of the parallel port connector 101 is configured to connect the electronic device, and the parallel port connector 101 is configured to receive data transmitted by the electronic device according to the parallel port protocol. And transmitting the data to the control unit 102 according to the parallel port protocol;
  • the second end of the control unit 102 is connected to the first end of the JTAG interface 103, and the control unit 102 is configured to receive the data transmitted by the parallel port connector 101, and convert the data transmission protocol into a JTAG protocol, which will be converted. Data is transmitted to the JTAG interface 103 in accordance with the JTAG protocol;
  • the second end of the JTAG interface 103 is configured to connect logic, and the JTAG interface 103 is configured to receive the data transmitted by the control unit 102 and to write the data to the logic device in accordance with the JTAG protocol.
  • the parallel port connector 101 can be a 25-pin parallel port connector, such as a DB25 parallel port connector.
  • the parallel port connector 101 can also be a parallel port connector of other pin numbers, for example: 24 pins or 36 pins.
  • the parallel port connector and the like are not limited in this embodiment.
  • the above electronic device may refer to a device capable of data transmission using a parallel port protocol, such as a computer, a server, or the like.
  • the parallel port connector 101 can be a parallel port connection with the electronic device.
  • control unit 102 may be a central processing unit (CPU), a single chip microcomputer (MCU), an FPGA, a CPLD, a system on chip (SoC), or a reduced instruction set processing.
  • CPU central processing unit
  • MCU single chip microcomputer
  • FPGA field-programmable gate array
  • SoC system on chip
  • the parallel port connector 101 is received at the control unit 102
  • the data transmission protocol is a parallel port protocol
  • the control unit 102 converts the data transmission protocol into a JTAG protocol, and transmits the converted data to the JTAG interface 103 according to the JTAG protocol.
  • the above data may be program code, so that when the program code is written into the logic device, the logic device can execute the program code.
  • the above logic device may be a logic device such as an FPGA or a CPLD.
  • the above writing can be understood as sintering or burning.
  • the ports of the various parts are described in the embodiment of the present invention, for example, the first end of the parallel port connector 101, the first end of the control unit 102, the second end of the parallel port connector 101, and the second end of the control unit 102.
  • the first end of the JTAG interface 103 and the second end of the JTAG interface 103 do not limit the number of pins of the port.
  • the second end of the parallel port connector 101 can be 25 pins, that is, 25 pins.
  • the port may be a bidirectional port, which is not limited in this embodiment.
  • the rate of data transmission can be increased, that is, the rate of writing data to the logic device is increased, and the control unit 102
  • the JTAG interface 103 and the logic device are transmitted using the JTAG protocol, so that the data cable virtual JTAG interface is not needed, and the rate of writing data to the logic device is further increased.
  • the timing virtualization is required to be completed in several cycles in the related art.
  • the JTAG protocol is directly used, so that the overall rate can be increased by more than ten times. Especially in the process of using the factory, the significance is very obvious. And greatly improve the success rate of data sintering, avoid the pain of repeated sintering, improve the production rate of one pass.
  • FIG. 2 is a schematic structural diagram of another data transmission cable according to an embodiment of the present invention.
  • the data transmission cable 200 includes a parallel port connector 201, a control unit 202, and a JTAG interface 203, where:
  • the first end of the parallel port connector 201 is connected to the first end of the control unit 202, and the second end of the parallel port connector 201 is configured to connect the electronic device, and the parallel port connector is configured to receive the electronic device
  • the data transmitted by the device according to the parallel port protocol, and the data is transmitted to the control unit 202 according to the parallel port protocol;
  • the second end of the control unit 201 is connected to the first end of the JTAG interface 203, and the control unit 202 is configured to receive the data transmitted by the parallel port connector, and convert the data transmission protocol into a JTAG protocol, which will be converted Data is transmitted to the JTAG interface according to the JTAG protocol;
  • a second end of the JTAG interface 203 is configured to connect to the logic device, the JTAG interface 203 being configured to receive the data transmitted by the control unit and to write the data to the logic device in accordance with the JTAG protocol.
  • the data transmission cable 200 may further include a first outputter 204, wherein the third end of the control unit 202 may be connected to the first output device 204, and the control unit 202 is further configured to be connected through the parallel port. And transmitting, by the electronic device, a first handshake signal, if the first handshake signal is successfully transmitted, transmitting, to the first output device 204, a first output signal indicating that the handshake with the electronic device is successful,
  • the first output device 204 is configured to output the first output signal;
  • the handshake signal can be understood as a handshake signal transmitted by the electronic device to the control unit 202 through the parallel port connector 201 when the parallel port connector 201 is connected to the electronic device. After receiving the handshake signal, the control unit 202 returns to the electronic device. Responding to the message or the confirmation message to determine the successful handshake; or the handshake signal transmitted by the control unit 202 to the electronic device through the parallel port connector 201, after receiving the handshake signal, the electronic device returns a response message or a confirmation message to the control unit 202 to determine The handshake was successful.
  • the first output device 204 may be a display device, such as an indicator light, such as an LED indicator.
  • the first output signal may be always on for the display device, and the second output signal may be blinking or the like. There is no limit here, just need to be able to distinguish.
  • the first output device 204 described above may also be an audio output device, such as a speaker, such that the handshake may succeed or fail through two different audio regions.
  • the first output device 204 it is possible to output a signal through the first output device 204 to prompt the user whether the handshake between the control unit 202 and the electronic device is successful, so that when the handshake fails, a prompt can be given immediately to enable the user to instantly find The connection between the data transmission cable 200 and the electronic device is faulty to prevent the user from finding the data write failure when using the logic device, thereby increasing the rate of data writing.
  • the data transmission cable 200 may further include a second outputter 205, wherein the fourth end of the control unit 202 is connected to the second output device 205, and the control unit is further configured to pass the JTAG interface with the
  • the logic device transmits a second handshake signal, and if the second handshake signal is successfully transmitted, transmitting, to the second output device 205, a third output signal indicating that the handshake with the logic device is successful, the second output
  • the device is configured to display the third output signal;
  • the data transmission cable 200 may further include: a third output device 206, the fifth end of the control unit 202 is connected to the third output device 206, and the control unit 202 may be connected to the third output device 206 when the power source is connected Fifth output signal of output power supply, third output The piece 206 outputs a fifth output signal to indicate that the power supply is successfully connected.
  • the third output device 206 can be understood as a power indicator light, and the indicator light indicates whether the power source is successfully connected.
  • the data transmission cable 200 may further include: a fourth output device 207, wherein the sixth end of the control unit 202 is connected to the fourth output device 207, and the control unit 202 may after the data writing logic device is completed, The sixth output signal that has been written is output to the fourth output device 207, and the fourth output device 207 outputs a sixth output signal to indicate that the data writing is completed.
  • the fourth output device 207 can be understood as a write indicator light, and the indicator light indicates whether the data is written or not, such as blinking during the writing process, and the display is always bright after the writing is completed.
  • the plurality of output devices connected by the control unit 202 may also be combined on the same device, for example, combined in a display screen, that is, each of the output devices described above may be a partial region in the display screen.
  • the data transmission cable 200 may further include at least two selection devices 208, wherein at least two selection ends of the control unit 202 are respectively connected to at least two selection devices 208, wherein each The selection signal transmitted by the selection device 208 to the control unit is used to select a transmission timing, and the control unit 202 is further configured to receive a selection signal transmitted by the target selection device in the at least two selection devices 208, and to target the target The selection timing of the selection signal transmitted by the selector transmits the data to the JTAG interface in accordance with the JTAG protocol.
  • the selection device 202 can be a switching device, that is, different transmission timings are selected by different switching devices, so that data can be written into the logic device through different transmission timings.
  • FIG. 3 is exemplified by setting four switching devices on the same device, that is, four different transmission timings can be realized. Since the logic devices of different manufacturers have different timing requirements in practical applications, in this implementation manner, the data transmission cable 200 can support the timing requirements of multiple manufacturers, so that the write data does not meet the timing. The speed reduction is used to increase the rate and success rate of write data at a time.
  • the data transmission cable 200 may further include a surge protection circuit 209, wherein the first end of the parallel port connector 201 is connected to one end of the surge protection circuit 209, and the surge protection The other end of the protection circuit 209 is connected to the first end of the control unit 201.
  • the surge protection circuit 209 can be composed of one or more of a Transient Voltage Suppressor (TVS), a varistor, and a dedicated surge protection device. Of course, the surge protection circuit 209 can also pass the light.
  • the implementation of the isolation device is not limited in this embodiment.
  • the surge protection circuit 209 eliminates surges generated by the parallel connector 201 during plugging and unplugging, such as high voltage, so that the surge can be prevented from causing damage to the data transmission cable 200. Improve the protection performance of the data transmission cable 200.
  • the data transmission cable 200 may further include a data transmission isolation circuit 2010 and/or a slow start circuit 2011, wherein the second end of the control unit 202 is connected to one end of the data transmission isolation circuit 2010.
  • the other end of the data transmission isolation circuit 2010 is connected to the first end of the JTAG interface 203; or
  • the second end of the control unit 202 is connected to one end of the slow start circuit 2011, and the other end of the slow start circuit 2011 is connected to the first end of the JTAG interface 203; or
  • the second end of the control unit 202 is connected to one end of the data transmission isolation circuit 2010, the other end of the data transmission isolation circuit 2010 is connected to one end of the slow start circuit 2011, and the other end of the slow start circuit 2011 is connected to the JTAG interface. Connecting the first end of 203; or
  • the second end of the control unit 203 is connected to one end of the slow start circuit 2011, the other end of the slow start circuit 2011 is connected to one end of the data transmission isolation circuit 2010, and the other end of the data transmission isolation circuit 2010 is connected to the JTAG interface.
  • the first end of 202 is connected.
  • the data transmission cable 200 shown in FIG. 5 includes an output device, a selection device, and a surge protection circuit, but these are optional for this embodiment.
  • the data transmission isolation circuit 2010 can be configured to protect the JTAG interface 202 of the data transmission cable 200.
  • the data transmission isolation circuit 2010 can be implemented by one or more of a TVS tube, a varistor, and a dedicated surge protection device, and can also be implemented by an isolation device such as an optocoupler, which is not limited in this embodiment.
  • the slow start circuit 2011 may be configured to prevent a large current surge to the upper circuit during the process of plugging and unplugging the data transmission cable 200, thereby causing damage to the power supply device to which the data transmission cable is connected.
  • the slow start circuit 2011 can be independently or combined by a MOS transistor, a triode, a slow start chip, etc., which is not limited in this embodiment.
  • a schematic flowchart of a data transmission method according to an embodiment of the present invention includes the following steps:
  • Step S601 The data transmission cable receives data transmitted by the electronic device through a parallel port protocol.
  • Step S602 The data transmission cable converts the data transmission protocol into a JTAG protocol.
  • Step S603 The data transmission cable writes the data to the logic device according to the JTAG protocol.
  • the method may further include:
  • the data transmission cable Transmitting, by the data transmission cable, the first handshake signal to the electronic device, if the first handshake signal is successfully transmitted, the data transmission cable outputs a first output signal indicating that the handshake with the electronic device is successful.
  • the data transmission cable outputs a second output signal indicating that the handshake with the electronic device fails.
  • the method may further include:
  • the data transmission cable and the logic device transmit a second handshake signal, and if the second handshake signal is successfully transmitted, the data transmission cable outputs a third output signal indicating that the handshake with the logic device is successful. ;
  • the data transmission cable outputs a fourth output signal indicating that the handshake with the logic device fails.
  • the data transmission cable may be any data transmission cable shown in FIG. 1 to FIG. 4 .
  • the data transmission cable may be any data transmission cable shown in FIG. 1 to FIG. 4 .
  • FIG. 1 to FIG. 4 For a specific implementation manner, refer to the related descriptions of FIG. 1 to FIG. 4, and details are not described herein again.
  • the data transmission cable receives the number of transmissions by the electronic device through the parallel port protocol.
  • the write data is transferred to the logic device, thereby increasing the rate of writing data to the logic device.
  • Embodiments of the present invention also provide a storage medium.
  • the foregoing storage medium stores an execution instruction, where the execution instruction is used to perform one or a combination of the steps in the foregoing method embodiments.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), and a Random Access Memory (RAM).
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • the data transmission cable of the embodiment of the present invention includes a control unit, and the control unit is respectively connected with the parallel port connector and the JTAG interface. Therefore, the parallel port protocol can receive the data transmitted by the electronic device, and the write data is transmitted to the logic device according to the JTAG protocol, and the data can be written into the logic device according to the virtual JTAG interface of the four data cables in the related art. Embodiments of the invention can increase the rate at which data is written to a logic device.

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Abstract

本发明实施例提供一种数据传输线缆和数据传输方法，该线缆可包括：并口连接器、控制单元和JTAG接口，其中：并口连接器的第一端与控制单元的第一端连接，并口连接器的第二端设置为连接电子设备，并口连接器设置为接收电子设备按照并口协议传输的数据，并按照并口协议向控制单元传输数据；控制单元的第二端与JTAG接口的第一端连接，控制单元设置为接收并口连接器传输的数据，并将数据的传输协议转换成JTAG协议，将转换后的数据按照JTAG协议向JTAG接口传输；JTAG接口的第二端设置为连接逻辑器件，JTAG接口设置为接收控制单元传输的数据，并按照JTAG协议向逻辑器件写入数据。本发明实施例可以提高向逻辑器件写入数据的速率。

Description

一种数据传输线缆和数据传输方法 技术领域
本发明实施例涉及通信技术领域，尤其涉及一种数据传输线缆和数据传输方法。
背景技术
随着电子技术的发展，目前逻辑器件使用越来越广泛，例如：现场可编程门阵列(Field Programmable Gate Array，FPGA)或者复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)等逻辑器件被广泛应用。这些逻辑器件在使用之前或者使用过程中往往需要将数据写入到逻辑器件中，逻辑器件再执行写入的数据。目前主要是使用联合测试工作组(Joint Test Action Group，JTAG)线缆将数据写入逻辑器件中。而目前的JTAG线缆的结构是并口连接器通过多根数据线缆与JTAG接口连接，其中，并口连接器与计算机连接，JTAG接口与逻辑器件连接。在这种结构下传输的数据是并口协议的，这样通过JTAG接口传输给逻辑器件时，需要使用并口的四根数据线缆虚拟JTAG接口，才可以将数据写入逻辑器件中，但这种方案中，实际传输数据的只有一根数据线缆。可见，目前向逻辑器件写入数据的速率低。
发明内容
本发明实施例的目的在于提供一种数据传输线缆和数据传输方法，解决了向逻辑器件写入数据的速率低的问题。
为了达到上述目的，本发明实施例提供一种数据传输线缆，包括：并口连接器、控制单元和JTAG接口，其中：
所述并口连接器的第一端与所述控制单元的第一端连接，所述并口连接器的第二端设置为连接电子设备，所述并口连接器设置为接收所述电子设备按照并口协议传输的数据，并按照所述并口协议向所述控制单元传输 所述数据；
所述控制单元的第二端与所述JTAG接口的第一端连接，所述控制单元设置为接收所述并口连接器传输的所述数据，并将所述数据的传输协议转换成JTAG协议，将转换后的数据按照所述JTAG协议向所述JTAG接口传输；
所述JTAG接口的第二端设置为连接逻辑器件，所述JTAG接口设置为接收所述控制单元传输的所述数据，并按照所述JTAG协议向所述逻辑器件写入所述数据。
可选地，所述控制单元的第三端与第一输出器件连接，所述控制单元还设置为通过所述并口连接器与所述电子设备传输第一握手信号，若所述第一握手信号传输成功时，则向所述第一输出器件传输用于表示与所述电子设备握手成功的第一输出信号，所述第一输出器件用于输出所述第一输出信号；若所述第一握手信号传输失败时，则向所述第一输出器件传输用于表示与所述电子设备握手失败的第二输出信号，所述第一输出器件用于输出所述第二输出信号。
可选地，所述控制单元的第四端与第二输出器件连接，所述控制单元还设置为通过所述JTAG接口与所述逻辑器件传输第二握手信号，若所述第二握手信号传输成功时，则向所述第二输出器件传输用于表示与所述逻辑器件握手成功的第三输出信号，所述第二输出器件设置为显示所述第三输出信号；若所述第二握手信号传输失败时，则向所述第二输出器件传输用于表示与所述逻辑器件握手失败的第四输出信号，所述第二输出器件设置为输出所述第四输出信号。
可选地，所述控制单元的第五端与第三输出器件连接，所述控制单元在电源连通时，向所述第三输出器件输出电源连通的第五输出信号，所述第三输出器件设置为输出所述第五输出信号；和/或，所述控制单元的第六端与第四输出器件连接，所述控制单元在所述数据写入所述逻辑器件完毕 后，向所述第四输出器件输出写入完毕的第六输出信号，所述第四输出器件设置为输出所述第六输出信号。
可选地，所述控制单元的至少两个选择端分别与至少两个选择器件连接，其中，每个选择器件向所述控制单元传输的选择信号用于选择一种传输时序，所述控制单元还设置为接收所述至少两个选择器件中的目标选择器件传输的选择信号，并以所述目标选择器传输的选择信号所选择的传输时序，且按照JTAG协议向所述JTAG接口传输所述数据。
可选地，所述并口连接器的第一端与浪涌保护电路的一端连接，所述浪涌保护电路的另一端与所述控制单元的第一端连接。
可选地，所述控制单元的第二端与数据传输隔离电路的一端连接，所述数据传输隔离电路的另一端与所述JTAG接口的第一端连接；或者，所述控制单元的第二端与缓启动电路的一端连接，所述缓启动电路的另一端与所述JTAG接口的第一端连接；或者，所述控制单元的第二端与数据传输隔离电路的一端连接，所述数据传输隔离电路的另一端与缓启动电路的一端连接，所述缓启动电路的另一端与所述JTAG接口的第一端连接；或者，所述控制单元的第二端与缓启动电路的一端连接，所述缓启动电路的另一端与数据传输隔离电路的一端连接，所述数据传输隔离电路的另一端与所述JTAG接口的第一端连接。
本发明实施例还提供一种数据传输方法，包括：
数据传输线缆接收电子设备通过并口协议传输的数据；
所述数据传输线缆将所述数据的传输协议转换成JTAG协议；
所述数据传输线缆按照所述JTAG协议向逻辑器件写入所述数据。
可选地，在所述数据传输线缆接收电子设备通过并口协议传输的数据之前，所述方法还包括：所述数据传输线缆与所述电子设备传输第一握手信号，若所述第一握手信号传输成功时，所述数据传输线缆输出用于表示与所述电子设备握手成功的第一输出信号；若所述第一握手信号传输失败 时，所述数据传输线缆输出用于表示与所述电子设备握手失败的第二输出信号。
可选地，在所述数据传输线缆按照所述JTAG协议向逻辑器件写入所述数据之前，所述方法还包括：所述数据传输线缆与所述逻辑器件传输第二握手信号，若所述第二握手信号传输成功时，所述数据传输线缆输出用于表示与所述逻辑器件握手成功的第三输出信号；若所述第二握手信号传输失败时，所述数据传输线缆输出用于表示与所述逻辑器件握手失败的第四输出信号。
本发明另一实施例提供了一种计算机存储介质，所述计算机存储介质存储有执行指令，所述执行指令用于执行上述方法实施例中的步骤之一或其组合。
上述技术方案中的一个技术方案具有如下优点或有益效果：由于本发明实施例的数据传输线缆包括控制单元，且控制单元分别连接并口连接器和JTAG接口，从而可以实现并口协议接收电子设备传输的数据，以及按照JTAG协议向逻辑器件传输写入数据，相比相关技术中使用四根数据线缆虚拟JTAG接口，才可以将数据写入逻辑器件，本发明实施例可以提高向逻辑器件写入数据的速率。
附图说明
图1为本发明实施例提供的一种数据传输线缆的结构示意图；
图2为本发明实施例提供的另一种数据传输线缆的结构示意图；
图3为本发明实施例提供的另一种数据传输线缆的结构示意图；
图4为本发明实施例提供的另一种数据传输线缆的结构示意图；
图5为本发明实施例提供的另一种数据传输线缆的结构示意图；
图6为本发明实施例提供的一种数据传输方法的流程示意图。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
如图1所示，本发明实施例提供的一种数据传输线缆的结构示意图，数据传输线缆100包括：并口连接器101、控制单元102和JTAG接口103，其中：
并口连接器101的第一端与控制单元102的第一端连接，并口连接器101的第二端设置为连接电子设备，并口连接器101设置为接收所述电子设备按照并口协议传输的数据，并按照所述并口协议向控制单元102传输所述数据；
控制单元102的第二端与JTAG接口103的第一端连接，控制单元102设置为接收并口连接器101传输的所述数据，并将所述数据的传输协议转换成JTAG协议，将转换后的数据按照所述JTAG协议向JTAG接口103传输；
JTAG接口103的第二端设置为连接逻辑器件，JTAG接口103设置为接收控制单元102传输的所述数据，并按照所述JTAG协议向所述逻辑器件写入所述数据。
本实施例中，并口连接器101可以是25针并口连接器，如DB25并口连接器，当然，在一些场景并口连接器101还可以是其他针数的并口连接器，例如：24针或者36针的并口连接器等，对此本实施例不作限定。
上述电子设备可以是指能够使用并口协议进行数据传输的设备，例如：电脑、服务器等设备。其中，并口连接器101可以是与电子设备的并口连接。
另外，上述控制单元102可以是中央处理器(Central Processing Unit，CPU)、单片微型计算机(Single Chip Microcomputer，MCU)、FPGA、CPLD、系统级芯片(System on Chip，SoC)或者精简指令集处理器(Advanced RISC Machine，ARM)等一系列的处理器或者控制器的一种或者组合，其中，上述MCU又可以理解为单片机。在控制单元102接收到并口连接器101 按照并口协议传输的上述数据时，该数据的传输协议为并口协议，控制单元102将该数据的传输协议转换成JTAG协议，并将转换后的数据按照JTAG协议向JTAG接口103传输。
另外，本实施例中，上述数据可以是程序代码，这样当程序代码写入到逻辑器件中后，逻辑器件就可以执行该程序代码。上述逻辑器件可以是FPGA或者CPLD等逻辑器件。另外，上述的写入可以理解为烧结或者烧写。
需要说明的是，本发明实施例中描述各个部分的端口，例如：并口连接器101的第一端、控制单元102的第一端、并口连接器101的第二端、控制单元102的第二端、JTAG接口103的第一端、JTAG接口103的第二端，对这些端口的引脚数量不作限定，例如：并口连接器101的第二端可以是25针，即25个引脚，另外，这里端口可以是双向端口，对此本实施例不作限定。
本实施例中，由于电子设备、并口连接器101和控制单元102之间是采用并口协议传输数据的，这样可以提高数据传输的速率，即提高向逻辑器件写入数据的速率，且控制单元102、JTAG接口103和逻辑器件之间是采用JTAG协议传输的，这样就不需要使用数据线缆虚拟JTAG接口，更进一步提高向逻辑器件写入数据的速率。例如：与相关技术中使用虚拟JTAG接口相比，由于相关技术中需要好几个周期才能完成时序虚拟，而本实施例中，直接使用JTAG协议，从而可以实现整体速率提高达到十几倍以上。尤其在工厂使用过程中，意义十分明显。并且大大的提高了数据烧结的成功率，避免重复烧结的痛苦，提高产线一次通过率。
如图2所示，本发明实施例提供的另一种数据传输线缆的结构示意图，数据传输线缆200包括：并口连接器201、控制单元202和JTAG接口203，其中：
并口连接器201的第一端与控制单元202的第一端连接，并口连接器201的第二端设置为连接电子设备，所述并口连接器设置为接收所述电子 设备按照并口协议传输的数据，并按照所述并口协议向所述控制单元202传输所述数据；
控制单元201的第二端与JTAG接口203的第一端连接，控制单元202设置为接收所述并口连接器传输的所述数据，并将所述数据的传输协议转换成JTAG协议，将转换后的数据按照所述JTAG协议向所述JTAG接口传输；
JTAG接口203的第二端设置为连接逻辑器件，所述JTAG接口203设置为接收所述控制单元传输的所述数据，并按照所述JTAG协议向所述逻辑器件写入所述数据。
可选的，数据传输线缆200还可以包括第一输出器204，其中，控制单元202的第三端可以与第一输出器204件连接，所述控制单元202还设置为通过所述并口连接器201与所述电子设备传输第一握手信号，若所述第一握手信号传输成功时，则向所述第一输出器件204传输用于表示与所述电子设备握手成功的第一输出信号，所述第一输出器件204设置为输出所述第一输出信号；
若所述第一握手信号传输失败时，则向所述第一输出器件204传输用于表示与所述电子设备握手失败的第二输出信号，所述第一输出器件设置为输出所述第二输出信号。
其中，上述握手信号可以理解为在并口连接器201与上述电子设备连接时，电子设备通过并口连接器201向控制单元202传输的握手信号，控制单元202接收到该握手信号后，向电子设备返回响应消息或者确认消息，以确定握手成功；或者控制单元202通过并口连接器201向电子设备传输的握手信号，电子设备接收到该握手信号后，向控制单元202返回响应消息或者确认消息，以确定握手成功。
另外，上述第一输出器件204可以是显示器件，例如：指示灯，如LED指示灯，其中，对于显示器件上述第一输出信号可以是常亮，上述第二输出信号可以是闪烁等，当然，这里不作限定，只需要能区分即可。当 然，上述第一输出器件204还可以是音频输出器件，例如：扬声器，这样可以通过两种不同的音频区域握手成功或者失败。
该实施方式中，可以实现通过第一输出器件204输出信号，以向用户提示控制单元202与电子设备之间的握手是否成功，这样当握手失败时，可即时给出提示，以使用户即时查找到数据传输线缆200与电子设备之间的连接故障，以避免用户在使用逻辑器件时，才发现数据写入失败，从而提高数据写入的速率。
可选的，数据传输线缆200还可以包括第二输出器205，其中，控制单元202的第四端与第二输出器件205连接，所述控制单元还设置为通过所述JTAG接口与所述逻辑器件传输第二握手信号，若所述第二握手信号传输成功时，则向所述第二输出器件205传输用于表示与所述逻辑器件握手成功的第三输出信号，所述第二输出器件设置为显示所述第三输出信号；
若所述第二握手信号传输失败时，则向所述第二输出器件205传输用于表示与所述逻辑器件握手失败的第四输出信号，所述第二输出器件205设置为输出所述第四输出信号。
其中，该实施方式中的握手信号的传输说明可以参见上面实施例的第一握手信号的相关说明，以及第二输出器件205的说明也可以参考上面实施例的第一输出器件204，此处不再赘述。
该实施方式中，可以实现通过第二输出器件205输出信号，以向用户提示控制单元202与逻辑器件之间的握手是否成功，这样当握手失败时，可即时给出提示，以使用户即时查找到数据传输线缆200与逻辑器件之间的连接故障，以避免用户在使用逻辑器件时，才发现数据写入失败，从而提高数据写入的速率。
可选的，数据传输线缆200还可以包括：第三输出器件206，控制单元202的第五端与第三输出器件206连接，控制单元202可以在电源连通时，可以向第三输出器件206输出电源连通的第五输出信号，第三输出器 件206输出第五输出信号，以提示电源连通成功。例如：第三输出器件206可以理解为电源指示灯，通过该指示灯指示电源是否连通成功。
可选的，数据传输线缆200还可以包括：第四输出器件207，其中，控制单元202的第六端与第四输出器件207连接，控制单元202可以在上述数据写入逻辑器件完毕后，向第四输出器件207输出写入完毕的第六输出信号，第四输出器件207输出第六输出信号，以提示数据写入完毕。例如：第四输出器件207可以理解为写入指示灯，通过该指示灯指示数据是否写入完成，如写入过程中显示闪烁，写入完毕后显示常亮等。
当然，在一些场景中控制单元202连接的多个输出器件还可以是结合在同一个器件上，例如：结合在一个显示屏，即上述每个输出器件可以该显示屏中的部分区域。
可选的，如图3所示，数据传输线缆200还可以包括至少两个选择器件208，其中，控制单元202的至少两个选择端分别与至少两个选择器件208连接，其中，每个选择器件208向所述控制单元传输的选择信号用于选择一种传输时序，控制单元202还设置为接收所述至少两个选择器件208中的目标选择器件传输的选择信号，并以所述目标选择器传输的选择信号所选择的传输时序，且按照JTAG协议向所述JTAG接口传输所述数据。
其中，上述选择器件202可以是开关器件，即通过不同的开关器件选择不同的传输时序，这样就可以实现通过不同的传输时序向逻辑器件中写入数据。其中，图3以4个开关器件设置在同一个器件上进行举例说明，即可以实现四4种不同的传输时序。由于在实际应用中，不同厂家的逻辑器件有不同的时序要求，这样该实施方式中，就可以实现数据传输线缆200支持多个厂家的时序要求，这样不会出现写入数据不符合时序时的降速使用，以提高了一次写入数据的速率和成功率。
可选的，如图4所示，数据传输线缆200还可以包括浪涌保护电路209，其中，并口连接器201的第一端与浪涌保护电路209的一端连接，浪涌保 护电路209的另一端与控制单元201的第一端连接。
其中，浪涌保护电路209可以通过瞬态抑制二极管(Transient Voltage Suppressor，TVS)、压敏电阻和专用的浪涌防护器件中的一个或者多个组成，当然，浪涌保护电路209还可以通过光耦等隔离器件实现，对此本实施例不作限定。
该实施方式中，通过浪涌保护电路209消除并口连接器201在插拔的过程中所产生的浪涌，如高电压，这样就可以实现避免浪涌对数据传输线缆200造成损坏，以提高提高数据传输线缆200的保护性能。
可选的，如图5所示，数据传输线缆200还可以包括数据传输隔离电路2010和/或缓启动电路2011，其中，控制单元202的第二端与数据传输隔离电路2010的一端连接，所述数据传输隔离电路2010的另一端与所述JTAG接口203的第一端连接；或者
控制单元202的第二端与缓启动电路2011的一端连接，缓启动电路2011的另一端与所述JTAG接口203的第一端连接；或者
控制单元202的第二端与数据传输隔离电路2010的一端连接，所述数据传输隔离电路2010的另一端与缓启动电路2011的一端连接，所述缓启动电路2011的另一端与所述JTAG接口203的第一端连接；或者
控制单元203的第二端与缓启动电路2011的一端连接，所述缓启动电路2011的另一端与数据传输隔离电路2010的一端连接，所述数据传输隔离电路2010的另一端与所述JTAG接口202的第一端连接。
需要说明的是，图5所示的数据传输线缆200包括了输出器件、选择器件和浪涌保护电路，但这些对于该实施方式来说，这些器件和电路是可选的。
其中，数据传输隔离电路2010可以设置为保护数据传输线缆200的JTAG接口202。其中，数据传输隔离电路2010可以通过TVS管、压敏电阻和专用的浪涌防护器件中的一个或者多个组成，同样还可以通过光耦等隔离器件实现，本实施例对此不作限定。
另外，缓启动电路2011可以设置为防止在插拔数据传输线缆200的过程中，对上级电路产生较大的电流冲击，从而导致数据传输线缆连接的电源器件的损坏。其中，缓启动电路2011可以通过MOS管、三极管、缓启动芯片等独立或者组合，本实施例对此不作限定。
如图6所示，本发明实施例提供的一种数据传输方法的流程示意图，包括以下步骤：
步骤S601、数据传输线缆接收电子设备通过并口协议传输的数据。
步骤S602、数据传输线缆将所述数据的传输协议转换成JTAG协议；
步骤S603、数据传输线缆按照所述JTAG协议向逻辑器件写入所述数据。
可选的，在所述数据传输线缆接收电子设备通过并口协议传输的数据之前，所述方法还可以包括：
所述数据传输线缆与所述电子设备传输第一握手信号，若所述第一握手信号传输成功时，所述数据传输线缆输出用于表示与所述电子设备握手成功的第一输出信号；
若所述第一握手信号传输失败时，所述数据传输线缆输出用于表示与所述电子设备握手失败的第二输出信号。
可选的，在所述数据传输线缆按照所述JTAG协议向逻辑器件写入所述数据之前，所述方法还可以包括：
所述数据传输线缆与所述逻辑器件传输第二握手信号，若所述第二握手信号传输成功时，所述数据传输线缆输出用于表示与所述逻辑器件握手成功的第三输出信号；
若所述第二握手信号传输失败时，所述数据传输线缆输出用于表示与所述逻辑器件握手失败的第四输出信号。
其中，上述数据传输线缆可以是图1至图4所示的任意数据传输线缆。其具体的实施方式可以参见图1至图4的相关说明，此处不再赘述。
本实施例中，由于数据传输线缆通过并口协议接收电子设备传输的数 据，以及按照JTAG协议向逻辑器件传输写入数据，从而可以提高向逻辑器件写入数据的速率。
本发明的实施例还提供了一种存储介质。可选地，在本实施例中，上述存储介质中存储有执行指令，该执行指令用于执行上述方法实施例中的步骤之一或其组合。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
工业实用性
如上所述，本发明实施例提供的一种数据传输线缆和数据传输方法具有以下有益效果：由于本发明实施例的数据传输线缆包括控制单元，且控制单元分别连接并口连接器和JTAG接口，从而可以实现并口协议接收电子设备传输的数据，以及按照JTAG协议向逻辑器件传输写入数据，相比相关技术中使用四根数据线缆虚拟JTAG接口，才可以将数据写入逻辑器件，本发明实施例可以提高向逻辑器件写入数据的速率。

Claims (10)

  1. 一种数据传输线缆，包括：并口连接器、控制单元和联合测试工作组JTAG接口，其中：
    所述并口连接器的第一端与所述控制单元的第一端连接，所述并口连接器的第二端设置为连接电子设备，所述并口连接器设置为接收所述电子设备按照并口协议传输的数据，并按照所述并口协议向所述控制单元传输所述数据；
    所述控制单元的第二端与所述JTAG接口的第一端连接，所述控制单元设置为接收所述并口连接器传输的所述数据，并将所述数据的传输协议转换成JTAG协议，将转换后的数据按照所述JTAG协议向所述JTAG接口传输；
    所述JTAG接口的第二端设置为连接逻辑器件，所述JTAG接口设置为接收所述控制单元传输的所述数据，并按照所述JTAG协议向所述逻辑器件写入所述数据。
  2. 如权利要求1所述的数据传输线缆，其中，所述控制单元的第三端与第一输出器件连接，所述控制单元还设置为通过所述并口连接器与所述电子设备传输第一握手信号，若所述第一握手信号传输成功时，则向所述第一输出器件传输用于表示与所述电子设备握手成功的第一输出信号，所述第一输出器件用于输出所述第一输出信号；
    若所述第一握手信号传输失败时，则向所述第一输出器件传输用于表示与所述电子设备握手失败的第二输出信号，所述第一输出器件用于输出所述第二输出信号。
  3. 如权利要求1或2所述的数据传输线缆，其中，所述控制单元的第四端与第二输出器件连接，所述控制单元还设置为通过所述JTAG接口与所述逻辑器件传输第二握手信号，若所述第二握手信号传输成功时，则向所述第二输出器件传输用于表示与所述逻辑器件握手成功的第三输出信号，所述第二输出器件设置为显示所述第三输出 信号；
    若所述第二握手信号传输失败时，则向所述第二输出器件传输用于表示与所述逻辑器件握手失败的第四输出信号，所述第二输出器件设置为输出所述第四输出信号。
  4. 如权利要求1或2所述的数据传输线缆，其中，所述控制单元的第五端与第三输出器件连接，所述控制单元在电源连通时，向所述第三输出器件输出电源连通的第五输出信号，所述第三输出器件设置为输出所述第五输出信号；和/或
    所述控制单元的第六端与第四输出器件连接，所述控制单元在所述数据写入所述逻辑器件完毕后，向所述第四输出器件输出写入完毕的第六输出信号，所述第四输出器件设置为输出所述第六输出信号。
  5. 如权利要求1或2所述的数据传输线缆，其中，所述控制单元的至少两个选择端分别与至少两个选择器件连接，其中，每个选择器件向所述控制单元传输的选择信号用于选择一种传输时序，所述控制单元还设置为接收所述至少两个选择器件中的目标选择器件传输的选择信号，并以所述目标选择器传输的选择信号所选择的传输时序，且按照JTAG协议向所述JTAG接口传输所述数据。
  6. 如权利要求1或2所述的数据传输线缆，其中，所述并口连接器的第一端与浪涌保护电路的一端连接，所述浪涌保护电路的另一端与所述控制单元的第一端连接。
  7. 如权利要求1或2所述的数据传输线缆，其中，所述控制单元的第二端与数据传输隔离电路的一端连接，所述数据传输隔离电路的另一端与所述JTAG接口的第一端连接；或者
    所述控制单元的第二端与缓启动电路的一端连接，所述缓启动电路的另一端与所述JTAG接口的第一端连接；或者
    所述控制单元的第二端与数据传输隔离电路的一端连接，所述数据传输隔离电路的另一端与缓启动电路的一端连接，所述缓启动电路的另一端与所述JTAG接口的第一端连接；或者
    所述控制单元的第二端与缓启动电路的一端连接，所述缓启动电路的另一端与数据传输隔离电路的一端连接，所述数据传输隔离电路的另一端与所述JTAG接口的第一端连接。
  8. 一种数据传输方法，包括：
    数据传输线缆接收电子设备通过并口协议传输的数据；
    所述数据传输线缆将所述数据的传输协议转换成JTAG协议；
    所述数据传输线缆按照所述JTAG协议向逻辑器件写入所述数据。
  9. 如权利要求8所述的方法，其中，在所述数据传输线缆接收电子设备通过并口协议传输的数据之前，所述方法还包括：
    所述数据传输线缆与所述电子设备传输第一握手信号，若所述第一握手信号传输成功时，所述数据传输线缆输出用于表示与所述电子设备握手成功的第一输出信号；
    若所述第一握手信号传输失败时，所述数据传输线缆输出用于表示与所述电子设备握手失败的第二输出信号。
  10. 如权利要求8或9所述的方法，其中，在所述数据传输线缆按照所述JTAG协议向逻辑器件写入所述数据之前，所述方法还包括：
    所述数据传输线缆与所述逻辑器件传输第二握手信号，若所述第二握手信号传输成功时，所述数据传输线缆输出用于表示与所述逻辑器件握手成功的第三输出信号；
    若所述第二握手信号传输失败时，所述数据传输线缆输出用于表示与所述逻辑器件握手失败的第四输出信号。
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