WO2017190425A1 - 栅极侧扇出区域电路 - Google Patents

栅极侧扇出区域电路 Download PDF

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Publication number
WO2017190425A1
WO2017190425A1 PCT/CN2016/089741 CN2016089741W WO2017190425A1 WO 2017190425 A1 WO2017190425 A1 WO 2017190425A1 CN 2016089741 W CN2016089741 W CN 2016089741W WO 2017190425 A1 WO2017190425 A1 WO 2017190425A1
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WIPO (PCT)
Prior art keywords
gate
circuit
chip
side fan
source
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Ceased
Application number
PCT/CN2016/089741
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English (en)
French (fr)
Inventor
黄笑宇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention generally relates to the field of liquid crystal panel display, and more particularly to a gate side fan-out area circuit.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD uses an active component such as a thin film transistor (TFT) to control the turning on and off of each pixel unit, and controls the transmittance of the liquid crystal material according to the image signal to display an image.
  • the liquid crystal display is provided with a display panel including a pixel array and a driving circuit for driving the liquid crystal display panel.
  • the display panel is provided with a plurality of parallel data lines and scan lines. The data lines and the scan lines are vertically interlaced with each other, and a pixel unit and a thin film transistor switch for controlling the pixel unit are disposed at the interlaced portion.
  • the driving circuit includes a source driver and a gate driver, the source driver provides a signal related to the display image, and the gate driver provides a signal for the scan line to turn on or off the thin film transistor.
  • FIG. 1 it is a schematic diagram of a TFT-LCD driving structure in the prior art.
  • the main driving principle of the existing TFT-LCD includes: the system motherboard passes the R/G/B signal, the control signal and the power through the wire and the PCB board 1 The connectors are connected, and the PCB board passes through S-COF (Source-Chip on Film) chip 2 and G-COF (Gate-Chip on Film) chip 3 The display area 4 is connected so that the LCD obtains the required power and signals.
  • S-COF Source-Chip on Film
  • G-COF Gate-Chip on Film
  • a fan out area 5 is a portion where the signal line of the display area 4 is connected to the driving chip, and the gate signal line and the source data line are connected to the S-COF chip 2 and G via the fan-out area 5.
  • the COF chip 3, the fan-out region 5 on the side of the gate drive chip G-COF chip 3, may be referred to as a gate side fan-out region.
  • the object of the present invention is to provide a gate side fan-out area circuit to solve the defects of the current PCB management cost and manufacturing cost, and can not meet the current requirements of reducing management costs and manufacturing costs.
  • An exemplary embodiment of the present invention provides a gate side fan-out area circuit including a gate chip group and a circuit module group, the gate chip group including N gate chips, wherein N is greater than or equal to a positive integer; the circuit module group generates and outputs a corresponding output signal according to an input signal provided by the N gate chips.
  • the timing controller of the display device detects an output signal generated from the circuit module group and controls a display mode of the display device based on the detected output signal.
  • the circuit module group includes N parallel circuit modules, each circuit module generates and outputs a corresponding output signal according to an input signal provided by a corresponding gate chip, wherein the N gate chips and the The N parallel circuit modules are in one-to-one correspondence.
  • each circuit module outputs the generated output signal to a corresponding source chip in the source chipset of the source side fan-out area, wherein the source chip set includes N source chips, the N The source chips are in one-to-one correspondence with the N parallel circuit modules.
  • the timing controller of the display device detects an output signal received by the source chip from the circuit module, and controls a display mode of the display device based on the detected output signal.
  • each of the N circuit modules is a switch, wherein each switch is turned on or off in response to an input signal provided by a corresponding gate chip.
  • the switch is an NMOS transistor.
  • the display device has N display modes.
  • each of the N gate chips is a gate chip on a thin film.
  • each of the N source chips is a thin film upper source chip.
  • the gate side fan-out area circuit provided by the exemplary embodiment of the present invention, not only the display mode of the display device can be automatically adjusted, but also the management cost and the manufacturing cost of the PCB are effectively reduced.
  • FIG. 1 is a schematic view showing the structure of a thin film transistor liquid crystal display in the prior art
  • FIG. 2 is a schematic structural view of a prior art heteromorphic thin film transistor liquid crystal display
  • FIG. 3 is a schematic structural view of another prior art heteromorphic thin film transistor liquid crystal display
  • FIG. 4 illustrates a block diagram of a gate side fanout area circuit in accordance with an exemplary embodiment of the present invention
  • FIG. 5 illustrates an example of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention
  • FIG. 6 illustrates a schematic diagram of signals detected by a timing controller in one cycle, according to an exemplary embodiment of the present invention
  • FIG. 7 illustrates another example of a gate side fan-out region circuit according to an exemplary embodiment of the present invention.
  • FIG. 8 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention
  • FIG. 9 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention.
  • FIG. 4 illustrates a block diagram of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention.
  • a gate side fan-out area circuit includes a gate chip group 10 and a circuit module group 20, wherein the gate chip group 10 includes N gate chips, wherein , N is a positive integer greater than or equal to 2.
  • the gate chip group 10 includes N gate chips, wherein , N is a positive integer greater than or equal to 2.
  • each of the N gate chips is a thin film on-film chip.
  • the circuit module group 20 generates and outputs a corresponding output signal according to an input signal provided by the N gate chips. The output signal can be used to control the display mode of the display device.
  • the timing controller disposed on the PCB of the display device can detect the slave circuit module group. 20 generating an output signal and controlling a display mode of the display device based on the detected output signal.
  • FIG. 5 illustrates an example of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention.
  • the gate chip group 10 included in the gate side fan-out area circuit includes three gate chips (such as G-COF1 - G-COF3 in FIG. 5), and the circuit module group 20 may include A wire A and a resistor R, wherein the wire A is a trace of the gate side fan-out area, and one end of the wire A passes through the source chip of the source side fan-out area (for example, a thin film on the source chip) and timing The controllers are connected, the other end of the wire A is grounded via a resistor R, and the output pins a, b and c of the gate chip G-COF1 - G-COF3 are respectively connected to the wire A.
  • the gate chip group 10 may include not only three gate chips but also more or less, but at least two.
  • the output pins a, b, and c of the G-COF1 - G-COF3 simultaneously output the vertical scanning signal and the gate chip G-COF1 -
  • the output of the G-COF3 is turned on to the display area, where the vertical scan signal is the same as the turn-on signal of the display area.
  • the circuit module group 20 can generate and output a corresponding output signal according to a signal provided by the gate chip G-COF1 - G-COF3, and the timing controller T-CON can be based on an output signal generated from the circuit module group 20 received via the source chip. To control the display mode of the display device.
  • the signal output from the wire A to the timing controller in one scanning period is as shown in (a) of FIG. 6, that is, three in one scanning period.
  • the square wave output (for example, three 33V square waves), at this time, the timing controller sets the display mode of the display device to the normal display mode based on the detected three square wave signals.
  • the signal output from the wire A to the timing controller in one scanning period is as shown in (b) of FIG. 6, and the wire A is in one scanning cycle.
  • There are two square wave outputs for example, two 33V square waves).
  • the timing controller T-CON sets the display mode of the display device to the vertical resolution based on the detected two square wave signals. Reduce to the original one-third of the alien display mode.
  • the signal output from the wire A to the timing controller in one scanning period is as shown in (c) of FIG. 6, and the wire A is in one scanning cycle.
  • a square wave output for example, a 33V square wave.
  • the timing controller T-CON sets the display mode of the display device to the vertical resolution based on the detected square wave signal. Two-thirds of the alien display mode.
  • the timing controller can set different display modes accordingly based on the detected number of high-voltage square wave signals, so that the architectures of the plurality of display devices can share the same PCB, thereby improving the PCB.
  • the commonality reduces management costs.
  • FIG. 7 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention.
  • the gate chip group 10 included in the gate side fan-out area circuit includes three gate chips (such as G-COF1 - G-COF3 in FIG. 7), and the circuit module group 20 may include Two wires A and B and two resistors R1 and R2 of the same resistance, wherein wires A and B are traces of the fan-side fan-out region, and one ends of wires A and B pass through the source-side fan-out region
  • the source chip is connected to the timing controller on the PCB board (not shown in FIG. 7), the other end of the wire A is connected to the output pin b of the gate chip G-COF2, and the output of the gate chip G-COF1 is cited.
  • the pin a is connected in series with the resistor R1 to the wire A, and the other end of the wire B is grounded via the resistor R2.
  • the gate chip group 10 according to the present example may include not only three gate chips but also more or less, but at least two.
  • the circuit module group 20 can generate and output a corresponding output signal according to a signal provided by the gate chip G-COF1 - G-COF3, and the timing controller T-CON can be based on the slave circuit module group 20 received via the source chip.
  • the resulting output signal controls the display mode of the display device.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 1, when the output signal generated by the timing controller via the source chip is a low level signal and a high level signal, the timing controller is based on The detected low level signal and high level signal will display the display mode of the device Set to normal display mode.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 2, when the output signal generated by the timing controller via the source chip from the circuit module 20 is two low level signals, the timing controller is based on The two low-level signals detected set the display mode of the display device to a profile display mode in which the vertical resolution is reduced to one-third of the original.
  • the timing controller sets the display mode of the display device to a profile display mode in which the vertical resolution is reduced to two-thirds of the original based on the detected high level signal and low level signal.
  • the timing controller can set different display modes accordingly based on the output signals generated by the detected circuit module group 20, so that the architectures of the plurality of display devices can share the same PCB. Improve PCB sharing and reduce management costs.
  • FIG. 8 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention.
  • the gate chip group 10 included in the gate side fan-out area circuit includes three gate chips (such as G-COF1 - G-COF3 in FIG. 8), and the circuit module group 20 may include Three wires A, B and C and resistors R1, R2 and R3 in series with wires A, B and C, respectively, wherein wires A, B and C are traces of the fan-side fan-out area, wires A, B and C One end of each of the wires is connected to the timing controller on the PCB (not shown in FIG. 8) through the source chip of the source side fan-out area, and the other ends of the wires A, B, and C are respectively connected in series with each of the wires.
  • the resistor is grounded.
  • the output pin a of the gate chip G-COF1 is connected to the wire A
  • the output pin b of the gate chip G-COF2 is connected to the wire B
  • the output pin c of the gate chip G-COF3 is connected to the wire C.
  • the gate chip group 10 according to the present example may include not only three gate chips but also more or less, but at least two.
  • the circuit module group 20 can generate and output a corresponding output signal according to an output signal provided by the gate chip G-COF1 - G-COF3, and the timing controller can be generated based on the slave circuit module group 20 received via the source chip.
  • the output signal is used to control the display mode of the display device.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 1 , when the output signal generated by the timing controller via the source chip from the circuit module 20 is three high level signals, the timing controller is based on detecting The three high level signals set the display mode of the display device to the normal display mode.
  • the output signals generated from the circuit module 20 received by the timing controller via the source chip are a high level signal, a high level signal, and a low level.
  • the timing controller sets the display mode of the display device to a profile display mode in which the vertical resolution is reduced to one-third of the original based on the detected high level signal, high level signal, and low level signal.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 3, when the timing controller generates an output signal from the circuit module group 20 via the source chip as three low level signals, the timing controller Setting the display mode of the display device to be vertical based on the detected three low level signals Straight resolution is reduced to the original two-thirds of the alien display mode.
  • the timing controller can set different display modes accordingly based on the output signals generated by the detected circuit module group 20, so that the architectures of the plurality of display devices can share the same PCB. Improve PCB sharing and reduce management costs.
  • the circuit module group includes N parallel circuit modules, each circuit module generates and outputs a corresponding output signal according to an input signal provided by a corresponding gate chip, wherein the N gates The chip has a one-to-one correspondence with the N parallel circuit modules.
  • each circuit module generates and outputs a corresponding output signal according to an input signal provided by a corresponding gate chip.
  • each of the gate chips in the gate chip set is a thin film on-film chip
  • each of the N circuit modules is a switch, wherein each switch is responsive to a corresponding gate
  • the input signal provided by the chip is turned on or off.
  • the output signal can be output to a source chipset for controlling a display mode of the display device.
  • the source chipset may include N source chips, where each of the N source chips may be a thin film source chip.
  • the N source chips are in one-to-one correspondence with the N parallel circuit modules, and each circuit module can output the generated output signals to corresponding source chips in the source chip group of the source side fan-out area.
  • the timing controller of the display device detects an output signal received by the source chip from the circuit module, and controls a display mode of the display device based on the detected output signal.
  • the display device may have N display modes.
  • the circuit module can generate and output a corresponding output signal according to the input signal, thereby causing the timing controller to set a display mode that matches the current display device architecture based on the output signal.
  • FIG. 9 illustrates an example of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention.
  • each circuit module in the circuit module group may be a switch
  • each switch can be turned on or off in response to an input signal provided by its corresponding gate chip, for example, when the switch is an NMOS transistor, when the input signal is a high level signal, the NMOS transistor Turn on.
  • the circuit module group 20 includes three parallel circuit modules, and of course, more or less, but at least two or more. Those skilled in the art will appreciate that other circuit modules that can perform similar functions are also suitable for use in the present invention. Further, as an example, the three gate chips and three switches one-to-one corresponding to the three gate chips may be disposed in a gate-side fan-out region of the liquid crystal display device.
  • the gates a1-a3 of each of the switches are respectively connected to the output pins A1-A3 of the corresponding gate chip G-COF1_G-COF3, for example, the gate chip G-COF1
  • the A1 output pin is connected to the gate a1 of the switch M1 corresponding to the gate chip G-COF1
  • the gate chip G-COF2 The A2 output pin is connected to the gate a2 of the switch M2 corresponding to the gate chip G-COF2
  • the A3 output pin of the gate chip G-COF3 is connected to the gate a3 of the switch M3 corresponding to the gate chip G-COF3.
  • the sources b1-b3 of the switches M1-M3 are respectively connected to corresponding source chips in the source chipset of the source fan-out region, for example, the source b1 of the switch M1 is connected to the source chip S-COF1.
  • the input pin d1, the source b2 of the switch M1 is connected to the input pin d2 of the source chip S-COF2, and the source b3 of the switch M3 is connected to the input pin d3 of the source chip S-COF3.
  • the input pin k of the timing controller T-CON is connected to the output pins e1-e3 of the source chip S-COF1_S-COF3, respectively, and the drains c1-c3 of the switches M1-M3 are grounded.
  • the resistor R in FIG. 9 is an equivalent resistance when the NMOS is turned on.
  • the gate chip can send an input signal to the corresponding switch, the switch is turned on or off according to the input signal sent by the gate chip, and outputs the generated corresponding output signal to the source of the source side fan-out area.
  • the chip, the timing controller of the display device detects the output signal received by the source chip from the switch, and sets a display mode suitable for the current liquid crystal display device architecture based on the detected output signal.
  • FIG. 1 the architecture of a standard thin film transistor liquid crystal display in the prior art is shown in FIG. 1.
  • the gate chip G-COF1 passes through the output pin A1 to the gate of the switch M1.
  • the pole a1 sends a high level signal
  • the G-COF2 sends a high level signal to the gate a2 of the switch M2 through the output pin A2
  • the G-COF3 sends a high level signal to the gate a3 of the switch M3 through the output pin A3.
  • the output signals transmitted to the source chips S-COF1, S-COF2, and S-COF3 through the sources b1-b3 are a low level signal, a low level signal, and a low level signal.
  • the timing controller T-CON detects three low-level signals received from the switches M1, M2, and M3, and sets the display mode of the display device to the normal display mode based on the detected three signals.
  • the gate chip G-COF1 sends a high level signal to the gate a1 of the switch M1 through the output pin A1, and the G-COF2 passes through the output pin.
  • A2 sends a high level signal to the gate a2 of the switch M2, and the gate a3 of M3 does not receive the input signal, then the switches M1, M2 are turned on, and M3 is turned off, and then transmitted to the source chip S through the source b1-b3.
  • the output signals of COF1, S-COF2 and S-COF3 are low level signal, low level signal and high level signal.
  • the timing controller T-CON detects low voltage received from switches M1, M2 and M3.
  • the flat signal, the low level signal, and the high level signal, and based on the detected three signals, the display mode of the display device is set to a vertical display mode in which the vertical resolution is reduced to one-third of the original.
  • the gate chip G-COF1 transmits a high level signal, a gate a2 of M2 and M3 to the gate a1 of the switch M1 through the output pin A1. And a3 does not receive the input signal, then the switch M1 is turned on, and M2 and M3 are turned off, then the output signals transmitted to the source chips S-COF1, S-COF2 and S-COF3 through the sources b1-b3 are low-level signals. High level signal and high level signal.
  • the display mode is set to reduce the vertical resolution to the original two-thirds of the alien display mode.
  • the gate side fan-out area circuit can not only automatically adjust the display mode of the display device, but also effectively reduce the management cost and manufacturing cost of the PCB.

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Abstract

一种栅极侧扇出区域电路，包括栅极芯片组（10）和电路模块组（20），栅极芯片组（10）包括N个栅极芯片，其中，N为大于等于2的正整数；电路模块组（20）根据N个栅极芯片提供的输入信号产生并输出相应的输出信号。根据该电路，能够提高PCB印刷电路板的共用性，降低管理成本。

Description

栅极侧扇出区域电路 技术领域
本发明总体说来涉及液晶面板显示领域，更具体地讲，尤其涉及一种栅极侧扇出区域电路。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。TFT-LCD使用薄膜晶体管(thin-film transistor，TFT)等主动式组件来控制每一像素单元的开启与关闭，并根据影像信号来控制液晶材质对光线的穿透率以显示影像。液晶显示器上设有包含像素阵列的显示面板及用来驱动液晶显示面板的驱动电路。显示面板上设有多条平行的数据线和扫描线，数据线和扫描线彼此垂直交错，且在交错处设有像素单元及控制像素单元的薄膜晶体管开关。驱动电路包含源极驱动器与栅极驱动器，源极驱动器提供数据线相关于显示影像的信号，而栅极驱动器提供扫描线开启或关闭薄膜晶体管的讯号。
如图1所示，其为现有技术中TFT-LCD驱动架构示意图，现有TFT-LCD主要驱动原理包括：系统主板将R/G/B信号、控制信号及动力通过线材与PCB板1上的连接器(connector)相连接，PCB板通过S-COF(Source-Chip on Film，薄膜上源极芯片)芯片2和G-COF(Gate-Chip on Film，薄膜上栅极芯片)芯片3与显示区域(Display Area)4连接，从而使得LCD获得所需的电源、以及信号。为了实施窄边框设计，并响应电子产品朝轻薄短小、功能好及速度快发展，驱动芯片封装的技术也朝向厚度愈薄、面积愈小的趋势发展，栅极芯片及源极芯片都采用了薄膜上芯片(Chip on Film，COF)型封装方式。图1中可见，扇出区域(Fan Out Area)5是显示区域4信号线路与驱动芯片连接的部分，栅极信号线及源极数据线经由扇出区域5连接至S-COF芯片2和G-COF芯片3，位于栅极驱动芯片G-COF芯片3一侧的扇出区域5可以称为栅极侧扇出区域。
但是，随着显示技术的发展，异形屏开始应用于商用显示中，由于异形屏其长宽与传统设计不同(例如，如图2和图3所示的异形屏)，因此，会导致异形屏的分辨率与传统设计的液晶显示装置的分辨率不同，因此，为了配合异形屏显示需要用户手动调整设置于与传统设计的液晶显示面板匹配的PCB板1 上的时序控制器(T-CON)的显示模式，或者，搭配针对异形屏的PCB，但是通过上述方式造成了PCB的管理成本和制作成本的提高，无法适应目前降低管理成本和制作成本的需求。
发明内容
有鉴于此，本发明目的是提供一种栅极侧扇出区域电路，以解决现有的PCB的管理成本和制作成本较高，无法适应目前降低管理成本和制作成本的需求的缺陷。
本发明示例性实施例提供栅极侧扇出区域电路，其特征在于，包括栅极芯片组和电路模块组，所述栅极芯片组包括N个栅极芯片，其中，N为大于等于2的正整数；所述电路模块组根据所述N个栅极芯片提供的输入信号产生并输出相应的输出信号。
可选地，显示装置的时序控制器侦测从电路模块组产生的输出信号，并基于侦测到的输出信号来控制显示装置的显示模式。
可选地，所述电路模块组包括N个并联的电路模块，每个电路模块根据相应的栅极芯片提供的输入信号产生并输出相应的输出信号，其中，所述N个栅极芯片与所述N个并联的电路模块一一对应。
可选地，每个电路模块将产生的输出信号输出到源极侧扇出区域的源极芯片组中的相应的源极芯片，其中，源极芯片组包括N个源极芯片，所述N个源极芯片与所述N个并联的电路模块一一对应。
可选地，显示装置的时序控制器侦测源极芯片从电路模块接收的输出信号，并基于侦测到的输出信号来控制显示装置的显示模式。
可选地，所述N个电路模块中的每个电路模块为一个开关，其中，每个开关响应于相应的栅极芯片提供的输入信号导通或截止。
可选地，所述开关为NMOS晶体管。
可选地，所述显示装置具有N种显示模式。
可选地，所述N个栅极芯片中的每个栅极芯片为薄膜上栅极芯片。
可选地，所述N个源极芯片中的每个源极芯片为薄膜上源极芯片。
根据本发明示例性实施例提供的栅极侧扇出区域电路，不仅可以自动地调整显示装置的显示模式，还有效地降低了PCB的管理成本和制作成本。
附图说明
通过下面结合附图进行的详细描述，本发明示例性实施例的上述和其它目的、特点和优点将会变得更加清楚，其中：
图1示出现有技术中薄膜晶体管液晶显示器的架构示意图；
图2示出一个现有技术中异形薄膜晶体管液晶显示器的架构示意图；
图3示出另一个现有技术中异形薄膜晶体管液晶显示器的架构示意图；
图4示出根据本发明示例性实施例的栅极侧扇出区域电路的框图；
图5示出根据本发明示例性实施例的栅极侧扇出区域电路的示例；
图6示出根据本发明示例性实施例的在一个周期内时序控制器侦测的信号的示意图；
图7示出另一根据本发明示例性实施例的栅极侧扇出区域电路的示例；
图8示出根据本发明另一示例性实施例的栅极侧扇出区域电路的示例；
图9示出根据本发明另一示例性实施例的栅极侧扇出区域电路的示例。
具体实施方式
现在，将参照附图更充分地描述不同的示例实施例，其中，一些示例性实施例在附图中示出，其中，相同的标号始终表示相同的部件。
图4示出根据本发明示例性实施例的栅极侧扇出区域电路的框图。
如图4所示，根据本发明示例性实施例的栅极侧扇出区域电路包括栅极芯片组10和电路模块组20，其中，所述栅极芯片组10包括N个栅极芯片，其中，N为大于等于2的正整数。这里，作为示例，所述N个栅极芯片中的每个栅极芯片均为薄膜上栅极芯片。具体说来，所述电路模块组20根据所述N个栅极芯片提供的输入信号产生并输出相应的输出信号。所述输出信号可用于控制显示装置的显示模式。
此外，作为示例，当电路模块组20根据所述N个栅极芯片提供的输入信号产生并输出相应的输出信号后，设置于显示装置的PCB板上的时序控制器可侦测从电路模块组20产生的输出信号，并基于侦测到的输出信号来控制显示装置的显示模式。
图5示出根据本发明示例性实施例的栅极侧扇出区域电路的示例。
如图5所示，假设栅极侧扇出区域电路所包括的栅极芯片组10包括三个栅极芯片(如图5中G-COF1—G-COF3)，所述电路模块组20可以包括一根导线A和电阻R，其中，导线A为栅极侧扇出区域的走线，导线A的一端通过源极侧扇出区域的源极芯片(例如，一个薄膜上源极芯片)与时序控制器相连接，导线A的另一端经过电阻R接地，栅极芯片G-COF1—G-COF3的输出引脚a、b和c分别连接至导线A。这里，应理解，根据本示例中的栅极芯片组10不仅可包括三个栅极芯片，也可以更多或更少，但至少包括两个。
具体说来，当垂直扫描信号传输至栅极芯片G-COF1—G-COF3时，G-COF1—G-COF3的输出引脚a、b和c同时输出垂直扫描信号和栅极芯片G-COF1— G-COF3的输出至显示区的开启信号，这里，所述垂直扫描信号与显示区的开启信号相同。电路模块组20可根据栅极芯片G-COF1—G-COF3提供的信号产生并输出相应的输出信号，时序控制器T-CON可基于经由源极芯片接收的从电路模块组20产生的输出信号来控制显示装置的显示模式。
例如，当薄膜晶体管液晶显示器的架构如图1所示时，导线A在一个扫描周期内输出至时序控制器的信号如图6中的(a)所示，即，在一个扫描周期内有三个方波输出(例如，三个33V的方波)，此时，时序控制器基于侦测到的这三个方波信号将显示装置的显示模式设定为正常显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图2所示时，导线A在一个扫描周期内输出至时序控制器的信号如图6中的(b)所示，导线A在一个扫描周期内有两个方波输出(例如，两个33V的方波)，此时，时序控制器T-CON基于侦测到的这两个方波信号将显示装置的显示模式设定为垂直分辨率减少至原来三分之一的异形显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图3所示时，导线A在一个扫描周期内输出至时序控制器的信号如图6中的(c)所示，导线A在一个扫描周期内有一个方波输出(例如，一个33V的方波)，此时，时序控制器T-CON基于侦测到的这一个方波信号将显示装置的显示模式设定为垂直分辨率减少至原来三分之二的异形显示模式。
通过上述方式，在显示装置为不同架构时，时序控制器可以基于检测的高压方波信号的数量，相应地设定不同的显示模式，使得多种显示装置的架构可以共用同一PCB，提高了PCB的共用性，降低了管理成本。
图7示出根据本发明另一示例性实施例的栅极侧扇出区域电路的示例。
如图7所示，假设栅极侧扇出区域电路所包括的栅极芯片组10包括三个栅极芯片(如图7中G-COF1—G-COF3)，所述电路模块组20可包括两根导线A和B以及两个相同阻值的电阻R1和R2，其中，导线A和B为栅极侧扇出区域的走线，导线A和B的一端均通过源极侧扇出区域的源极芯片与PCB板上的时序控制器相连接(图7中未示出)，导线A的另一端连接至栅极芯片G-COF2的输出引脚b，栅极芯片G-COF1的输出引脚a与电阻R1串联后连接至导线A，导线B的另一端经过电阻R2接地。这里，应理解，根据本示例中的栅极芯片组10不仅可包括三个栅极芯片，也可以更多或更少，但至少包括两个。
具体说来，电路模块组20可根据栅极芯片G-COF1—G-COF3提供的信号产生并输出相应的输出信号，时序控制器T-CON可基于经由源极芯片接收的从电路模块组20产生的输出信号来控制显示装置的显示模式。
例如，当薄膜晶体管液晶显示器的架构如图1所示时，当时序控制器经由源极芯片接收的从电路模块20产生的输出信号为低电平信号和高电平信号时，时序控制器基于侦测到的低电平信号和高电平信号将显示装置的显示模式 设定为正常显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图2所示时，当时序控制器经由源极芯片接收的从电路模块20产生的输出信号为两个低电平信号时，时序控制器基于侦测到的两个低电平信号将显示装置的显示模式设定为垂直分辨率减少至原来三分之一的异形显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图3所示时，当时序控制器经由源极芯片接收的从电路模块组20产生的输出信号为高电平信号和低电平信号时，时序控制器基于侦测到的高电平信号和低电平信号将显示装置的显示模式设定为垂直分辨率减少至原来三分之二的异形显示模式。
通过上述方式，可以在显示装置为不同架构时，时序控制器可以基于检测的电路模块组20产生的输出信号，相应地设定不同的显示模式，使得多种显示装置的架构可以共用同一PCB，提高了PCB的共用性，降低了管理成本。
图8示出根据本发明另一示例性实施例的栅极侧扇出区域电路的示例。
如图8所示，假设栅极侧扇出区域电路所包括的栅极芯片组10包括三个栅极芯片(如图8中G-COF1—G-COF3)，所述电路模块组20可包括三根导线A、B和C以及分别与导线A、B和C串联的电阻R1、R2和R3，其中，导线A、B和C为栅极侧扇出区域的走线，导线A、B和C的一端均通过源极侧扇出区域的源极芯片与PCB板上的时序控制器相连接(图8中未示出)，导线A、B和C的另一端分别经由与每根导线串联的电阻接地。栅极芯片G-COF1的输出引脚a连接导线A，栅极芯片G-COF2的输出引脚b连接导线B，栅极芯片G-COF3的输出引脚c连接导线C。这里，应理解，根据本示例中的栅极芯片组10不仅可包括三个栅极芯片，也可以更多或更少，但至少包括两个。
具体说来，电路模块组20可根据栅极芯片G-COF1—G-COF3提供的输出信号产生并输出相应的输出信号，时序控制器可基于经由源极芯片接收的从电路模块组20产生的输出信号来控制显示装置的显示模式。
例如，当薄膜晶体管液晶显示器的架构如图1所示时，当时序控制器经由源极芯片接收的从电路模块20产生的输出信号为三个高电平信号时，时序控制器基于侦测到的三个高电平信号将显示装置的显示模式设定为正常显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图2所示时，当时序控制器经由源极芯片接收的从电路模块20产生的输出信号为高电平信号、高电平信号和低电平信号时，时序控制器基于侦测到的高电平信号、高电平信号和低电平信号将显示装置的显示模式设定为垂直分辨率减少至原来三分之一的异形显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图3所示时，当时序控制器经由源极芯片接收的从电路模块组20产生的输出信号为三个低电平信号时，时序控制器基于侦测到的三个低电平信号将显示装置的显示模式设定为垂 直分辨率减少至原来三分之二的异形显示模式。
通过上述方式，可以在显示装置为不同架构时，时序控制器可以基于检测的电路模块组20产生的输出信号，相应地设定不同的显示模式，使得多种显示装置的架构可以共用同一PCB，提高了PCB的共用性，降低了管理成本。
在另一实施例中，所述电路模块组包括N个并联的电路模块，每个电路模块根据相应的栅极芯片提供的输入信号产生并输出相应的输出信号，其中，所述N个栅极芯片与所述N个并联的电路模块一一对应。
具体说来，每个电路模块根据相应的栅极芯片提供的输入信号产生并输出相应的输出信号。例如，所述栅极芯片组中的每个栅极芯片为薄膜上栅极芯片，所述N个电路模块中的每个电路模块为一个开关，其中，每个开关可响应于相应的栅极芯片提供的输入信号导通或截止。
此外，作为示例，当每个电路模块产生了相应的输出信号后，可将所述输出信号输出到源极芯片组中，以用于控制显示装置的显示模式。
具体说来，源极芯片组可包括N个源极芯片，这里，所述N个源极芯片中的每个源极芯片可以为薄膜上源极芯片。所述N个源极芯片与所述N个并联的电路模块一一对应，每个电路模块可将产生的输出信号输出到源极侧扇出区域的源极芯片组中的相应的源极芯片。显示装置的时序控制器侦测源极芯片从电路模块接收的输出信号，并基于侦测到的输出信号来控制显示装置的显示模式。这里，作为示例，所述显示装置可具有N种显示模式。
通过上述方式，电路模块可根据输入信号产生并输出相应的输出信号，从而使时序控制器基于输出信号设定与当前显示装置架构匹配的显示模式。
下面，将结合具体的示例进行详细说明。
图9示出根据本发明示例性实施例的栅极侧扇出区域电路的示例。
参照图9，作为示例，假设栅极侧扇出区域电路100所包括的栅极芯片组10包括三个栅极芯片(如图5中G-COF1—G-COF3)，相应地，电路模块组20包括与栅极芯片G-COF1—G-COF3一一对应的电路模块(如图5中的M1-M3)，这里，作为示例，所述电路模块组中的每个电路模块可以为一个开关，例如，NMOS管，其中，每个开关可响应于与其相应的栅极芯片提供的输入信号导通或截止，例如，当开关为NMOS管时，当输入信号为高电平信号时，NMOS管导通。这里，应理解，在该示例中，电路模块组20包括3个并联的电路模块，当然，也可以更多或更少，但至少两个以上。本领域技术人员可以理解，其他可以实现类似功能的电路模块也适用于本发明。此外，作为示例，所述三个栅极芯片和与所述三个栅极芯片一一对应的三个开关可设置于液晶显示装置的栅极侧扇出区域中。
具体说来，每个开关(即，M1-M3)的栅极a1-a3分别连接相应的栅极芯片G-COF1—G-COF3的输出引脚A1-A3，例如，栅极芯片G-COF1的A1输出引脚连接栅极芯片G-COF1对应的开关M1的栅极a1，栅极芯片G-COF2的 A2输出引脚连接栅极芯片G-COF2对应的开关M2的栅极a2，栅极芯片G-COF3的A3输出引脚连接栅极芯片G-COF3对应的开关M3的栅极a3。此外，开关M1-M3的源极b1-b3分别与源极扇出区域的源极芯片组中的相应的源极芯片连接，例如，开关M1的源极b1连接至源极芯片S-COF1的输入引脚d1，开关M1的源极b2连接至源极芯片S-COF2的输入引脚d2，开关M3的源极b3连接至源极芯片S-COF3的输入引脚d3。时序控制器T-CON的输入引脚k分别与源极芯片S-COF1—S-COF3的输出引脚e1-e3相连接，开关M1-M3的漏极c1-c3接地。这里，图9中的电阻R为NMOS导通时的等效电阻。
以下，对根据本发明示例性实施例的栅极侧扇出区域电路的工作原理进行描述。
具体说来，栅极芯片可向与其对应的开关发送输入信号，开关根据栅极芯片发送的输入信号导通或截止，并将产生的相应的输出信号输出给源极侧扇出区域的源极芯片，显示装置的时序控制器侦测源极芯片从开关接收的输出信号，并基于侦测到的输出信号来设定适合当前液晶显示装置架构的显示模式。
例如，现有技术中标准的薄膜晶体管液晶显示器的架构如图1所示，当薄膜晶体管液晶显示器的架构如图1所示时，栅极芯片G-COF1通过输出引脚A1向开关M1的栅极a1发送高电平信号、G-COF2通过输出引脚A2向开关M2的栅极a2发送高电平信号、G-COF3通过输出引脚A3向开关M3的栅极a3发送高电平信号，开关M1、M2和M3导通，则通过源极b1-b3传输到源极芯片S-COF1、S-COF2和S-COF3的输出信号为低电平信号、低电平信号和低电平信号，此时，时序控制器T-CON侦测从开关M1、M2和M3接收的三个低电平信号，并基于侦测到的三个信号将显示装置的显示模式设定为正常显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图2所示时，栅极芯片G-COF1通过输出引脚A1向开关M1的栅极a1发送高电平信号、G-COF2通过输出引脚A2向开关M2的栅极a2发送高电平信号，M3的栅极a3未接收到输入信号，则开关M1、M2导通，M3截止，则通过源极b1-b3传输到源极芯片S-COF1、S-COF2和S-COF3的输出信号为低电平信号、低电平信号和高电平信号，此时，时序控制器T-CON侦测从开关M1、M2和M3接收的低电平信号、低电平信号和高电平信号，并基于侦测到的三个信号将显示装置的显示模式设定为垂直分辨率减少至原来三分之一的异形显示模式。
作为另一示例，当薄膜晶体管液晶显示器的架构如图3所示时，栅极芯片G-COF1通过输出引脚A1向开关M1的栅极a1发送高电平信号、M2和M3的栅极a2和a3未接收到输入信号，则开关M1导通，M2、M3截止，则通过源极b1-b3传输到源极芯片S-COF1、S-COF2和S-COF3的输出信号为低电平信号、高电平信号和高电平信号，此时，侦测从开关M1、M2和M3接收的低电平信号、高电平信号和高电平信号，并基于侦测到的三个信号将显示装置的 显示模式设定为垂直分辨率减少至原来三分之二的异形显示模式。
综上所述，根据本发明示例性实施例的栅极侧扇出区域电路，不仅可以自动地调整显示装置的显示模式，还有效地降低了PCB的管理成本和制作成本。
显然，本发明的保护范围并不局限于上诉的具体实施方式，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种栅极侧扇出区域电路，其中，包括栅极芯片组和电路模块组，
    所述栅极芯片组包括N个栅极芯片，其中，N为大于等于2的正整数；
    所述电路模块组根据所述N个栅极芯片提供的输入信号产生并输出相应的输出信号。
  2. 如权利要求1所述的栅极侧扇出区域电路，其中，显示装置的时序控制器侦测从电路模块组产生的输出信号，并基于侦测到的输出信号来控制显示装置的显示模式。
  3. 如权利要求1所述的栅极侧扇出区域电路，其中，所述电路模块组包括N个并联的电路模块，每个电路模块根据相应的栅极芯片提供的输入信号产生并输出相应的输出信号，
    其中，所述N个栅极芯片与所述N个并联的电路模块一一对应。
  4. 如权利要求3所述的栅极侧扇出区域电路，其中，每个电路模块将产生的输出信号输出到源极侧扇出区域的源极芯片组中的相应的源极芯片，
    其中，源极芯片组包括N个源极芯片，所述N个源极芯片与所述N个并联的电路模块一一对应。
  5. 如权利要求4所述的栅极侧扇出区域电路，其中，显示装置的时序控制器侦测源极芯片从电路模块接收的输出信号，并基于侦测到的输出信号来控制显示装置的显示模式。
  6. 如权利要求3所述的栅极侧扇出区域电路，其中，所述N个电路模块中的每个电路模块为一个开关，其中，每个开关响应于相应的栅极芯片提供的输入信号导通或截止。
  7. 如权利要求6所述的栅极侧扇出区域电路，其中，所述开关为NMOS晶体管。
  8. 如权利要求5所述的栅极侧扇出区域电路，其中，所述显示装置具有N种显示模式。
  9. 如权利要求1所述的栅极侧扇出区域电路，其中，所述N个栅极芯片中的每个栅极芯片为薄膜上栅极芯片。
  10. 如权利要求4所述的栅极侧扇出区域电路，其中，所述N个源极芯片中的每个源极芯片为薄膜上源极芯片。
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