WO2017190392A1 - 一种单片集成的紫外焦平面器件及其制备方法 - Google Patents

一种单片集成的紫外焦平面器件及其制备方法 Download PDF

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WO2017190392A1
WO2017190392A1 PCT/CN2016/083874 CN2016083874W WO2017190392A1 WO 2017190392 A1 WO2017190392 A1 WO 2017190392A1 CN 2016083874 W CN2016083874 W CN 2016083874W WO 2017190392 A1 WO2017190392 A1 WO 2017190392A1
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type epitaxial
focal plane
substrate
epitaxial layer
layer
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李成
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李成
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a monolithically integrated ultraviolet focal plane device and a method of fabricating the same.
  • UV detection and ultraviolet imaging have a wide range of application requirements in aerospace, communications, military, and civil inspection fields.
  • Demand has accelerated the development of UV focal plane devices.
  • focal plane array detection The principle of focal plane array detection is that an array of photosensitive elements is arranged on its focal plane. Light emitted from infinity is imaged by optical system on these photosensitive elements in the focal plane of the system, and the detector converts the received optical signals into electricity. The signal is amplified, sampled and held, and the electrical signal is finally sent to the monitoring system to form image information through the output buffer and multiplex system.
  • the mainstream UV focal plane detectors are based on GaN/AlxGa1-xN material systems.
  • UV detectors made of GaN/AlxGa1-xN have high UV/visible suppression ratio and are not sensitive to visible light. Reduce the use of filters. Since the forbidden band width of GaN is 3.4 eV, the spectral response has a cutoff wavelength of 365 nm, while the forbidden band width of AlN is 6.2 eV, and the corresponding cutoff wavelength is 200 nm. Therefore, by adjusting the composition ratio of the epitaxial material, that is, the aluminum doping content, the band gap energy can be continuously adjusted from 3.4 to 6.2 eV, and the corresponding cutoff wavelength can be randomly cut between 200 and 365 nm.
  • the ultraviolet focal plane detectors 1 currently on the market are fabricated by hybrid integration, respectively fabricating a GaN/AlxGa1-xN photodiode array 11 and a silicon-based readout circuit 12, and then passing through an indium column. 13 ways of interconnecting the two together.
  • the GaN/AlxGa1-xN photodiode array 11 includes a sapphire substrate 111, an N-type AlGaN layer 112, a P-type AlGaN layer 113, and a SiN protective layer 114;
  • the silicon-based readout circuit 12 includes a Si substrate 121.
  • a readout circuit 122 prepared on the Si substrate 121 the readout circuit 122 is represented by a symbol, and a specific structure is not shown.
  • This hybrid integration method requires separately preparing the GaN/AlxGa1-xN photodiode array 11 and the silicon-based readout circuit 12, and then interconnecting the two by bonding, the preparation process is complicated, and the yield is low, and the production cost is low. High, not conducive to mass production.
  • the object of the present invention is to provide a monolithically integrated ultraviolet focal plane device and a preparation method thereof for solving the complicated production process of the ultraviolet focal plane detector in the prior art, and the product is good.
  • the low rate and high production cost are not conducive to large-scale production and other issues.
  • the present invention provides a monolithically integrated ultraviolet focal plane device, the monolithically integrated ultraviolet focal plane device comprising at least:
  • the photodiode array includes a plurality of photosensitive cells, each photosensitive element comprising an N-type epitaxial layer prepared on the substrate, and a P-type epitaxial layer prepared on the N-type epitaxial layer for receiving on an ultraviolet focal plane Light
  • the readout circuit is connected to the photodiode array through a metal line for reading the charge in each photosensitive element and outputting.
  • the substrate is a P-type substrate.
  • the material of the N-type epitaxial layer and the P-type epitaxial layer is AlGaN.
  • each photosensitive element is isolated by an isolation layer.
  • the photodiode array surface further includes a SiN protective layer
  • the surface of the readout circuit further includes a SiO 2 protective layer.
  • the present invention provides a method for fabricating the above-described monolithically integrated ultraviolet focal plane device, and the method for preparing the monolithically integrated ultraviolet focal plane device comprises at least:
  • Step S1 providing a substrate, etching a trench on the substrate according to a design layout, determining a position of each photosensitive element;
  • Step S2 forming an N-type epitaxial layer and a P-type epitaxial layer layer by layer in the trench by using an epitaxial growth technique;
  • Step S3 etching the P-type epitaxial layer to expose a portion of the N-type epitaxial layer
  • Step S4 preparing each device in the readout circuit on the substrate
  • Step S5 preparing electrodes of the respective photosensitive elements, and connecting the electrodes to corresponding devices in the readout circuit through metal wires.
  • the step S3 further comprises forming a first protective layer on the surface of the substrate, the N-type epitaxial layer and the P-type epitaxial layer.
  • the protective layer and the substrate are etched according to a design layout to form an isolation region, and an isolation layer is formed in the isolation region, the isolation layer blocking the photosensitive cells.
  • step S4 further comprises forming a second protective layer on each device surface in the readout circuit.
  • each device in the readout circuit is fabricated using a standard CMOS process.
  • the monolithically integrated ultraviolet focal plane device of the present invention and the preparation method thereof have the following beneficial effects:
  • the monolithically integrated ultraviolet focal plane device and the preparation method thereof of the invention are prepared on the same substrate by the photodiode array and the readout circuit, thereby avoiding complicated preparation processes such as bonding, improving the yield of the product, and greatly simplifying the production process. , reducing production costs, is conducive to large-scale production of UV focal plane devices.
  • Figure 1 shows a schematic view of the structure of an ultraviolet focal plane detector in the prior art.
  • FIG. 2 is a schematic view showing the structure of a monolithically integrated ultraviolet focal plane device of the present invention.
  • 3 to 9 are schematic flow charts showing a method of preparing a monolithically integrated ultraviolet focal plane device of the present invention.
  • the present invention provides a monolithically integrated ultraviolet focal plane device 2, the monolithically integrated ultraviolet focal plane device 2 comprising at least:
  • a photodiode array and a readout circuit 23 are formed on the same substrate 21.
  • the substrate 21 is located on the bottom layer.
  • the substrate 21 is a P-type Si substrate.
  • the photodiode array includes a plurality of photosensitive cells 22, each of which comprises an N-type epitaxial layer 221 prepared on the substrate 21, and a P prepared on the N-type epitaxial layer 221 An epitaxial layer 222 for receiving light on the ultraviolet focal plane.
  • the material of the N-type epitaxial layer 221 and the P-type epitaxial layer 222 is AlGaN.
  • the N-type epitaxial layer 221 and the P-type epitaxial layer 222 form a PN junction that responds to light on the external ultraviolet focal plane and generates a corresponding charge.
  • the surface of the N-type epitaxial layer 221 and the P-type epitaxial layer 222 is further provided with a first protective layer 24, and the material of the first protective layer 24.
  • a first protective layer 24 For SiN.
  • the readout circuit 23 is connected to the photodiode array by a metal line, and the readout circuit 23 is for reading and outputting charges in the respective photosensors 22.
  • the readout circuit 23 is only represented by a symbol, and does not specifically show an internal structure diagram. Those skilled in the art should understand the meaning of the representation, and the specific structure is based on the circuit structure. Not limited by one.
  • the readout circuit 23 includes a circuit structure composed of a plurality of devices. The surface of each device is covered with a second protective layer 26. In the embodiment, the second protective layer 26 is made of SiO 2 .
  • each photosensitive element 22 is blocked by the isolation layer 25 to reduce the influence of the electron movement and improve the detection. accuracy.
  • the working principle of the monolithically integrated ultraviolet focal plane device 2 is as follows:
  • the monolithically integrated ultraviolet focal plane device 2 is placed on an ultraviolet focal plane, each photosensitive element 22 receives light on the ultraviolet focal plane, and generates a corresponding amount of charge according to the difference in light intensity, and the readout circuit 23 receives The charge on each of the photosensors 22 transmits the read electrical signals to the processor, which restores and displays the image on the ultraviolet focal plane.
  • the present invention provides a method for fabricating the monolithically integrated ultraviolet focal plane device 1 , and the method for preparing the monolithically integrated ultraviolet focal plane device comprises at least:
  • Step S1 providing a substrate 21, and etching a trench on the substrate 21 by using a photolithography plate according to a design layout to determine the position of each photosensor 22.
  • a substrate 21 is provided.
  • the substrate 21 is a P-type Si substrate, and the material of the substrate 21 is not limited to the Si listed in the embodiment. Any material that can be used as a substrate in the prior art is suitable.
  • a trench 211 is formed on the substrate 21, and the trench 211 is used to prepare each photosensor 22.
  • Step S2 forming an N-type epitaxial layer 221 and a P-type epitaxial layer 222 layer by layer in the trench 211 by an epitaxial growth technique.
  • the material of the photo-sensitive element 22 is epitaxially grown, and after growth, a high-quality AlGaN epitaxial structure is grown in the trench 211, and AlGaN is formed on the surface of the substrate outside the trench 211. Crystal layer.
  • an N-type epitaxial layer 221 is formed in the trench 211, and the material of the N-type epitaxial layer 221 is AlGaN; a P-type epitaxial layer 222, and the material of the P-type epitaxial layer 222 is AlGaN.
  • the N-type epitaxial layer 221 and the P-type epitaxial layer 222 form a PN junction.
  • the AlGaN polycrystalline layer on the surface of the substrate 21 is removed.
  • the AlGaN polycrystalline layer on the surface of the substrate 21 can be formed by an etching process using the reverse plate of the photoresist in step S1. Remove.
  • the AlGaN polycrystalline layer on the surface of the substrate 21 may also be removed by grinding, which is not limited to this embodiment.
  • Step S3 etching the P-type epitaxial layer 222 to expose a portion of the N-type epitaxial layer 221.
  • the P-type epitaxial layer 222 is etched, and an etched trench is formed on the surface of the N-type epitaxial layer 221 to expose a portion of the N-type epitaxial layer 221 to facilitate preparation of the contact electrode.
  • a first protective layer 24 is formed on the surface of the substrate 21, the N-type epitaxial layer 221, and the P-type epitaxial layer 222.
  • the material of the first protective layer 24 is SiN.
  • Step S4 Each device in the readout circuit 23 is prepared on the substrate 21.
  • the LOCOS Local Oxidation of Silicon
  • the specific steps are as follows: as shown in FIG. 7, the first is etched according to the design layout.
  • the protective layer 24 and the substrate 21 form an isolation region, and the isolation layer 25 is formed by thermally oxidizing SiO 2 in the isolation region, and the isolation layer 25 blocks the photosensitive cells 22, thereby greatly improving the accuracy of detection. .
  • each device in the readout circuit 23 is prepared by a standard CMOS process, and the specific circuit structure and preparation steps are not described herein.
  • the readout circuit 23 is only a schematic diagram and does not represent a true readout circuit. In each of the actual units, the area of the photosensitive element is much larger than the area of the readout circuit, and is merely illustrated here.
  • the SiN protective layer on the surface of the readout circuit 23 is etched away, after the devices in the readout circuit 23 are prepared, A surface of the substrate 21 on which each device in the readout circuit 23 is located forms a second protective layer 26.
  • the material of the second protective layer 26 is SiO 2 .
  • the top metal layer of the readout circuit 23 is formed, which will not be described herein.
  • Step S5 The electrodes of the respective photosensors 22 are fabricated, and the electrodes are connected to corresponding devices in the readout circuit 23 by metal wires.
  • the first protective layer 24 is etched, and an etched trench is formed on the surface of the P-type epitaxial layer 222 to expose a portion of the P-type epitaxial layer 222.
  • the first protective layer 24 and the P-type epitaxial layer 222 are etched, and an etched trench is formed on the surface of the N-type epitaxial layer 221 to expose a portion of the N-type epitaxial layer 221.
  • Metal is filled in each etching bath to form electrodes of the respective photosensors 22.
  • each electrode is connected to a corresponding device in the readout circuit 23 by a metal wire to form a complete ultraviolet focal plane device.
  • the monolithically integrated ultraviolet focal plane device of the present invention and the preparation method thereof have the following beneficial effects:
  • the monolithically integrated ultraviolet focal plane device and the preparation method thereof of the invention are prepared on the same substrate by the photodiode array and the readout circuit, thereby avoiding complicated preparation processes such as bonding, improving the yield of the product, and greatly simplifying the production process. , reducing production costs, is conducive to large-scale production of UV focal plane devices.
  • the present invention provides a monolithically integrated ultraviolet focal plane device comprising: a photodiode array and a readout circuit fabricated on the same substrate; the photodiode array comprising a plurality of photosensitive cells, each photosensitive element An N-type epitaxial layer prepared on the substrate, a P-type epitaxial layer prepared on the N-type epitaxial layer for receiving light on an ultraviolet focal plane; the readout circuit and the photodiode array Connected by a metal wire for reading the charge in each photosensitive cell and outputting it.
  • a method for fabricating a monolithically integrated ultraviolet focal plane device comprising: providing a substrate, etching a trench on the substrate according to a design layout, determining a position of each photosensitive element; using an epitaxial growth technique, Forming an N-type epitaxial layer and a P-type epitaxial layer layer by layer in the trench; etching the P-type epitaxial layer to expose part of the N-type epitaxial layer; and preparing devices in the readout circuit on the substrate An electrode of each photosensitive element is fabricated, and each electrode is connected to a corresponding device in the readout circuit through a metal wire.

Abstract

一种单片集成的紫外焦平面器件（2）及其制备方法，包括：制备于同一衬底（21）上的光电二极管阵列和读出电路（23）；提供一衬底（21），根据设计布局在所述衬底（21）上刻蚀沟槽（211），确定各光敏元（22）的位置；利用外延生长技术，在所述沟槽（211）内逐层形成N型外延层（221）及P型外延层（222）；刻蚀所述P型外延层（222）以露出部分所述N型外延层（221）；在所述衬底（21）上制备读出电路（23）中的各器件；制作各光敏元（22）的电极，通过金属线将各电极与所述读出电路（23）中相应的器件连接。所述单片集成的紫外焦平面器件（2）及其制备方法将光电二极管阵列和读出电路（23）制备于同一衬底（21）上，避免了键合等复杂的制备工艺，提高产品的良率，简化生产工艺，降低生产成本，有利于紫外焦平面器件的大规模生产。

Description

一种单片集成的紫外焦平面器件及其制备方法 技术领域
本发明涉及半导体领域，特别是涉及一种单片集成的紫外焦平面器件及其制备方法。
背景技术
在现代光电探测技术中，紫外波段越来越受到人们的关注。由于宇宙空间、火焰、石油、气体污染物分子，以及高压线的电晕现象等都会含有紫外线辐射，因此紫外探测及紫外成像在航天、通讯、军事、民用检测等领域都有着广泛的应用需求，这些需求加快了紫外焦平面器件的发展速度。
焦平面阵列探测的原理为在其焦平面上排列着感光元件阵列，从无限远处发射的光线经过光学系统成像在系统焦平面的这些感光元件上，探测器将接受到的光信号转换为电信号并进行积分放大、采样保持，通过输出缓冲和多路传输系统，最终将电信号送达监视系统形成图像信息。
主流的紫外焦平面探测器都是基于GaN/AlxGa1-xN材料体系，采用GaN/AlxGa1-xN制作的紫外探测器，其紫外光/可见光抑制比高，对可见光不敏感，工作时不需要或者可以减少使用滤波器。由于GaN的禁带宽度为3.4eV，其光谱响应的截止波长为365nm，而AlN的禁带宽度为6.2eV，相应的截止波长为200nm。所以通过调整外延材料的组分比即掺铝含量，带隙能可以从3.4～6.2eV之间连续可调，对应的截止波长可以在200～365nm之间随意裁剪。
如图1所示，目前市面上的紫外焦平面探测器1均采用混合集成的方式制成，分别制作出GaN/AlxGa1-xN光电二极管阵列11和硅基的读出电路12，然后通过铟柱13互连的方式将二者键合在一起。其中，所述GaN/AlxGa1-xN光电二极管阵列11包括蓝宝石衬底111、N型AlGaN层112、P型AlGaN层113以及SiN保护层114；所述硅基的读出电路12包括Si衬底121和制备于所述Si衬底121上的读出电路122，所述读出电路122以符号代表，未显示具体结构。这种混合集成方法需要分别制备GaN/AlxGa1-xN光电二极管阵列11和硅基的读出电路12，然后通过键合的方式将两者互连，制备工艺复杂，而且良率较低，生产成本高，不利于大规模生产。
因此，如何简化紫外焦平面探测器的生产工艺，提高产品良率，已成为本领域技术人员亟待解决的问题之一。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种单片集成的紫外焦平面器件及其制备方法，用于解决现有技术中紫外焦平面探测器的生产工艺复杂，产品良率低，生产成本高，不利于大规模生产等问题。
为实现上述目的及其他相关目的，本发明提供一种单片集成的紫外焦平面器件，所述单片集成的紫外焦平面器件至少包括：
制备于同一衬底上的光电二极管阵列和读出电路；
所述光电二极管阵列包括多个光敏元，各光敏元包括制备于所述衬底上的N型外延层、制备于所述N型外延层上的P型外延层，用于接收紫外焦平面上的光；
所述读出电路与所述光电二极管阵列通过金属线连接，用于读取各光敏元中的电荷并输出。
优选地，所述衬底为P型衬底。
优选地，所述N型外延层和所述P型外延层的材质为AlGaN。
优选地，各光敏元之间通过隔离层进行隔离。
优选地，所述光电二极管阵列表面还包括SiN保护层，所述读出电路的表面还包括SiO2保护层。
为实现上述目的及其他相关目的，本发明提供一种上述单片集成的紫外焦平面器件的制备方法，所述单片集成的紫外焦平面器件的制备方法至少包括：
步骤S1：提供一衬底，根据设计布局在所述衬底上刻蚀沟槽，确定各光敏元的位置；
步骤S2：利用外延生长技术，在所述沟槽内逐层形成N型外延层及P型外延层；
步骤S3：刻蚀所述P型外延层以露出部分所述N型外延层；
步骤S4：在所述衬底上制备读出电路中的各器件；
步骤S5：制作各光敏元的电极，通过金属线将各电极与所述读出电路中相应的器件连接。
优选地，步骤S3还包括，在所述衬底、所述N型外延层及所述P型外延层的表面形成第一保护层。
优选地，在执行步骤S4之前，根据设计布局刻蚀所述保护层及所述衬底以形成隔离区，并在所述隔离区中形成隔离层，所述隔离层将各光敏元阻隔开。
优选地，步骤S4还包括在所述读出电路中的各器件表面形成第二保护层。
优选地，所述读出电路中的各器件采用标准CMOS工艺制备。
如上所述，本发明的单片集成的紫外焦平面器件及其制备方法，具有以下有益效果：
本发明的单片集成的紫外焦平面器件及其制备方法将光电二极管阵列和读出电路制备于同一衬底上，避免了键合等复杂的制备工艺，提高产品的良率，大大简化生产工艺，降低生产成本，有利于紫外焦平面器件的大规模生产。
附图说明
图1显示为现有技术中的紫外焦平面探测器的结构示意图。
图2显示为本发明的单片集成的紫外焦平面器件的结构示意图。
图3～图9显示为本发明的单片集成的紫外焦平面器件的制备方法的流程示意图。
元件标号说明
1    紫外焦平面探测器
11   GaN/AlxGa1-xN光电二极管阵列
111  蓝宝石衬底
112  N型AlGaN层
113  P型AlGaN层
114  SiN保护层
12   硅基的读出电路
121  Si衬底
122  读出电路
13   铟柱
2    单片集成的紫外焦平面器件
21   衬底
211  沟槽
22   光敏元
221  N型外延层
222  P型外延层
23   读出电路
24   第一保护层
25   隔离层
26   第二保护层
S1～S5   步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图2～图9。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图2所示，本发明提供一种单片集成的紫外焦平面器件2，所述单片集成的紫外焦平面器件2至少包括：
制备于同一衬底21上的光电二极管阵列和读出电路23。
如图2所示，所述衬底21位于底层，在本实施例中，所述衬底21为P型Si衬底。
如图2所示，所述光电二极管阵列包括多个光敏元22，各光敏元22包括制备于所述衬底21上的N型外延层221、制备于所述N型外延层221上的P型外延层222，所述光电二极管阵列用于接收紫外焦平面上的光。
具体地，如图2所示，在本实施例中，所述N型外延层221和所述P型外延层222的材质为AlGaN。所述N型外延层221和所述P型外延层222形成PN结，对外部紫外焦平面上的光进行响应，并产生相应的电荷。
具体地，如图2所示，在本实施例中，所述N型外延层221和所述P型外延层222的表面还铺设有第一保护层24，所述第一保护层24的材质为SiN。
如图2所示，所述读出电路23与所述光电二极管阵列通过金属线连接，所述读出电路23用于读取各光敏元22中的电荷并输出。
具体地，如图2所示，所述读出电路23仅以符号表示，并未具体呈现内部结构示意图，本领域技术人员应当理解其表示的含义，其具体结构以电路结构为准，在此不一一限定。所述读出电路23包括多个器件构成的电路结构，各器件的表面铺设有第二保护层26，在本实施例中，所述第二保护层26的材质为SiO2。
如图2所示，各光敏元22之间通过隔离层25阻隔，以减小电子运动的影响，提高检测 准确性。
所述单片集成的紫外焦平面器件2的工作原理如下：
所述单片集成的紫外焦平面器件2被放置于紫外焦平面上，各光敏元22接收紫外焦平面上的光，并根据光强的不同产生相应的电荷量，所述读出电路23接收各光敏元22上的电荷，并将读取到的电信号传输到处理器，处理器还原并显示紫外焦平面上的图像。
如图3～图9所示，本发明提供一种所述单片集成的紫外焦平面器件1的制备方法，所述单片集成的紫外焦平面器件的制备方法至少包括：
步骤S1：提供一衬底21，根据设计布局采用光刻板在所述衬底21上刻蚀沟槽，确定各光敏元22的位置。
具体地，如图3所示，提供一衬底21，在本实施例中，所述衬底21为P型Si衬底，所述衬底21的材质不限于本实施例所列举的Si，任何现有技术中可作为基底的材料均适用。在所述衬底21上刻蚀沟槽211，所述沟槽211中用于制备各光敏元22。
步骤S2：利用外延生长技术，在所述沟槽211内逐层形成N型外延层221及P型外延层222。
具体地，如图4所示，外延生长光敏元22的材料，经过生长，在所述沟槽211内生长出高质量的AlGaN外延结构，在所述沟槽211外的衬底表面形成AlGaN多晶层。在本实施例中，在所述沟槽211内分别形成N型外延层221，所述N型外延层221的材质为AlGaN；P型外延层222，所述P型外延层222的材质为AlGaN。其中所述N型外延层221和所述P型外延层222形成PN结。
具体地，去除所述衬底21表面的AlGaN多晶层，在本实施例中，可使用步骤S1中的光刻板的反板，通过刻蚀工艺将所述衬底21表面的AlGaN多晶层去除。也可使用研磨的方法去除所述衬底21表面的AlGaN多晶层，不以本实施例为限。
步骤S3：刻蚀所述P型外延层222以露出部分所述N型外延层221。
具体地，如图5所示，刻蚀所述P型外延层222，在所述N型外延层221表面形成刻蚀槽，以露出部分所述N型外延层221，便于制备接触电极。
具体地，如图6所示，在所述衬底21、所述N型外延层221及所述P型外延层222的表面形成第一保护层24。在本实施例中，所述第一保护层24的材质为SiN。
步骤S4：在所述衬底21上制备读出电路23中的各器件。
为了减少器件之间的相互影响，用LOCOS(Local Oxidation of Silicon，硅的局部氧化)工艺进行各个光敏元22的隔离，具体步骤如下：如图7所示，根据设计布局刻蚀所述第一保 护层24及所述衬底21形成隔离区，并在所述隔离区中通过热氧化生长SiO2形成隔离层25，所述隔离层25将各光敏元22阻隔开，大大提高检测的准确性。
具体地，如图8所示，采用标准CMOS工艺制备所述读出电路23中的各器件，具体电路结构及制备步骤在此不一一赘述。在本实施例中，所述读出电路23只是示意图，不代表真实的读出电路，在实际每个单元中，光敏元的面积比读出电路面积要大很多，这里只是示意。在制备所述读出电路23中的各器件的过程中，所述读出电路23表面的SiN保护层被刻蚀掉，在制备完所述读出电路23中的各器件后，在所述读出电路23中的各器件所在衬底21的表面形成第二保护层26。在本实施例中，所述第二保护层26的材质为SiO2。同时形成所述读出电路23的顶层金属层，在此不一一赘述。
步骤S5：制作各光敏元22的电极，通过金属线将各电极与所述读出电路23中相应的器件连接。
具体地，如图9所示，刻蚀所述第一保护层24，在所述P型外延层222表面形成刻蚀槽，以露出部分所述P型外延层222。同样地，刻蚀所述第一保护层24和所述P型外延层222，在所述N型外延层221表面形成刻蚀槽，以露出部分所述N型外延层221。在各刻蚀槽中填充金属，形成各光敏元22的电极。
具体地，如图9所示，通过金属线将各电极与所述读出电路23中相应的器件连接，形成完整的紫外焦平面器件。
如上所述，本发明的单片集成的紫外焦平面器件及其制备方法，具有以下有益效果：
本发明的单片集成的紫外焦平面器件及其制备方法将光电二极管阵列和读出电路制备于同一衬底上，避免了键合等复杂的制备工艺，提高产品的良率，大大简化生产工艺，降低生产成本，有利于紫外焦平面器件的大规模生产。
综上所述，本发明提供一种单片集成的紫外焦平面器件，包括：制备于同一衬底上的光电二极管阵列和读出电路；所述光电二极管阵列包括多个光敏元，各光敏元包括制备于所述衬底上的N型外延层、制备于所述N型外延层上的P型外延层，用于接收紫外焦平面上的光；所述读出电路与所述光电二极管阵列通过金属线连接，用于读取各光敏元中的电荷并输出。还提供一种单片集成的紫外焦平面器件的制备方法，包括：提供一衬底，根据设计布局在所述衬底上刻蚀沟槽，确定各光敏元的位置；利用外延生长技术，在所述沟槽内逐层形成N型外延层及P型外延层；刻蚀所述P型外延层以露出部分所述N型外延层；在所述衬底上制备读出电路中的各器件；制作各光敏元的电极，通过金属线将各电极与所述读出电路中相应的器件连接。本发明的单片集成的紫外焦平面器件及其制备方法将光电二极管阵列和读出电路 制备于同一衬底上，避免了键合等复杂的制备工艺，提高产品的良率，大大简化生产工艺，降低生产成本，有利于紫外焦平面器件的大规模生产。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种单片集成的紫外焦平面器件，其特征在于，所述单片集成的紫外焦平面器件至少包括：
    制备于同一衬底上的光电二极管阵列和读出电路；
    所述光电二极管阵列包括多个光敏元，各光敏元包括制备于所述衬底上的N型外延层、制备于所述N型外延层上的P型外延层，用于接收紫外焦平面上的光；
    所述读出电路与所述光电二极管阵列通过金属线连接，用于读取各光敏元中的电荷并输出。
  2. 根据权利要求1所述的单片集成的紫外焦平面器件，其特征在于：所述衬底为P型衬底。
  3. 根据权利要求1所述的单片集成的紫外焦平面器件，其特征在于：所述N型外延层和所述P型外延层的材质为AlGaN。
  4. 根据权利要求1所述的单片集成的紫外焦平面器件，其特征在于：各光敏元之间通过隔离层进行隔离。
  5. 根据权利要求1所述的单片集成的紫外焦平面器件，其特征在于：所述光电二极管阵列表面还包括SiN保护层，所述读出电路的表面还包括SiO2保护层。
  6. 一种如权利要求1～5任意一项所述的单片集成的紫外焦平面器件的制备方法，其特征在于，所述单片集成的紫外焦平面器件的制备方法至少包括：
    步骤S1：提供一衬底，根据设计布局在所述衬底上刻蚀沟槽，确定各光敏元的位置；
    步骤S2：利用外延生长技术，在所述沟槽内逐层形成N型外延层及P型外延层；
    步骤S3：刻蚀所述P型外延层以露出部分所述N型外延层；
    步骤S4：在所述衬底上制备读出电路中的各器件；
    步骤S5：制作各光敏元的电极，通过金属线将各电极与所述读出电路中相应的器件连接。
  7. 根据权利要求6所述的单片集成的紫外焦平面器件的制备方法，其特征在于：步骤S3还包括，在所述衬底、所述N型外延层及所述P型外延层的表面形成第一保护层。
  8. 根据权利要求6所述的单片集成的紫外焦平面器件的制备方法，其特征在于：在执行步骤 S4之前，根据设计布局刻蚀所述保护层及所述衬底以形成隔离区，并在所述隔离区中形成隔离层，所述隔离层将各光敏元阻隔开。
  9. 根据权利要求6所述的单片集成的紫外焦平面器件的制备方法，其特征在于：步骤S4还包括在所述读出电路中的各器件表面形成第二保护层。
  10. 根据权利要求6所述的单片集成的紫外焦平面器件的制备方法，其特征在于：所述读出电路中的各器件采用标准CMOS工艺制备。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314561A (zh) * 2021-05-27 2021-08-27 复旦大学 一种深紫外波段发光单片集成器件及制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625210A (en) * 1995-04-13 1997-04-29 Eastman Kodak Company Active pixel sensor integrated with a pinned photodiode
CN1481585A (zh) * 2000-10-19 2004-03-10 ���Ӱ뵼�����޹�˾ 制作和cmos电路集成在一起的异质结光电二极管的方法
CN101661943A (zh) * 2008-08-26 2010-03-03 北京大学 一种单片集成紫外图像传感器及其像素单元以及制备方法
US20130214161A1 (en) * 2010-11-03 2013-08-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Visible and near-infrared radiation detector
CN103594468A (zh) * 2013-11-29 2014-02-19 电子科技大学 一种快速光电探测器
CN104362199A (zh) * 2014-11-19 2015-02-18 中国电子科技集团公司第二十四研究所 用于单片光探测与电信号处理集成器件的基材结构及其形成方法
CN104505410A (zh) * 2014-12-31 2015-04-08 杭州士兰微电子股份有限公司 光电二极管、紫外探测器集成电路及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231193B (zh) * 2008-02-01 2010-06-09 中国电子科技集团公司第四十四研究所 单片式可见光/红外光双光谱焦平面探测器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625210A (en) * 1995-04-13 1997-04-29 Eastman Kodak Company Active pixel sensor integrated with a pinned photodiode
CN1481585A (zh) * 2000-10-19 2004-03-10 ���Ӱ뵼�����޹�˾ 制作和cmos电路集成在一起的异质结光电二极管的方法
CN101661943A (zh) * 2008-08-26 2010-03-03 北京大学 一种单片集成紫外图像传感器及其像素单元以及制备方法
US20130214161A1 (en) * 2010-11-03 2013-08-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Visible and near-infrared radiation detector
CN103594468A (zh) * 2013-11-29 2014-02-19 电子科技大学 一种快速光电探测器
CN104362199A (zh) * 2014-11-19 2015-02-18 中国电子科技集团公司第二十四研究所 用于单片光探测与电信号处理集成器件的基材结构及其形成方法
CN104505410A (zh) * 2014-12-31 2015-04-08 杭州士兰微电子股份有限公司 光电二极管、紫外探测器集成电路及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314561A (zh) * 2021-05-27 2021-08-27 复旦大学 一种深紫外波段发光单片集成器件及制备方法

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