WO2017185437A1 - 削角调节电路及具有该削角调节电路的液晶显示器 - Google Patents

削角调节电路及具有该削角调节电路的液晶显示器 Download PDF

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WO2017185437A1
WO2017185437A1 PCT/CN2016/083076 CN2016083076W WO2017185437A1 WO 2017185437 A1 WO2017185437 A1 WO 2017185437A1 CN 2016083076 W CN2016083076 W CN 2016083076W WO 2017185437 A1 WO2017185437 A1 WO 2017185437A1
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Prior art keywords
resistor
chamfering
adjustment circuit
field effect
effect transistor
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PCT/CN2016/083076
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English (en)
French (fr)
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王照
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深圳市华星光电技术有限公司
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Priority to US15/116,927 priority Critical patent/US10192496B2/en
Publication of WO2017185437A1 publication Critical patent/WO2017185437A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp

Definitions

  • the present invention relates to the field of display driving technologies, and in particular, to a chamfering adjustment circuit and a liquid crystal display having the chamfering adjustment circuit.
  • the chamfering function is usually added to achieve a more uniform picture in the horizontal direction.
  • the working principle is: controlling the discharge action of the cornering voltage output terminal VGH by the Thin Film Transistor-Liquid Crystral Display (TFT-LCD) through the timing signal, so that the actual control TFT-LCD is turned on.
  • the waveform of the voltage output terminal VGH is converted from a constant voltage to a voltage having a periodic ramp down.
  • FIG. 2 is a schematic diagram of the waveform of the square wave GVON and the chamfering resistor R.
  • the chamfering time can be determined by the time when the square wave GVON is at a low level, and the chamfering rate is affected by the magnitude of the resistance of the chamfering resistor R.
  • the optimum chamfer waveforms required may also be different.
  • the time of the chamfering can be changed by the change of the square wave GVON waveform outputted by the timing control terminal T-con, but the chamfering resistance R that affects the chamfering rate cannot be adjusted, resulting in other The optimal chamfer waveform cannot be obtained in mode.
  • a chamfering adjustment circuit capable of changing the chamfering rate in real time with different display modes of the liquid crystal display and a liquid crystal display having the chamfering adjustment circuit are provided.
  • a liquid crystal display having a chamfering adjustment circuit, the liquid crystal display comprising a chamfering adjustment circuit and a thin film transistor, the chamfering adjustment circuit comprising a first adjustment circuit and a a second adjustment circuit, wherein the chamfering adjustment circuit is configured to select one of the first adjustment circuit and the second adjustment circuit to perform the adjustment of the resistance of the chamfering resistance when the display mode of the liquid crystal display is switched,
  • the chamfering of the gate voltage supplied to the thin film transistor by the chamfering adjustment circuit in the different display modes of the liquid crystal display is optimized.
  • the chamfering adjustment circuit includes a chamfering resistor, a first resistor connected in parallel with the chamfering resistor and selectively connectable, a second resistor, a third resistor connected to the second resistor, and a third resistor connected a fourth resistor, a fifth resistor, a first field effect transistor and a second field effect transistor, wherein the second resistor forms the first adjustment circuit, the third resistor, the fourth resistor, and the fifth resistor And the second field effect transistor jointly forms the second adjusting circuit, wherein the first resistor is respectively connected to the first adjusting circuit and the second adjusting circuit through the first field effect transistor
  • One end of the chamfering resistor and one end of the first resistor are connected to the control end, and the other end of the first resistor is connected to a source stage of the first field effect transistor, and the gate of the first field effect transistor The pole is connected to one end of the second resistor and the third resistor.
  • the other end of the third resistor is connected to one end of the fourth resistor and a source of the second field effect transistor, and a gate of the second field effect transistor is connected to one end of the fifth resistor.
  • the other end of the second resistor and the other end of the fifth resistor are connected in common to the enable control terminal.
  • the other end of the fourth resistor is connected to the power terminal, and the other end of the chamfering resistor, the drain of the first field effect transistor and the drain of the second field effect transistor are commonly grounded.
  • the first field effect transistor and the second field effect transistor are N-type field effect transistors.
  • the first adjusting circuit is selected to perform the driving, and the second adjusting circuit does not hit the component.
  • the second adjusting circuit is selected to perform the driving, and the first adjusting circuit does not punch.
  • a chamfering adjustment circuit comprising a chamfering resistor, a first resistor connected in parallel with the chamfering resistor and selectively connectable, a second resistor, a third resistor connected to the second resistor, and a third resistor Connected a fourth resistor, a fifth resistor, a first field effect transistor and a second field effect transistor, wherein the second resistor forms a first adjustment circuit, the third resistor, the fourth resistor, the fifth resistor, and The second field effect transistor forms a second adjustment circuit, and the first resistance is respectively connected to the first adjustment circuit and the second adjustment circuit through the first field effect transistor, and the chamfer adjustment circuit
  • the adjustment of the resistance of the chamfering resistor is achieved by selecting one of the first adjustment circuit and the second adjustment circuit.
  • the invention has the beneficial effects that the chamfering rate can be changed in real time with different working modes of the liquid crystal display, so that the chamfering in different modes can achieve the optimization purpose.
  • 1 is a circuit diagram of a conventional chamfering circuit
  • FIG. 2 is a waveform diagram of a square wave GVON and a chamfering resistor R;
  • FIG. 3 is a circuit diagram of a chamfering adjustment circuit of a liquid crystal display having a chamfering adjustment circuit according to the present invention.
  • FIG. 3 is a schematic circuit diagram of a chamfering adjustment circuit of a liquid crystal display having a chamfering adjustment circuit according to the present invention.
  • the chamfering adjustment circuit includes a chamfering resistor R, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first field effect transistor Q1, and a second field effect transistor Q2.
  • the second resistor R2 forms a first adjustment circuit PartA
  • the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the second field effect transistor Q2 together form a second adjustment circuit PartB.
  • One end of the chamfering resistor R and one end of the first resistor R1 are connected to the control terminal RE, and the first resistor R1 The other end is connected to the source of the first field effect transistor Q1, and the gate of the first field effect transistor Q1 is connected to one end of the second resistor R2 and the third resistor R3.
  • the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the source of the second field effect transistor Q2, the gate of the second field effect transistor Q2 is connected to one end of the fifth resistor R5, and the second resistor R2 is The other end of the one end and the fifth resistor R5 are connected in common to the enable control terminal OM_EN.
  • the other end of the fourth resistor R4 is connected to the power supply terminal VCC, and the other end of the chamfering resistor R, the drain of the first field effect transistor Q1, and the drain of the second field effect transistor Q2 are commonly grounded.
  • the first field effect transistor Q1 and the second field effect transistor Q2 are both N-type field effect transistors. In other embodiments, the first field effect transistor Q1 and the second field effect transistor Q2 may be other A switching element that can achieve the same function.
  • the working principle of the liquid crystal display having the chamfering adjustment circuit of the present invention is as follows:
  • the enable control terminal OM_EN is at a low level, the first FET Q1 is turned off, and the resistance of the chamfer resistor of the actual access circuit is R.
  • the enable control terminal OM_EN is at a high level, the first field effect transistor Q1 is turned on, and the first resistor R1 is connected in parallel with the chamfering resistor R, and the cornering resistance of the actual access circuit is at this time.
  • the resistance value is R//R1, and its value is less than R, so the function of reducing the chamfering resistance is realized.
  • the second adjustment circuit PartB is selected for the driving, and the first adjustment circuit PartA does not punch.
  • the enable control terminal OM_EN is at a low level
  • the second FET Q2 is turned off
  • the gate of the first FET Q1 is pulled high
  • the first FET Q1 is turned on
  • actually The resistance of the cornering resistor of the access circuit is R//R1.
  • the enable control terminal OM_EN is at a high level
  • the second FET Q2 is turned on, the gate of the first FET Q1 is pulled low, and the first FET Q1 is turned off.
  • the value of the chamfering resistor of the actual access circuit is only R, and its value is greater than R//R1. Therefore, the function of increasing the chamfering resistance is realized.
  • R and the first resistor R1 two The optimization of the resistance of the chamfering resistor in the mode.
  • the liquid crystal display with the chamfering adjustment circuit of the present invention has a selectively connected first resistor R1 in parallel with the chamfering resistor R, and is selectively connected to the first resistor by enabling the control terminal OM_EN.
  • R1's access control allows switching regardless of whether the normal mode is the same as the chamfering resistance required by other modes. Therefore, the chamfering in different modes can be optimized.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种具有削角调节电路的液晶显示器，其包括削角调节电路及薄膜晶体管，所述削角调节电路包括第一调节电路（PartA）及第二调节电路（PartB），所述削角调节电路用于选择所述第一调节电路（PartA）与所述第二调节电路（PartB）其中之一进行打件来实现所述液晶显示器显示模式切换时削角电阻（R）阻值的调节，使得所述液晶显示器不同显示模式下通过削角调节电路提供给薄膜晶体管的栅极电压的削角均达到最优化。

Description

削角调节电路及具有该削角调节电路的液晶显示器 技术领域
本发明涉及显示驱动技术领域，尤其是涉及一种削角调节电路及具有该削角调节电路的液晶显示器。
背景技术
为了优化液晶显示的效果，在现有的驱动电路的设计中，通常都会增加削角功能，以实现水平方向显示的画面更加均匀。其工作原理为：通过时序信号控制薄膜显示管-液晶显示装置(Thin Film Transistor-Liquid Crystral Display，TFT-LCD)开启削角电压输出端VGH的放电动作，使得实际控制TFT-LCD开启的削角电压输出端VGH的波形由恒定电压转变为有周期性坡形下降的电压。
如图1所示，现有的削角电路往往采用图1所示的结构，通过控制方波GVON的波形及削角电阻R的大小，即可改变削角电压输出端VGH的波形，从而实现优化画面显示的目的。同时，请参阅图2，图2为方波GVON及削角电阻R的波形示意图，当方波GVON处于低电平时，电压输入端VGHF输入的恒定电压经过电压放电，波形变为削角后VGH波形，其中，削角的时间可由方波GVON处于低电平的时间来决定，削角速率受到削角电阻R的阻值大小的影响。
由于液晶显示器的工作模式的不同，其所需要的最佳削角波形也可能不同。在其他模式下，例如3D功能模式下，可以通过时序控制端T-con输出方波GVON波形的变化来改变削角的时间，但影响削角速率的削角电阻R无法调节，从而导致在其他模式下无法获得最优的削角波形。
发明内容
为克服现有技术的不足，提供一种可以随着液晶显示器的不同显示模式，实时改变削角速率的削角调节电路及具有该削角调节电路的液晶显示器。
本发明的目的是通过以下技术方案来实现的：一种具有削角调节电路的液晶显示器，所述液晶显示器包括削角调节电路及薄膜晶体管，所述削角调节电路包括第一调节电路及第二调节电路，所述削角调节电路用于选择所述第一调节电路与所述第二调节电路其中之一进行打件来实现所述液晶显示器显示模式切换时削角电阻阻值的调节，使得所述液晶显示器不同显示模式下通过削角调节电路提供给薄膜晶体管的栅极电压的削角均达到最优化。
所述削角调节电路包括削角电阻、与所述削角电阻并联连接并可选择性接入的第一电阻、第二电阻、与第二电阻相连的第三电阻、与第三电阻相连的第四电阻、第五电阻、第一场效应管及第二场效应管，所述第二电阻形成所述第一调节电路，所述第三电阻、所述第四电阻、所述第五电阻及所述第二场效应管共同形成所述第二调节电路，所述第一电阻通过所述第一场效应管与所述第一调节电路及所述第二调节电路分别连接
所述削角电阻的一端及所述第一电阻的一端与控制端相连，所述第一电阻的另一端与所述第一场效应管的源级相连，所述第一场效应管的栅极与所述第二电阻及所述第三电阻的一端相连。
所述第三电阻的另一端与所述第四电阻的一端及所述第二场效应管的源级相连，所述第二场效应管的栅极与所述第五电阻的一端相连，所述第二电阻的另一端及所述第五电阻的另一端共同连接使能控制端。
所述第四电阻的另一端连接电源端，所述削角电阻的另一端、所述第一场效应管的漏极及所述第二场效应管的漏极共同接地。
所述第一场效应管与第二场效应管为N型场效应管。
当所需的常规模式的削角电阻的阻值大于其他模式的削角电阻的阻值时，选择所述第一调节电路进行打件，所述第二调节电路不打件。
当所需的常规模式的削角电阻的阻值小于其他模式的削角电阻的阻值时，选择所述第二调节电路进行打件，所述第一调节电路不打件。
一种削角调节电路，其包括削角电阻、与所述削角电阻并联连接并可选择性接入的第一电阻、第二电阻、与第二电阻相连的第三电阻、与第三电阻相连 的第四电阻、第五电阻、第一场效应管及第二场效应管，所述第二电阻形成第一调节电路，所述第三电阻、所述第四电阻、所述第五电阻及所述第二场效应管共同形成第二调节电路，所述第一电阻通过所述第一场效应管与所述第一调节电路及所述第二调节电路分别连接，所述削角调节电路通过选择所述第一调节电路与所述第二调节电路其中之一进行打件来实现削角电阻阻值的调节。
本发明的有益效果是：可以随着液晶显示器的不同工作模式，实时改变削角速率，使得不同模式下的削角都可以达到最优化的目的。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1为现有的削角电路的电路图；
图2为方波GVON及削角电阻R的波形示意图；
图3为本发明具有削角调节电路的液晶显示器中削角调节电路的电路示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
请参阅图3，图3为本发明具有削角调节电路的液晶显示器中削角调节电路的电路示意图。削角调节电路包括削角电阻R、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第一场效应管Q1及第二场效应管Q2。其中，第二电阻R2形成第一调节电路PartA，第三电阻R3、第四电阻R4、第五电阻R5及第二场效应管Q2共同形成第二调节电路PartB。
削角电阻R的一端及第一电阻R1的一端与控制端RE相连，第一电阻R1 的另一端与第一场效应管Q1的源级相连，第一场效应管Q1的栅极与第二电阻R2及第三电阻R3的一端相连。第三电阻R3的另一端与第四电阻R4的一端及第二场效应管Q2的源级相连，第二场效应管Q2的栅极与第五电阻R5的一端相连，第二电阻R2的另一端及第五电阻R5的另一端共同连接使能控制端OM_EN。第四电阻R4的另一端连接电源端VCC，削角电阻R的另一端、第一场效应管Q1的漏极及第二场效应管Q2的漏极共同接地。
其中，在本发明中，第一场效应管Q1与第二场效应管Q2均为N型场效应管，在其他实施方式中，第一场效应管Q1与第二场效应管Q2可为其他可以实现相同功能的开关元件。
本发明具有削角调节电路的液晶显示器的工作原理如下所述：
当所需的常规模式的削角电阻R的阻值大于其他模式的削角电阻R的阻值时，选择第一调节电路PartA进行打件，第二调节电路PartB不打件。此时，在常规模式下，使能控制端OM_EN为低电平，第一场效应管Q1关断，实际接入电路的削角电阻的阻值为R。当切换到其他模式时，使能控制端OM_EN为高电平，第一场效应管Q1导通，第一电阻R1接入电路与削角电阻R并联，此时实际接入电路的削角电阻的阻值为R//R1，其值小于R，因此实现了降低削角电阻的功能，通过调节削角电阻R及第一电阻R1的大小即可实现两种模式下削角电阻阻值的最优化。
当所需的常规模式的削角电阻R的阻值小于其他模式的削角电阻R的阻值时，选择第二调节电路PartB进行打件，第一调节电路PartA不打件。此时，在常规模式下，使能控制端OM_EN为低电平，第二场效应管Q2关断，第一场效应管Q1的栅极被拉高，第一场效应管Q1导通，实际接入电路的削角电阻的阻值为R//R1。当切换到其他模式时，使能控制端OM_EN为高电平，第二场效应管Q2导通，第一场效应管Q1的栅极被拉低，第一场效应管Q1关断，此时实际接入电路的削角电阻的阻值仅为R，其值大于R//R1，因此实现了增加削角电阻的功能，通过调节削角电阻R及第一电阻R1的大小即可实现两种模式下削角电阻阻值的最优化。
本发明具有削角调节电路的液晶显示器为削角电阻R并联一个可选择性接入的第一电阻R1，并通过使能控制端OM_EN来实现可选择接入第一电阻 R1的接入控制，无论常规模式与其他模式所需的削角电阻大小是否相同，均可实现切换，因此，使得不同模式下的削角均可以达到最优化。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (11)

  1. 一种具有削角调节电路的液晶显示器，其中，所述液晶显示器包括削角调节电路及薄膜晶体管，所述削角调节电路包括第一调节电路及第二调节电路，所述削角调节电路用于选择所述第一调节电路与所述第二调节电路其中之一进行打件来实现所述液晶显示器显示模式切换时削角电阻阻值的调节，使得所述液晶显示器不同显示模式下通过削角调节电路提供给薄膜晶体管的栅极电压的削角均达到最优化。
  2. 根据权利要求1所述的具有削角调节电路的液晶显示器，其中，所述削角调节电路包括削角电阻、与所述削角电阻并联连接并可选择性接入的第一电阻、第二电阻、与第二电阻相连的第三电阻、与第三电阻相连的第四电阻、第五电阻、第一场效应管及第二场效应管，所述第二电阻形成所述第一调节电路，所述第三电阻、所述第四电阻、所述第五电阻及所述第二场效应管共同形成所述第二调节电路，所述第一电阻通过所述第一场效应管与所述第一调节电路及所述第二调节电路分别连接。
  3. 根据权利要求2所述的具有削角调节电路的液晶显示器，其中，所述削角电阻的一端及所述第一电阻的一端与控制端相连，所述第一电阻的另一端与所述第一场效应管的源级相连，所述第一场效应管的栅极与所述第二电阻及所述第三电阻的一端相连。
  4. 根据权利要求3所述的具有削角调节电路的液晶显示器，其中，所述第三电阻的另一端与所述第四电阻的一端及所述第二场效应管的源级相连，所述第二场效应管的栅极与所述第五电阻的一端相连，所述第二电阻的另一端及所述第五电阻的另一端共同连接使能控制端。
  5. 根据权利要求4所述的具有削角调节电路的液晶显示器，其中，所述第四电阻的另一端连接电源端，所述削角电阻的另一端、所述第一场效应管的漏极及所述第二场效应管的漏极共同接地。
  6. 根据权利要求2所述的具有削角调节电路的液晶显示器，其中，当所需的常规模式的削角电阻的阻值大于其他模式的削角电阻的阻值时，选择所述第一调节电路进行打件，所述第二调节电路不打件；当所需的常规模式的削角电阻的阻值小于其他模式的削角电阻的阻值时，选择所述第二调节电路进行打 件，所述第一调节电路不打件。
  7. 一种削角调节电路，其中，所述削角调节电路包括削角电阻、与所述削角电阻并联连接并可选择性接入的第一电阻、第二电阻、与第二电阻相连的第三电阻、与第三电阻相连的第四电阻、第五电阻、第一场效应管及第二场效应管，所述第二电阻形成第一调节电路，所述第三电阻、所述第四电阻、所述第五电阻及所述第二场效应管共同形成第二调节电路，所述第一电阻通过所述第一场效应管与所述第一调节电路及所述第二调节电路分别连接，所述削角调节电路通过选择所述第一调节电路与所述第二调节电路其中之一进行打件来实现削角电阻阻值的调节。
  8. 根据权利要求7所述的削角调节电路，其中，所述削角电阻的一端及所述第一电阻的一端与控制端相连，所述第一电阻的另一端与所述第一场效应管的源级相连，所述第一场效应管的栅极与所述第二电阻及所述第三电阻的一端相连。
  9. 根据权利要求8所述的削角调节电路，其中，所述第三电阻的另一端与所述第四电阻的一端及所述第二场效应管的源级相连，所述第二场效应管的栅极与所述第五电阻的一端相连，所述第二电阻的另一端及所述第五电阻的另一端共同连接使能控制端。
  10. 根据权利要求9所述的削角调节电路，其中，所述第四电阻的另一端连接电源端，所述削角电阻的另一端、所述第一场效应管的漏极及所述第二场效应管的漏极共同接地。
  11. 根据权利要求7所述的削角调节电路，其中，当所需的常规模式的削角电阻的阻值大于其他模式的削角电阻的阻值时，选择所述第一调节电路进行打件，所述第二调节电路不打件；当所需的常规模式的削角电阻的阻值小于其他模式的削角电阻的阻值时，选择所述第二调节电路进行打件，所述第一调节电路不打件。
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