WO2017177611A1

WO2017177611A1 - Chip security detection method, chip structure and chip module

Info

Publication number: WO2017177611A1
Application number: PCT/CN2016/098796
Authority: WO
Inventors: 段维虎; 车诒恒
Original assignee: 广州小微电子技术有限公司
Priority date: 2016-04-13
Filing date: 2016-09-13
Publication date: 2017-10-19
Also published as: CN105930237A

Abstract

A chip security detection method. The chip at least comprises an integrated circuit, and a metal layer covering the integrated circuit. The method comprises: building a current loop on a metal layer; setting a signal generator, a signal receiver and a determination circuit in the integrated circuit; the signal generator outputting a specific signal, and the specific signal being input into the current loop; the current loop converting the specific signal into a detection signal, receiving the detection signal via the signal receiver and inputting the detection signal into the determination circuit; and the determination circuit determines whether the chip has a security risk according to the detection signal and the specific signal. In the chip security detection method, a current loop converting a specific signal into a detection signal, and then determining whether an abnormality occurs by comparing the detection signal with the specific signal, and therefore, a chip can be prevented from sustaining an unpredictable risk due to a damaged external factor.

Description

Chip safety detection method, chip structure and chip module

Technical field

The present invention relates to the field of electronics, and in particular, to a chip security detection method, a chip structure, and a chip module.

Background technique

With the development of the economy, the use of electronic chips is becoming more and more important and more and more important. Therefore, the requirements for security are also getting higher and higher. In order to ensure the security of the internal data of the chip, it is common practice to check the correctness of the data through various error correction algorithms to ensure the security of the data. This traditional approach is to verify chip data based on the fact that the chip is not physically damaged. However, when the chip is applied to the product, the product often needs to be moved, handled, etc., and the chip may be physically damaged due to collision or the like, which may cause various unpredictable errors and malfunctions of the chip. . This unpredictable error and failure sometimes cannot be verified by an algorithm to check if the chip has a problem. If such a physically damaged chip is applied to some potentially dangerous devices, there is an unpredictable risk.

In order to prevent this kind of risk, it is necessary to design a solution. When the physical structure of the chip changes or is damaged, the feedback information can be output in time, so that the system can immediately enable the spare device and remind the management personnel to replace the damaged chip in time. .

In view of this, the present invention proposes a security detection circuit structure that can be used in a chip. In addition, the present invention also provides a chip security detection method, a chip structure, and a chip module.

Summary of the invention

In order to achieve the above object, the present invention provides a chip security detection method, including the following steps:

a component reflow circuit that generates a detection signal after passing a specific signal through the reflow circuit;

Generating a determination signal according to the detection signal;

Comparing the determination signal with a specific signal, and judging whether the chip is working normally according to the result of the comparison.

Preferably, the specific signal is a square wave signal;

Preferably, the determination signal is compared with a specific signal by using an exclusive OR operation.

Preferably, the result of the comparison includes: the determination signal is the same as the specific signal or the determination signal is different from the specific signal;

Preferably, when the determination signal is the same as the specific signal, the chip works normally; otherwise the chip operates abnormally.

The invention also provides a chip security detecting method, the chip comprising at least one integrated circuit and a metal layer covering the integrated circuit;

The method includes: constructing a current loop on the metal layer;

Providing a signal generator, a signal receiver, and a judging circuit in the integrated circuit;

The signal generator outputs a specific signal, and the specific signal is input to the current loop;

The signal receiver receives a signal output by the current loop and inputs the signal to the determining circuit;

The determining circuit is based on the signal received by the signal receiver and the specific signal No. to determine whether the chip has a security risk.

Preferably, the determining circuit compares the signal received by the signal receiver with the specific signal, and if the two are the same, the chip is considered to be normal; if different, the current loop is considered to be abnormal. The chip has security risks.

Preferably, the determining circuit is an exclusive OR gate, and the XOR gate performs an exclusive OR operation on the specific signal and the signal received by the signal receiver, and determines whether the chip is in danger according to the operation result.

Preferably, the area of the current loop covering the integrated circuit and the routing direction are designed according to the size of the integrated circuit or the area of a part of the integrated circuit that needs to be safely detected.

The invention also provides a chip comprising a safety detection circuit structure, characterized in that it comprises at least one integrated circuit and a metal layer covering the integrated circuit; the metal layer contains a current loop, and the current loop covers the required Safely detecting at least a portion of the upper surface of the integrated circuit; the integrated circuit includes at least one signal generator for providing a specific signal to the current loop; and a signal receiver for receiving a signal output by the current loop; A judging circuit is configured to judge whether the chip has a security risk according to a signal received by the signal receiver and a specific signal sent by the signal generator.

The invention also provides a chip module comprising a chip of a safety detecting circuit structure.

The invention has the beneficial effects of constructing a reflow circuit in a chip metal layer, and setting a signal generator, a signal receiver, a judging circuit and the like in the chip integrated circuit to form a safety detection circuit structure, and performing safety detection on the chip when the chip When the physical structure changes or is damaged during the application process, if there is a signal abnormality in the current loop covering the surface of the integrated circuit, the chip can output feedback information in time; the chip security detection method does not need to set the chip peripheral device, and the integration degree is high and reliability. Ok, responsive. In addition, according to the application needs, the current loop of the metal layer can freely adjust the size of the area that needs to be safely detected. The chip provided by the invention avoids unpredictable risks during use, especially in devices or devices with poor working conditions.

DRAWINGS

1 and 2 are structural diagrams of a chip security detecting circuit of the present invention;

3 and FIG. 4 are schematic diagrams showing waveforms of a normal and abnormal operation of a chip safety detecting circuit according to the present invention;

5 and 6 are schematic diagrams showing the wiring direction and coverage area of the current loop of the present invention.

detailed description

The present invention will be further described below in conjunction with the drawings and specific embodiments.

The invention provides a safety detecting circuit structure, comprising a current loop structure, and a signal detecting structure for performing corresponding processing according to the signal outputted by the detecting circuit structure to determine whether an abnormality occurs.

The safety detection circuit structure is used in the chip. When the signal is abnormal, the system can be notified to enable the backup device, or the management personnel can be promptly replaced with the damaged chip to prevent the chip from continuing to be used in the event of destruction. Various A significant risk of prediction.

The invention also proposes the application of the safety detection circuit structure, and a chip safety detection method, a chip structure and a chip module structure used in the chip module.

The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

Safety detection circuit structure embodiment

As shown in FIG. 1 to FIG. 2, the security detection circuit structure provided by the embodiment includes a current loop structure, and a signal detection structure that performs corresponding processing according to the signal outputted by the detection circuit structure to determine whether an abnormality occurs. ;

The current loop structure includes at least one current loop.

The signal detecting structure includes at least: a signal generator for outputting a specific signal; a signal receiver for receiving a signal output by the current loop structure; a specific signal outputting the signal generator and the The signal receiver receives the signal to judge the structure of the circuit. Referring to Fig. 2, a square wave signal is generated by a signal generator, and then a square wave signal is sent to a return circuit and a judging circuit. The square wave signal passes through the reflow circuit to generate a detection signal. The judging circuit compares the detection received by the judging circuit with the specific signal to determine whether the chip works normally.

In this embodiment, the signal output by the signal generator is a square wave signal, and the output level is “10101010...”; after the signal receiver receives the current signal of the current loop, the current loop is not subjected to In the case of destruction, if the current is normal, the output detection signal is still a square wave signal. For example, the output level is “10101010...”. In an abnormal situation, such as when the current loop is broken, the detection signal is inconsistent with the square wave signal, for example, Return circuit There is no signal output, that is, the output level is "00000000...".

In this embodiment, the determining circuit is configured as an exclusive OR gate structure, and the signal output by the signal generator and the signal sent by the signal receiver are input to the XOR gate, and the two signals are subjected to an exclusive OR operation. Output the result of the operation.

In this embodiment, the security detection circuit structure is specifically operated to determine whether an abnormal condition occurs, as shown in Table 1, together with the table and FIG. 3 to FIG. 4, the XOR gate outputs a square wave. abnormal situation. When it is detected that the waveform of the output of the chip safety detection circuit structure is a square wave, it may be predicted that the object detected by the chip safety detection circuit structure may be abnormal.

Table 1: List of possible conditions for the signalling of the safety detection circuit structure

In other embodiments, the determining circuit structure may also be other logic gate structures, and the determining abnormality method is set according to the characteristics of the specific logic gate; the signal output by the signal generator is not limited to the square wave signal, and may be based on It is specifically designed as needed, and is not limited to this embodiment.

A chip security detection circuit structure provided by this embodiment has the beneficial effects that: the chip security detection circuit structure has a physical structure security detection function, and when the detection structure has a physical structure change or damage, the feedback information can be output in time.

Safety detection circuit structure application example

Method embodiment

The invention provides a chip security detecting method, the chip comprising at least one integrated circuit and a metal layer covering the integrated circuit;

The method includes: constructing a current loop on the metal layer;

Providing a signal generator, a signal receiver, and a determining circuit in the integrated circuit;

The determining circuit determines whether the chip has a security risk by using the signal received by the signal receiver and the specific signal.

In this embodiment, the determining circuit compares whether the signal received by the signal receiver is compared with the specific signal, and if they are the same, the current loop is considered to be working normally, that is, the chip is normal; if different It is considered that the current loop is abnormal, that is, the metal layer covering the integrated circuit is damaged, and the chip has a safety risk.

In other embodiments, the determining circuit may be an exclusive OR gate, and when the specific signal and the signal received by the signal receiver are input to the XOR gate for exclusive OR operation, finally according to the signal output by the XOR gate. Determine if the chip is at risk.

The coverage area of the current loop and the routing direction may be designed according to the size of the integrated circuit or the area of a portion of the integrated circuit that needs to be safely detected.

A chip security detection method provided by this embodiment has the beneficial effects of constructing a reflow circuit in a metal layer of the chip, and setting a signal generator, a signal receiver, a judgment circuit, and the like in the chip integrated circuit to form a safety detection circuit structure. The chip performs safety detection. When the physical structure changes or is damaged during the operation of the chip, if a signal abnormality occurs in the current loop covering the surface of the integrated circuit, the chip can output feedback information in time; the chip security detection method does not need to set the chip. Peripheral devices with high integration, good reliability and fast response. In addition, according to the application needs, the current loop of the metal layer can freely adjust the size of the area that needs to be safely detected.

Chip embodiment with safety detection circuit structure

This embodiment provides a chip having a security detection circuit structure, including the security detection circuit structure described in the foregoing embodiment.

Specifically, a chip including a safety detecting circuit structure includes at least one integrated circuit and a metal layer covering the integrated circuit; the metal layer includes a current loop covering at least a portion of the required safety detection An upper surface of the integrated circuit; the integrated circuit includes at least one signal generator for providing a specific signal to the current loop; a signal receiver for receiving a signal output by the current loop; and a determining circuit for It is determined whether the signal received by the signal receiver and the specific signal sent by the signal generator are consistent. If they are consistent, the chip is considered to be safe, otherwise the chip is considered to have a security risk.

The current loop overlies the integrated circuit as part of the metal layer surface. The reflow circuit can also adjust the routing direction and the coverage area of the current loop according to the size of the chip integrated circuit and the needs of the specific application, as shown in the schematic diagrams of FIGS. 4 and 5.

During the operation of the chip, the safety detection circuit structure may be energized periodically or randomly according to specific requirements, and the current signal output of the safety detection circuit structure is detected. When an abnormal signal is detected, the outer casing and the metal of the chip are described. The layer has been corrupted and a warning signal is sent to the CPU to put the chip into a safe state for replacement.

Since the current loop in the safety detecting circuit structure is built on the metal layer, covering the upper surface of the integrated circuit, when the chip has a physical structure change or damage during the application, covering the surface of the integrated circuit If there is a signal abnormality in the current loop, the chip can output feedback information in time, so that the system can immediately enable the spare device and remind the management to replace the damaged chip in time. Avoiding the use of the chip to some dangerous devices may bring unpredictable risks. The chip provided in this embodiment is particularly suitable for use in a device or device with a harsh working environment.

The safety detection circuit structure is integrated inside the chip, has no peripheral components, has high integration, good reliability, and rapid response. In addition, according to the needs of the application, the adjustment of the wiring of the current loop of the metal layer can be adjusted to prevent the area of the safety detection.

Chip embodiment with safety detection circuit structure

Specifically, a chip containing a security detection circuit structure includes at least one integration a circuit and a metal layer covering the integrated circuit; the metal layer comprising a current loop covering at least a portion of the upper surface of the integrated circuit required for safe detection; the integrated circuit including at least one signal generator Providing a specific signal to the current loop; a signal receiver for receiving a signal output by the current loop; and a determining circuit for determining a signal received by the signal receiver and the signal generator Whether the specific signals sent are consistent, if they are consistent, the chip is considered to be safe, otherwise the chip is considered to be a security risk.

The current loop overlies the upper surface of the integrated circuit as part of the metal layer. The reflow circuit can also adjust the routing direction and the coverage area of the current loop according to the size of the chip integrated circuit and the needs of the specific application, as shown in the schematic diagrams of FIGS. 5 and 6.

Safety detection circuit structure used in chip module embodiment

The present invention provides the chip module structure including at least one of the above-described security detection circuit structures.

The safety detection circuit structure is used in a chip module, and the circuit circuit structure covers a portion of the chip module that needs to be safely detected.

The present invention also provides the chip module structure comprising at least one of the aforementioned chips including a safety detecting circuit structure.

Various other changes and modifications may be made by those skilled in the art in light of the above-described technical solutions and concepts, and all such changes and modifications are intended to fall within the scope of the appended claims.

Claims

A chip security detection method, comprising the steps of:

Constructing a reflow circuit to generate a detection signal after passing a specific signal through the reflow circuit;

Generating a determination signal according to the detection signal;

Comparing the determination signal with a specific signal, and judging whether the chip is working normally according to the result of the comparison.
The chip security detecting method according to claim 1, wherein the specific signal is a square wave signal.
The chip security detecting method according to claim 1 or 2, wherein the determination signal and the specific signal are compared by using an exclusive OR operation.
The chip security detecting method according to claim 3, wherein the result of the comparing comprises: the determining signal is the same as the specific signal, or the determining signal is different from the specific signal.
The chip security detection method according to claim 4, wherein when the determination signal is the same as the specific signal, the chip operates normally; otherwise, the chip operates abnormally.
A chip security detecting method, the chip comprising at least an integrated circuit and a metal layer covering the integrated circuit;

The method includes constructing a current loop on the metal layer;

Providing a signal generator, a signal receiver, and a judging circuit in the integrated circuit;

Generating a specific signal by the signal generator and inputting the specific signal to the current loop;

After the signal receiver receives the signal output by the current loop, and the signal is received Number input to the determination circuit;

After the judging circuit receives the signal sent by the signal receiver, it determines whether the chip has a security risk according to the signal and the specific signal.
The chip security detecting method according to claim 6, wherein

The determining circuit compares the signal received by the signal receiver with the specific signal, and if the two are the same, the chip is considered to be normal; if different, the current loop is considered to be abnormal, and the chip is There is a security risk.
The chip security detecting method according to claim 6, wherein

The determining circuit is an exclusive OR gate, and the XOR gate performs an exclusive OR operation on the specific signal and the signal received by the signal receiver, and determines whether the chip is at risk according to the operation result.
The chip security detecting method according to claim 6, wherein

The area of the current loop covering the integrated circuit is determined according to the size of the integrated circuit or the area of a portion of the integrated circuit that needs to be safely detected.
A chip comprising a safety detection circuit structure, comprising at least one integrated circuit and a metal layer covering the integrated circuit; the metal layer containing a current loop covering at least a portion of the required safety detection The upper surface of the integrated circuit;

The integrated circuit includes:

a signal generator for providing a specific signal to the current loop;

a signal receiver, configured to receive a signal output by the current loop;

And a judging circuit for receiving a signal according to the signal receiver and the The specific signal from the signal generator determines if the chip is at risk of security.
A chip including a security detecting circuit structure according to claim 10, wherein

The determining circuit is an exclusive OR gate, and the XOR gate performs an exclusive OR operation on the specific signal and the signal received by the signal receiver, and determines whether the chip is in danger according to the operation result.
A chip module comprising at least the chip of claim 8 having a security detection circuit structure.