WO2017176309A1 - Polar codes for harq transmissions - Google Patents

Abstract

The present disclosure provides for performing polar encoding. Performing polar encoding can include selecting a length S of a number of shortened bits and a length P of a number of punctured bits based on a HARQ scheme, encoding the plurality of information bits to generate a base code, interleaving a result of shortened polar encoder module to generate a codeword which includes the base code minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E, and providing the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation and providing a result of the division to a channel to transmit a polar code to a receiving device.

Description

POLAR CODES FOR HARQ TRANSMISSIONS

Related Applications

[0001] This application is a non-provisional of U.S. Provisional Patent Application No. 62/334,772, filed May 1 1 , 2016 and U.S. Provisional Patent Application No. 62/320,094, filed April 8, 2016, each of which is hereby incorporated by reference herein in its entirety.

Technical Field

[0002] The present disclosure relates to polar code design including support for hybrid automatic repeat request (HARQ) transmissions. In particular, the present disclosure relates to polar encoding and decoding for HARQ transmissions.

Brief Description of the Drawings

[0003] FIG. 1 is a system diagram illustrating a polar coding chain according to one embodiment.

[0004] FIG. 2 is a block diagram illustrating rate matching and interleaving according to one embodiment.

[0005] FIG. 3 is a diagram illustrating performance of different parameter setups depending on HARQ scheme according to one embodiment.

[0006] FIG. 4 is a diagram illustrating polar encoding circuitry according to one embodiment.

[0007] FIG. 5 is a block diagram illustrating a receive processing chain according to one embodiment.

[0008] FIG. 6 is a diagram illustrating polar decoding circuitry according to one embodiment.

[0009] FIG. 7 is a diagram illustrating nodes in a polar decoding circuitry according to one embodiment. [0010] FIG. 8 is a block diagram illustrating electronic device circuitry that may be eNodeB circuitry, user equipment (UE) circuitry, network node circuitry, or some other type of circuitry according to one embodiment.

[0011] FIG. 9 is a block diagram illustrating a method for performing polar encoding according to one embodiment.

[0012] FIG. 10 is a block diagram illustrating a method for performing polar encoding according to one embodiment.

[0013] FIG. 1 1 is a block diagram illustrating a method for a polar decoder according to one embodiment.

[0014] FIG. 12 is a block diagram illustrating components of a device according to one embodiment.

[0015] FIG. 13 is a block diagram illustrating components according to some embodiments.

Detailed Description of Preferred Embodiments

[0016] Wireless mobile communication technology uses various standards and protocols to generate and/or transmit data between a base station and a wireless communication device. Wireless communication system standards and protocols can include, for example, 3rd Generation Partnership Project (3GPP) long term evolution (LTE); the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard, which is commonly known to industry groups as worldwide interoperability for microwave access (WiMAX); and the IEEE 802.1 1 standard, which is commonly known to industry groups as Wireless Local Area Network (WLAN) or Wi-Fi. In 3GPP radio access networks (RANs) in LTE systems, a base station may include Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (also commonly denoted as evolved Node B, enhanced Node B, eNodeB, or eNB) and/or Radio Network Controllers (RNCs) in the E-UTRAN, which communicate with a wireless communication device, known as user equipment (UE). In LTE networks, the E-UTRAN may include a plurality of eNodeBs and may communicate with the plurality of UEs. LTE networks include a radio access technology (RAT) and core radio network architecture that can provide high data rate, low latency, packet optimization, and improved system capacity and coverage.

[0017] Polar codes are a class of error-correction codes that achieve the capacity of memoryless communication channels. Some examples described herein reference binary polar codes, although non-binary polar codes can also be employed using the examples descried herein.

[0018] An encoder can compute = U^G_N , where t/ is a vector of binary bits, G_N is the n^Ath Kronecker power of the 2x2 matrix G = [^] . ^anc' %i '^{s a} codeword. The codeword can comprise a vector of binary bits. N denotes the length of a vector. For example, the vector of binary bits and the codeword can each comprise N binary bits. The codeword can be transm itted through a communication channel such as a physical uplink shared channel (PUSCH) and/or a physical downlink shared channel (PDSCH), among other examples of a communication channel, t/ can be provided to an encoder to encode.

[0019] Various coding rates can be achieved by setting the desired number of encoder inputs U_t to data bits (e.g. , information bits) and freezing the remaining bit values to predeterm ined values (e.g. , zeros) and encoding the result to form an output codeword. A coding rate can be defined as the ratio of the number of data bits that are input to the encoder to the number of codeword bits output by the encoder. For example, to obtain a rate of a half code, half of the Ui bits can be set to data bits (e.g. , information bits) and the remaining half of the Ui bits can be frozen to their predeterm ined values (e. g. zeros). The choice of which bit indices to freeze, what values to freeze to, and which bits to use for data can be fixed before transmission and can be known at both the transm itter and the receiver.

[0020] If the receiver (e.g. , user equipment (UE)) detects an error in the reception of a data packet, for example, via perform ing a cyclic redundancy check (CRC), the UE can request additional transm issions of the data packet. The transm itter (e.g. , evolved node B (eNodeB)) can then send more coded bits and/or parity bits associated with the data packet to aid the receiver in recovering the original data packet. This may be in the form of a repetition of the same codeword (or a part of it) via a Chase combining transm ission of a HARQ transm ission and/or fresh information about the original data often in the form of additional parity bits via an incremental redundancy I R transm ission of a HARQ transm ission (HARQ-IR), or a combination thereof. Several

retransm issions may take place (e.g. , until the receiver UE can correctly decode the data packet). [0021] In a HARQ operation, if a first transmission of a data packet fails, the transmitter can repeat the same packet or transport block in a second transmission. Based on the encoding (e.g. , redundancy version, allocated modulation, and coding schemes, etc.), the parity bits selected for the second transmission may or may not be identical to that transmitted in the first transmission.

[0022] Information and frozen bits can be decoded based on the prem ise that each code bit X_t can be sent through independent realizations of a channel W. In some examples such as frequency selective fading channels, high order modulation, and/or puncturing for HARQ-I R purposes, each code bit X_t can pass through a different type of channel. The qualities of these different types of channels can vary widely.

[0023] In some examples, a polar coding chain can be implemented for HARQ transm ission that address coding for high order modulation, robust performance under varying channel conditions, support Chase combining HARQ transm issions and HARQ-IR transm issions, and/or rate matching that provides flexible polar codeword length.

[0024] Reference is now made to the figures, in which like reference numerals refer to like elements. For clarity, the first digit of a reference numeral indicates the figure number in which the corresponding element is first used. In the following description, numerous specific details are provided for a thorough understanding of the embodiments disclosed herein. However, those skilled in the art will recognize that the embodiments described herein can be practiced without one or more of the specific details, or with other methods, components, or materials. Further, in some cases, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] FIG. 1 is a system diagram illustrating a polar coding chain according to one embodiment. FIG. 1 includes a polar coding chain 100 comprising a shortened polar encoder module 1 10, a rate matching and channel interleaver (RM&CI) module 1 12, a modulation module 1 14, a channel 1 16, a demodulation module 1 18, a derate matching and channel interleaver (D-MR&CI) module 120, and a shortened polar decoder module 122. [0026] The shortened polar encoder module 1 10, the RM&CI 1 12 module 1 12, and the modulation module 1 14 can including a coding scheme that can be performed by a UE and/or an eNodeB. The demodulation module 1 18, the D- MR&CI module 120, and the shortened polar decoder module 122 can include a decomding scheme that can also be performed by the UE and/or the eNodeB.

[0027] As used in FIG. 1 and the description of FIG. 1 , N is a base code output length of 2". 102 is a number of information bits. S is a number of shortened bits. P is a number of punctured bits. E is a number of extension and/or repeated bits. Ns is a number of spatial streams. M is a number of bits per modulation. N_Bc 104 (e.g., also referred to as N-S 104) is a base codeword length after shortened polar encoder equal to N-S. N_CB 106 (e.g., also referred to as N-S-P+E 106) is a codeword length after rate matching and channel interleaving (e.g., RM&CI module 1 12) equal to N-S-P+E.

[0028] A number of log-likelihood ratios (LLRs) associated with the K 102 are represented by k 103. A number of LLRs associated with S are represented by s. A number of LLRs associated with P are represented by p. A number of LLRs associated with E are represented by e. An LLR associated with M is represented by m. A number of LLRs associated with N-S 104 is represented by n-s 105. A number of LLRs associated with N-S-P+E 106 is represented by n-s-p+e 107. A number of LLRs associated with a (N-S-P+E)/( N_S ^*M) 108 is represented by (n-s- p+e)/( n_s ^*m) 109.

[0029] As used herein, K 102, N, S, P, E, N_S, and M can refer to a plurality of bits and/or a quantity of bits, k 103, n, s, p, e, n_s, and m can refer to a plurality of received bits, LLRs, and/or a quantity of LLRs. For example, the 102 can be a bit- vector comprising 512 bits. The 102 can refer to both the bits in the bit-vector and/or the quantity of bits (e.g., bit-vector length) such as 512 bits. The N-S 104 can refer to both the bit-vector resulting from removing the bit-vector S from the bit-vector N and the quantity of bits (e.g., bit-vector length) in a result bit-vector from removing the bit-vector S from the bit-vector N.

[0030] For encoding, the K 102 can be provided to the shortened polar encoder 1 10 to produce the N-S 104. The N-S 104 is provided to the RM&CI module 1 12 to produce the N-S-P+E 106. The N-S-P+E 106 is provided to the modulation module 1 14 to produce a (N-S-P+E)/( N_S ^*M) 108. The (N-S-P+E)/( N_S ^*M) 108 is provided to the channel 1 16 for transmission. [0031] The channel 1 16 can provide the (n-s-p+e)/(n_s ^*m) 109 to a demodulation module 1 18 go generate the n-s-p+e 107. The n-d-p+r 107 can be provided to the D-RM&CI module 120 to generate the n-d 104. The n-d 104 is provided to the shortened polar decoder module 122 to generate the k 102. The shortened polar encoder module 1 10, the RM&CI module 1 12, the modulation module 1 14, and/or the channel 1 16 can be provided as part of a transmitting (e.g., eNodeB). The channel 1 16, the demodulation module 1 18, the D-RM&CI module 120, and/or the shortened polar decoder module 122 can be provided as part of a receiver (e.g., UE).

[0032] The shortened polar encoder module 1 10 has access to polar code constructions optimized for one or more signal-to-noise ratio (SNR) levels and base code output lengths N=2ⁿ where n is a positive integer. That is, given an SNR and a code length, the shortened polar encoder module 1 10 can have a predetermined rule for choosing which bits to use as data and which to freeze for supporting several coding rates between 0 and 1 .

[0033] Constructions for base codeword length N_BC (e.g. , N-S 104), other than powers of 2, are obtained by the shortening procedure with a minimal loss in performance. The shortened polar encoder 1 10 can select a shortening length S and use the shortened polar code of length N_BC = N - S 104 as the base codeword length to be used in rate matching. The shortening length S can be chosen in conjunction with the puncturing and extension parameters.

[0034] The polar coding chain can be used in conjunction with any modulation scheme such as QAM, multiple antenna mapping, resource mapping, OFDM, and/or single carrier modulation, for example. The receiver performs the reverse operations of the transmitter. The LLR values are calculated at the demodulator module 1 18. The LLR values for extended bits are added together. Punctured bit LLRs are set to zero, and the whole LLR block is then de- interleaved via the D-RM&CI module 120. The LLR block N-S 104 is then decoded via the shortened polar decoder module 122. Any polar decoding schemes can be utilized in the shortened polar decoder module 122.

[0035] FIG. 2 is a block diagram illustrating rate matching and interleaving according to one embodiment. FIG. 2 includes an RM&CI module 212 comprising an interleaving module 230 and a rate-matching module 232. An N-S 204-1 can be provided to the interleaving module 230 to generate an N-S 204-2. The N-S 204-2 can be provided to the rate-matching module 232 to generate an N-S-P+E 206.

[0036] Code shortening is followed by the interleaving module 230 in the RM&CI module 212. The RM&CI module 212 can configure the codeword such that each bit in the codeword statistically suffers the same amount of noise. That is, the RM&CI module 212 can configure the codeword such that each bit in the codeword is equally protected. In some examples, the RM&CI module 212 can be analogous to a bit-interleaver in a bit interleaved coded modulation (BICM) or a sub-block interleaver in LTE rate matching.

[0037] The proposed embodiments avoid constructing different polar codes for every possible channel variation pattern. For example, channel gains at different subcarriers can be different in a frequency selective fading channel in orthogonal frequency division multiplexing (OFDM)/orthogonal frequency division multiple access (OFDMA) systems. Different bits have different bit channel qualities for most high order modulation methods, such as 16

quadrature amplitude modulation (16QAM) or higher. Code puncturing can also cause a time varying channel, where punctured code bits have zero reliability at the receiver.

[0038] The interleaving module 230 can be optimized for shortening, puncturing, extension, and/or fading patterns. Since shortening, puncturing, and/or extension patterns may be optimized based on the channel's fading or time-variation patterns, the number of optimizations can be very large and/or the optimization may be intractable. As such, a single interleaving module 230 as part of the RM&CI module 212 is used in the embodiments described herein.

[0039] In some examples, the interleaving module 230 can be a random interleaver. Existing interleaving rules (e.g. , the sub-block interleaver and/or the turbo code internal interleaver) can be utilized in LTE/LTE-A systems.

[0040] Rate matching starts with a choice of shortening length for the base code output length (mother polar code). The rate-matching module 232 completes the rate matching procedure by puncturing and/or extending the shortened and interleaved codeword N-S 204-2. The shortening, puncturing, and/or extension lengths are chosen jointly to match the dictated code rate and HARQ requirements. [0041] Puncturing a bit refers to removing a bit from a bit-vector. Extending the code refers to resending certain code bits. N, S, P, and/or E are positive integers. If P > 0, then the last P bits of the shortened and interleaved base codeword can be punctured. The last bit can refer to the bit associated with the greatest index of a bit-vector such as the codeword. The last P bits refers to the P bits associated with the greatest indexes of the codeword. If E > 0, then the first E bits can be extended (e.g. , repeated). The first bit of the codeword is a bit associated with a first index of the codeword bit-vector. The first E bits refers to first E bits from the codeword bit-vector. If the (c₀, c-i , C/v-s-i ) bit-vector represents the shortened and interleaved base codeword (e.g. , N-S 204-2), then the output of the rate-matching module 232 can be the (c₀, c-i , . . . , C/V-S-P-I , c₀, c-i , c_E-1 ) bit-vector (e.g. , N-S-P+E 206). The N-S-P+E 206 can then be provided via a circular buffer for HARQ-IR transmission.

[0042] The parameters N, S, P, and/or E can be selected. The number of coded bits before modulation for the initial transmission can be N_CB = N— S— P + E = 768 and the number of information bits can be K = 512, for example. The HARQ can dictate the number of IR bits to also be N_CB = 768. A code rate can be defined as R = K/N_CB . There are many choices of S, P, and/or E that can satisfy N_CB and K. A number of examples for satisfying N_CB and K are provided.

[0043] In a first example, N = 2^ ^1o^ⁿC S = N - N_cb, P = 0, and/or £ = 0. In a second example, N = 2^{i log2 WcB l}, S = 0, P = N— N_CB , and/or E = 0. That is, in some examples, E = 0 and/or at least two of S, P, and E can be equal to zero. In other examples, N =

s = 0, P = 0, and/or E = N_CB - N for HARQ Chase combining. In some examples, [xj = min{n ε Z\n≥ x} represents the ceiling function.

[0044] Since shortening incurs a minimal error performance penalty, the first example with shortening alone may be used for aiming an initial transmission. In the first example, no bits are punctured or extended. Subsequent transmissions of the first example include a simple repetition of the first transmission. For example, a HARQ transmission can be performed using chase combining. As such, the first example can be selected for Chase combining HARQ

transmissions. [0045] The second example can be selected for HARQ-IR transmissions. The second example may perform worse than the first example for initial

transmission as shown in FIG. 3. However, the second example may perform better than the first example for subsequent HARQ transmissions as shown in FIG. 3. As such, the selecting S, P, and/or E may depend on the HARQ scheme used to transmit the codeword. Some of these values may be predetermined for a given transport block size and HARQ version, or may be explicitly signaled in a control channel such as a physical downlink control channel (PDCCH).

[0046] FIG. 3 is a diagram illustrating the performance of different parameter setups depending of HARQ scheme according to one embodiment. FIG. 3 includes the graph 336 comprising a block error rate (BLER) axis 338 and an SNR 340.

[0047] The graph 336 shows that an initial transmission 342 of the first example, described with relation to FIG. 2, performs better than an initial transmission 344 of the second example. Performance can be judged based on the BLER. As such, the initial transmission 342 can have a lower BLER than the initial transmission 344. The graph 336 also shows that the second transmission 346 of the second example performs better than the second transmission 348 of the first example.

[0048] FIG. 4 is a diagram illustrating polar encoding circuitry 410 according to one embodiment. The polar encoding circuitry 410 can correspond to the shortened polar encoder 1 10 in FIG. 1 . The polar encoding circuitry 410 shows an A bit-vector 450 which corresponds to the 102 in FIG. 1 . The polar encoding circuitry 410 also shows a D bit-vector 456 which corresponds to the N-S 104 in FIG. 1 . The polar encoding circuitry 410 further shows a B bit-vector 452 and a C bit-vector 454. The A bit-vector 450 can be an input bit-vector and the D bit-vector 456 can be a result bit-vector. The B bit-vector 452 and the C bit-vector 454 are internal bit-vectors.

[0049] The A bit-vector 450 comprises the bits (a₀, . . . , ₇). The B bit-vector 452 comprises the bits (b₀, . . . , b₇). The C bit-vector 454 comprises the bits

(c₀, . . . , c₇). The D bit-vector 456 comprises the bits (d₀, . . . , d₇).

[0050] To generate a codeword of length 8, as shown in the polar encoding circuitry 41 0, a total of 32 bits can come into existence. For a length N code, a total of N * (log₂N + 1) bits are generated. The A bit-vector 450 can include the original data bits (e.g. , the K 1 02 in FIG. 1 ) and frozen bits that are input to the polar encoding circuitry 41 0. The D bit-vector 456 comprises codeword bits (d₀, . . . , d₇) that are output by the polar encoding circuitry 410. The B bit-vector 452 (e.g. , (b_Q, . . . , b₇)) and the C bit-vector 454 (e.g. , (c₀, . . . , c₇)) comprise internal bits that are computed in the course of encoding but are normally not

transmitted or considered as part of the codeword. There are some equalities among bits. For example, a₇ = b₇ = c₇ = d₇, and b₂ = c₂. In the proposed method, the transmitter (e.g. , eNodeB) can generate and/or transmit a subset of the 32 bits in each retransmission. The transmitter can select different subsets based on different system requirements and/or capabilities.

[0051] The stage corresponding to generating the B bit-vector 452 and/or the C bit-vector 454 is referred to as an intermediate stage or a stage associated with internal bits. The stage corresponding to the D bit-vector 456 is referred to as a stage associated with a conventional codeword of a polar coding.

[0052] The transmitter can generate, provide, and/or transmit a subset of the D bit-vector 456 in each transmission and retransmission to generate, provide, and/or transmit a chase combining HARQ transmission. Retransmissions can include internal bits (e.g. , subsets of the B bit-vector 452 and/or the C bit-vector 454) that do not necessarily appear in the typical polar codeword. As such, generating and/or transmitting internal bits can include generating and/or transmitting a fresh set of parity bits.

[0053] A number of examples can support HARQ transmissions by utilizing bits that are typically internal to the polar encoding circuitry 410 and that do not typically appear in the original codeword. For retransmissions, the selected subset of bits can include a mixture of the typical codeword bits and internal bits. For example, this corresponds to a mixture of chase/IR scheme. An example of this is to send (b₀, . . . , b₇) in retransmission.

[0054] For general modes of transmission including puncturing and extension for rate matching, the unique bits may be placed in a circular buffer. For example, the buffer can be unrolled as

d₀, ... , d₇, c_Q, ... , c₆, b₀, b_lt b₄, b₅, a₀, a₂, a₄, a₆, (start agairi)d₀, ... , d₇, c₀, .... In some examples, bits can be placed in the circular buffer in any other order. In each transmission, the transmitter can send the next bits in the buffer. The next bits can comprise as many bits in the buffer as required. The buffer can wrap around to the beginning upon arriving at the last bit in the buffer. The encoding can be systematic or partially systematic. That is, the information block bits or some of the information block bits can appear in the buffer.

[0055] The polar encoding circuitry 410 can comprise a plurality of nodes wherein a plurality of operations are performed. For example, the polar encoding circuitry 410 can comprise check nodes 460 and variable nodes 462.

[0056] The check nodes 460 are shown in FIG. 4 as circles with a plus sign inside the circles. The check nodes 460 can perform an operation such as an exclusive OR (XOR) operation. Each of the check nodes 460 can receive two bits as input and can generate an output by applying the operation on both the bits. For example, a check node in line with bit a₀ can receive as input the a₀ bit and the ai bit. The check node can generate the b₀ node. A check node in line with the a₂ bit can receive the a₂ bit and the a₃ bit to generate the b₂ bit. A check node in line with the a₀ bit and the bo bit can receive the b₀ bit and the b₂ bit to generate the c₀ bit, among other examples of check nodes 460. The bits that are generated by the check nodes 460 are unique bits.

[0057] The variable nodes 462 are shown as dots in the polar encoding circuitry 410. The variable nodes 462 can perform a copy operation. For example, the variable node in line with the ai bit can copy the ai bit to generate the bi bit. As such, the ai bit is equal to the bi bit. That is, neither the ai bit nor the bi bit is unique. The bits generated by the variable nodes 462 are non- unique bits.

[0058] FIG. 5 is a block diagram illustrating a receive processing chain 500 according to one embodiment. The receive processing chain 500 includes decoder module 522, HARQ memory module 560, soft-combining module 562, and LLR initializer for internal bits module 564. The receive processing chain 500 also includes channel LLRs. The decoder module 522, the HARQ memory module 560, the soft-combining module 562, and/or the LLR initializer for internal bits module 564 can be analogous to the shortened polar decoder 122 in FIG. 1 .

[0059] The receive processing chain 500 can be implemented as part of a receiver (e.g., UE). The channel LLRs module 568 can provide LLRs corresponding to bits provided by a channel. The channel LLRs module 568 can generate the LLRs and/or can provide LLRs generated by the channel. The LLRs correspond to the current transmission of the packet. [0060] The soft-combining module 562 combines the LLRs of the current packet provided by the channel LLRs module 568 and LLRs of previous transmissions of the packet stored in the HARQ memory module 560. Since the transmissions (e.g., combined previous transmissions and current transmissions) may include LLRs corresponding to codeword bits and internal bits, the soft combining module 562 outputs both types of LLRs. That is, the soft combining module 562 generates and/or initializes the LLRs for internal bits via the LLR initializer for internal bits module 564. The LLRs for internal bits are input to the decoder module 522 separately (e.g., logically) from the LLRs corresponding to the codeword LLRs such that the decoder module 522 can use the internal bit LLRs for initializing step in the decoding (e.g., list decoding, successive cancellation decoding, etc.).

[0061] FIG. 6 is a diagram illustrating polar decoding circuitry 622 according to one embodiment. The polar decoding circuitry 622 can be part of a decoder 522 in FIG. 5. The polar decoding circuitry 622 can include a D vector 656, a C vector 654, a B vector 652, and an A vector 650. The polar decoding circuitry 622 can also include the check nodes 650 and the variable nodes 662. The polar decoding circuitry 622 can also include dangling edges 670.

[0062] Polar decoders can be augment by incorporating information from (re)transmissions as shown by the dangling edges 670. The polar decoder can be any message passing algorithm; for example, a successive cancellation decoder, a list decoder, and/or a belief propagation. The augmentation including the dangling edges 670 can be incorporated into any polar decoder.

[0063] In the polar decoder circuitry 622, each edge can hold a message (e.g. , a list of messages, for example in the case of list decoding) in the form of LLRs. Edges are shown in the polar decoder circuitry 622 both as edges that are connected at both ends to nodes, and as dangling edges that are connected to a node only at one end..

[0064] In FIG. 6, the vectors 650, 652, 654, and 656 represent bits and/or messages. The messages can include the LLRs and/or the bits provided by the channel. The messages associated with vectors 650, 652, 654, and 656 correspond to the A bit-vector 450, the B bit-vector 452, the C bit-vector 456, and the D bit-vector 458 in FIG. 4, respectively. [0065] As described above, the augmented retransmission comprises sending parity bits that are typically internal to the original encoder in addition to the polar codeword. To use the parity bits (e.g. , internal unique bits or internal bits) in decoding, the variable nodes 662 with additional dangling edges 670 corresponding to strictly internal bit positions (e.g. , unique bits) are incorporated into the decoder circuitry 622. The unique bits can include, for example, a bit c₀ in FIG. 4 which can correspond to the c₀ message in FIG. 6 and a corresponding dangling edge coupled to the decoder circuitry 622 via a variable node 662.

[0066] Utilizing the dangling edges 670 associated with the unique bits can include initializing the LLRs and/or the messages associated with the dangling edges 670. That is, a decoder comprising decoder circuitry 622 can be initialized with the LLRs of the received bits. For example, if a₀ was frozen to zero in FIG. 4, then the a₀ message comprising an associated LLR can be initialized to infinity, or a very large number in schemes associating positive LLR to binary 0-bits and negative LLR to binary 1 -bits. In some examples, frozen bits on the edges of the decoder circuitry and/or the encoder circuitry can result in frozen internal bits. As such, bits from the encoder can be selected for transmission can exclude frozen bits given that the values for frozen bits are already known and can be recreated at the decoder with certainty. If a bit in the graph is not frozen, then its dangling edge LLR can be initialized to the sum of received LLRs for that bit and to zero if it was never transmitted. For example, the LLR for a dangling edge 670 corresponding to an internal bit on a third transmission can be initialized to the sum of a corresponding received LLR for that bit during a first transmission, a second transmission, and a third transmission,. The LLRs can be utilized to determine whether the bit-vector received from a channel is the bit-vector provided to the channel.

[0067] FIG. 7 is a diagram illustrating nodes in a polar decoding circuitry according to one embodiment. FIG. 7 includes nodes 772-1 and 772-2 shown in four different examples. FIG. 7 also includes messages 780-1 and 780-2 and messages 784.

[0068] The message 780-1 can be provided from the node 772-2 to the node 772-1 . The message 780-2 can also be provided from the node 772-1 to the node 772-2. In some examples, the message 780-1 can be provided from the node 772-2 to the node 772-1 through the node 772-3. The message 780-2 can be provided from the node 772-1 to the node 772-2 through the node 772-3.

[0069] Adding variable nodes (e.g. , nodes 773) and dangling edges corresponding to internal bits can allow to augment any existing message passing schedule in a decoder. The edges in FIG. 7 represent horizontal edges in FIG. 6. The nodes 772-1 and 772-2 (e.g. , nodes X and Y) may be any two neighboring nodes in FIG. 6. The augmented decoder can include added variable node 772-3 between the nodes 772-1 and 772-2 and the corresponding dangling edge with an associated message 784 (e.g. , message l_XY). In the decoder, each visit to the node 772-1 that generates the message 780-2 (e.g. , message m_XY) is followed by a visit to the newly introduced node 772-3, which computes l_XY + m_YX and writes the result to the node 772-2. The same can be done in the reverse direction. That is, following a visit to the node 772-2 that generates the message 780-1 (e.g. , message m_YX) is followed by a visit to the newly introduced node 772-3, which computes l_XY + m_YX and writes the result to the node 772-1 .

[0070] At the transmitter, a redundancy version indicator may be used to indicate which bits of the buffer are transmitted in a given transmission for a data packet. The redundancy version may be explicitly indicated in the control information associated with the information block (or a transport block) or may be implicitly tied to a known parameter such as a subframe number or a transmission number. For example, the redundancy version indicator can be equal to one for the first transmission and/or two for the second transmission, etc. ). The transmission number can be used in self-decodable transmissions.

[0071] FIG. 8 is a block diagram illustrating electronic device circuitry that may be eNodeB circuitry, user equipment (UE) circuitry, network node circuitry, or some other type of circuitry according to one embodiment. FIG. 8 illustrates an electronic device 800 that may be, or may be incorporated into or otherwise part of, an eNodeB, a UE, or some other type of electronic device in accordance with various embodiments. Specifically, the electronic device 800 may be logic and/or circuitry that may be at least partially implemented in one or more of hardware, software, and/or firmware. In embodiments, the electronic device logic may include radio transmit/transmitter logic (e.g., a first transmitter logic 877) and receive/receiver logic (e.g., a first receiver logic 883) coupled to a control logic 873 and/or a processor 871 . In embodiments, the transmit/transmitter and/or receive/receiver logic may be elements or modules of transceiver logic. The first transmitter logic 877 and the first receiver logic 883 may be housed in separate devices. For example, the first transmitter logic 877 can be incorporated into a first device while the first receiver logic 883 is incorporated into a second device, or the first transmitter logic 877 and the first receiver logic 883 can be incorporated into a device separate from a device including any combination of the control logic 873, a memory 879, and/or the processor 871 . The electronic device 800 may be coupled with or include one or more antenna elements 885 of one or more antennas. The electronic device 800 and/or the components of the electronic device 800 may be configured to perform operations similar to those described elsewhere in this disclosure.

[0072] In embodiments where the electronic device 800 implements, is

incorporated into, or is otherwise part of a UE and/or an eNodeB, or a device portion thereof, the electronic device 800 can generate and/or transmit polar codes. The processor 871 may be coupled to the first receiver and first transmitter. The memory 879 may be coupled to the processor 871 having control logic instructions thereon that, when executed, generate and/or transmit polar codes.

[0073] In embodiments where the electronic device 800 receives data, generates data, and/or transmits data to/from a UE to implement a downlink signal including the polar codes, the processor 871 may be coupled to a receiver and a transmitter. The memory 879 may be coupled to the processor 871 having the control logic

instructions thereon that, when executed, may be able to configure a V2X

communication based on geographical location.

[0074] As used herein, the term "logic" may refer to, be part of, or include an application specific integrated circuit (ASIC), an electronic circuit, the processor 871 (shared, dedicated, or group), and/or the memory 879 (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide

the described functionality. Specifically, the logic may be at least partially

implemented in, or an element of, hardware, software, and/or firmware. In some embodiments, the electronic device logic may be implemented in, or functions associated with the logic may be implemented by, one or more software or firmware modules. [0075] FIG. 9 is a block diagram illustrating a method 985 for performing polar encoding according to one embodiment. The method 985 includes selecting 903 a length S of a number of shortened bits and a length P of a number of punctured bits based on a HARQ scheme, encoding 905 the plurality of information bits via a polar encoder module to generate a base code, with a length of N, minus the number of shortened bits, interleaving 907, via an interleaver module, a result of the polar encoder module to generate a codeword which includes the base code minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E, providing 909 the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation, and providing 91 1 a result of the division to a channel to transmit a polar code to a receiving device.

[0076] The HARQ scheme can include a chase combining transmission and/or a HARQ-IR transmission. The method 985 further comprises setting N to

2^A(ceil(log2(N_CB)) and E to zero, where N_CB is a length of the codeword. The method 985 also comprises setting S to N-N_CB and P to zero. The method 985 can further comprise setting S to zero and P to N-N_CB-

[0077] The method 985 can further comprise setting N to 2^A(floor(log2(N_CB)), wherein N_CB is a length of the codeword and E to N_CB-N. The method 985 can also comprise setting S to zero and P to zero.

[0078] FIG. 10 is a block diagram illustrating a method 1087 for performing polar encoding according to one embodiment. The method 1087 comprises generating 1021 at least a plurality of B internal bits by performing a plurality of operations on the A data bits, generating 1023 a plurality of D codeword bits by performing a plurality of operations on the B internal bits, wherein the D codeword bits correspond to a first stage of a polar encoder, and the B internal bits correspond to a second stage of the polar encoder and wherein the first stage and second stage are distinct stages of the polar encoder, and providing 1025 a subset of the A data bits, the D codeword bits, and the B internal bits to a channel for a transmission.

[0079] The HARQ transmission can be at least one of a chase combining HARQ transmission and a HARQ-IR transmission. The A data bits can comprise data bits and frozen bits. The length of the A data bits, the length of the B internal bits, and the length of the D codeword bits can be the same length. The method 1087 further comprises generating a subsequent HARQ transmission comprising a subset of the A data bits, the B internal bits, and the D codeword bits.

[0080] The HARQ transmission can include a circular buffer of the subset of the A data bits, the B internal bits, and the D codeword bits. The subset of the A data bits, the B internal bits, and the D codeword bits can include at least one of the D codeword bits and the B internal bits, the D codeword bits and a portion of the B internal bits, the B internal bits and a portion of the D codeword bits, or the B internal bits.

[0081] FIG. 1 1 is a block diagram illustrating a method 1 189 for a polar decoder according to one embodiment. The method 1 189 comprises initializing 1 131 a first plurality of LLRs for a plurality of bits received from a channel associated with a HARQ transmission, initializing 1 133 a second plurality of LLRs for a plurality of dangling edges associated with the plurality of bits, performing 1 135 a plurality of operations on a first plurality of messages and a second plurality of messages to generate a third plurality of LLRs, where the first plurality of messages comprise the first plurality of LLRs and the second plurality of messages comprise the second plurality of LLRs, and determining 1 137 an estimate of an information block comprising the first plurality of bits and the second plurality of bits based on the third LLRs.

[0082] In some examples, the plurality of operations comprise addition

operations. Each of the plurality of operations can also comprise a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second LLR, a multiplication operation to determine a sign by multiplying a sign of the first LLR and a sign of the second LLR, and providing the minimum LLR with the sign.

[0083] The method 1 189 also comprises initializing LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to a predefined value, initializing LLRs from the first plurality of LLRs and the second plurality of LLRs associated with non- frozen bits from the first plurality of bits and the second plurality of bits to a sum of received LLRs that are associated with a bit, and initializing LLRs from the first plurality of LLRs and the second plurality of LLRs to zeros for bits that were not received. The estimate of information block can comprise which codeword was transmitted through the channel. The second plurality of bits can be associated with internal bits of a polar code.

[0084] FIG. 12 is a block diagram illustrating components of a device according to one embodiment. In some embodiments, the device may include application circuitry 1203, baseband circuitry 1205, Radio Frequency (RF) circuitry 1207, front- end module (FEM) circuitry 1209, and one or more antennas 1214, coupled together at least as shown in FIG. 12. Any combination or subset of these components can be included, for example, in a UE device or an eNodeB device.

[0085] The application circuitry 1203 may include one or more application processors. By way of non-limiting example, the application circuitry 1203 may include one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processor(s) may be operably coupled and/or include memory/storage, and may be configured to execute instructions stored in the memory/storage to enable various applications

and/or operating systems to run on the system.

[0086] By way of non-limiting example, the baseband circuitry 1205 may include one or more single-core or multi-core processors. The baseband circuitry 1205 may include one or more baseband processors and/or control logic. The baseband circuitry 1205 may be configured to process baseband signals received from a receive signal path of the RF circuitry 1207. The baseband circuitry 1205 may also be configured to generate baseband signals for a transmit signal path of the RF circuitry 1207. The baseband circuitry 1205 may interface with the application circuitry 1203 for generation and processing of the baseband signals, and for controlling operations of the RF circuitry 1207.

[0087] By way of non-limiting example, the baseband circuitry 1205 may include at least one of a second generation (2G) baseband processor 121 1 A, a third generation (3G) baseband processor 121 1 B, a fourth generation (4G) baseband processor 121 1 C, and other baseband processor(s) 121 1 D for other existing generations and generations in development or to be developed in the future (e.g., fifth generation (5G), sixth generation (6G), etc.). The baseband circuitry 1205 (e.g., at least one of the baseband processors 121 1 A-121 1 D) may handle various radio control functions that enable communication with one or more radio networks via the

RF circuitry 1207. By way of non-limiting example, the radio control functions may include signal modulation/demodulation, encoding/decoding, radio

frequency shifting, other functions, and combinations thereof. In some

embodiments, modulation/demodulation circuitry of the baseband circuitry 1205 may be programmed to perform Fast-Fourier Transform (FFT), precoding, and

constellation mapping/demapping functions, other functions, and combinations thereof. In some embodiments, encoding/decoding circuitry of the baseband circuitry 1205 may be programmed to perform convolutions, tail-biting convolutions, turbo, Viterbi, Low Density Parity Check (LDPC) encoder/decoder functions, other functions, and combinations thereof. Embodiments of modulation/demodulation and encoder/decoder functions are not limited to these examples, and may include other suitable functions.

[0088] In some embodiments, the baseband circuitry 1205 may include elements of a protocol stack. By way of non-limiting example, elements of an evolved universal terrestrial radio access network (E-UTRAN) protocol include, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), and/or radio resource control (RRC) elements. A central processing unit (CPU) 121 1 E of the baseband circuitry 1205 may be programmed to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers. In some embodiments, the baseband circuitry 1205 may include one or more audio digital signal processor(s) (DSP) 121 1 F. The audio DSP(s) 121 1 F may include elements for compression/decompression and echo cancellation. The audio DSP(s) 121 1 F may also include other suitable processing elements.

[0089] The baseband circuitry 1205 may further include a memory/storage

121 1 G. The memory/storage 121 1 G may include data and/or instructions for operations performed by the processors of the baseband circuitry 1205 stored thereon. In some embodiments, the memory/storage 121 1 G may include any combination of suitable volatile memory and/or non-volatile memory. The

memory/storage 121 1 G may also include any combination of various levels of memory/storage including, but not limited to, read-only memory (ROM) having embedded software instructions (e.g., firmware), random access memory (e.g., dynamic random access memory (DRAM)), caches, buffers, etc. In some

embodiments, the memory/storage 121 1 G may be shared among the various processors or dedicated to particular processors. [0090] Components of the baseband circuitry 1205 may be suitably combined in a single chip or a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 1205 and the application circuitry 1203 may be

implemented together, such as, for example, on a system on a chip (SOC).

[0091] In some embodiments, the baseband circuitry 1205 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 1205 may support communication with an evolved universal terrestrial radio access network (E-UTRAN) and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), or a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 1205 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0092] The RF circuitry 1207 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 1207 may include switches, filters, amplifiers, etc., to facilitate the communication with the wireless network. The RF circuitry 1207 may include a receive signal path, which may include circuitry to down-convert RF signals received from the FEM circuitry 1209, and provide baseband signals to the

baseband circuitry 1205. The RF circuitry 1207 may also include a transmit signal path, which may include circuitry to up-convert baseband signals provided by the baseband circuitry 1205, and provide RF output signals to the FEM circuitry 1209 for transmission.

[0093] In some embodiments, the RF circuitry 1207 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 1207 may include a mixer circuitry 1213A, an amplifier circuitry 1213B, and a filter circuitry

1213C. The transmit signal path of the RF circuitry 1207 may include the filter circuitry 1213C and the mixer circuitry 1213A. The RF circuitry 1207 may further include a synthesizer circuitry 1213D configured to synthesize a frequency for use by the mixer circuitry 1213A of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 1213A of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 1209 based on the synthesized frequency provided by the synthesizer circuitry 1213D. The amplifier circuitry 1213B may be configured to amplify the down-converted signals. [0094] The filter circuitry 1213C may include a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 1205 for further processing. In some embodiments, the output baseband signals may include zero-frequency baseband signals, although this is not a requirement. In some embodiments, the mixer circuitry 1213A of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

[0095] In some embodiments, the mixer circuitry 1213A of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 1213D to generate RF output signals for the FEM circuitry 1209. The baseband signals may be provided by the baseband circuitry 1205 and may be filtered by the filter circuitry 1213C. The filter circuitry 1213C may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.

[0096] In some embodiments, the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may include two or more mixers, and may be arranged for quadrature downconversion and/or upconversion, respectively. In some embodiments, the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may be arranged for direct downconversion and/or direct upconversion, respectively. In some embodiments, the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may be configured for super-heterodyne operation.

[0097] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In such embodiments, the RF circuitry 1207 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and the baseband circuitry 1205 may include a digital baseband interface to communicate with the RF circuitry 1207. [0098] In some dual-mode embodiments, separate radio interference cancellation (IC) circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

[0099] In some embodiments, the synthesizer circuitry 1213D may include one or more of a fractional-N synthesizer and a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect, as other types of frequency synthesizers may be suitable. For example, the synthesizer circuitry 1213D may include a delta-sigma synthesizer, a frequency multiplier, a synthesizer comprising a phase-locked loop with a frequency divider, other synthesizers, and combinations thereof.

[0100] The synthesizer circuitry 1213D may be configured to synthesize an output frequency for use by the mixer circuitry 1213A of the RF circuitry 1207 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 1213D may be a fractional N/N+1 synthesizer.

[0101] In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 1205 or the application circuitry 1203 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the application circuitry 1203.

[0102] The synthesizer circuitry 1213D of the RF circuitry 1207 may include a divider, a delay-locked loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the divider may include a dual modulus divider (DMD), and the phase accumulator may include a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry-out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements; a phase detector; a charge pump; and a D-type flip-flop. In such embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL may provide negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0103] In some embodiments, the synthesizer circuitry 1213D may be configured to generate a carrier frequency as the output frequency. In some embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency, etc.) and used in conjunction with a quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be an LO frequency (fLO). In some embodiments, the RF circuitry 1207 may include an IQ/polar converter.

[0104] The FEM circuitry 1209 may include a receive signal path, which may include circuitry configured to operate on RF signals received from the one or more antennas 1214, amplify the received signals, and provide the amplified versions of the received signals to the RF circuitry 1207 for further processing. The FEM circuitry 1209 may also include a transmit signal path, which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 1207 for transmission by at least one of the one or more antennas 1214.

[0105] In some embodiments, the FEM circuitry 1209 may include a TX/RX switch configured to switch between a transmit mode and a receive mode operation. The FEM circuitry 1209 may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry 1209 may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 1207). The transmit signal path of the FEM circuitry 1209 may include a power amplifier (PA) configured to amplify input RF signals (e.g., provided by the RF circuitry 1207), and one or more filters configured to generate RF signals for subsequent transmission (e.g., by the one or more antennas 1214).

[0106] In some embodiments, the device may include additional elements such as, for example, memory/storage, a display, a camera, one of more sensors, an input/output (I/O) interface, other elements, and combinations thereof.

[0107] In some embodiments, the device may be configured to perform one or more processes, techniques, and/or methods as described herein, or portions thereof.

[0108] FIG. 13 is a block diagram illustrating components according to some embodiments. Specifically, FIG. 13 shows a diagrammatic representation of hardware resources 1300 including one or more processors (or processor cores)

1310, one or more memory/storage devices 1320, and one or more communication resources 1330, which are communicatively coupled via a bus 1340. [0109] The processors 1310 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, a processor 1312 and a processor 1314. The memory/storage devices 1320 may include main memory, disk storage, or any suitable combination thereof.

[0110] The communication resources 1330 may include interconnection and/or network interface components or other suitable devices to communicate with one or more peripheral devices 1304 and/or one or more databases 131 1 via a network 1308. For example, the communication resources 1330 may include wired

communication components (e.g., for coupling via a Universal Serial Bus (USB)), cellular communication components, Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components.

[0111] Instructions 1350 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least one of the processors 1310 to perform any one or more of the methodologies discussed herein. The instructions 1350 may reside, completely or partially, within at least one of the processors 1310 (e.g., within the processor's cache memory), the memory/storage devices 1320, or any suitable combination thereof. Furthermore, any portion of the instructions 1350 may be transferred to the hardware resources 1300 from any combination of the peripheral devices 1304 and/or the databases 131 1 . Accordingly, the memory of the processors 1310, the memory/storage devices 1320, the peripheral devices 1304, and the databases 131 1 are examples of computer- readable and machine-readable media.

Example Embodiments

[0112] Example 1 is an apparatus for performing polar encoding. The apparatus includes electronic memory to store a variety of data bits for use in a first stage of a polar encoder distinct from a second stage of the polar encoder. The apparatus includes one or more baseband processing units designed to generate at least a variety of internal bits in the first stage of the polar encoder by performing a variety of operations on the data bits, where the internal bits are internal to the polar encoder. The apparatus includes one or more baseband processing units designed to generate a variety of codeword bits in the second stage of the polar encoder by performing a variety of operations on the internal bits, where the codeword bits correspond to the second stage of a polar encoder, and the internal bits correspond to the first stage of the polar encoder. The apparatus includes one or more baseband processing units designed for a hybrid automatic repeat request (HARQ) transmission, provide a subset of the data bits, the codeword bits, and the internal bits to a channel of a physical layer.

[0113] Example 2 is the apparatus of Example 1 , where the apparatus is a user equipment (UE) and where the channel is at least one of an uplink channel and a sidelink channel.

[0114] Example 3 is the apparatus of Example 1 , where the apparatus is an evolved user node (eNodeB) and where the channel is at least one of a downlink channel.

[0115] Example 4 is the apparatus of Example 1 , where the transmission is at least one of a Chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.

[0116] Example 5 is the apparatus of Example 1 , where the data bits for use in the first stage of the polar encoder include bits set to a predetermined value.

[0117] Example 6 is the apparatus of Example 1 , where a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.

[0118] Example 7 is the apparatus of Example 1 , where the one or more processing units are further designed to generate a subsequent HARQ transmission including a subsequent subset of the data bits, the internal bits, and the codeword bits that are different than the subset of the data bits, the internal bits, and the codeword bits.

[0119] Example 8 is the apparatus of Example 1 , where the HARQ transmission includes a circular buffer of the subset of the data bits, the internal bits, and the codeword bits.

[0120] Example 9 is the apparatus of Example 1 , where the subset of the data bits, the internal bits, and the codeword bits includes one of the codeword bits and the internal bits, the codeword bits and a portion of the internal bits, the internal bits and a portion of the codeword bits; and the internal bits. [0121] Example 10 is a computer-readable storage medium. The computer- readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to initialize a first variety of log- likelihood ratios (LLRs) for a variety of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission. The computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to initialize a second variety of LLRs for a variety of dangling edges, associated with the variety of bits, of a polar decoder. The computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to perform a variety of operations on the first variety of LLRs and the second variety of LLRs to generate a third variety of LLRs. . The computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to determine an estimate of an information block including a first variety of bits and a second variety of bits including data bits based on the third variety of LLRs.

[0122] Example 1 1 is the computer-readable storage medium of Example 10, where a user equipment (UE) or an evolved node B (eNodeB) includes the computer-readable storage medium.

[0123] Example 12 is the computer-readable storage medium of Example 10, where the variety of operations include addition operations.

[0124] Example 13 is the computer-readable storage medium of Example 10, where each of the variety of operations include a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second

LLR, a multiplication operation to determine a sign by multiplying a sign of the first

LLR and a sign of the second LLR, and providing the minimum LLR with the sign.

[0125] Example 14 is the computer-readable storage medium of Example 10, where the instructions designed to initialize the first variety of LLRs and initialize the second variety of LLRs further include instructions to initialize LLRs from the first variety of LLRs and the second variety of LLRs associated with frozen bits from the first variety of bits and the second variety of bits to a predefined value. The computer-readable storage medium of Example 10, where the instructions designed to initialize the first variety of LLRs and initialize the second variety of LLRs further include instructions to initialize each of the first variety of LLRs and the second variety of LLRs associated with non-frozen bits from the variety of bits to a sum of received LLRs of a corresponding one of the non-frozen bits, and initialize LLRs from the first variety of LLRs and the second variety of LLRs to zeros for bits that were not received.

[0126] Example 15 is the computer-readable storage medium of Example 10, where the estimate of information block includes which codeword was transmitted through the channel.

[0127] Example 16 is the computer-readable storage medium of Example 10, where zero or more of the variety of bits are associated with internal bits of a polar encode.

[0128] Example 17 is an apparatus for performing polar encoding. The apparatus includes electronic memory to store a variety of information bits, to be encoded by a polar encoder module, with a length K. The apparatus includes one or more processing units designed to select a length S of a number of shortened bits and a length P of a number of punctured bits based on a hybrid automatic repeat request (HARQ) scheme and encode the variety of information bits via the polar encoder module to generate a base codeword, with a length of N, minus the number of shortened bits. The apparatus includes one or more processing units designed to interleave, via a interleaver module, a result of the polar encoder module to generate a codeword which includes the base codeword minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E. The apparatus includes one or more processing units designed to provide the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation, and provide a result of the division to a channel of a physical layer to transmit a polar code to a receiving device.

[0129] Example 18 is the apparatus of Example 17, where the apparatus is one of a user equipment (UE) or an evolved node B (eNodeB).

[0130] Example 19 is the apparatus of Example 17, where the HARQ scheme includes a chase combining transmission.

[0131] Example 20 is the apparatus of Example 17, where the HARQ scheme includes a HARQ incremental redundancy (HARQ-IR) transmission. [0132] Example 21 is the apparatus of Example 17, where the one or more processing units are further designed to set N to 2^A(ceil(log2(N_CB)), where N_CB is a length of the codeword, and E to zero.

[0133] Example 22 is the apparatus of Example 17, where the one or more processing units are further designed to set S to N-N_CB, and P to zero.

[0134] Example 23 is the apparatus of Example 17, where the one or more processing units are further designed to set S to zero, and P to N-N_CB- [0135] Example 24 is the apparatus of Example 17, where the one or more processing units are further designed to set N to 2^A(floor(log2(N_CB)), where N_CB is a length of the codeword, and E to N_CB-N.

[0136] Example 25 is the apparatus of Example 17, where the one or more processing units are further designed to set S to zero, and P to zero.

[0137] Example 26 is a method including generating at least a variety of internal bits in a first stage of the polar encoder by performing a variety of operations on a variety of data bits for use in the first stage of a polar encoder distinct from a second stage of the polar encoder, where the internal bits are internal to the polar encoder. The method also includes generating a variety of codeword bits in the second stage of the polar encoder by performing a variety of operations on the internal bits, where the codeword bits correspond to the second stage of a polar encoder, and the internal bits correspond to the first stage of the polar encoder. The method also includes for a hybrid automatic repeat request (HARQ) transmission, providing a subset of the data bits, the codeword bits, and the internal bits to a channel of a physical layer.

[0138] Example 27 is the method of Example 26, where providing includes providing, by an apparatus of a user equipment (UE), the subset of the data bits, the codeword bits, and the internal bits to the channel of a physical layer and where the channel is at least one of an uplink channel and a sidelink channel.

[0139] Example 28 is the method of Example 26, where providing includes providing, by an apparatus of an evolved user node (eNodeB), the subset of the data bits, the codeword bits, and the internal bits to the channel of a physical layer and where the channel is at least one of a downlink channel.

[0140] Example 29 is the method of Example 26, where the HARQ transmission is at least one of a Chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission. [0141] Example 30 is the method of Example 26, where the data bits for use in the first stage of the polar encoder include bits set to a predetermined value.

[0142] Example 31 is the method of Example 26, where a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.

[0143] Example 32 is the method of Example 26, further including generating a subsequent HARQ transmission including a subsequent subset of the data bits, the internal bits, and the codeword bits that are different than the subset of the data bits, the internal bits, and the codeword bits.

[0144] Example 33 is the method of Example 26, where the HARQ transmission includes a circular buffer of the subset of the data bits, the internal bits, and the codeword bits.

[0145] Example 34 is the method of Example 26, where the subset of the data bits, the internal bits, and the codeword bits includes one of the codeword bits and the internal bits, the codeword bits and a portion of the internal bits, the internal bits and a portion of the codeword bits, and the internal bits.

[0146] Example 35 is a method which includes initializing a first variety of log- likelihood ratios (LLRs) for a variety of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission. The method also includes initializing a second variety of LLRs for a variety of dangling edges, associated with the variety of bits, of a polar decoder. The methods also includes performing a variety of operations on the first variety of LLRs and the second variety of LLRs to generate a third variety of LLRs. The methods also includes determining an estimate of an information block including a first variety of bits and a second variety of bits including data bits based on the third variety of LLRs.

[0147] Example 36 is the method of Example 35, where the initializing of the variety of LLRs, the initializing the second variety of LLRs, the performing the variety of operations, and the determining an estimate of the information block, are performed by a user equipment (UE) or an evolved node B (eNodeB).

[0148] Example 37 is the method of Example 35, where the variety of operations include addition operations.

[0149] Example 38 is the method of Example 35, where each of the variety of operations includes a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second LLR. The variety of operations includes a multiplication operation to determine a sign by multiplying a sign of the first LLR and a sign of the second LLR, and providing the minimum LLR with the sign.

[0150] Example 39 is the method of Example 35, where initializing the first variety of LLRs and initializing the second variety of LLRs further includes initializing LLRs from the first variety of LLRs and the second variety of LLRs associated with frozen bits from the first variety of bits and the second variety of bits to a predefined value. Initializing the first variety of LLRs and initializing the second variety of LLRs further includes initializing each of the first variety of LLRs and the second variety of LLRs associated with non-frozen bits from the variety of bits to a sum of received LLRs of a corresponding one of the non-frozen bits, and initializing LLRs from the first variety of LLRs and the second variety of LLRs to zeros for bits that were not received.

[0151] Example 40 is the method of Example 35, where the estimate of information block includes which codeword was transmitted through the channel.

[0152] Example 41 is the method of Example 35, where zero or more of the variety of bits are associated with internal bits of a polar encode.

[0153] Example 42 is a method. The method includes electronic memory to store a variety of information bits, to be encoded by a polar encoder module, with a length K. The method also includes one or more processing units designed to selecting a length S of a number of shortened bits and a length P of a number of punctured bits based on a hybrid automatic repeat request (HARQ) scheme. The method also includes one or more processing units designed to encoding a variety of information bits with a length K via the polar encoder module to generate a base codeword, with a length of N, minus the number of shortened bits. The method also includes one or more processing units designed to interleaving, via a interleaver module, a result of the polar encoder module to generate a codeword which includes the base codeword minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E. The method also includes one or more processing units designed to providing the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation, and providing a result of the division to a channel of a physical layer to transmit a polar code to a receiving device. [0154] Example 43 is the method of Example 42, where the HARQ scheme includes a chase combining transmission.

[0155] Example 44 is the method of Example 42, where the HARQ scheme includes a HARQ incremental redundancy (HARQ-IR) transmission.

[0156] Example 45 is the method of Example 42, further including setting N to

2^A(ceil(log2(NcB)), where N_CB is a length of the codeword, and E to zero.

[0157] Example 46 is the method of Example 42, further including setting S to N-

NCB, and P to zero.

[0158] Example 47 is the method of Example 42, further including setting S to zero, and P to N-N_CB-

[0159] Example 48 is the method of Example 42, further including setting N to 2^A(floor(log2(N_CB)), where N_CB is a length of the codeword, and E to N_CB-N .

[0160] Example 49 is the method of Example 42, further including setting S to zero, and P to zero.

[0161] Example 50 is at least one computer-readable storage medium having stored thereon computer-readable instructions, when executed, to implement a method as exemplified in any of Examples 26-44.

[0162] Example 51 is an apparatus including means to perform a method as exemplified in any of Examples 26-44.

[0163] Example 52 is a means for performing a method as exemplified in any of Examples 26-44.

[0164] Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, a non-transitory computer-readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of program code execution on programmable computers, the computing device may include a processor, a storage medium readable by the processor (including volatile and nonvolatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and non-volatile memory and/or storage elements may be a RAM, an EPROM, a flash drive, an optical drive, a magnetic hard drive, or another medium for storing electronic data. The eNodeB (or other base station) and UE (or other mobile station) may also include a transceiver component, a counter component, a processing component, and/or a clock component or timer component. One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like. Such programs may be implemented in a high-level procedural or an object-oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or an interpreted language, and combined with hardware implementations.

[0165] It should be understood that many of the functional units described in this specification may be implemented as one or more components, which is a term used to more particularly emphasize their implementation independence. For example, a component may be implemented as a hardware circuit comprising custom very large scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

[0166] Components may also be implemented in software for execution by various types of processors. An identified component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, a procedure, or a function.

Nevertheless, the executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations that, when joined logically together, comprise the component and achieve the stated purpose for the component.

[0167] Indeed, a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code

segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within components, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. The components may be passive or active, including agents operable to perform desired functions. [0168] Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, appearances of the phrase "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0169] As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on its presentation in a common group without indications to the contrary. In addition, various embodiments and examples may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of embodiments.

[0170] Although the foregoing has been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be made without departing from the principles thereof. It should be noted that there are many alternative ways of implementing both the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1 . An apparatus for performing polar encoding, comprising:

electronic memory to store a plurality of data bits for use in a first stage of a polar encoder distinct from a second stage of the polar encoder; and

one or more baseband processing units configured to:

generate at least a plurality of internal bits in the first stage of the polar encoder by performing a plurality of operations on the data bits, wherein the internal bits are internal to the polar encoder;

generate a plurality of codeword bits in the second stage of the polar encoder by performing a plurality of operations on the internal bits, wherein the codeword bits correspond to the second stage of a polar encoder, and the internal bits correspond to the first stage of the polar encoder; and

for a hybrid automatic repeat request (HARQ) transmission, provide a subset of the data bits, the codeword bits, and the internal bits to a channel of a physical layer.

2. The apparatus of claim 1 , wherein the apparatus is a user equipment (UE) and wherein the channel is at least one of an uplink channel and a sidelink channel.

3. The apparatus of claim 1 , wherein the apparatus is an evolved user node (eNodeB) and wherein the channel is at least one of a downlink channel.

4. The apparatus of claim 1 , wherein the HARQ transmission is at least one of a Chase combining HARQ transmission and a HARQ incremental redundancy (HARQ- IR) transmission.

5. The apparatus as in claims 1 , 2, 3, or 4, wherein the data bits for use in the first stage of the polar encoder include bits set to a predetermined value.

6. The apparatus as in claims 1 , 2, 3, or 4, wherein a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.

7. The apparatus as in claims 1 , 2, 3, or 4, wherein the one or more processing units are further configured to generate a subsequent HARQ transmission

comprising a subsequent subset of the data bits, the internal bits, and the codeword bits that are different than the subset of the data bits, the internal bits, and the codeword bits.

8. The apparatus as in claims 1 , 2, 3, or 4, wherein the HARQ transmission includes a circular buffer of the subset of the data bits, the internal bits, and the codeword bits.

9. The apparatus as in claims 1 , 2, 3, or 4, wherein the subset of the data bits, the internal bits, and the codeword bits includes one of:

the codeword bits and the internal bits;

the codeword bits and a portion of the internal bits;

the internal bits and a portion of the codeword bits; and

the internal bits.

10. A computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to:

initialize a first plurality of log-likelihood ratios (LLRs) for a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission;

initialize a second plurality of LLRs for a plurality of dangling edges, associated with the plurality of bits, of a polar decoder;

perform a plurality of operations on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs; and

determine an estimate of an information block comprising a first plurality of bits and a second plurality of bits comprising data bits based on the third plurality of LLRs.

1 1 . The computer-readable storage medium of claim 10, wherein a user equipment (UE) or an evolved node B (eNodeB) comprises the computer-readable storage medium.

12. The computer-readable storage medium of claim 10, wherein the plurality of operations comprise addition operations.

13. The computer-readable storage medium of claim 10, wherein each of the plurality of operations comprises:

a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second LLR;

a multiplication operation to determine a sign by multiplying a sign of the first LLR and a sign of the second LLR; and

providing the minimum LLR with the sign.

14. The computer-readable storage medium of claim 10, wherein the instructions configured to initialize the first plurality of LLRs and initialize the second plurality of LLRs further comprise instructions to:

initialize LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to a predefined value;

initialize each of the first plurality of LLRs and the second plurality of LLRs associated with non-frozen bits from the plurality of bits to a sum of received LLRs of a corresponding one of the non-frozen bits; and

initialize LLRs from the first plurality of LLRs and the second plurality of LLRs to zeros for bits that were not received.

15. The computer-readable storage medium as in claims 10, 1 1 , 12, 13, or 14, wherein the estimate of information block comprises which codeword was

transmitted through the channel.

16. The computer-readable storage medium as in claims 10, 1 1 , 12, 13, or 14, wherein zero or more of the plurality of bits are associated with internal bits of a polar encode.

17. An apparatus for performing polar encoding, comprising:

electronic memory to store a plurality of information bits, to be encoded by a polar encoder module, with a length K; and

one or more processing units configured to:

select a length S of a number of shortened bits and a length P of a number of punctured bits based on a hybrid automatic repeat request (HARQ) scheme;

encode the plurality of information bits via the polar encoder module to generate a base codeword, with a length of N, minus the number of shortened bits;

interleave, via a interleaver module, a result of the polar encoder module to generate a codeword which includes the base codeword minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E;

provide the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation; and provide a result of the division to a channel of a physical layer to transmit a polar code to a receiving device.

18. The apparatus of claim 17, wherein the apparatus is one of a user equipment (UE) or an evolved node B (eNodeB).

19. The apparatus of claim 17, wherein the HARQ scheme includes a chase combining transmission.

20. The apparatus of claim 17, wherein the HARQ scheme includes a HARQ incremental redundancy (HARQ-IR) transmission.

21 . The apparatus as in claims 17, 18, 19, or 20, wherein the one or more processing units are further configured to set:

N to 2^A(ceil(log2(N_CB)), wherein N_CB is a length of the codeword; and

E to zero.

22. The apparatus as in claims 17, 18, 19, or 20, wherein the one or more processing units are further configured to set:

P to zero.

23. The apparatus as in claims 17, 18, 19, or 20, wherein the one or more processing units are further configured to set:

S to zero; and

24. The apparatus as in claims 17, 18, 19, or 20, wherein the one or more processing units are further configured to set:

N to 2^A(floor(log2(N_CB)), wherein N_CB is a length of the codeword; and

E to Nc_B-N.

25. The apparatus as in claims 17, 18, 19, or 20, wherein the one or more processing units are further configured to set:

S to zero; and

P to zero.