CN114679242A - Polarization code for HARQ transmission - Google Patents

Abstract

Embodiments of the present disclosure relate to polarization codes for HARQ transmissions. The present disclosure provides performing polar encoding. Performing polar coding may include selecting a length of a shortened number of bits S and a length of a punctured number of bits P based on the HARQ scheme, encoding a plurality of information bits to generate a base code, interleaving a result of the shortened polar encoder module to generate a codeword including the base code minus the shortened bits, minus the punctured number of bits, plus a number of spread bits of length E, and providing the codeword to a modulation module to generate a result of division of the codeword by a multiplication of the number of spatial streams and the number of bits per modulation, and providing the result of the division to a channel to transmit the polar code to a receiving device.

Description

Polarization code for HARQ transmission

RELATED APPLICATIONS

The application is a divisional application of an invention patent application with the international application date of 2016, 9 and 22 months, the international application number of PCT/US2016/053026, the stage of entering China at 9 and 10 months in 2018, the Chinese national application number of 201680083369.0 and the invention name of 'polarization code for HARQ transmission'.

This application is a non-provisional application for U.S. provisional patent application No.62/334,772 filed on day 11/5/2016 and U.S. provisional patent application No.62/320,094 filed on day 8/4/2016, each of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to polar code (polar code) design, including support for hybrid automatic repeat request (HARQ) transmissions. In particular, the present disclosure relates to polar encoding and decoding for HARQ transmissions.

Drawings

FIG. 1 is a system diagram illustrating a polar code chain according to one embodiment.

Fig. 2 is a block diagram illustrating rate matching and interleaving according to one embodiment.

Fig. 3 is a diagram illustrating performance according to different parameter settings of a HARQ scheme according to an embodiment.

FIG. 4 is a diagram illustrating a polarization encoding circuit according to one embodiment.

Fig. 5 is a block diagram illustrating a receive processing chain according to one embodiment.

FIG. 6 is a diagram illustrating a polarization decoding circuit according to one embodiment.

FIG. 7 is a diagram illustrating nodes in a polarization decoding circuit according to one embodiment.

Fig. 8 is a block diagram illustrating electronic device circuitry, which may be eNodeB circuitry, User Equipment (UE) circuitry, network node circuitry, or some other type of circuitry, in accordance with one embodiment.

FIG. 9 is a block diagram illustrating a method for performing polar encoding according to one embodiment.

FIG. 10 is a block diagram illustrating a method for performing polar encoding according to one embodiment.

FIG. 11 is a block diagram illustrating a method for a polar decoder, according to one embodiment.

FIG. 12 is a block diagram that illustrates components of the device, according to one embodiment.

FIG. 13 is a block diagram that illustrates components, according to some embodiments.

Description of The Preferred Embodiment

Wireless mobile communication technologies use various standards and protocols to generate and/or transmit data between base stations and wireless communication devices. Wireless communication system standards and protocols may include, for example, third generation partnership project (3GPP) Long Term Evolution (LTE); the Institute of Electrical and Electronics Engineers (IEEE)802.16 standard, commonly referred to in the industry as Worldwide Interoperability for Microwave Access (WiMAX); and the IEEE 802.11 standard, commonly referred to in the industry as Wireless Local Area Network (WLAN) or Wi-Fi. In a 3GPP Radio Access Network (RAN) in an LTE system, a base station may include an evolved universal terrestrial radio access network (E-UTRAN) node B (also commonly denoted as evolved node B, enhanced node B, eNodeB, or eNB) and/or a Radio Network Controller (RNC) in the E-UTRAN, which communicates with wireless communication devices known as User Equipment (UE). In an LTE network, the E-UTRAN may include multiple enodebs and may communicate with multiple UEs. LTE networks include Radio Access Technologies (RATs) and core radio network architectures, which may provide high data rates, low latency, packet optimization, and improved system capacity and coverage.

Polar codes are a class of error correction codes that enable the capability of memoryless communication channels. Some examples described herein refer to binary polar codes, but non-binary polar codes may also be employed using examples described herein.

The encoder can calculate

Wherein the content of the first and second substances,

is a vector of binary bits, G_NIs a 2x 2 matrix

Of Kronecker power n times, and

is a codeword. The codeword may comprise a vector of binary bits. N denotes the length of the vector. For example, a vector of binary bits and a codeword may each include N binary bits. The codeword may be transmitted over a communication channel, such as a Physical Uplink Shared Channel (PUSCH) and/or a Physical Downlink Shared Channel (PDSCH), among other examples of communication channels. Can be combined with

Is provided to an encoder for encoding.

Can be determined by inputting a desired number of encoders into U_iSet to data bits (e.g., information bits) and freeze the remaining bit values to predetermined values (e.g., zeros) and encode the result to form an output codeword to achieve various coding rates. The coding rate may be defined as the ratio of the number of data bits input to the encoder to the number of codeword bits output by the encoder. For example, to obtain a half code rate, one half of U may be used_iThe bits are set to data bits (e.g., information bits), and the remaining half of the U may be set_iThe bits are frozen to their predetermined values (e.g., zero). The choice of which bit indices to freeze, what values to freeze, and which bits to use for data can be fixed prior to transmission and can be known at both the sender and receiver.

If a receiver (e.g., User Equipment (UE)) detects an error in the reception of a data packet, e.g., by performing a Cyclic Redundancy Check (CRC), the UE may request additional transmission of the data packet. A transmitter (e.g., an evolved node b (enodeb)) may then transmit more coding bits and/or parity bits associated with the data packet to assist the receiver in recovering the original data packet. This may be in the form of repetitions of the same codeword (or part thereof) transmitted via Chase combining of HARQ transmissions and/or in the form of new information about the original data, typically in the form of additional parity bits, of incremental redundancy IR transmissions (HARQ-IR) via HARQ transmissions, or a combination thereof. Several retransmissions may be made (e.g., until the receiver UE can correctly decode the data packet).

In HARQ operation, if a first transmission of a data packet fails, the transmitter may repeat the same packet or transport block in a second transmission. The parity bits selected for the second transmission may or may not be the same as the parity bits sent in the first transmission based on the encoding (e.g., redundancy version, assigned modulation and coding scheme, etc.).

May be based on each code bit X_iThe information and the frozen bits can be decoded by the precondition of the independent realization of the transmission of the channel W. In some examples, such as frequency selective fading channel, higher order modulation, and/or puncturing (puncturing) for HARQ-IR purposes, each code bit X_iDifferent types of channels may be passed. The quality of these different types of channels may vary widely.

In some examples, a polar coding chain may be implemented for HARQ transmissions that addresses issues with coding for high order modulation, robust performance under varying channel conditions, support for chase combining HARQ transmissions and HARQ-IR transmissions, and/or rate matching that provides flexible polar codeword lengths.

Referring now to the drawings, in which like reference numbers represent like elements. For clarity, the first digit of a reference number identifies the figure number in which the corresponding element is first used. In the following description, numerous specific details are provided for a thorough understanding of the embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments described herein can be practiced without one or more of the specific details, or with other methods, components, or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1 is a system diagram illustrating a polar code chain according to one embodiment. Fig. 1 includes a polar code chain 100, which includes: a shortened polar encoder module 110, a rate matching and channel interleaver (RM & CI) module 112, a modulation module 114, a channel 116, a demodulation module 118, a de-rate matching and channel interleaver (D-MR & CI) module 120, and a shortened polar decoder module 122.

The shortened polarization encoder module 110, the RM & CI module 112, and the modulation module 114 may include coding schemes that may be performed by the UE and/or the eNodeB. The demodulation module 118, D-MR & CI module 120, and shortened polarization decoder module 122 may include decoding schemes that may also be performed by the UE and/or eNodeB.

As used in FIG. 1 and as described in FIG. 1, N is 2ⁿThe output length of the base code. K102 is the number of information bits. S is the number of shortening bits. P is the number of punctured bits. E is the number of extension and/or repetition bits. N is a radical of_sIs the number of spatial streams. M is the number of bits per modulation. N is a radical of_BC104 (also referred to as N-S104, for example) shortens the base codeword length after the polar encoder, equal to N-S. N is a radical of_CB106 (e.g., also referred to as N-S-P + E106) is rate matching and channel interleaving (e.g., RM)&CI block 112) is equal to N-S-P + E.

The plurality of log-likelihood ratios (LLRs) associated with K102 is represented by K103. The plurality of LLRs associated with S is denoted by S. The plurality of LLRs associated with P is denoted by P. The plurality of LLRs associated with E is denoted by E. The LLR associated with M is denoted by M. The plurality of LLRs associated with N-S104 is represented by N-S105. The plurality of LLRs associated with N-S-P + E106 is represented by N-S-P + E107. And (N-S-P + E)/(N)_SM)108 by (n-s-p + e)/(n)_sM) 109.

As used herein, K102, N, S, P, E, N_SAnd M may refer to a number of bits and/or bits, k 103, n, s, p, e, n_sAnd m may refer to a number of received bits, LLRs, and/or LLRs. For example, K102May be a bit vector comprising 512 bits. K102 may refer to a bit and/or a number of bits in a bit vector (e.g., a bit vector length), such as 512 bits. N-S104 may refer to both the bit vector from which the bit vector S is removed from the bit vector N and the number of bits (e.g., bit vector length) in the bit vector from which the bit vector S is removed from the bit vector N.

For encoding, K102 may be provided to shortened polar encoder 110 to produce N-S104. Providing N-S104 to RM&A CI module 112 to generate N-S-P + E106. The N-S-P + E106 is provided to the modulation module 114 to produce (N-S-P + E)/(N)_SM) 108. Will (N-S-P + E)/(N)_SM)108 are provided to channel 116 for transmission.

Channel 116 may convert (n-s-p + e)/(n)_sM)109 is provided to the demodulation module 118 to generate n-s-p + e 107. n-D-p + r 107 may be provided to the D-RM&The CI module 120 to generate n-d 104. N-d104 is provided to shortened polarization decoder module 122 to generate k 102. Shortened polar encoder Module 110, RM&The CI module 112, the modulation module 114, and/or the channel 116 may be provided as part of a transmission (e.g., eNodeB). Channel 116, demodulation module 118, D-RM&The CI module 120 and/or the shortened polarization decoder module 122 may be provided as part of a receiver (e.g., a UE).

The shortened polar encoder module 110 may have access to a length N-2 for one or more signal-to-noise ratio (SNR) levels and a base code output lengthⁿOptimized polar code structure, where n is a positive integer. That is, given SNR and code length, the shortened polar encoder module 110 may have a predetermined rule for selecting which bits to use as data and which bits to freeze to support several coding rates between 0 and 1.

Base codeword length N other than power of 2_BCThe configuration of (e.g., N-S104) is obtained by shortening the process with minimal loss of performance. The shortened polar encoder 110 may select the shortened length S and use the shortened polar code length N_BCN-S104 as the base codeword length to be used in rate matching. The shortening length S may be selected in combination with puncturing and spreading parameters.

For example, the polarization code chains may be used in conjunction with any modulation scheme, e.g., QAM, multi-antenna mapping, resource mapping, OFDM, and/or single carrier modulation. The receiver performs the inverse operation of the transmitter. LLR values are calculated at the demodulator module 118. The LLR values for the extension bits are added together. The punctured bit LLRs are set to zero and then the entire LLR block is deinterleaved by the D-RM & CI module 120. The LLR blocks N-S104 are then decoded via the shortened polar decoder module 122. Any polar decoding scheme may be utilized in shortened polar decoder module 122.

Fig. 2 is a block diagram illustrating rate matching and interleaving according to one embodiment. Fig. 2 includes an RM & CI module 212 that includes an interleaving module 230 and a rate matching module 232. N-S204-1 may be provided to interleaving module 230 to generate N-S204-2. N-S204-2 may be provided to a rate matching module 232 to generate N-S-P + E206.

Following the code shortening is an interleaving module 230 in the RM & CI module 212. The RM & CI module 212 may configure the codeword such that each bit in the codeword statistically suffers from the same amount of noise. That is, the RM & CI module 212 may configure the codeword such that each bit in the codeword is protected equally. In some examples, the RM & CI module 212 may be similar to a bit interleaver or sub-block interleaver in Bit Interleaved Coded Modulation (BICM) in LTE rate matching.

The proposed embodiment avoids constructing a different polarization code for each possible channel variation pattern. For example, in a frequency selective fading channel in an Orthogonal Frequency Division Multiplexing (OFDM)/Orthogonal Frequency Division Multiple Access (OFDMA) system, channel gains at different subcarriers may be different. For most high order modulation methods, such as 16 quadrature amplitude modulation (16QAM) or higher, different bits have different bit channel qualities. Code puncturing may also result in a time-varying channel where the punctured code bits have zero reliability at the receiver.

The interleaving module 230 may be optimized for shortening, puncturing, spreading, and/or fading patterns. Since the shortening, puncturing and/or spreading pattern may be optimized based on the fading or time varying pattern of the channel, the number of optimizations may be very large and/or the optimizations may be difficult to handle. As such, a single interleaving module 230 is used in the embodiments described herein as part of the RM & CI module 212.

In some examples, interleaving module 230 may be a random interleaver. Existing interleaving rules (e.g., sub-block interleaver and/or turbo code inner interleaver) may be used in LTE/LTE-a systems.

Rate matching begins with selecting a shortened length of the base code output length (parent polar code). The rate matching module 232 performs the rate matching process by puncturing and/or spreading the shortened and interleaved codeword N-S204-2. The shortening, puncturing, and/or extension lengths are jointly selected to match the specified code rate and HARQ requirements.

Puncturing bits refers to deleting bits from the bit vector. Extending a code refers to resending certain code bits. N, S, P and/or E is a positive integer. If P is>0, the last P bits of the shortened and interleaved base codeword may be punctured. The last bit may refer to the bit associated with the largest index of a bit vector (e.g., codeword). The last P bits refer to the P bits associated with the largest index of the codeword. If E is>0, then the first E bits may be extended (e.g., repeated). The first bit of the codeword is the bit associated with the first index of the codeword bit vector. The first E bits refer to the first E bits from the codeword bit vector. If (c)₀,c₁,…,c_N-S-1) The bit vector represents a shortened and interleaved base codeword (e.g., N-S204-2), the output of the rate matching module 232 may be (c)₀,c₁,…,c_N-S-P-1,c₀,c₁,…,c_E-1) A bit vector (e.g., N-S-P + E206). The N-S-P + E206 may then be provided via a circular buffer for HARQ-IR transmission.

Parameters N, S, P and/or E may be selected. For example, the number of coded bits before modulation for initial transmission may be N_CBN-S-P + E768 and the number of information bits may be K12. HARQ may indicate that the number of IR bits is also N _CB768. The code rate may be defined as R ═ K/N_CB. There are many choices of S, P and/or E that satisfy N_CBAnd K. Provide and satisfy N_CBAnd many examples of K.

In the first example of the present invention,

S＝N-N_CBp-0 and/or E-0. In a second example of the above-described method,

S＝0，P＝N-N_CBand/or E ═ 0. That is, in some examples, E-0 and/or at least two of S, P and E may be equal to zero. In other examples, for HARQ chase combining,

s-0, P-0 and/or E-N_CB-N. In some examples of the method of the present invention,

representing a rounding-up (ceiling) function.

Only the first example using shortening is available for initial transmission, since shortening results in minimal loss of error performance. In a first example, no bits are punctured or extended. The subsequent transmission of the first example comprises a simple repetition of the first transmission. For example, HARQ transmission may be performed using chase combining. As such, the first example may be selected for chase combining HARQ transmissions.

The second example may be selected for HARQ-IR transmission. For the initial transmission, the second example may perform worse than the first example, as shown in fig. 3. However, for subsequent HARQ transmissions, the second example may perform better than the first example, as shown in fig. 3. As such, S, P and/or E may be selected according to the HARQ scheme used to transmit the codeword. Some of these values may be predetermined for a given transport block size and HARQ release, or may be explicitly signaled in a control channel such as the Physical Downlink Control Channel (PDCCH).

Fig. 3 is a diagram illustrating performance according to different parameter settings of a HARQ scheme according to an embodiment. Fig. 3 includes a graph 336 that includes a block error rate (BLER) axis 338 and an SNR 340.

Graph 336 shows that the first example initial transmission 342 described with respect to fig. 2 performs better than the second example initial transmission 344. Performance may be judged based on BLER. As such, the initial transmission 342 may have a lower BLER than the initial transmission 344. Graph 336 also shows that the second transmission 346 of the second example performs better than the second transmission 348 of the first example.

FIG. 4 is a diagram illustrating a polarization encoding circuit 410 according to one embodiment. The polarization encoding circuit 410 may correspond to the shortened polarization encoder 110 of fig. 1. Polarization encoding circuit 410 shows an a-bit vector 450, which corresponds to K102 in fig. 1. Polarization encoding circuit 410 also shows a D-bit vector 456, which corresponds to N-S104 in FIG. 1. Polarization encoding circuit 410 also shows a B-bit vector 452 and a C-bit vector 454. The a-bit vector 450 may be an input bit vector and the D-bit vector 456 may be a result bit vector. The B-bit vector 452 and the C-bit vector 454 are internal bit vectors.

The A-bit vector 450 includes bits (a)₀，...，a₇). The B-bit vector 452 includes bits (B)₀，...，b₇). The C-bit vector 454 includes bits (C)₀，...，c₇). The D-bit vector 456 includes bits (D)₀，...，d₇)。

To generate a codeword of length 8, there may be a total of 32 bits as shown in polar encoding circuit 410. For a code of length N, a total of N x (log) is generated₂N +1) bits. The a-bit vector 450 may include the original data bits (e.g., K102 in fig. 1) and the frozen bits that are input to the polar encoding circuit 410. D-bit vector 456 includes codeword bits (D) output by polar encoding circuit 410₀，...，d₇). B bit vector 452 (e.g., (B)₀，...，b₇) And a C bit vector 454 (e.g., (C)₀，...，c₇) Includes inner bits that are calculated during the encoding process but are not normally transmitted or considered part of the codeword. There is some equality between the bits. For example, a₇＝b₇＝c₇＝d₇And b is₂＝c₂. In the proposed method, the sender (e.g. eNodeB) can retransmit at each timeTo generate and/or transmit a 32-bit subset. The transmitter may select different subsets based on different system requirements and/or capabilities.

The stages corresponding to the generation of the B-bit vector 452 and/or the C-bit vector 454 are referred to as intermediate stages or stages associated with the inner bits. The level corresponding to the D bit vector 456 is referred to as the level associated with the polarization encoded legacy codeword.

The transmitter may generate, provide, and/or transmit a subset of the D-bit vectors 456 in each transmission and retransmission to generate, provide, and/or transmit chase combining HARQ transmissions. Retransmissions may include internal bits (e.g., a subset of the B-bit vector 452 and/or the C-bit vector 454) that do not necessarily occur in typical polarization codewords. As such, generating and/or transmitting the internal bits may include generating and/or transmitting a new set of parity bits.

Many examples may support HARQ transmissions by utilizing bits that are typically internal to the polar encoding circuit 410 and that are not typically in the original codeword. For retransmission, the selected subset of bits may include a mixture of typical codeword bits and inner bits. This corresponds to a mix of catch-up/IR schemes, for example. An example of this is sending in retransmission (b)₀，...，b₇)。

For a general transmission mode including puncturing and spreading for rate matching, unique bits may be placed in the circular buffer. For example, the buffer may be expanded to d₀，...，d₇，c₀，...，c₆，b₀，b_l，b₄，b₅，a₀，a₂，a₄，a₆(again) d₀，...，d₇C 0. In some examples, the bits may be placed in the circular buffer in any other order. In each transmission, the transmitter may send the next bit in the buffer. These next bits may include multiple bits in the buffer as needed. The buffer may wrap around to the beginning when the last bit in the buffer is reached. The encoding may be systematic or part systematic. That is, the information block bits or some of the information block bits may be present in the buffer.

The polarization encoding circuit 410 may include a plurality of nodes in which a plurality of operations are performed. For example, the polarization encoding circuit 410 may include a check node 460 and a variable node 462.

The check node 460 is shown in figure 4 with a circle having a plus sign therein. The check node 460 may perform operations such as exclusive-or (XOR) operations. Each check node 460 may receive two bits as inputs and may generate an output by applying an operation to the two bits. E.g. AND bit a₀The consistent check node may receive a₀Bit sum a₁The bits are used as inputs. The check node may generate b₀And (4) nodes. And a₂The check node of bit identity can receive a₂Bit sum a₃Bit to generate b₂A bit. In other examples of the inspection node 460, and a₀Bit sum b₀The check node of bit identity can receive b₀Bit sum b₂Bit to generate c₀A bit. The bit generated by the check node 460 is a unique bit.

Variable node 462 is shown as a point in polarization encoding circuit 410. Variable node 462 may perform a copy operation. For example, with a₁Bit-consistent variable nodes may replicate a₁Bit to generate b₁A bit. Thus, a₁Bit is equal to b₁A bit. That is, a₁Bit sum b₁None of the bits are unique. The bits generated by variable node 462 are non-unique bits.

Fig. 5 is a block diagram illustrating a receive processing chain 500 according to one embodiment. The receive processing chain 500 includes a decoder module 522, a HARQ memory module 560, a soft combining module 562, and an LLR initializer for an internal bit module 564. The receive processing chain 500 also includes channel LLRs. The decoder module 522, HARQ memory module 560, soft combining module 562, and/or LLR initializer for inner bit module 564 may be similar to shortened polarization decoder 122 in fig. 1.

The receive processing chain 500 may be implemented as part of a receiver (e.g., a UE). The channel LLR module 568 may provide LLRs corresponding to the bits provided by the channel. The channel LLR module 568 may generate LLRs and/or may provide LLRs generated by the channel. The LLRs correspond to the current transmission of the packet.

The soft combining module 562 combines the LLRs for the current packet provided by the channel LLR module 568 with the LLRs for the previous transmission of the packet stored in the HARQ memory module 560. Since the transmissions (e.g., the combined previous and current transmissions) may include LLRs corresponding to codeword bits and inner bit bits, the soft combining module 562 outputs two types of LLRs. That is, the soft combining module 562 generates and/or initializes LLRs for the inner bits via the LLR initializer of the inner bit module 564. The LLRs for the inner bits are input (e.g., logically) separately to the decoder module 522 from the LLRs corresponding to the codeword LLRs so that the decoder module 522 can use the inner bit LLRs to initiate steps in decoding (e.g., list decoding, successive de-decoding, etc.).

Fig. 6 is a diagram illustrating a polarization decoding circuit 622 according to one embodiment. The polarization decoding circuit 622 may be part of the decoder 522 in fig. 5. The polarization decoding circuit 622 may include a D vector 656, a C vector 654, a B vector 652, and an a vector 650. The polarization decoding circuit 622 may also include a check node 650 and a variable node 662. The polarization decoding circuit 622 may also include a dangling edge (dangling edge) 670.

The polar decoder can be enhanced by combining information from transmissions (retransmissions) as shown by the hanging edge 670. The polar decoder may be any message passing algorithm; such as successive erasure decoders, list decoders, and/or belief propagation. The enhancement including the hanging edge 670 can be incorporated into any polarization decoder.

In the polar decoder circuit 622, each edge may hold a message in the form of an LLR (e.g., a message list, such as in the case of list decoding). The edges are shown in the polar decoder circuit 622 as edges connected to nodes at both ends, and hanging edges connected to nodes at only one end.

In fig. 6, vectors 650, 652, 654, and 656 represent bits and/or messages. The message may include LLRs and/or bits provided by the channel. The messages associated with vectors 650, 652, 654 and 656 correspond to a-bit vector 450, B-bit vector 452, C-bit vector 456 and D-bit vector 458, respectively, in fig. 4.

As described above, enhanced retransmission involves sending parity bits, typically internal to the original encoder, in addition to the polarized codeword. To use parity bits (e.g., inner unique bits or inner bits) in decoding, variable nodes 662 with additional hanging edges 670 that correspond exactly to inner bit positions (e.g., unique bits) are incorporated into the decoder circuit 622. The unique bits may include, for example, bit c in FIG. 4₀Which may correspond to c in fig. 6₀The messages and the corresponding hanging edges coupled to the decoder circuit 622 via variable nodes 662.

Utilizing the hanging edge 670 associated with the unique bit may include initializing LLRs and/or messages associated with the hanging edge 670. That is, a decoder including the decoder circuit 622 may be initialized with LLRs for received bits. For example, if in FIG. 4 a₀Is frozen to zero, then a comprising the associated LLR₀The message may be initialized to infinity or to a very large number in a scheme that associates positive LLRs with binary 0-bits and negative LLRs with binary 1-bits. In some examples, frozen bits on edges of the decoder circuit and/or the encoder circuit may produce frozen internal bits. As such, bits from the encoder may be selected for transmission, frozen bits may be excluded as long as their values are known and can be deterministically recreated at the decoder. If a bit in the graph is not frozen, its hanging edge LLR can be initialized to the sum of the LLRs received for that bit and to zero if it is never sent. For example, the LLRs for the hanging edge 670 corresponding to the inner bit on the third transmission may be initialized to the sum of the LLRs that were respectively received for the bit during the first, second, and third transmissions. The LLRs may be used to determine whether a bit vector received from a channel is the bit vector provided to the channel.

FIG. 7 is a diagram illustrating nodes in a polarization decoding circuit according to one embodiment. FIG. 7 includes nodes 772-1 and 772-2 shown in four different examples. FIG. 7 also includes messages 780-1 and 780-2 and message 784.

Message 780-1 may be provided from node 772-2 to node 772-1. Message 780-2 may also be provided from node 772-1 to node 772-2. In some examples, message 780-1 may be provided from node 772-2 to node 772-1 through node 772-3. Message 780-2 may be provided from node 772-1 to node 772-2 through node 772-3.

Adding variable nodes (e.g., node 773) and hanging edges corresponding to internal bits may allow for any existing messaging schedule in the enhanced decoder. The edges in fig. 7 represent the horizontal edges in fig. 6. Nodes 772-1 and 772-2 (e.g., nodes X and Y) may be any two neighboring nodes in fig. 6. The enhanced decoder may include the added variable node 772-3 between nodes 772-1 and 772-2 and have an associated message 784 (e.g., message l)_XY) Respectively, of the suspension edge. In the decoder, a message 780-2 (e.g., message m) is generated_XY) After each access to node 772-1, a newly introduced node 772-3 is accessed, which computes l_XY+m_XYAnd writes the result to node 772-2. The same operation can be done in the opposite direction. That is, message 780-1 (e.g., message m) is being generated_XY) After accessing node 772-2, a newly introduced node 772-3 is accessed, which calculates l_XY+m_XYAnd writes the result to node 772-1.

At the transmitter, a redundancy version indicator may be used to indicate which bits of the buffer are to be transmitted in a given transmission for a data packet. The redundancy version may be explicitly indicated in the control information associated with the information block (or transport block) or may be implicitly tied to a known parameter such as the subframe number or transport number. For example, the redundancy version indicator may be equal to 1 for the first transmission and/or equal to 2 for the second transmission, and so on. The transmission number may be used for a self-decodable transmission.

Fig. 8 is a block diagram illustrating electronic device circuitry, which may be eNodeB circuitry, User Equipment (UE) circuitry, network node circuitry, or some other type of circuitry, in accordance with one embodiment. Fig. 8 illustrates an electronic device 800, in accordance with various embodiments, the electronic device 800 can be an eNodeB, a UE, or some other type of electronic device; or may be incorporated into an eNodeB, a UE, or some other type of electronic device; or may otherwise be part of an eNodeB, a UE, or some other type of electronic device. In particular, electronic device 800 may be logic and/or circuitry that may be implemented, at least in part, in one or more of hardware, software, and/or firmware. In an embodiment, the electronic device logic may include radio transmit/transmitter logic (e.g., first transmitter logic 877) and receive/receiver logic (e.g., first receiver logic 883) coupled to the control logic 873 and/or the processor 871. In an embodiment, the transmit/transmitter and/or receive/receiver logic may be elements or modules of transceiver logic. The first transmitter logic 877 and the first receiver logic 883 may be housed in separate devices. For example, the first transmitter logic 877 may be incorporated into a first device and the first receiver logic 883 into a second device, or the first transmitter logic 877 and the first receiver logic 883 may be incorporated into a device separate from the device including any combination of the control logic 873, the memory 879, and/or the processor 871. The electronic device 800 may be coupled with, or may include, one or more antenna elements 885 of one or more antennas. Electronic device 800 and/or components of electronic device 800 may be configured to perform operations similar to those described elsewhere in this disclosure.

In some embodiments, the electronic device 800 implements a UE, and/or an eNodeB, or a device portion thereof, or the electronic device 800 is incorporated into a UE, and/or an eNodeB, or a device portion thereof, or the electronic device 800 is otherwise part of a UE, and/or an eNodeB, or a device portion thereof, and the electronic device 800 can generate and/or transmit the polarization code. Processor 871 can be coupled to a first receiver and a first transmitter. A memory 879 may be coupled to the processor 871 having control logic instructions thereon that, when executed, generate and/or transmit polarization codes.

In some embodiments thereof, the electronic device 300 receives data from, generates data, and/or transmits data to a UE to implement a downlink signal including a polarization code, and a processor 871 may be coupled to the receiver and the transmitter. A memory 879 may be coupled to the processor 871 having control logic instructions that, when executed, are capable of configuring V2X communication based on geographic location.

The term "logic" as used herein may be, may be part of, or may include: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor 871 (shared, dedicated, or group) and/or memory 879 (shared, dedicated, or group), combinational logic circuit, and/or other suitable hardware components that perform the described functions. In particular, the logic may be implemented at least in part in hardware, software, and/or firmware, or in elements thereof. In some embodiments, the electronic device logic may be implemented by one or more software or firmware modules, or the functions associated with the logic may be implemented by one or more software or firmware modules.

Fig. 9 is a block diagram illustrating a method 985 for performing polarization encoding according to one embodiment. The method 985 comprises: selecting (903) a length S of the number of shortening bits and a length P of the number of puncturing bits based on the HARQ scheme; encoding (905) the plurality of information bits via a polar encoder module to generate a base code having a length of N minus a number of shortening bits; interleaving (907), via an interleaver module, the results of the polar encoder module to generate a codeword comprising the base code minus the shortened bits, minus the number of punctured bits, plus the number of extended bits of length E; providing (909) the codeword to a modulation module to generate a result of the multiplication of the codeword divided by the number of spatial streams and the number of bits per modulation; and providing (911) the result of the division to the channel for transmitting the polarization code to the receiving device.

The HARQ scheme may include chase combining transmission and/or HARQ-IR transmission. The method 985 further includes setting N to 2^ (ceil (log2 (N)_CB) And E is set to zero, where N_CBIs the length of the codeword. Method 985 further includes setting S to N-N_CBAnd P is set to zero. Method 985 may also include setting S to zero andsetting P to N-N_CB。

Method 985 may also include setting N to 2^ (floor (log2 (N)_CB) Wherein N) is_CBIs the length of the codeword and sets E to N_CB-N. Method 985 may also include setting S to zero and P to zero.

FIG. 10 is a block diagram illustrating a method 1087 for performing polarization encoding, in accordance with one embodiment. The method 1087 includes: generating (1021) at least a plurality of B inner bits by performing a plurality of operations on the A data bits; generating (1023) a plurality of D codeword bits by performing a plurality of operations on the B internal bits, wherein the D codeword bits correspond to a first stage of a polar encoder and the B internal bits correspond to a second stage of the polar encoder, and wherein the first and second stages are different stages of the polar encoder; and providing (1025) a subset of the a data bits, the D codeword bits, and the B inner bits to a channel for transmission.

The HARQ transmission may be at least one of a chase combining HARQ transmission and a HARQ-IR transmission. The a data bits may include a data bit and a freeze bit. The length of the a data bits, the length of the B inner bits, and the length of the D codeword bits may be the same length. The method 1087 also includes generating a subsequent HARQ transmission including a subset of the a data bits, the B inner bits, and the D codeword bits.

The HARQ transmission may include a circular buffer of a data bits, B inner bits, and a subset of D codeword bits. The subset of a data bits, B inner bits, and D codeword bits may include at least one of: d codeword bits and B inner bits, a portion of the B inner bits and D codeword bits, a portion of the D codeword bits and B inner bits, or B inner bits.

Fig. 11 is a block diagram illustrating a method 1189 for a polar decoder, according to one embodiment. The method 1189 includes: initializing (1131) a first plurality of LLRs for a plurality of bits received from a channel associated with a HARQ transmission; initializing (1133) a second plurality of LLRs for a plurality of suspension edges associated with the plurality of bits; performing (1135) a plurality of operations on the first plurality of messages and the second plurality of messages to generate a third plurality of LLRs, wherein the first plurality of messages comprises the first plurality of LLRs and the second plurality of messages comprises the second plurality of LLRs; and determining (1137) an estimate of an information block comprising the first plurality of bits and the second plurality of bits based on the third LLRs.

In some examples, the plurality of operations includes an add operation. Each of the plurality of operations may further include a minimization operation for determining a minimum LLR of the absolute value of the first LLR and the absolute value of the second LLR, a multiplication operation for determining a symbol by multiplying the symbol of the first LLR by the symbol of the second LLR, and providing the minimum LLR having the symbol.

The method 1189 further includes initializing LLRs from the first and second pluralities of LLRs associated with frozen bits from the first and second pluralities of bits to a predefined value, initializing LLRs from the first and second pluralities of LLRs associated with non-frozen bits from the first and second pluralities of bits to a sum of received LLRs associated with the bits, and initializing LLRs from the first and second pluralities of LLRs to zero for the bits that were not received. The estimate of the information block may comprise which codeword was transmitted over the channel. The second plurality of bits may be associated with inner bits of the polarization code.

FIG. 12 is a block diagram that illustrates components of the device, according to one embodiment. In some embodiments, the device may include at least application circuitry 1203, baseband circuitry 1205, Radio Frequency (RF) circuitry 1207, front-end module (FEM) circuitry 1209, and one or more antennas 1214, coupled to each other as shown in fig. 12. Any combination or subset of these components may be included in, for example, a UE device or an eNodeB device.

The application circuitry 1203 may include one or more application processors. By way of non-limiting example, the application circuitry 1203 may include one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). The processor(s) may be operably coupled to and/or may include memory/storage and may be configured to execute instructions stored in the memory/storage to cause various applications and/or operating systems to run on the system.

As a non-limiting example, baseband circuitry 1205 may include one or more single-core or multi-core processors. Baseband circuitry 1205 may include one or more baseband processors and/or control logic. Baseband circuitry 1205 may be configured to process baseband signals received from the receive signal path of RF circuitry 1207. The baseband circuitry 1205 may also be configured to generate baseband signals for the transmit signal path of the RF circuitry 1207. Baseband circuitry 1205 may interact with application circuitry 1203 for generating and processing baseband signals and for controlling operation of RF circuitry 1207.

As non-limiting examples, baseband circuitry 1205 may include at least one of a second generation (2G) baseband processor 1211A, a third generation (3G) baseband processor 1211B, a fourth generation (4G) baseband processor 1211C, and other baseband processor(s) 1211D for other existing, developing, or future developed generations (e.g., fifth generation (5G), sixth generation (6G), etc.). Baseband circuitry 1205 (e.g., at least one of the baseband processors 1211A-1211D) may handle various radio control functions that enable communication with one or more radio networks through the RF circuitry 1207. By way of non-limiting example, the radio control functions may include signal modulation/demodulation, encoding/decoding, radio frequency shifting, other functions, and combinations thereof. In some embodiments, the modulation/demodulation circuitry of the baseband circuitry 1205 may be programmed to perform Fast Fourier Transform (FFT), precoding, and constellation mapping/demapping functions, other functions, and combinations thereof. In some embodiments, encoding/decoding circuitry of baseband circuitry 1205 can be programmed to perform convolution, tail-biting convolution, turbo, viterbi, and Low Density Parity Check (LDPC) encoder/decoder functions, other functions, and combinations thereof. Embodiments of modulation/demodulation and encoder/decoder functions are not limited to these examples and may include other suitable functions.

In some embodiments, baseband circuitry 1205 may include elements of a protocol stack. By way of non-limiting example, elements of the Evolved Universal Terrestrial Radio Access Network (EUTRAN) protocol include, for example, Physical (PHY), Medium Access Control (MAC), Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), and/or Radio Resource Control (RRC) elements. A Central Processing Unit (CPU)1211E of the baseband circuitry 1205 may be programmed to run elements of a protocol stack for signaling of the PHY, MAC, RLC, PDCP, and/or RRC layers. In some embodiments, baseband circuitry 1205 may include one or more audio Digital Signal Processors (DSPs) 1211F. The audio DSP 1211F(s) may include elements for compression/decompression and echo cancellation. The audio DSP(s) 1211F may also include other suitable processing elements.

Baseband circuitry 1205 may also include memory/storage 1211G. Memory/storage 1211G may include data and/or instructions stored thereon for operations performed by the processor of baseband circuitry 1205. In some embodiments, memory/storage 1211G may include any combination of suitable volatile memory and/or non-volatile memory. Memory/storage 1211G may also include any combination of various levels of memory/storage including, but not limited to, Read Only Memory (ROM) with embedded software instructions (e.g., firmware), random access memory (e.g., Dynamic Random Access Memory (DRAM)), cache, buffers, and the like. In some embodiments, memory/storage 1211G may be shared among various processors or dedicated to a particular processor.

In some embodiments, the components of baseband circuitry 1205 may be suitably combined in a single chip or a single chipset, or suitably arranged on the same circuit board. In some embodiments, some or all of the constituent components of the baseband circuitry 1205 and the application circuitry 1203 may be implemented together, for example, on a system on a chip (SOC).

In some embodiments, baseband circuitry 1205 may provide communication compatible with one or more radio technologies. For example, in some embodiments, baseband circuitry 1205 may support communication with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) and/or other Wireless Metropolitan Area Networks (WMANs), Wireless Local Area Networks (WLANs), or Wireless Personal Area Networks (WPANs). In some embodiments, baseband circuitry 1205 is configured to support radio communications of more than one wireless protocol, which embodiments may be referred to as multi-mode baseband circuitry.

The RF circuitry 1207 may enable communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 1207 may include switches, filters, amplifiers, and the like to facilitate communication with a wireless network. The RF circuitry 1207 may include a receive signal path, which may include circuitry to downconvert RF signals received from the FEM circuitry 1209 and provide baseband signals to the baseband circuitry 1205. The RF circuitry 1207 may also include transmit signal paths, which may include circuitry to upconvert baseband signals provided by the baseband circuitry 1205 and provide RF output signals to the FEM circuitry 1209 for transmission.

In some embodiments, RF circuitry 1207 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 1207 may include mixer circuitry 1213A, amplifier circuitry 1213B, and filter circuitry 1213C. The transmit signal path of the RF circuitry 1207 may include filter circuitry 1213C and mixer circuitry 1213A. The RF circuitry 1207 may also include synthesizer circuitry 1213D configured to synthesize frequencies for use by the mixer circuitry 1213A of the receive and transmit signal paths. In some embodiments, the mixer circuitry 1213A of the receive signal path may be configured to down-convert the RF signal received from the FEM circuitry 1209 based on the synthesized frequency provided by the synthesizer circuitry 1213D. The amplifier circuit 1213B may be configured to amplify the downconverted signal.

The filter circuit 1213C may include a Low Pass Filter (LPF) or a Band Pass Filter (BPF) configured to remove unwanted signals from the down-converted signals to generate an output baseband signal. The output baseband signal may be provided to baseband circuitry 1205 for further processing. In some embodiments, the output baseband signal may comprise a zero frequency baseband signal, but this is not required. In some embodiments, mixer circuitry 1213A of the receive signal path may comprise a passive mixer, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 1213A of the transmit signal path may be configured to upconvert the input baseband signal based on a synthesis frequency provided by the synthesizer circuitry 1213D to generate an RF output signal for the FEM circuitry 1209. Baseband signals may be provided by baseband circuitry 1205 and may be filtered by filter circuitry 1213C. The filter circuit 1213C may include a Low Pass Filter (LPF), although the scope of the embodiments is not limited in this respect.

In some embodiments, mixer circuitry 1213A of the receive signal path and mixer circuitry 1213A of the transmit signal path may comprise two or more mixers and may be arranged for quadrature down-conversion or up-conversion, respectively. In some embodiments, the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may be arranged for direct down-conversion and/or direct up-conversion, respectively. In some embodiments, mixer circuitry 1213A of the receive signal path and mixer circuitry 1213A of the transmit signal path may be configured for superheterodyne operation.

In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In such embodiments, the RF circuitry 1207 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and the baseband circuitry 1205 may include a digital baseband interface for communicating with the RF circuitry 1207.

In some dual-mode embodiments, separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

In some embodiments, synthesizer circuit 1213D may include one or more of a fractional-N synthesizer or a fractional-N/N +1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, the synthesizer circuitry 1213D may include a delta sigma synthesizer, a frequency multiplier, or a synthesizer including a phase locked loop with a frequency divider, other synthesizers, and combinations thereof.

The synthesizer circuit 1213D may be configured to synthesize an output frequency based on the frequency input and the divider control input for use by the mixer circuit 1213A of the RF circuit 1207. In some embodiments, the synthesizer circuit 1213D may be a fractional N/N +1 synthesizer.

In some embodiments, the frequency input may be provided by a Voltage Controlled Oscillator (VCO), but this is not required. The divider control input may be provided by baseband circuitry 1205 or application circuitry 1203 depending on the desired output frequency. In some embodiments, the divider control input (e.g., N) may be determined from a look-up table based on the channel indicated by application circuitry 1203.

Synthesizer circuit 1213D of RF circuit 1207 may include a frequency divider, a Delay Locked Loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the frequency divider may comprise a dual mode frequency divider (DMD) and the phase accumulator may comprise a Digital Phase Accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by N or N +1 (e.g., based on a carry bit) to provide a fractional division ratio. In some example embodiments, a DLL may include a set of cascaded tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In such embodiments, the delay elements may be configured to decompose the VCO period into at most Nd equal phase groups, where Nd is the number of delay elements in the delay line. In this way, the DLL can provide negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

In some embodiments, the synthesizer circuit 1213D may be configured to generate a carrier frequency as the output frequency. In some embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency, etc.) and used in conjunction with a quadrature generator and divider circuit to generate multiple signals having multiple phases different from each other at the carrier frequency. In some embodiments, the output frequency may be the LO frequency (fLO). In some embodiments, the RF circuitry 1207 may include an IQ/polarity converter.

FEM circuitry 1209 may include a receive signal path, which may include circuitry configured to operate on RF signals received from the one or more antennas 1214, amplify the received signals, and provide amplified versions of the received signals to RF circuitry 1207 for further processing. The FEM circuitry 1209 may also include a transmit signal path, which may include circuitry configured to amplify signals provided by the RF circuitry 1207 for transmission by at least one of the one or more antennas 1214.

In some embodiments, the FEM circuitry 1209 may include a TX/RX switch configured to switch between transmit mode and receive mode operation. FEM circuitry 1209 may include receive and transmit signal paths. The receive signal path of FEM circuitry 1209 may include a Low Noise Amplifier (LNA) to amplify a received RF signal and provide the amplified received RF signal as an output (e.g., to RF circuitry 1207). The transmit signal path of the FEM circuitry 1209 may include a Power Amplifier (PA) configured to amplify an input RF signal (e.g., provided by the RF circuitry 1207), and may include one or more filters configured to generate an RF signal for subsequent transmission (e.g., by one or more of the one or more antennas 1214).

In some embodiments, the device may include additional elements, such as memory/storage, a display, a camera, one or more sensors, an input/output (I/O) interface, other elements, or a combination thereof.

In some embodiments, a device may be configured to perform one or more of the processes, techniques, and/or methods described herein, or portions thereof.

FIG. 13 is a block diagram that illustrates components, according to some embodiments. In particular, fig. 13 shows a diagram of a hardware resource 1300, the hardware resource 1300 including one or more processors (or processor cores) 1310, one or more memory/storage devices 1320, and one or more communication resources 1330, all of which are communicatively coupled by a bus 1340.

Processor 1310 (e.g., a Central Processing Unit (CPU), a Reduced Instruction Set Computing (RISC) processor, a Complex Instruction Set Computing (CISC) processor, a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP) (e.g., a baseband processor), an Application Specific Integrated Circuit (ASIC), a Radio Frequency Integrated Circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processor 1312 and processor 1314. Memory/storage 1320 may include main memory, disk storage, or any suitable combination thereof.

Communication resources 1330 may include interconnection and/or network interface components or other suitable devices for communicating with one or more peripherals 1304 and/or one or more databases 1311 over network 1308. For example, communication resources 1330 can include a wired communication component (e.g., for coupling over a Universal Serial Bus (USB)), a cellular communication component, a Near Field Communication (NFC) component, a wireless communication component, and/wireless communication component,

The components (e.g.,

low power consumption),

Components, and other communication components.

The instructions 1350 may include software, programs, applications, applets, apps, or other executable code for causing the at least one processor 1310 to perform any one or more of the methods discussed herein. The instructions 1350 may reside, completely or partially, within the at least one processor 1310 (e.g., within a cache memory of the processor), the memory/storage 1320, or any suitable combination thereof. Further, any portion of instructions 1350 may be transferred to hardware resource 1300 from any combination of peripherals 1304 and/or database 1311. Thus, the memory of processor 1310, memory/storage 1320, peripherals 1304, and database 1311 are examples of computer-readable and machine-readable media.

Example embodiments

Example 1 is an apparatus for performing polar encoding. The apparatus includes an electronic memory for storing a plurality of data bits for use in a first stage of a polarization encoder different from a second stage of the polarization encoder. The apparatus includes one or more baseband processing units designed to generate at least a plurality of internal bits in a first stage of a polar encoder by performing a plurality of operations on data bits, wherein the internal bits are internal to the polar encoder. The apparatus includes one or more baseband processing units designed to generate a plurality of codeword bits in a second stage of a polar encoder by performing a plurality of operations on internal bits, wherein the codeword bits correspond to the second stage of the polar encoder and the internal bits correspond to the first stage of the polar encoder. The apparatus includes one or more baseband processing units designed to provide a subset of data bits, codeword bits, and internal bits to a channel of a physical layer for hybrid automatic repeat request (HARQ) transmission.

Example 2 is the apparatus of example 1, wherein the apparatus is a User Equipment (UE), and wherein the channel is at least one of an uplink channel and a sidelink channel.

Example 3 is the apparatus of example 1, wherein the apparatus is an evolved user node (eNodeB), and wherein the channel is at least one of downlink channels.

Example 4 is the apparatus of example 1, wherein the transmission is at least one of a chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.

Example 5 is the apparatus of example 1, wherein the data bits for the first stage of the polarization encoder comprise bits set to a predetermined value.

Example 6 is the apparatus of example 1, wherein a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.

Example 7 is the apparatus of example 1, wherein the one or more processing units are further designed to generate a subsequent HARQ transmission comprising a subsequent subset of data bits, inner bits, and codeword bits that is different from the subset of data bits, inner bits, and codeword bits.

Example 8 is the apparatus of example 1, wherein the HARQ transmission comprises a circular buffer of data bits, inner bits, and a subset of codeword bits.

Example 9 is the apparatus of example 1, wherein the subset of data bits, inner bits, and codeword bits comprises one of: codeword bits and inner bits, codeword bits and a portion of inner bits, inner bits and a portion of codeword bits, and inner bits.

Example 10 is a computer-readable storage medium. The computer-readable storage medium has stored thereon instructions that, when implemented by a computing device, cause the computing device to initialize a first plurality of log-likelihood ratios (LLRs) for a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission. The computer-readable storage medium has stored thereon instructions that, when implemented by a computing device, cause the computing device to initialize a second plurality of LLRs for a plurality of hanging edges associated with a plurality of bits of a polarization decoder. The computer-readable storage medium has stored thereon instructions that, when implemented by a computing device, cause the computing device to perform a plurality of operations on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs. The computer-readable storage medium has stored thereon instructions that, when implemented by a computing device, cause the computing device to determine an estimate of an information block comprising a first plurality of bits and a second plurality of bits based on a third plurality of LLRs, wherein the first plurality of bits and the second plurality of bits comprise data bits.

Example 11 is the computer-readable storage medium of example 10, wherein a User Equipment (UE) or an evolved node b (enodeb) comprises the computer-readable storage medium.

Example 12 is the computer-readable storage medium of example 10, wherein the plurality of operations comprises an add operation.

Example 13 is the computer-readable storage medium of example 10, wherein each of the plurality of operations comprises: the method includes determining a minimization operation of a minimum LLR of absolute values of the first LLR and absolute values of the second LLR, determining a multiplication operation of a symbol by multiplying the symbol of the first LLR by the symbol of the second LLR, and providing the minimum LLR having the symbol.

Example 14 is the computer-readable storage medium of example 10, wherein the instructions designed to initialize the first plurality of LLRs and initialize the second plurality of LLRs further comprise: instructions to initialize LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to predefined values. The computer-readable storage medium of example 10, wherein the instructions designed to initialize the first plurality of LLRs and initialize the second plurality of LLRs further comprise: instructions to initialize each of the first plurality of LLRs and the second plurality of LLRs associated with a non-frozen bit from the plurality of bits to a sum of received LLRs for a respective one of the non-frozen bits, and to initialize the LLRs from the first plurality of LLRs and the second plurality of LLRs to zero for bits that are not received.

Example 15 is the computer-readable storage medium of example 10, wherein the estimation of the information block includes which codeword is transmitted over the channel.

Example 16 is the computer-readable storage medium of example 10, wherein zero or more bits of the plurality of bits are associated with polarization encoded inner bits.

Example 17 is an apparatus for performing polar encoding. The apparatus includes an electronic memory for storing a plurality of information bits to be encoded by the polar encoder module, the plurality of information bits having a length K. The apparatus includes one or more processing units designed to select a length of a shortened bit number S and a length of a punctured bit number P based on a hybrid automatic repeat request (HARQ) scheme, and encode a plurality of information bits via a polar encoder module to generate a base codeword having a length N minus the shortened bit number. The apparatus includes one or more processing units designed to interleave, via an interleaver module, the results of the polar encoder module to generate a codeword comprising a base codeword minus shortened bits, minus a number of punctured bits, plus a number of extended bits of length E. The apparatus includes one or more processing units designed to provide codewords to a modulation module to generate a result of multiplying the codewords by the number of spatial streams and the number of bits per modulation, and to provide the result of the division to a channel of a physical layer to transmit a polar code to a receiving device.

Example 18 is the apparatus of example 17, wherein the apparatus is one of a User Equipment (UE) or an evolved node b (enodeb).

Example 19 is the apparatus of example 17, wherein the HARQ scheme comprises chase combining transmission.

Example 20 is the apparatus of example 17, wherein the HARQ scheme comprises HARQ incremental redundancy (HARQ-IR) transmission.

Example 21 is the apparatus of example 17, wherein the one or more processing units are further designed to set N to 2^ (ceil (log2 (N)_CB) Wherein N) is_CBIs the length of the codeword and E is set to zero.

Example 22 is the apparatus of example 17, wherein the one or more processing units are further designed to set S to N-N_CBAnd P is set to zero.

Example 23 is the apparatus of example 17, wherein the one or more processing units are further designed to set S to zero and P to N-N_CB。

Example 24 is the apparatus of example 17, wherein the one or more processing units are further designed to set N to 2^ (floor (log2 (N)_CB) Wherein N) is_CBIs the length of the codeword and sets E to N_CB-N。

Example 25 is the apparatus of example 17, wherein the one or more processing units are further designed to set S to zero and P to zero.

Example 26 is a method, comprising: at least a plurality of internal bits are generated in a first stage of a polar encoder by performing a plurality of operations on a plurality of data bits used in the first stage of the polar encoder that are different from a second stage of the polar encoder, wherein the internal bits are internal to the polar encoder. The method further comprises the following steps: a plurality of codeword bits are generated in a second stage of the polar encoder by performing a plurality of operations on the internal bits, wherein the codeword bits correspond to the second stage of the polar encoder and the internal bits correspond to the first stage of the polar encoder. The method further comprises the following steps: for hybrid automatic repeat request (HARQ) transmission, a subset of the data bits, codeword bits, and inner bits are provided to a channel of the physical layer.

Example 27 is the method of example 26, wherein providing comprises providing, by an apparatus of a User Equipment (UE), a subset of the data bits, the codeword bits, and the inner bits to a channel of a physical layer, and wherein the channel is at least one of an uplink channel and a sidelink channel.

Example 28 is the method of example 26, wherein providing comprises providing, by an apparatus of an evolved user node (eNodeB), a subset of the data bits, the codeword bits, and the inner bits to a channel of a physical layer, and wherein the channel is at least one of a downlink channel.

Example 29 is the method of example 26, wherein the HARQ transmission is at least one of a chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.

Example 30 is the method of example 26, wherein the data bits for the first stage of the polar encoder comprise bits set to a predetermined value.

Example 31 is the method of example 26, wherein a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.

Example 32 is the method of example 26, further comprising generating a subsequent HARQ transmission comprising a subsequent subset of data bits, inner bits, and codeword bits that is different from the subset of data bits, inner bits, and codeword bits.

Example 33 is the method of example 26, wherein the HARQ transmission comprises a circular buffer of data bits, inner bits, and a subset of codeword bits.

Example 34 is the method of example 26, wherein the subset of data bits, inner bits, and codeword bits comprises one of: codeword bits and inner bits, codeword bits and a portion of inner bits, inner bits and a portion of codeword bits, and inner bits.

Example 35 is a method, comprising: a first plurality of log-likelihood ratios (LLRs) of a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission is initialized. The method further comprises the following steps: a second plurality of LLRs for a plurality of hanging edges associated with the plurality of bits of the polarization decoder are initialized. The method further comprises the following steps: a plurality of operations is performed on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs. The method further comprises the following steps: an estimate of an information block comprising a first plurality of bits and a second plurality of bits is determined based on the third plurality of LLRs, wherein the first plurality of bits and the second plurality of bits comprise data bits.

Example 36 is the method of example 35, wherein initializing the plurality of LLRs, initializing the second plurality of LLRs, performing the plurality of operations, and determining the estimate of the information block are performed by a User Equipment (UE) or an evolved node b (enodeb).

Example 37 is the method of example 35, wherein the plurality of operations comprises an add operation.

Example 38 is the method of example 35, wherein each of the plurality of operations comprises: a minimization operation of a minimum LLR of the absolute value of the first LLR and the absolute value of the second LLR is determined. The plurality of operations includes a multiplication operation to determine a symbol by multiplying the symbol of the first LLR by the symbol of the second LLR and provide a minimum LLR having the symbol.

Example 39 is the method of example 35, wherein initializing the first plurality of LLRs and initializing the second plurality of LLRs further comprises: instructions to initialize LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to predefined values. Initializing the first plurality of LLRs and initializing the second plurality of LLRs further comprises: each LLR from the first and second pluralities of LLRs associated with a non-frozen bit from the plurality of bits is initialized to a sum of received LLRs for a respective one of the non-frozen bits, and the LLRs from the first and second pluralities of LLRs are initialized to zero for the bits that were not received.

Example 40 is the method of example 35, wherein the estimation of the information block includes which codeword was transmitted over the channel.

Example 41 is the method of example 35, wherein zero or more bits of the plurality of bits are associated with inner bits of the polarization encoding.

Example 42 is a method. The method includes an electronic memory for storing a plurality of information bits to be encoded by the polar encoder module, the plurality of information bits having a length K. The method further comprises one or more processing units designed to select the length of the number of shortened bits S and the length of the number of punctured bits P based on a hybrid automatic repeat request (HARQ) scheme. The method also includes one or more processing units designed to encode the plurality of information bits via the polar encoder module to generate a base code having a length of N minus the number of shortening bits. The method also includes one or more processing units designed to interleave, via an interleaver module, the results of the polar encoder module to generate a codeword comprising the base codeword minus the shortened bits, minus the number of punctured bits, plus the number of extended bits of length E. The method also includes one or more processing units designed to provide the codewords to a modulation module to generate a result of multiplying the codewords by the number of spatial streams and the number of bits per modulation, and to provide the result of the division to a channel of a physical layer to transmit the polar code to a receiving device.

Example 43 is the method of example 42, wherein the HARQ scheme comprises chase combining transmissions.

Example 44 is the method of example 42, wherein the HARQ scheme comprises HARQ incremental redundancy (HARQ-IR) transmission.

Example 45 is the method of example 42, further comprising setting N to 2^ (ceil (log2 (N)_CB) Wherein N) is_CBIs the length of the codeword and E is set to zero.

Embodiment 46 is the method of embodiment 42, further comprising setting S to N-N_CBAnd P is set to zero.

Example 47 is the method of example 42, further comprising setting S to zero and P to N-N_CB。

Example 48 is the method of example 42, further comprising setting N to 2^ (floor (log2 (N)_CB) Wherein N) is_CBIs the length of the codeword and sets E to N_CB-N。

Example 49 is the method of example 42, further comprising setting S to zero and setting P to zero.

Example 50 is at least one computer-readable storage medium having computer-readable instructions stored thereon that, when executed, implement the method of any of examples 26-44.

Embodiment 51 is an apparatus comprising means for performing the method of any of examples 26-44.

Embodiment 52 is an apparatus to perform the method of any of examples 26-44.

Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, non-transitory computer-readable storage media, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of program code execution on programmable computers, the computing device can include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and non-volatile memory and/or storage elements can be a RAM, an EPROM, a flash drive, an optical drive, a magnetic hard drive, or another medium for storing electronic data. The eNodeB (or other base station) and the UE (or other mobile station) may also include a transceiver component, a counter component, a processing component, and/or a clock component or timer component. One or more programs that may implement or utilize the various techniques described herein may use an Application Programming Interface (API), reusable controls, and the like. Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

It should be understood that many of the functional units described in this specification can be implemented as one or more components, which are terms used to more emphasize their implementation independence. For example, a component may be implemented as a hardware circuit comprising custom Very Large Scale Integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

Components may also be implemented in software for execution by various types of processors. For example, an identified component of executable code may comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the component and achieve the stated purpose for the component.

Indeed, a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified or illustrated herein within components, and may be embodied in any suitable form or organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. The components may be passive or active, including agents operable to perform desired functions.

Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, the appearances of the phrase "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment.

Various items, structural elements, compositional elements, and/or materials used herein may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. Moreover, various embodiments and examples, as well as alternatives to their various components, may be referred to herein. It should be understood that such embodiments, examples, and alternatives are not to be considered as actual equivalents of each other, but rather as separate and independent representations of the embodiments.

Although the foregoing has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be made without departing from the principles thereof. It should be noted that there are many alternative ways of implementing the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims (9)

1. A method of polar decoding, comprising:

initializing a first plurality of log-likelihood ratios (LLRs) of a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with hybrid automatic repeat request (HARQ) transmission;

initializing a second plurality of LLRs for a plurality of hanging edges of a polarization decoder associated with the plurality of bits;

performing a plurality of operations on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs; and

determining an estimate of an information block comprising a first plurality of bits and a second plurality of bits comprising data bits based on the third plurality of LLRs.

2. The method of claim 1, wherein initializing the first plurality of LLRs, initializing the second plurality of LLRs, performing the plurality of operations, and determining an estimate of the information block are performed by a User Equipment (UE) or an evolved node b (enodeb).

3. The method of claim 1, wherein the plurality of operations comprises an add operation.

4. The method of claim 1, wherein each of the plurality of operations comprises:

a minimization operation for determining a minimum LLR of the absolute values of the first and second LLRs;

a multiplication operation to determine a sign by multiplying the sign of the first LLR by the sign of the second LLR; and

providing the minimum LLR with the symbol.

5. The method of claim 1, wherein initializing the first plurality of LLRs and initializing the second plurality of LLRs further comprises:

initializing LLRs from the first and second pluralities of LLRs associated with frozen bits from the first and second pluralities of bits to a predefined value;

initializing each LLR of the first and second pluralities of LLRs associated with a non-frozen bit from the plurality of bits to a sum of received LLRs for a respective one of the non-frozen bits; and is

For bits not received, initializing LLRs from the first and second pluralities of LLRs to zero.

6. The method of claim 1, 2, 3, 4 or 5, wherein the estimation of information blocks includes which codeword is transmitted over the channel.

7. The method of claim 1, 2, 3, 4, or 5, wherein zero or more bits of the plurality of bits are associated with inner bits of a polarization encoding.

8. An apparatus for performing the method of any one of claims 1-7.

9. At least one computer-readable storage medium having computer-readable instructions stored thereon that, when executed, implement the method of any one of claims 1-7.

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