CN108432167B - Apparatus, system, and computer readable medium for encoding and decoding a message - Google Patents

Abstract

A set of information bits to be transmitted is encoded according to a parity block to produce a first codeword that represents a set of parity nodes based on the set of information bits and based on a set of parity bits. The parity bits to be de-prioritized from the first codeword are selected based on a selection criterion that de-prioritizes those parity bits associated with a relatively large number of parity nodes. An output data set is generated for transmission based on the first codeword, wherein selected parity bits are of reduced priority.

Description

Apparatus, system, and computer readable medium for encoding and decoding a message

Priority requirement

This application claims benefit of U.S. provisional application No. 62/278,742 entitled "LDPC PUNCTURING PATTERN SELECTION" filed on 14.1.2016, the disclosure of which is incorporated herein by reference.

Technical Field

Embodiments pertain to wireless communications. Some embodiments relate to wireless networks including 3GPP (third generation partnership project) networks, 3GPP LTE (long term evolution) networks, 3GPP LTE-a (LTE-advanced) networks, and 5G networks. Other embodiments relate to Wi-Fi alliance wireless networks. Further embodiments are more generally applicable outside the scope of LTE and Wi-Fi networks.

Background

In communication systems, particularly wireless systems, the communication channel between the transmitter and the receiver is subject to noise, which may interfere with the integrity of the data being communicated. For example, signal interference may cause errors in the communicated information bits. One way to deal with this problem is to use error correction coding. Error correction is the addition of redundant information to the message transmission that enables the receiver to detect errors and to recover the expected error-free data.

Low Density Parity Check (LDPC) codes are the first proposed forward error correction codes in the early 60's of the 20 th century. At that time, no potential was found due to the limitations of the computer system required to perform the simulation. Researchers have ignored LDPC codes for decades until the mid-90 20 th century, when it was discovered that LDPC codes have the ability to outperform other existing forward error correction schemes.

As with any forward error correction coding, the information redundancy introduced using LDPC codes represents an engineering tradeoff between data communication rate on the one hand and communication system robustness on the other hand. The ratio of the information to be communicated to the total message size is referred to as the coding rate. To accommodate the increasing demand for data communication speed, solutions are needed to increase the coding rate with negligible impact on the robustness provided by the error correction coding overhead.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. In the following figures of the drawings, some embodiments are shown by way of example and not by way of limitation.

Fig. 1 is a functional diagram of a 3GPP network according to some embodiments.

Fig. 2 is a block diagram of a User Equipment (UE) in accordance with some embodiments.

Fig. 3 is a block diagram of an evolved node b (enb) in accordance with some embodiments.

Fig. 4 is a diagram illustrating an example parity check matrix according to an example embodiment.

Fig. 5A to 5C show simplified examples of permutated identity matrices used as sub-matrices in a parity check matrix of the type illustrated in fig. 4.

FIG. 6 illustrates a system for performing LDPC encoding and optimization according to some embodiments.

Fig. 7 is a diagram illustrating an example of the operation of the system of fig. 6, according to some embodiments.

Fig. 8 is a flow diagram illustrating a process for puncturing (puncturing) parity bits, according to some embodiments.

Fig. 9 is a diagram illustrating a permutation operation for systematic bits and parity bits, in accordance with some embodiments.

FIG. 10 illustrates a system for performing LDPC receive side decoding according to some embodiments.

Fig. 11 is a diagram illustrating an example of the operation of the system of fig. 10 according to an embodiment.

FIG. 12 is a diagram illustrating operations in a layered iterative decoding scheme, according to some embodiments.

Detailed Description

The following description and the annexed drawings set forth in detail certain illustrative embodiments sufficiently to enable those skilled in the art to practice them. A number of examples are described in the context of a 3GPP communication system and its components. It will be understood that the principles of the embodiments are applicable to other types of communication systems, such as Wi-Fi or Wi-Max networks, bluetooth or other personal area networks, Zigbee or other home networks, wireless mesh networks, and the like, and are not so limited unless expressly limited by the corresponding claims. Those skilled in the art, having the benefit of this disclosure, will be able to devise suitable variations to implement the principles of embodiments in other types of communication systems. Various different embodiments may include structural differences, logical differences, electrical differences, processing differences, and other differences. Portions and features of some embodiments may be included in or substituted for those of others. Embodiments set forth in the claims encompass all currently known and later-presented matters, as well as equivalents of those claims.

Fig. 1 is a functional diagram of a 3GPP network according to some embodiments. The network includes a Radio Access Network (RAN) (e.g., E-UTRAN or evolved universal terrestrial radio access network, as depicted) 101 and a core network 120 (e.g., shown as Evolved Packet Core (EPC)) coupled together by an S1 interface 115. For convenience and brevity, only a portion of the core network 120 and the RAN 101 are shown.

The core network 120 includes a Mobility Management Entity (MME)122, a serving gateway (serving GW)124, and a packet data network gateway (PDN GW) 126. RAN 101 includes an evolved node b (enb)104 (which may operate as a base station) for communicating with User Equipment (UE) 102. The enbs 104 may include macro enbs and Low Power (LP) enbs. According to some embodiments, the eNB 104 may send a downlink control message to the UE 102 to indicate allocation of Physical Uplink Control Channel (PUCCH) channel resources. The UE 102 may receive a downlink control message from the eNB 104 and may transmit an uplink control message to the eNB 104 in at least a portion of the PUCCH channel resources. These embodiments will be described in more detail below.

The MME 122 is functionally similar to the control plane of a legacy Serving GPRS Support Node (SGSN). The MME 122 manages mobility aspects in access such as gateway selection and tracking area list management. The serving GW 124 terminates the interface towards the RAN 101 and routes data packets between the RAN 101 and the core network 120. In addition, it may be a local mobility anchor for inter-eNB handover and may also provide an anchor for inter-3 GPP mobility. Other responsibilities may include statutory interception, charging, and certain policy enforcement. The serving GW 124 and MME 122 may be implemented in one physical node or in separate physical nodes. The PDN GW 126 terminates the SGi interface towards the Packet Data Network (PDN). The PDN GW 126 routes data packets between the EPC 120 and the external PDN, and may be a key node for policy enforcement and charging data collection. It may also provide an anchor point for mobility for non-LTE accesses. The external PDN may be any kind of IP network as well as IP Multimedia Subsystem (IMS) domain. The PDN GW 126 and the serving GW 124 may be implemented in one physical node or in separate physical nodes.

The enbs 104 (macro and micro enbs) terminate the air interface protocol and may be the first contact point for the UE 102. In some embodiments, the eNB 104 may perform various logical functions of the RAN 101 including, but not limited to, RNC (radio network controller) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management. According to an embodiment, the UE 102 may be configured to: the communications with the eNB 104 are conducted over a multipath fading channel in accordance with Orthogonal Frequency Division Multiple Access (OFDMA) communication techniques. The OFDM signal may include a plurality of orthogonal subcarriers.

S1 interface 115 is an interface that separates RAN 101 from EPC 120. It is divided into two parts: S1-U carrying traffic data between the eNB 104 and the serving GW 124, and S1-MME as a signaling interface between the eNB 104 and the MME 122. The X2 interface is the interface between enbs 104. The X2 interface comprises two parts, X2-C and X2-U. X2-C is the control plane interface between eNBs 104, while X2-U is the user plane interface between eNBs 104.

In the case of cellular networks, LP cells are typically used to extend coverage to indoor areas where outdoor signals do not reach well, or to increase network capacity in areas where telephone use is very dense (e.g., train stations). As used herein, the term Low Power (LP) eNB refers to any suitable low power eNB for implementing a narrower cell (narrower than a macrocell), such as a femtocell, picocell, or microcell. Femtocell enbs are typically provided by mobile network operators to their home or business customers. A femto cell is typically the size of a home gateway or smaller and is typically connected to a subscriber's broadband line. Once plugged in, the femto cell connects to the mobile operator's mobile network and provides additional coverage for the home femto cell, typically within a range of 30 to 50 meters. Thus, the LP eNB may be a femto cell eNB as it is coupled through the PDN GW 126. Similarly, a picocell is a wireless communication system that typically covers a small area, such as within a building (office, mall, train station, etc.), or more recently, within an aircraft. A picocell eNB is typically connected to another eNB through an X2 link, for example to a macro eNB through its Base Station Controller (BSC) functionality. Thus, the LP eNB may be implemented with a picocell eNB because it is coupled to a macro eNB via an X2 interface. A pico eNB or other LP eNB may incorporate some or all of the functionality of a macro eNB. In some cases, this may be referred to as an access point base station or an enterprise femtocell.

In some embodiments, the downlink resource grid may be used for downlink transmissions from the eNB 104 to the UE 102, while uplink transmissions from the UE 102 to the eNB 104 may utilize similar techniques. The grid may be a time-frequency grid, referred to as a resource grid or time-frequency resource grid, which is a physical resource in the downlink in each slot. Such a time-frequency plane representation is common practice for OFDM systems, which makes radio resource allocation intuitive. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in the radio frame. The smallest time-frequency unit in a resource grid is called a Resource Element (RE). Each resource grid includes a plurality of Resource Blocks (RBs) that describe the mapping of certain physical channels to resource elements. Each resource block includes a set of resource elements in the frequency domain and may represent a minimum amount of resources that can currently be allocated. There are several different physical downlink channels transmitted using such resource blocks. Of particular relevance to the present disclosure, two of these physical downlink channels are a physical downlink shared channel and a physical downlink control channel.

The Physical Downlink Shared Channel (PDSCH) carries user data and higher layer signaling to the UE 102 (fig. 1). The Physical Downlink Control Channel (PDCCH) carries information about the transport format and resource allocation associated with the PDSCH channel. It also informs the UE 102 of transport format, resource allocation and hybrid automatic repeat request (HARQ) information related to the uplink shared channel. In general, downlink scheduling may be performed at the eNB 104 (e.g., assigning control and shared channel resource blocks to UEs 102 within a cell) based on channel quality information fed back from the UEs 102 to the eNB 104, and then downlink resource assignment information may be sent to the UEs 102 on a control channel (PDCCH) used for (assigned to) the UEs 102.

The PDCCH transmits control information using CCEs (control channel elements). The PDCCH complex-valued symbols are first organized into quadruplets before being mapped to resource elements, and then permuted using a sub-block interleaver for rate matching. Each PDCCH is transmitted using one or more of these Control Channel Elements (CCEs), where each CCE corresponds to nine sets of four physical resource elements called Resource Element Groups (REGs). Four QPSK symbols are mapped to each REG. Depending on the size of Downlink Control Information (DCI) and channel conditions, the PDCCH may be transmitted using one or more CCEs. There may be four or more different PDCCH formats defined in LTE, with different numbers of CCEs (e.g., aggregation level, L ═ 1,2, 4, or 8).

As used herein, the term "circuitry" may refer to, be a part of, or include: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry may be implemented in, or functions associated with, one or more software or firmware modules. In some embodiments, the circuitry may comprise logic operable, at least in part, in hardware. The embodiments described herein may be implemented into a system using any suitably configured hardware or software.

Fig. 2 is a functional diagram of a User Equipment (UE) according to some embodiments. The UE 200 may be suitable for use as the UE 102 depicted in fig. 1. In some embodiments, the UE 200 may include application circuitry 202, baseband circuitry 204, Radio Frequency (RF) circuitry 206, Front End Module (FEM) circuitry 208, and a plurality of antennas 210A-210D coupled together at least as shown. In some embodiments, other circuits or arrangements may include one or more, and in some cases may also include other, elements or components in the application circuitry 202, the baseband circuitry 204, the RF circuitry 206, or the FEM circuitry 208. By way of example, "processing circuitry" may include one or more elements or components, some or all of which may be included in application circuitry 202 or baseband circuitry 204. As another example, a "transceiver circuit" may include one or more elements or components, some or all of which may be included in the RF circuitry 206 or the FEM circuitry 208. However, these examples are not limiting as the processing circuitry or transceiver circuitry may also include other elements or components in some cases.

The application circuitry 202 may include one or more application processors. For example, the application circuitry 202 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). The processor may be coupled to or may include memory/storage and may be configured to: the instructions stored in the memory/storage are executed to enable various applications or operating systems to run on the system.

The baseband circuitry 204 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. Baseband circuitry 204 may include one or more baseband processors or control logic to process baseband signals received from the receive signal path of RF circuitry 206 and to generate baseband signals for the transmit signal path of RF circuitry 206. The baseband circuitry 204 may interface with the application circuitry 202 for generating and processing baseband signals and controlling operation of the RF circuitry 206. For example, in some embodiments, the baseband circuitry 204 may include a second generation (2G) baseband processor 204a, a third generation (3G) baseband processor 204b, a fourth generation (4G) baseband processor 204c, or other baseband processor 204d for other existing generations, generations in development or to be developed in the future (e.g., fifth generation (5G), 6G, etc.). The baseband circuitry 204 (e.g., one or more of the baseband processors 204 a-d) may process various radio control functions that enable communication with one or more radio networks via the RF circuitry 206. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, and the like. In some embodiments, the modulation/demodulation circuitry of the baseband circuitry 204 may include Fast Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality. In some embodiments, the encoding/decoding circuitry of the baseband circuitry 204 may include Low Density Parity Check (LDPC) encoder/decoder functionality, optionally accompanied by other techniques, such as block codes, convolutional codes, turbo codes, etc., which may be used to support legacy protocols. Embodiments of modulation/demodulation and encoder/decoder functions are not limited to these examples, and other suitable functions may be included in other embodiments.

In some embodiments, baseband circuitry 204 may include elements of a protocol stack, such as elements of an Evolved Universal Terrestrial Radio Access Network (EUTRAN) protocol, including, for example, a Physical (PHY) element, a Medium Access Control (MAC) element, a Radio Link Control (RLC) element, a Packet Data Convergence Protocol (PDCP) element, or a Radio Resource Control (RRC) element. The Central Processing Unit (CPU)204e of the baseband circuitry 204 may be configured to: elements of the protocol stack are run for signaling of the PHY layer, MAC layer, RLC layer, PDCP layer, or RRC layer. In some embodiments, the baseband circuitry may include one or more audio Digital Signal Processors (DSPs) 204 f. The audio DSP 204f may include elements for compression/decompression and echo cancellation, and may include other suitable processing elements in other embodiments. In some embodiments, the components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on the same circuit board. In some embodiments, some or all of the constituent components of the baseband circuitry 204 and the application circuitry 202 may be implemented together, for example, on a system on a chip (SOC).

In some embodiments, the baseband circuitry 204 may provide communications compatible with one or more radio technologies. For example, in some embodiments, baseband circuitry 204 may support communication with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) or other Wireless Metropolitan Area Network (WMAN), Wireless Local Area Network (WLAN), Wireless Personal Area Network (WPAN). Embodiments in which the baseband circuitry 204 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

The RF circuitry 206 may enable communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 206 may include switches, filters, amplifiers, and the like to facilitate communication with the wireless network. RF circuitry 206 may include a receive signal path that may include circuitry to down-convert RF signals received from FEM circuitry 208 and provide baseband signals to baseband circuitry 204. RF circuitry 206 may also include a transmit signal path, which may include circuitry to up-convert baseband signals provided by baseband circuitry 204 and provide an RF output signal to FEM circuitry 208 for transmission.

In some embodiments, RF circuitry 206 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 206 may include a mixer circuit 206a, an amplifier circuit 206b, and a filter circuit 206 c. The transmit signal path of the RF circuitry 206 may include filter circuitry 206c and mixer circuitry 206 a. RF circuitry 206 may further include synthesizer circuitry 206d for synthesizing the frequencies used by mixer circuitry 206a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuit 206a of the receive signal path may be configured to: the RF signal received from the FEM circuitry 208 is downconverted based on the synthesized frequency provided by the synthesizer circuitry 206 d. The amplifier circuit 206b may be configured to: the downconverted signal is amplified, and the filter circuit 206c may be a Low Pass Filter (LPF) or a Band Pass Filter (BPF) configured to: unwanted signals are removed from the down-converted signal to generate an output baseband signal. The output baseband signal may be provided to baseband circuitry 204 for further processing. In some embodiments, the output baseband signal may be a zero frequency baseband signal, but this is not required. In some embodiments, mixer circuit 206a of the receive signal path may comprise a passive mixer, although the scope of the embodiments is not limited in this respect. In some embodiments, the mixer circuit 206a of the transmit signal path may be configured to: the input baseband signal is upconverted based on the synthesized frequency provided by the synthesizer circuit 206d to generate an RF output signal for the FEM circuit 208. The baseband signal may be provided by the baseband circuitry 204 and may be filtered by the filter circuitry 206 c. Filter circuit 206c may include a Low Pass Filter (LPF), although the scope of the embodiments is not limited in this respect.

In some embodiments, mixer circuit 206a of the receive signal path and mixer circuit 206a of the transmit signal path may include two or more mixers and may be arranged for quadrature down-conversion or up-conversion, respectively. In some embodiments, the mixer circuit 206a of the receive signal path and the mixer circuit 206a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuit 206a of the receive signal path and the mixer circuit 206a of the transmit signal path may be arranged for direct down-conversion or direct up-conversion, respectively. In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may be configured for superheterodyne operation.

In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In these alternative embodiments, RF circuitry 206 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and baseband circuitry 204 may include a digital baseband interface to communicate with RF circuitry 206. In some dual-mode embodiments, separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

In some embodiments, the synthesizer circuit 206d may be a fractional-N synthesizer or a fractional-N/N +1 synthesizer, although the scope of the embodiments is not so limited as other types of frequency synthesizers may be suitable. For example, the synthesizer circuit 206d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase locked loop with a frequency divider. The synthesizer circuit 206d may be configured to: the output frequency used by the mixer circuit 206a of the RF circuit 206 is synthesized based on the frequency input and the divider control input. In some embodiments, the synthesizer circuit 206d may be a fractional N/N +1 synthesizer. In some embodiments, the frequency input may be provided by a Voltage Controlled Oscillator (VCO), but this is not required. The divider control input may be provided by the baseband circuitry 204 or the application processor 202, depending on the desired output frequency. In some embodiments, the divider control input (e.g., N) may be determined from a look-up table based on the channel indicated by the application processor 202.

Synthesizer circuit 206d of RF circuit 206 may include dividers, Delay Locked Loops (DLLs), multiplexers, and phase accumulators. In some embodiments, the divider may be a dual-mode divider (DMD) and the phase accumulator may be a Digital Phase Accumulator (DPA). In some embodiments, the DMD may be configured to: the input signal is divided by N or N +1 (e.g., based on a carry) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In these embodiments, the delay elements may be configured to decompose the VCO period into Nd equal phase groups, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

In some embodiments, the synthesizer circuit 206d may be configured to: a carrier frequency is generated as the output frequency, while in other embodiments the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with a quadrature generator and divider circuit to generate a plurality of signals at the carrier frequency having a plurality of different phases relative to each other. In some embodiments, the output frequency may be the LO frequency (f)_LO). In some embodiments, the RF circuitry 206 may include an IQ/polar converter.

FEM circuitry 208 may include a receive signal path, which may include circuitry configured to operate on RF signals received from one or more of antennas 210A-D, amplify the received signals, and provide amplified versions of the received signals to RF circuitry 206 for further processing. The FEM circuitry 208 may further include a transmit signal path, which may include circuitry configured to amplify signals provided by the RF circuitry 206 for transmission by one or more of the one or more antennas 210A-D.

In some embodiments, FEM circuitry 208 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include a Low Noise Amplifier (LNA) to amplify the received RF signal and provide the amplified received RF signal as an output (e.g., to RF circuitry 206). The transmit signal path of the FEM circuitry 208 may include: a Power Amplifier (PA) to amplify an input RF signal (e.g., provided by RF circuitry 206); and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 210). In some embodiments, the UE 200 may include additional elements, such as memory/storage, a display, a camera, sensors, or an input/output (I/O) interface.

Fig. 3 is a functional diagram of an evolved node b (enb) according to some embodiments. It should be noted that in some embodiments, eNB 300 may be a fixed, non-mobile device. The eNB 300 may be suitable for use as the eNB 104 depicted in fig. 1. The components of eNB 300 may be included in a single device or multiple devices. The eNB 300 may include physical layer circuitry 302 and a transceiver 305, one or both of which may use one or more antennas 301A-B to enable transmission and reception of signals with the UE 200, other enbs, other UEs, or other devices. As an example, the physical layer circuitry 302 may perform various encoding and decoding functions, which may include forming baseband signals for transmission and decoding received signals. For example, the physical layer circuitry 302 may include LDPC encoder/decoder functionality, optionally accompanied by other techniques, such as block codes, convolutional codes, turbo codes, etc., which may be used to support legacy protocols. Embodiments of modulation/demodulation and encoder/decoder functions are not limited to these examples, and other suitable functions may be included in other embodiments. As another example, transceiver 305 may perform various transmit and receive functions, such as conversion of signals between the baseband range and the Radio Frequency (RF) range. Thus, the physical layer circuit 302 and the transceiver 305 may be separate components or may be part of a combined component. Additionally, some of the functions described in relation to the transmission and reception of signals may be performed by a combination that may include one, any or all of physical layer circuitry 302, transceiver 305, and other components or layers. The eNB 300 may also include medium access control layer (MAC) circuitry 304 to control access to the wireless medium. The eNB 300 may also include processing circuitry 306 and memory 308 arranged to perform the operations described herein. eNB 300 may also include one or more interfaces 310 that may enable communication with other components, including other eNB 104 (fig. 1), components in EPC 120 (fig. 1), or other network components. In addition, interface 310 may enable communication with other components that may not be shown in FIG. 1, including components external to the network. The interface 310 may be wired or wireless or a combination thereof.

Antennas 210A-D, 301A-B may include one or more directional or omnidirectional antennas, including, for example, dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas or other types of antennas suitable for transmission of RF signals. In some multiple-input multiple-output (MIMO) embodiments, the antennas 210A-D, 301A-B may be effectively separated to take advantage of spatial diversity and the different channel characteristics that may be obtained.

In some embodiments, the UE 200 or eNB 300 may be a mobile device and may be a portable wireless communication device such as a Personal Digital Assistant (PDA), a laptop or portable computer with wireless communication capability, a network tablet, a wireless telephone, a smart phone, a wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a wearable device such as a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), or other device that may receive or transmit information wirelessly. In some embodiments, UE 200 or eNB 300 may be configured to operate in accordance with 3GPP standards, although the scope of the embodiments is not limited in this respect. The mobile device or other device in some embodiments may be configured to operate in accordance with other protocols or standards, including IEEE 802.11 or other IEEE standards. In some embodiments, the UE 200, eNB 300, or other device may include one or more of a keypad, a display, a non-volatile memory port, multiple antennas, a graphics processor, an application processor, speakers, and other mobile device elements. The display may be an LCD screen including a touch screen.

Although each of the UE 200 and eNB 300 are illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including Digital Signal Processors (DSPs), or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Radio Frequency Integrated Circuits (RFICs), and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some embodiments, a functional element may refer to one or more processes operating on one or more processing elements.

Embodiments may be implemented in one or a combination of hardware, firmware, and software. Embodiments may also be implemented as instructions stored on a computer-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. A computer-readable storage device may include any non-transitory mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a computer-readable storage device may include Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and other storage devices and media. Some embodiments may include one or more processors and may be configured with instructions stored on a computer-readable storage device.

It should be noted that in some embodiments, the apparatus used by the UE 200 or eNB 300 may include various components of the UE 200 or eNB 300, as shown in fig. 2-3. Thus, the techniques and operations described herein relating to the UE 200 (or 102) may be applicable to the UE's apparatus. Additionally, the techniques and operations described herein relating to eNB 300 (or 104) may be applicable to an apparatus of an eNB.

Some aspects of the embodiments relate to efficient coding schemes for Forward Error Correction (FEC). LTE supports adaptive modulation and coding schemes with fine granularity supported resource allocation sets, Modulation and Coding Schemes (MCS), block sizes (or Transport Block (TB) sizes), and turbo code based rate compatible channel coding with circular buffer rate matching for incremental redundancy hybrid automatic repeat request (IR-HARQ) support. Turbo codes and LDPC codes are two capacity-achieving codes. In some embodiments, the set of supported spectral efficiencies is in the range of 0.1bps/Hz to 7.6bps/Hz (for 256-QAM), with the MCS levels roughly defined to correspond to 1dB steps. This may require rate-compatible channel coding to encode the packet (or TB) at any arbitrary coding rate according to the selected MCS level and define multiple redundancy versions to support HARQ operation.

As an example of the current application of LDPC, 802.11n/11ac LDPC code design is based on a limited set of coding rates and block sizes as shown in Table 1 below. The information block size is tabulated according to a Codeword (CW) length and a coding rate.

TABLE 1

The standard also specifies Physical Layer Convergence Protocol (PLCP) protocol data unit (PPDU) coding rules, including mechanisms for shortening and puncturing, in order to code and transmit packets over available channel resources. In the shortening-based method, packets of smaller size are zero-padded to a desired information block size and encoded with a parity check matrix, and the zero-padding is removed after encoding to achieve an effectively lower encoding rate. In the puncturing-based method, packets are encoded using a parity check matrix, and a part of the parity bits after encoding is punctured, for example, removed (the relative positions of other bits remain unchanged) to improve the effective encoding rate. Rate matching is achieved by shortening the higher rate codes or puncturing the lower rate codes, e.g., by selecting from 4 specified rate matrices, etc.

Both turbo codes and LDPC codes are decoded using iterative decoding techniques. Notably, LDPC codes may provide improvements over Turbo codes in implementation complexity and performance, and are currently considered as potential channel coding candidates in future 3GPP standardization efforts (commonly referred to as 5G standard development).

In general, puncturing and zero padding operations are used in conjunction with LDPC coding in order to support adaptive MCS. This allows the design to support the parity check matrix only for a given set of coding rates and LDPC information block sizes. Other coding rates and block sizes may be supported using puncturing, repetition, or zero padding operations. A limited set of parity check matrices may provide advantages in reducing implementation complexity while also allowing sufficient flexibility to adapt the scheme (similar to LTE turbo codes). Since puncturing (especially of parity bits) in LDPC is known to achieve higher coding rates, any adverse impact on FEC performance due to puncturing should be considered.

Embodiments described herein recognize that selecting a good perforation pattern can provide improved performance with a negligible (or even zero) increase in implementation complexity. Selecting a good puncturing pattern may increase the success rate of the first transmission even in HARQ-based operation, and in turn, achieve fewer retransmissions occurring and increase throughput.

One aspect of the embodiments relates to a solution for predictively/preferentially selecting a puncturing pattern for LDPC parity coding. Technical effects provided by some embodiments include: for a given FEC performance level, the communication data rate is increased, and likewise, for a given data communication rate, the FEC performance is increased. In addition, some embodiments may efficiently support HARQ based operations using LDPC.

According to one type of embodiment, certain parity check bits corresponding to larger column weights are punctured preferentially over parity check bits corresponding to smaller column weights in the LDPC parity check matrix. In a related aspect, a decoder is provided that utilizes a layered decoding scheme for fast and computationally efficient decoding of LDPC codewords.

In an embodiment, an LDPC coding scheme for transmitting digital data is a structured LDPC code based on a shifted identity matrix. Length n of code word is z.n_bAnd the information block k is z k_bAnd the LDPC code with shift size or sub-block size z has a coding rate r-k/n-k_b/n_b. The LDPC encoder sets the information block i ═ i (i)₀,i₁,i₂,...,i_k-1) Coded as a codeword c of size n, where c ═ (c)₀,c₁,...,c_k-1,c_k,...,c_n-1). In systematic coding, the first k bits of a codeword are usually identical to the information bits, i.e. for j 0 to k-1, c_j＝i_jOr c ═ i (i)₀,i₁,...,i_k-1,p₀,...,p_n-k-1). The code word c satisfies the parity check formula H.c^TWhere H is an n-kxn parity check matrix. In this arrangement, typically, the first k columns (or k) of the parity check matrix_b) May be referred to as a systematic column, the remaining n-k columns (or n)_b-k_b) May be referred to as parity columns. For a parity check matrix, each column has a column weight that represents the number of 1's in the column, and each row has a row weight that represents the number of 1's in the row.

FIG. 4 is a diagram of an example parity check matrix, according to an example embodiment. As depicted, the parity check matrix H is comprised of systematic columns 402 and parity columns 404. Each element of the parity check matrix H represents a square sub-matrix P having a size z × z (in the depicted example, z ═ 27)_i. These sub-matrices may be cyclic permutations of identity matrices (i.e., shifted identity matrices), where the numerical values of the elements represent the amount of permutation (where 0 is a non-shifted identity matrix). The elements filled with the value "-" represent empty matrices (i.e., all zeros).

Fig. 5A to 5C show simplified examples of permutated identity matrices used as sub-matrices in a parity check matrix of the type illustrated in fig. 4. As depicted, for convenience of explanation, the permuted identity matrix P is shown for the case where z is 5_i. Obtaining cyclic permutation from a zxz identity matrix by cyclically shifting columns to the right by i elementsMatrix P_i. FIG. 5A shows a cross-section of a silicon-carbon nanotube₀A corresponding non-shifted identity matrix. FIG. 5B shows a cross-point with P₂Corresponding to a cyclic shift of 2. FIG. 5C shows a cross-point with P₄Corresponding to a cyclic shift of 4.

In an embodiment, the coding rate of 8/9 is achieved for various codeword sizes defined for different shift sizes z. In various examples, the supported shift size z may be 12, 24, 36, 48, 60, 72, 84, and 96. Assume a size of 4 x 36 (i.e., n)_b36, and k_b32), which correspond to codeword block sizes zx 36-432, 864, 1296, 1728, 2160, 2592, 3024, and 3456, respectively.

FIG. 6 illustrates a system for performing LDPC encoding and optimization according to some embodiments. As depicted, the system may be implemented using the baseband processor 204 of the UE or the physical layer circuitry 302 of the eNB. The system includes an LDPC encoder 602 and a puncturer 604. According to various embodiments, LDPC encoder 602 and puncturer 604 may be implemented using hardware circuitry, or as a combination of hardware circuitry and software/firmware instructions stored on a tangible, non-transitory computer-readable medium. In the latter case, the instructions, when executed on the processor circuit, cause the processor circuit to perform data transformations as will be described in greater detail below.

Fig. 7 is a diagram illustrating an example of the operation of the system of fig. 6, according to some embodiments. As depicted, the input to LDPC encoder 602 is information block S702 (which contains the information bits to be transmitted and, optionally, additional CRC bits). LDPC encoder 602 also reads parity check matrix H704. The LDPC encoder 602 is configured to generate LDPC codewords at a set encoding rate (e.g., r ═ k/n, which represents the ratio of information block size to total block size). LDPC encoder 602 produces codeword 706 comprising systematic portion S indicated at 706A and parity portion P indicated at 706B.

The codeword 706 is input to a puncturer 604 that operates to remove (i.e., puncture) a portion of the parity portion 706B to increase the coding rate r. The output of the puncturer 604 is a punctured codeword 708 comprising the systematic portion S706A and the non-punctured portion of the parity portion 708B. Parity portion 708B has a gap X in the selected bit position indicated at 708C. Although the data bits are omitted in the punctured parity portion 708B, their bit positions are labeled in a manner such that the omitted parity portion of the space X708C can be reconstructed at the receiver.

In an embodiment, the puncturer 604 preferentially selects the puncturing pattern based on the structure of the parity check matrix H and based on the decoding algorithm to be used at the receiver (e.g., scheduling in hierarchical belief propagation). In general, when a particular parity bit is punctured, a decoder at the receiver may assume that the corresponding bit is erased, and it may attempt to decode the information block by helping to recover the erased bits with the parity node corresponding to each erased bit. The parity check nodes may be represented as rows of an H matrix.

According to a related embodiment, a biased choice for the puncturing pattern is to select bits corresponding to those parity bits participating in a greater number of parity formulas to puncture than other parity bits. In this embodiment, the parity bits corresponding to the relatively large weight parity columns tend to be preferentially selected for puncturing and therefore have a lower priority when selected for transmission than the parity bits corresponding to the relatively small weight parity columns. In this context, a relatively more weighted column has parity bits associated with a relatively greater number of parity nodes, and a relatively less weighted column has parity bits associated with a relatively less number of parity nodes. Notably, the relatively more weighted columns and the relatively less weighted columns have greater and lesser weights, respectively, relative to each other. Thus, the terms "larger" and "smaller" are comparative rather than absolute terms.

Generally, LDPC decoders are based on a hierarchical belief propagation algorithm, in which one or more rows of a structured parity check matrix are processed simultaneously. In a related embodiment, to receive the punctured LDPC code, the ordering of rows in the decoder may take into account the puncturing scheme. For example, the ordering of the rows may be such that punctured bits are recovered as early as possible in the decoding process, which tends to help recover the punctured bit values.

Fig. 8 is a flow diagram illustrating a process for puncturing parity bits, in accordance with some embodiments. This process may be performed by, for example, the puncturer 604. At 802, a number of bits to be punctured is determined. This determination may be a function of the encoding rate at which the encoder 602 is configured and the desired encoding rate. Puncturing reduces the overall size of the LDPC code block, resulting in a reduction in the effective total length to be transmitted over the communication channel. At 804, puncturer 604 initializes a list of null elements having a length equal to the determined number of parity bits to be punctured. Operation 806 then fills 812 the list with punctured bits.

To illustrate the puncturing process according to some embodiments, the term "effective column weight" of a parity bit is defined as the number of parity nodes to which the parity bit is connected that do not contain other punctured bits that have not yet been recovered. At 806, puncturer 604 searches for the parity bit with the highest effective column weight, and if that bit is punctured, it can be restored immediately at the current iteration, independent of other punctured bits that have not yet been restored. As described above, in embodiments, parity bits having a greater effective column weight and thus participating in a greater number of parity formulas are preferentially selected for puncturing. Punctured bits that have been recovered from a previous iteration are considered non-punctured bits for the current iteration. At 808, all bits found as a result of the search operation at 806 are marked. At 810, the list is populated with the found bits to replace the initial null value. In one embodiment, the list is ordered such that the parity bit with the largest active column weight is listed first, then the second largest bit with the active column weight, and so on. If two or more parity bits are equal (tipped), their ordering is chosen arbitrarily.

Decision operation 812 determines whether the list is full and if not, the process loops back to operation 806 to continue searching for the appropriate parity bits to be punctured. Otherwise, if the bit list is complete, processing proceeds to 814 where puncturer 604 applies column permutations to the systematic bits and parity bits to prioritize the non-punctured parity bits. At 816, the systematic bits and parity bits are concatenated to form a circular buffer to be used for the transport block. At 818, bits are read from the circular buffer and passed to the transceiver for transmission over the wireless medium.

In a related embodiment, incremental redundancy hybrid ARQ operation (IR-HARQ) is supported by using a circular buffer and column replacement. The permutation pi 1 is applied to the parity bits to reorder the bits that need to be punctured in the order they are placed at the end. The permutation pi 0 is applied to the systematic bits.

Fig. 9 is a diagram illustrating a permutation operation for systematic bits and parity bits, in accordance with some embodiments. For ease of illustration, only two redundancy version blocks, a first transmission 902 and a second transmission 904, are shown. S and P indicated at 906 and 908, respectively, represent systematic bits and parity bits. Permute operations π 0910 and π 1912 are applied to S and P as shown to generate permuted systematic bits S 'at 914 and permuted parity bits P' at 916. The concatenation of S '914 and P'916 is a data structure that serves as a circular buffer 918 upon which redundancy versions are defined.

For each transfer, the bits selected for transfer may be read in a circular buffer starting from the starting point and continuing the bit reading sequentially until the desired number of bits are read out. If the end of the circular buffer is reached, the reading is resumed from the beginning of the circular buffer. In the depicted example, the first transmission 902 from the circular buffer 918 begins at bit position RV 0. The second transmission 904 begins at bit position RV 1. Here, the abbreviation RV denotes a redundancy version that can be used to support HARQ operation. For Chase combining, only one RV may be sufficient. For IR-based HARQ, multiple RVs may be defined.

FIG. 10 illustrates a system for performing LDPC receive side decoding according to some embodiments. As depicted, the system may be implemented using the baseband processor 204 of the UE or the physical layer circuitry 302 of the eNB. The system includes HARQ memory 1002, soft combining unit 1004, H matrix determination unit 1006, inverse permutation computer 1008, and decoder 1010. According to various embodiments, components of the system may be implemented using hardware circuitry, or as a combination of hardware circuitry and software/firmware instructions stored on a tangible, non-transitory computer-readable medium. In the latter case, the instructions, when executed on the processor circuit, cause the processor circuit to perform data transformations as will be described in greater detail below.

Input 1012 to the system includes received bits (in the form of log-likelihood ratios (LLRs)), and soft combining unit 1004 soft combines the received bits with any previous LLRs stored in HARQ memory 1002. Inverse permutation computer 1008 applies inverse permutation pi 0^-1And pi 1^-1To prepare the result for LDPC decoding. The H matrix determination unit operates by considering information about the received blocks and their LLRs (e.g., channel LLRs and LLRs stored in the HARQ memory) available at the decoder to determine an appropriate parity check matrix H for decoding by decoder 1010 to produce information output 1014.

Fig. 11 is a diagram illustrating an example of the operation of the system of fig. 10 according to an embodiment. First transmission 902 and second transmission 904 are received as LLRs and combined by soft combining unit 1004. The results are stored in a circular buffer 1118 implemented in the HARQ memory 1002. The received data at this time are permuted bits 914 and 916. Inverse permutation operations are performed 1102 and 1104 on the systematic bits and parity bits, respectively, to produce reordered LLR values for a codeword comprised of systematic bits 1106 and recovered parity bits 1108. The determined H matrix is then used to decode the codeword.

FIG. 12 is a diagram illustrating operations in a layered iterative decoding scheme, according to some embodiments. As depicted, the received LDPC codeword includes LLR values for information bits S1202, parity bits P1204, and punctured parity bit positions 1206. Hierarchical decoding ordering may be performed in LDPC decoder 1010 to further improve performance. The layered decoding is performed in accordance with the punctured parity bit ordering in the list. The row-by-row permutation matrix pi 21208 may reorder the sequence of check nodes such that all check nodes connected to the first punctured bit in the list are processed first (e.g., have a higher priority), then check nodes connected to the second punctured node, and so on. Such ordering may facilitate recovery of punctured bits to some extent following the puncturing order. This operation is advantageous because recovery of punctured bits in early iterations can be achieved with relatively high confidence. Subsequent punctured parity bit recovery is assisted by recovery of the previous parity bits. As a result, faster and more computationally efficient LDPC decode convergence may be achieved.

As an example embodiment, in a WiFi-like matrix, the parity columns may have a first weight (weight 3) or a second weight (weight 2). The permutation pi 1 is used to permute the parity portion so that after the permutation, the punctured parity bits are placed at the end. The permutation pi 0 used to permute the systematic bits may be an identity (i.e., invariant). In a related example, the permutation pi 0 used to permute the systematic bits may be another permutation for additional diversity.

As another example, the parity columns may have a first weight (weight 3) or a second weight (weight 2), or more generally, columns having multiple weights. For example, the permutation π 1 used to permute the parity portion causes punctured parity bits to appear later in the circular buffer relative to non-punctured bits after the permutation. The permutation pi 0 used to permute the systematic bits may be an identity. For additional diversity, the permutation pi 0 used to permute the systematic bits may be another permutation.

As an illustrative example, with reference to fig. 4, the puncturing pattern selection and layered decoding process will be described. In this example, the 802.11 n-type LDPC parity check matrix H has an encoding rate of 5/6, a block length of 648 bits, and a sub-block size of z 27 bits. The parity portion 404 is the last four columns of H, containing 108 single columns and 108 rows, 4 x 27.

To increase the coding rate from 5/6 to 0.9, 48 bits need to be punctured given n 648 and information bit length k 540. First, a list is generated containing 48 NULL elements. Next, note that the column weight of the first z columns is 3. If all 27 corresponding parity bits are punctured, they can be recovered without relying on the remaining 48-27-21 punctured bit positions. Check nodes connected to the 27 punctured bits and not connected to the remaining 21 punctured bits are identifiable. Columns 1 through 27 are added in a punch ordering in the list, which now contains {1, 2.., 27, NULL. }.

Since the first 27 bits can be recovered first, the remaining 21 bits punctured can be randomly selected from all other columns since they all have a column weight of 2, which is the second largest weight after the removal of the column with weight 3. The list is now fully populated and the selection of the punctured bits is complete, with the list including {1, 2.

Next, a column permutation of π 1 is applied which permutes the punctured bits to the end of the parity block and moves all the non-punctured bits to the beginning of the parity block. After the permutation, the parity bit sequence has an index order of { 49., 108, 1., 48 }. Parity bits 49 through 108 are transmitted along with the information bits as part of the codeword shortened by puncturing.

At the LDPC decoder, the LDPC codeword may be decoded using standard belief propagation techniques, e.g., using a non-layered decoding algorithm.

In embodiments using a layered decoding algorithm, the order in which the layers are decoded may be determined as follows. To sequentially recover the punctured bits in the list, at the LDPC decoder side, after reverse permuting pi 1 to recover the original codeword sequence (including adding back the punctured bits), layered decoding may begin with check nodes in the order {82, 83.. once, 108,55,56, …,81,1,2,. once, 27,28, 29.. once, 54} or {55,56,. once, 81,82,83,. once, 108,1,2,. once, 27,28,29,. once, 54} in order to decode the first 27 punctured bits. This hierarchical decoding ordering is achieved by permuting pi 2. One layer may include a single check node or multiple check nodes. In the 802.11n case, since there are no two or more check nodes within the zxz submatrix connected to the same LDPC coded bits, all check nodes within the submatrix may be updated simultaneously. In this case, one layer includes z check nodes within the submatrix.

Additional notes and examples:

example 1 is an apparatus of a communication device configured to encode a message for transmission, the apparatus comprising: a memory; and processing circuitry for controlling the apparatus to: encoding a set of information bits to be transmitted according to a parity block to produce a first codeword, the first codeword representing a set of parity nodes based on the set of information bits and based on a set of parity bits, the set of parity bits including parity bits associated with a relatively large number of parity nodes and parity bits associated with a relatively small number of parity nodes; selecting from the set of parity bits selected parity bits to be de-prioritized from the first codeword based on a selection criterion that de-prioritizes those parity bits associated with a relatively large number of parity nodes; and generating an output data set for transmission based on the first codeword, wherein selected parity bits are of reduced priority.

In example 2, the subject matter of example 1 optionally includes wherein the parity block is represented in memory as a parity check matrix data structure arranged as a set of rows and columns.

In example 3, the subject matter of example 2 optionally includes wherein each column of the parity check matrix has a valid column weight defined as a number of parity check nodes to which the corresponding parity check bit is connected that do not contain other not yet recovered reduced priority bits.

In example 4, the subject matter of any one or more of examples 1-3 optionally includes wherein the first codeword is represented in memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

In example 5, the subject matter of example 4 optionally includes wherein the parity bit column having the largest number of non-zero elements has at least 3 non-zero elements.

In example 6, the subject matter of any one or more of examples 4 to 5 optionally includes wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

In example 7, the subject matter of any one or more of examples 1 to 6 can optionally include wherein the de-prioritized selected parity bits are omitted from the output data set to be transmitted.

In example 8, the subject matter of any one or more of examples 1 to 7 optionally includes wherein the de-prioritized selected parity bits are permuted to least significant positions within the output data set to be transmitted.

In example 9, the subject matter of any one or more of examples 1 to 8 optionally includes wherein the first codeword comprises at least a portion of the set of information bits as a systematic portion concatenated with a parity portion of the bits.

In example 10, the subject matter of any one or more of examples 1 to 9 optionally includes, wherein the first codeword comprises a first portion comprising information bits and a second portion comprising parity bits, and wherein the processing circuitry is further to control the apparatus to: calculating a first permutation of the information bits to produce a first permutation result and calculating a second permutation of the set of parity bits to obtain a second permutation result; and concatenating the first permutation result with the second permutation result to produce a circular buffer from which the output data set is produced.

In example 11, the subject matter of example 10 can optionally include, wherein the second permutation result comprises a bit ordering having a start and an end, wherein the de-prioritized selected parity bits are at the end.

In example 12, the subject matter of any one or more of examples 10 to 11 optionally includes, wherein the output data set is generated by the circular buffer based on a plurality of read iterations, wherein different read iterations have different starting points within the circular buffer based on the redundancy version.

In example 13, the subject matter of any one or more of examples 1 to 12 optionally includes, wherein the apparatus comprises a baseband processor.

In example 14, the subject matter of any one or more of examples 1-13 optionally includes, wherein the apparatus comprises transceiver circuitry coupled to an antenna.

In example 15, the subject matter of any one or more of examples 1 to 14 optionally includes, wherein the apparatus comprises an e-Node B device.

In example 16, the subject matter of any one or more of examples 1 to 15 optionally includes, wherein the apparatus comprises a User Equipment (UE) device.

Example 17 is an apparatus of a communication device configured to decode an encoded message, the apparatus comprising: a memory; and processing circuitry for controlling the apparatus to: accessing a received messaging, the messaging comprising a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity bits; calculating a first inverse permutation of the first permutated portion and a second inverse permutation of the second permutated portion to produce a codeword comprising an un-permutated first portion representing information bits and an un-permutated second portion representing parity bits; and decoding the codeword using the low density parity check matrix, the codeword having been previously encoded as a set of parity check nodes based on the set of information bits and based on a set of parity check bits, the set of parity check bits including parity check bits associated with a relatively large number of parity check nodes and parity check bits associated with a relatively small number of parity check nodes, some of the parity check bits having been de-prioritized from the codeword based on a selection criterion that de-prioritizes those parity check bits associated with the relatively large number of parity check nodes.

In example 18, the subject matter of example 17 can optionally include wherein the received messaging comprises a set of log likelihood ratios.

In example 19, the subject matter of any one or more of examples 17 to 18 optionally includes, wherein the received messaging comprises a first transmission and a second transmission.

In example 20, the subject matter of any one or more of examples 17 to 19 optionally includes, wherein the received messaging comprises circularly buffered data.

In example 21, the subject matter of any one or more of examples 17 to 20 optionally includes wherein the codeword is represented in memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

In example 22, the subject matter of example 21 can optionally include wherein the parity bit column having the largest number of non-zero elements has at least 3 non-zero elements.

In example 23, the subject matter of any one or more of examples 21 to 22 optionally includes wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

In example 24, the subject matter of any one or more of examples 17 to 23 optionally includes wherein the reduced priority parity bits are omitted from the messaging.

In example 25, the subject matter of any one or more of examples 17 to 24 optionally includes wherein the reduced priority parity bits are permuted to least significant positions within the messaging.

In example 26, the subject matter of any one or more of examples 17 to 25 optionally includes wherein the codeword comprises at least a portion of the set of information bits as a systematic portion concatenated with a parity portion of the bits.

In example 27, the subject matter of any one or more of examples 17 to 26 optionally includes, wherein the apparatus comprises a baseband processor.

In example 28, the subject matter of any one or more of examples 17 to 27 optionally includes, wherein the apparatus comprises transceiver circuitry coupled to an antenna.

In example 29, the subject matter of any one or more of examples 17 to 28 may optionally include, wherein the apparatus comprises an e-Node B device.

In example 30, the subject matter of any one or more of examples 17 to 29 optionally includes, wherein the apparatus comprises a User Equipment (UE) device.

Example 31 is a computer-readable medium comprising instructions that, when executed on a processing device, cause the device to: encoding a set of information bits to be transmitted according to a parity block to produce a first codeword representing a set of parity nodes based on the set of information bits and based on a set of parity bits, the set of parity bits including parity bits associated with a relatively large number of parity nodes and parity bits associated with a relatively small number of parity nodes; selecting parity bits to be de-prioritized from the first codeword based on selection criteria that de-prioritize those parity bits associated with a relatively large number of parity nodes; and generating an output data set for transmission based on the first codeword, wherein selected parity bits are of reduced priority.

In example 32, the subject matter of example 31 optionally includes wherein the parity blocks are represented as a parity check matrix data structure arranged as a set of rows and columns.

In example 33, the subject matter of example 32 can optionally include wherein each column of the parity check matrix has a valid column weight defined as a number of parity check nodes to which the corresponding parity check bit is connected that do not contain other not yet recovered reduced priority bits.

In example 34, the subject matter of any one or more of examples 31 to 33 optionally includes wherein the first codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

In example 35, the subject matter of example 34 can optionally include wherein the parity bit column having the largest number of non-zero elements has at least 3 non-zero elements.

In example 36, the subject matter of any one or more of examples 34 to 35 optionally includes wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

In example 37, the subject matter of any one or more of examples 31 to 36 can optionally include wherein the de-prioritized selected parity bits are omitted from the output data set to be transmitted.

In example 38, the subject matter of any one or more of examples 31 to 37 optionally includes wherein the de-prioritized selected parity bits are permuted to least significant positions within the output data set to be transmitted.

In example 39, the subject matter of any one or more of examples 31 to 38 optionally includes wherein the first codeword comprises at least a portion of the set of information bits as a systematic portion concatenated with a parity portion of the bits.

In example 40, the subject matter of any one or more of examples 31 to 39 optionally includes wherein the first codeword comprises a first portion comprising information bits and a second portion comprising parity bits, and wherein the instructions further control the apparatus to: calculating a first permutation of the information bits to produce a first permutation result and calculating a second permutation of the set of parity bits to obtain a second permutation result; and concatenating the first permutation result with the second permutation result to produce a circular buffer from which the output data set is produced.

In example 41, the subject matter of example 40 can optionally include, wherein the second permutation result comprises a bit ordering having a start and an end, wherein the de-prioritized selected parity bits are at the end.

In example 42, the subject matter of any one or more of examples 40-41 optionally includes, wherein the output data set is generated by the circular buffer based on a plurality of read iterations, wherein different read iterations have different starting points within the circular buffer based on the redundancy version.

Example 43 is a computer-readable medium comprising instructions that, when executed on a processing device, cause the device to: accessing a received messaging, the messaging comprising a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity bits; calculating a first inverse permutation of the first permutated portion and a second inverse permutation of the second permutated portion to produce a codeword comprising an un-permutated first portion representing information bits and an un-permutated second portion representing parity bits; and decoding the codeword using the low density parity check matrix, the codeword having been previously encoded as a set of parity check nodes based on the set of information bits and based on a set of parity check bits, the set of parity check bits including parity check bits associated with a relatively large number of parity check nodes and parity check bits associated with a relatively small number of parity check nodes, some of the parity check bits having been de-prioritized from the codeword based on a selection criterion that de-prioritizes those parity check bits associated with the relatively large number of parity check nodes.

In example 44, the subject matter of example 43 can optionally include wherein the received messaging comprises a set of log likelihood ratios.

In example 45, the subject matter of any one or more of examples 43 to 44 optionally includes wherein the received messaging comprises a first transmission and a second transmission.

In example 46, the subject matter of any one or more of examples 43 to 45 optionally includes, wherein the received messaging comprises circularly buffered data.

In example 47, the subject matter of any one or more of examples 43 to 46 optionally includes wherein the codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

In example 48, the subject matter of example 47 can optionally include wherein the parity bit column having the largest number of non-zero elements has at least 3 non-zero elements.

In example 49, the subject matter of any one or more of examples 47-48 optionally includes wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

In example 50, the subject matter of any one or more of examples 43 to 49 optionally includes wherein the reduced priority parity bits are omitted from the messaging.

In example 51, the subject matter of any one or more of examples 43 to 50 optionally includes, wherein the reduced priority parity bits are permuted to least significant positions within the messaging.

In example 52, the subject matter of any one or more of examples 43 to 51 optionally includes wherein the codeword comprises at least a portion of the set of information bits as a systematic portion concatenated with a parity portion of the bits.

Example 53 is a system to encode a message for transmission, the system comprising: means for encoding a set of information bits to be transmitted according to a parity block to produce a first codeword representing a set of parity nodes based on the set of information bits and based on a set of parity bits, the set of parity bits including parity bits associated with a relatively large number of parity nodes and parity bits associated with a relatively small number of parity nodes; means for selecting parity bits to be de-prioritized from the first codeword based on a selection criterion that de-prioritizes those parity bits associated with a relatively larger number of parity nodes; and means for generating an output data set for transmission based on the first codeword, wherein the selected parity bits are of reduced priority.

In example 54, the subject matter of example 53 optionally includes wherein the parity blocks are represented as a parity check matrix data structure arranged as a set of rows and columns.

In example 55, the subject matter of example 54 optionally includes wherein each column of the parity check matrix has a valid column weight defined as a number of parity check nodes to which the corresponding parity check bit is connected that do not contain other not yet recovered reduced priority bits.

In example 56, the subject matter of any one or more of examples 53-55 optionally includes wherein the first codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

In example 57, the subject matter of example 56 can optionally include wherein the parity bit column having the largest number of non-zero elements has at least 3 non-zero elements.

In example 58, the subject matter of any one or more of examples 56 to 57 optionally includes wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

In example 59, the subject matter of any one or more of examples 53-58 optionally includes wherein the de-prioritized selected parity bits are omitted from the output data set to be transmitted.

In example 60, the subject matter of any one or more of examples 53-59 optionally includes wherein the de-prioritized selected parity bits are permuted to least significant positions within the output data set to be transmitted.

In example 61, the subject matter of any one or more of examples 53-60 optionally includes wherein the first codeword comprises at least a portion of the set of information bits as a systematic portion concatenated with a parity portion of the bits.

In example 62, the subject matter of any one or more of examples 53 to 61 optionally includes, wherein the first codeword comprises a first portion comprising information bits and a second portion comprising parity bits, and wherein the means for encoding comprises: the apparatus includes means for computing a first permutation of information bits to produce a first permutation result, means for computing a second permutation of the set of parity bits to obtain a second permutation result, and means for concatenating the first permutation result with the second permutation result to produce a circular buffer from which an output data set is produced.

In example 63, the subject matter of example 62 can optionally include, wherein the second permutation result comprises a bit ordering having a start and an end, wherein the de-prioritized selected parity bits are at the end.

In example 64, the subject matter of any one or more of examples 62 to 63 optionally includes wherein the output data set is generated by the circular buffer based on a plurality of read iterations, wherein different read iterations have different starting points within the circular buffer based on the redundancy version.

In example 65, the subject matter of any one or more of examples 53-64 optionally includes, wherein the system includes a baseband processor.

In example 66, the subject matter of any one or more of examples 53-65 optionally includes, wherein the system comprises transceiver circuitry coupled to an antenna.

In example 67, the subject matter of any one or more of examples 53-66 can optionally include, wherein the system includes the e-Node B device.

In example 68, the subject matter of any one or more of examples 53 to 67 optionally includes, wherein the system comprises a User Equipment (UE) device.

Example 69 is a system of communication devices configured to receive and decode an encoded message, the system comprising: means for accessing a received messaging, the messaging comprising a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity bits; means for calculating a first inverse permutation of the first permutated portion and a second inverse permutation of the second permutated portion to produce a codeword comprising an un-permutated first portion representing information bits and an un-permutated second portion representing parity bits; and means for decoding the codeword using the low density parity check matrix, the codeword having been previously encoded into a set of parity check nodes based on the set of information bits and based on a set of parity check bits, the set of parity check bits including parity check bits associated with a relatively large number of parity check nodes and parity check bits associated with a relatively small number of parity check nodes, some of the parity check bits having been de-prioritized from the codeword based on a selection criterion that de-prioritizes those parity check bits associated with the relatively large number of parity check nodes.

In example 70, the subject matter of example 69 optionally includes wherein the received messaging comprises a set of log likelihood ratios.

In example 71, the subject matter of any one or more of examples 69 to 70 optionally includes wherein the received messaging comprises a first transmission and a second transmission.

In example 72, the subject matter of any one or more of examples 69 to 71 optionally includes, wherein the received messaging comprises circularly buffered data.

In example 73, the subject matter of any one or more of examples 69 to 72 optionally includes wherein the codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

In example 74, the subject matter of example 73 optionally includes wherein the parity bit column having the largest number of non-zero elements has at least 3 non-zero elements.

In example 75, the subject matter of any one or more of examples 73 to 74 optionally includes wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

In example 76, the subject matter of any one or more of examples 69 to 75 optionally includes wherein the reduced priority parity bits are omitted from the messaging.

In example 77, the subject matter of any one or more of examples 69 to 76 optionally includes wherein the reduced priority parity bits are permuted to least significant positions within the messaging.

In example 78, the subject matter of any one or more of examples 69 to 77 optionally includes wherein the codeword comprises at least a portion of the set of information bits as a systematic portion concatenated with a parity portion of the bits.

In example 79, the subject matter of any one or more of examples 69 to 78 optionally includes wherein the system includes a baseband processor.

In example 80, the subject matter of any one or more of examples 69 to 79 optionally includes wherein the system comprises transceiver circuitry coupled to an antenna.

In example 81, the subject matter of any one or more of examples 69 to 80 can optionally include wherein the system includes an e-Node B device.

In example 82, the subject matter of any one or more of examples 69 to 81 optionally includes wherein the system comprises a User Equipment (UE) device.

The foregoing detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments that can be practiced. These embodiments are also referred to herein as "examples. Such examples may include elements other than those shown or described. However, examples including the elements shown or described are also contemplated. Moreover, it is also contemplated to use examples of any combination or permutation of those elements (or one or more aspects thereof) shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

The publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. The usage in the incorporated references is supplementary to the usage in this document if the usage between this document and those incorporated by reference is inconsistent; for irreconcilable inconsistencies, the usage in this document controls.

In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, regardless of any other instances or usages of "at least one" or "one or more. Unless otherwise indicated, in this document, the term "or" is used to refer to a non-exclusive "or" such that "a or B" includes "a, but not B", "B, but not a" and "a and B". In the appended claims, the terms "including" and "in which" are used as the plain-english equivalents of the respective terms "comprising" and "wherein". Furthermore, in the claims that follow, the terms "comprise" and "comprise" are open-ended; that is, a system, device, article, or process that includes an element other than those listed after such a word in a claim is still considered to be within the scope of that claim. Furthermore, in the claims that follow, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to imply a numerical order of their objects.

The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with other examples. For example, other embodiments may be used by those skilled in the art upon reading the above description. The Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the following understanding: it is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to streamline the disclosure. However, the claims may not set forth every feature disclosed herein because embodiments may feature a subset of the features. Moreover, embodiments may include fewer features than those disclosed in the specific examples. Thus, the following claims are hereby incorporated into the detailed description, with claims standing on their own as separate embodiments. The scope of the embodiments disclosed herein should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (40)

1. An apparatus of a communication device configured to encode a message for transmission, the apparatus comprising:

a memory; and

processing circuitry to control the apparatus to:

encoding a set of information bits to be transmitted in accordance with a parity block to produce a first codeword representing a set of parity nodes based on the set of information bits and based on a set of parity bits, the set of parity bits including parity bits associated with a relatively large number of parity nodes and parity bits associated with a relatively small number of parity nodes;

selecting selected parity bits from the set of parity bits to be de-prioritized from the first codeword based on a selection criterion that de-prioritizes those parity bits associated with the relatively larger number of parity nodes; and

generating an output data set for transmission based on the first codeword, wherein the selected parity bits are of reduced priority.

2. The apparatus of claim 1, wherein the parity block is represented in the memory as a parity check matrix data structure arranged as a set of rows and columns.

3. The apparatus of claim 2, wherein each column of the parity check matrix has an active column weight defined as a number of parity check nodes to which the corresponding parity check bit is connected that do not contain other, yet unrecovered, reduced priority bits.

4. The apparatus of claim 1, wherein a codeword is represented in the memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column with a largest number of non-zero elements of all parity bit columns.

5. The apparatus of claim 4, wherein a parity bit column having a maximum number of non-zero elements has at least 3 non-zero elements.

6. The apparatus of claim 4, wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

7. The apparatus of any of claims 1 to 3, wherein the reduced priority parity bits are omitted from the messaging.

8. The apparatus of any of claims 1 to 3, wherein the reduced priority parity bits are permuted to least significant positions within the messaging.

9. The apparatus of any of claims 1 to 3, wherein a codeword contains at least a portion of the set of information bits as a systematic part concatenated with a parity part of the bits.

10. The apparatus of any of claims 1-3, wherein the apparatus comprises a baseband processor.

11. The apparatus of any of claims 1-3, wherein the apparatus comprises a transceiver circuit coupled to an antenna.

12. The apparatus of any of claims 1-3, wherein the apparatus comprises a base station device.

13. The apparatus of any of claims 1-3, wherein the apparatus comprises a User Equipment (UE) device.

14. An apparatus of a communication device configured to decode an encoded message, the apparatus comprising:

a memory; and

processing circuitry to control the apparatus to:

accessing a received messaging comprising a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity bits;

calculating a first inverse permutation of the first permutated portion and a second inverse permutation of the second permutated portion to produce a codeword comprising a first portion representing the information bits and a second portion representing the parity bits; and

decoding the codeword using a low density parity check matrix, the codeword having been previously encoded as a set of parity check nodes based on the set of information bits and based on a set of parity check bits, the set of parity check bits including parity check bits associated with a relatively large number of parity check nodes and parity check bits associated with a relatively small number of parity check nodes, some of the parity check bits having been de-prioritized from the codeword based on a selection criterion that de-prioritizes those parity check bits associated with the relatively large number of parity check nodes.

15. The apparatus of claim 14, wherein the received messaging comprises a set of log-likelihood ratios.

16. The apparatus of claim 14, wherein the received messaging comprises a first transmission and a second transmission.

17. The apparatus of claim 14, wherein the received messaging comprises circularly buffered data.

18. The apparatus of claim 14, wherein the codeword is represented in the memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column having a largest number of non-zero elements of all parity bit columns.

19. The apparatus of claim 18, wherein a parity bit column having a maximum number of non-zero elements has at least 3 non-zero elements.

20. The apparatus of claim 18, wherein the parity bit column having the largest number of non-zero elements has an odd number of non-zero elements.

21. The apparatus of any of claims 14 to 17, wherein reduced priority parity bits are omitted from the messaging.

22. The apparatus of any of claims 14 to 17, wherein the reduced priority parity bits are permuted to least significant positions within the messaging.

23. The apparatus of any of claims 14 to 17, wherein the codeword contains at least a portion of the set of information bits as a systematic part concatenated with a parity part of bits.

24. The apparatus of any of claims 14 to 17, wherein the apparatus comprises a baseband processor.

25. The apparatus of any of claims 14 to 17, wherein the apparatus comprises a transceiver circuit coupled to an antenna.

26. The apparatus of any of claims 14 to 17, wherein the apparatus comprises a base station device.

27. The apparatus of any of claims 14 to 17, wherein the apparatus comprises a User Equipment (UE) device.

28. A computer-readable medium comprising instructions that, when executed on a processing device, cause the device to:

encoding a set of information bits to be transmitted in accordance with a parity block to produce a first codeword representing a set of parity nodes based on the set of information bits and based on a set of parity bits, the set of parity bits including parity bits associated with a relatively large number of parity nodes and parity bits associated with a relatively small number of parity nodes;

selecting parity bits to be de-prioritized from the first codeword based on selection criteria that de-prioritizes those parity bits associated with the relatively larger number of parity nodes; and

generating an output data set for transmission based on the first codeword, wherein the selected parity bits are of reduced priority.

29. The computer-readable medium of claim 28, wherein the parity blocks are represented as a parity check matrix data structure arranged as a set of rows and columns.

30. The computer readable medium of claim 29, wherein each column of the parity check matrix has an active column weight defined as a number of parity check nodes to which the corresponding parity check bit is connected that do not contain other not yet recovered reduced priority bits.

31. A system for encoding a message for transmission, the system comprising:

means for encoding a set of information bits to be transmitted according to a parity block to produce a first codeword representing a set of parity nodes based on the set of information bits and based on a set of parity bits, the set of parity bits including parity bits associated with a relatively large number of parity nodes and parity bits associated with a relatively small number of parity nodes;

means for selecting parity bits to be de-prioritized from the first codeword based on a selection criterion that de-prioritizes those parity bits associated with a relatively larger number of parity nodes; and

means for generating an output data set for transmission based on the first codeword, wherein selected parity bits are of reduced priority.

32. The system of claim 31, wherein the parity blocks are represented as a parity check matrix data structure arranged as a set of rows and columns.

33. The system of claim 32, wherein each column of the parity check matrix has an active column weight defined as the number of parity check nodes to which the corresponding parity check bit is connected that do not contain other, yet unrecovered, reduced priority bits.

34. The system of any of claims 31 to 33, wherein the first codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces the priority of those parity bits belonging to a parity bit column of all parity bit columns having a largest number of non-zero elements.

35. The system of any of claims 31-33, wherein the first codeword comprises a first portion containing the information bits and a second portion containing the parity bits, and wherein the means for encoding comprises:

means for calculating a first permutation of the information bits to produce a first permutation result;

means for computing a second permutation of the set of parity bits to obtain a second permutation result; and

means for concatenating the first permutation result with the second permutation result to generate a circular buffer from which the output data set is generated.

36. The system of claim 35, wherein the second permutation result comprises a bit ordering having a start and an end, wherein the de-prioritized selected parity bits are at the end.

37. A system of communication devices configured to receive and decode encoded messages, the system comprising:

means for accessing a received messaging comprising a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity bits;

means for computing a first inverse permutation of the first permutated portion and a second inverse permutation of the second permutated portion to produce a codeword comprising an un-permutated first portion representing the information bits and an un-permutated second portion representing the parity bits; and

means for decoding the codeword using a low density parity check matrix, the codeword having been previously encoded as a set of parity check nodes based on the set of information bits and based on a set of parity check bits, the set of parity check bits including parity check bits associated with a relatively large number of parity check nodes and parity check bits associated with a relatively small number of parity check nodes, some of the parity check bits having been de-prioritized from the codeword based on a selection criterion that de-prioritizes those parity check bits associated with the relatively large number of parity check nodes.

38. The system of claim 37, wherein the codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criterion reduces priority of those parity bits belonging to a parity bit column having a largest number of non-zero elements of all parity bit columns.

39. The system of any one of claims 37 to 38, wherein reduced priority parity bits are omitted from the messaging.

40. The system of any of claims 37 to 38, wherein the reduced priority parity bits are permuted to least significant positions within the messaging.

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