WO2017166465A1 - 扇出线结构、显示面板及其制造方法 - Google Patents

扇出线结构、显示面板及其制造方法 Download PDF

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Publication number
WO2017166465A1
WO2017166465A1 PCT/CN2016/087810 CN2016087810W WO2017166465A1 WO 2017166465 A1 WO2017166465 A1 WO 2017166465A1 CN 2016087810 W CN2016087810 W CN 2016087810W WO 2017166465 A1 WO2017166465 A1 WO 2017166465A1
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Prior art keywords
fan
conductive film
out line
additional conductive
photoresist
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Ceased
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PCT/CN2016/087810
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English (en)
French (fr)
Inventor
王劭颛
金熙哲
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/533,693 priority Critical patent/US20180190541A1/en
Publication of WO2017166465A1 publication Critical patent/WO2017166465A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/067—Manufacture or treatment of conductive parts of the interconnections by modifying the pattern of conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/498—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07555—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a fan-out line structure, a display panel including the fan-out line structure, and a method of fabricating the same.
  • the display panel includes a TFT array and a driving circuit module for driving the TFT array (for example, a driving circuit board provided with a driving IC).
  • a driving circuit module for driving the TFT array for example, a driving circuit board provided with a driving IC.
  • a driving circuit module for driving the TFT array for example, a driving circuit board provided with a driving IC.
  • a connecting wire for example, a data line or a gate line
  • the plurality of output pins of the driving circuit module are relatively concentrated and the plurality of signal lines of the TFT array are relatively dispersedly arranged.
  • the driving circuit module is A similar "fan” structure is formed between the TFT arrays. Therefore, the connecting wire is generally referred to as a "fan-out line", and the setting area of the fan-out line is referred to as a "fan-out area”.
  • the distance from the output pin of the driving circuit module to the signal line of the TFT array is inconsistent, which inevitably results in a large difference in the lengths of the fan-out lines, so that the impedance between the plurality of fan-out lines in the fan-out area is uneven. This uneven impedance affects the display of the display panel and needs to be avoided as much as possible.
  • a short-circuit fan-out line is usually used to increase the impedance by adopting a winding design.
  • this method requires an area for winding, which tends to cause an increase in the overall width of the fan-out area, and the overall width of the fan-out area is reflected in the frame size of the display using the display panel, The increase in the overall width of the fan-out area is highly detrimental to the development and design of narrow-frame displays.
  • the present disclosure provides the following technical solutions.
  • a fan-out line structure which includes a plurality of fan-out lines of different lengths
  • Each of the fan-out lines includes a wiring layer
  • the plurality of fan-out lines have the same impedance.
  • a fan-out line structure according to an embodiment of the present disclosure, in which impedances of the wiring layers of different lengths are different.
  • a fan-out line structure wherein, among the plurality of fan-out lines, except for the wiring layer having the shortest length, the wiring layers of each of the plurality of fan-out lines are provided with An additional conductive film electrically connected to the wiring layer.
  • each of the wiring layers is provided with an additional conductive film electrically connected to the wiring layer.
  • the additional conductive film has the same thickness and width.
  • the lengths of the additional conductive films disposed over the wiring layers of different lengths are different.
  • the additional conductive film is disposed over the wiring layer continuously or in sections.
  • the additional conductive film material is the same as the wiring layer material.
  • the additional conductive film material is different from the wiring layer material, and a material of the additional conductive film has a resistivity lower than a resistivity of a material of the wiring layer.
  • a display panel including a driving circuit module and a TFT array, and any of the fan-out line structures described above, wherein the fan-out line structure is used to connect a driving circuit module and a TFT Array.
  • a method of manufacturing a display panel includes:
  • the wiring layer and the additional conductive film are respectively formed by etching the first conductive layer and the second conductive layer.
  • the forming the wiring layer and the additional conductive film by etching the first conductive layer and the second conductive layer, respectively includes:
  • the photoresist of the photoresist completely reserved region and the photoresist semi-reserved region is simultaneously subjected to ashing treatment to expose a portion of the photoresist semi-reserved region corresponding to the second conductive layer;
  • the remaining photoresist is removed.
  • the fan-out line structure of the present disclosure changes the impedance of the fan-out lines of different lengths by providing an additional conductive film, so that the impedances of the plurality of fan-out lines can be the same, the impedance consistency is good, the preparation process is simple, and the display panel using the fan-out line structure is used. The display is good.
  • FIG. 1 is a schematic diagram of a fan-out line structure in accordance with an embodiment of the present disclosure.
  • FIG. 2 is a plan view of a fan-out line of a fan-out line structure according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of the fan-out line of the embodiment shown in FIG.
  • 4 to 10 are schematic views showing a process of preparing a fan-out line structure according to a preparation method according to an embodiment of the present disclosure.
  • 10-fan outgoing structure 100, 100 1 , 100 2 , 100 3 , 100 5 , 100 6 , 100 7 - fan-out line; 110'-first conductive layer; 110-wiring layer; 130'-second conductive layer; 130, 130a, 130b - additional conductive film; 131 - section without additional conductive film; 200 - pin; 300 - signal line; 80 - photoresist; 80b - photoresist completely reserved area; 80c - lithography Glue semi-retained area; 80a-resist completely removed area; 90-glass substrate.
  • FIG. 1 illustrates a schematic diagram of a fan-out line structure in accordance with an embodiment of the present disclosure.
  • the fan-out line structure 10 is disposed in a fan-out area between the driving circuit module and the TFT array, and the fan-out line structure 10 is used to drive a plurality of pins 200 of a certain driving circuit module (for example, a driving IC).
  • the driving circuit module can drive an area corresponding to the plurality of signal lines of the TFT array to realize a display function.
  • a fan-out line structure including seven fan-out lines 100 that is, fan-out lines 100 1 , 100 2 , 100 3 , 100 4 , 100 5 , 100 6 , and 100 7 is exemplarily shown in FIG. 1 .
  • the specific number of fan-out lines 100 is not limitative and may be set according to the size of the TFT array area that the driver circuit module needs to drive.
  • the plurality of fan-out lines 100 have different lengths.
  • the length of the fan-out line 100 4 located in the middle is the shortest, and the lengths of the other fan-out lines on both sides of the fan-out line 100 4 are sequentially increased.
  • the lengths of the fan-out line 100 5 , the fan-out line 100 6 , and the fan-out line 100 7 increase sequentially, and the lengths of the fan-out line 100 3 , the fan-out line 100 2 , and the fan-out line 100 1 also increase in sequence.
  • a wiring layer 110 is disposed, and wiring layers respectively disposed on the plurality of fan-out lines 100 1 , 100 2 , 100 3 , 100 4 , 100 5 , 100 6 , and 100 7 are respectively disposed.
  • the lengths of 110 are different, that is, their lengths are different.
  • the wiring layers 110 of the different fan-out lines 100 may be made of the same material, and their widths and thicknesses are also substantially the same, and therefore, the impedances of the wiring layers of different lengths of the different fan-out lines 100 are different.
  • the width or thickness of the plurality of wiring layers may be specifically set, for example, the shorter the length of the wiring layer is set, the narrower the width of the wiring layer is. Thereby the impedance of the plurality of wiring layers is substantially the same.
  • an additional conductive film 130 is provided, and the additional conductive film 130 is electrically connected to the wiring layer 110.
  • the fan-out line 100 as a whole is also electrically conductive.
  • the additional conductive film 130 has a smaller resistivity with respect to the wiring layer 110, and therefore, in the section of the fan-out line 100 where the additional conductive film 130 is provided, the corresponding impedance can be reduced, and the magnitude of the impedance reduction can be
  • the length, width and/or thickness of the additional conductive film 130 are determined, in particular, by the length of the additional conductive film 130.
  • the additional conductive film 130 may be a continuous segment, such as an additional conductive film 130 on the fan-out lines 100 1 and 100 7 , which are continuously disposed over the wiring layer 110.
  • the additional conductive film 130 may also be provided in sections, for example, additional conductive films 130a and 130b disposed on the fan-out lines 100 2 , 100 3 , 100 5 , and 100 6 , which are disposed in sections over the wiring layer 110 .
  • the additional conductive films 130 may be all continuously disposed, or may be disposed in all segments, or partially segmentally arranged as shown in FIG. Partially set.
  • the length of the additional conductive film 130 of each of the fan-out lines 100 (for the plurality of segments of the additional conductive films 130a and 130b refers to the total length), the width and/or the thickness, etc., can be determined according to the resistance of the wiring layer 110 of each of the fan-out lines 100,
  • the impedance between the plurality of fan-out lines 100 1 , 100 2 , 100 3 , 100 4 , 100 5 , 100 6 and 100 7 is substantially the same, that is, the impedance of each of the fan-out lines 100 of the fan-out structure 10 is substantially the same.
  • the lengths of the additional conductive films 130 disposed on the wiring layers 110 of different lengths are different, so that the fan-out lines 100 of different lengths can be adjusted. Impedance consistency between.
  • the impedances of the plurality of fan-out lines 100 are set to be substantially the same as the impedance of the shortest fan-out line, that is, the other fan-out lines are adjusted based on the impedance of the shortest fan-out line, so that they are aligned with the shortest fan-out line 100 4 .
  • the impedance is basically the same. Therefore, in an embodiment, the additional conductive film 130 may not be disposed for the shortest fan-out line 100 4 , and additional conductive is provided for the other fan-out lines 100 1 , 100 2 , 100 3 , 100 5 , 100 6 , and 100 7 . Film 130.
  • an additional conductive film 130 electrically connected to the wiring layer is disposed on the wiring layer 110 of the plurality of fan-out lines.
  • the additional conductive film 130 may not be disposed on the wiring layer 110 of a plurality of fan-out lines having a short length.
  • the impedances of the fan-out lines 100 can be made uniform by adjusting the widths of the wiring layers 110 having different lengths. Embodiments of a specific structure in which the fan-out lines 100 1 , 100 2 , 100 3 , 100 5 , 100 6 , and 100 7 of the additional conductive film 130 are provided are described below.
  • the additional conductive film 130 may be disposed on the shortest length fan-out line 100 4 to reduce the impedance of the shortest fan-out line 100 4 so that each of the fan-out line structures 100 The impedance of the fanout line is further uniformly reduced.
  • an additional conductive film is provided on the wiring layers of all the fan-out lines of the fan-out line structure.
  • Fig. 2 illustrates a top view of a fan-out line of a fan-out line structure in accordance with an embodiment of the present disclosure.
  • Fig. 3 is a schematic cross-sectional view showing the A-A cross section of the fan-out line of the embodiment shown in Fig. 2.
  • the fan-out line 100 is electrically conductive as a whole and can be used to conduct drive signals from the drive circuit module to the signal lines of the TFT array.
  • the fan-out line 10 includes a wiring layer 110 and an additional conductive film 130 stacked on the wiring layer 110, wherein the wiring layer 110 has a resistivity greater than that of the additional conductive film 130.
  • the wiring layer 110 may select an ITO wiring made of an ITO (Indium Tin Oxide) material having a relatively high resistivity
  • the additional conductive film 130 may select a metal wiring made of a metal material having a relatively small resistivity (for example, aluminum or the like).
  • the resistivity of the wiring layer 110 may be 10 times or more, for example, 100 times the resistivity of the additional conductive film 130. Therefore, in the case where the wiring layer 110 and the additional conductive film 130 are simultaneously present, the conductive film 130 is substantially electrically conductive, and thus, the additional conductive film 130 can also be understood as a conductive working layer. Specifically, the wiring directions of the wiring layer 110 and the additional conductive film 130 are substantially the same. It should be noted that the additional conductive film 130 is embedded on the surface of the wiring layer 110. It can also be understood that the additional conductive film 130 is disposed on the wiring layer 110.
  • a section 131 in which an additional conductive film is not provided is provided.
  • the additional conductive film 130a and the additional conductive film 130b are not electrically conductive between themselves, and must be electrically conductive by the partial wiring layer 110 corresponding to the section 131;
  • the section in which the additional conductive film is not provided is also present in the case of the continuously provided additional conductive film.
  • the additional conductive film 130a is bonded to the additional conductive film 130b, and the portion other than the additional conductive film is a portion in which the additional conductive film is not provided.
  • the corresponding sections of the additional conductive films 130a and 130b are substantially electrically conductive with the additional conductive films 130a and 130b (because their resistivity is relatively small), and the section 131 in which the additional conductive film is not provided is completely in the wiring layer. 110 conducts electricity.
  • the resistance of the wiring layer 110 corresponding to the segment 131 is also different. Therefore, the overall resistance or impedance of the fan-out line 100 is also different. The longer the length L of the segment 131 in which the additional conductive film is not provided, the greater the impedance of the fan-out line 100.
  • the width of the wiring layer 110 is greater than the width of the additional conductive film 130 (eg, Figure 1). In still another alternative embodiment, the width of the wiring layer 110 may be substantially equal to the width of the additional conductive film 130.
  • the thickness and width of the segmented additional conductive film 130a and the additional conductive film 130b of the same wiring layer 110 are set to be the same; the thickness and width of the additional conductive film 130 of the different wiring layers 110 may also be set to be the same.
  • the additional conductive film 130 may also be made of the same material as the wiring layer 110.
  • the conductive cross-sectional area increases, and the corresponding impedance also decreases, so that an additional conductive film can also be provided.
  • the length, width and/or height of 130 adjusts the impedance of the fanout line 100.
  • the fan-out line structure of the above embodiment can achieve uniform impedance. Therefore, when the fan-out line structure is used to form the display panel, the display effect can be improved. Moreover, the fan-out line of the fan-out line structure is not a winding method, and does not need to additionally increase the width of the fan-out area required for the fan-out line structure, and is very suitable for application in a narrow-frame display.
  • FIG. 4 through 10 illustrate schematic views of a process for preparing a method of fabricating a fan-out line structure, in accordance with an embodiment of the present disclosure.
  • the process of preparing the fan-out line structure of the embodiment shown in Fig. 1 will be described below with reference to Figs. 4 to 10, which are illustrated by taking a certain fan-out line as an example. It should be understood that in the case where the length L of the segment of the other fan-out line where the additional conductive film is not provided is determined, other fan-out lines may be formed simultaneously.
  • a first conductive layer 110' is formed on the glass substrate 90, which is patterned to form a wiring layer 110, and then a second conductive layer 130' is deposited and formed on the first conductive layer 110'. It is patterned to form an additional conductive film 130.
  • the thicknesses of the first conductive layer 110' and the second conductive layer 130' may be determined according to the thicknesses of the wiring layer 110 and the additional conductive film 130 to be formed, respectively.
  • the first conductive layer 110' may specifically, but not limited to, be an ITO layer, and the second conductive layer 130' may specifically, but not limited to, be a metal layer.
  • a photoresist 80 is coated on the second conductive layer 130'.
  • the photoresist 80 is exposed by a half tone mask, and then a photoresist completely remaining region 80b, a photoresist semi-retained region 80c, and the like are formed after development and de-glue.
  • the photoresist completely removes the region 80a.
  • the above photoresist completely remaining region 80b, the photoresist semi-retained region 80c, and the photoresist completely removed region 80a are defined relative to the photoresist 80 of FIG.
  • the photoresist half-retained region 80c is at least adapted to correspond to a portion patterned to form an additional conductive film, which may be defined according to a section to be formed which is not provided with an additional conductive film.
  • etching is performed by using the photoresist 80 as a mask, that is, the photoresist of the photoresist completely reserved region and the photoresist semi-reserved region is used as a mask to the first conductive layer 110 ′.
  • the additional conductive film 130 is etched to form a plurality of fan-out line structures including double-layer wirings on the glass substrate 90 (the additional conductive film 130 is continuous at this time).
  • the etching can be specifically performed by wet etching and cleaned after etching.
  • the photoresist 80 which completely retains the photoresist and the photoresist semi-reserved region is simultaneously subjected to ashing treatment. Since the thickness of the photoresist completely reserved region and the semi-reserved region of the photoresist are inconsistent, the photoresist of the thinner photoresist semi-reserved region will be first ashed away, thereby exposing the corresponding portion of the photoresist semi-reserved region. Wiring layer 130.
  • the ashing process ends, and thus the corresponding photoresist 80 is left on the wiring layer 130 in the completely remaining region of the photoresist.
  • the glue 80 can be used as a mask during subsequent etching.
  • the thickness of the fully retained region of the photoresist is greater than the thickness of the semi-reserved region of the photoresist. Specifically, the thickness of the semi-reserved region of the photoresist is 1/2 of the thickness of the fully retained region of the photoresist.
  • the exposed portion of the additional conductive film 130 is etched to form segmented additional conductive films 130a and 130b of each fan-out line.
  • a section 131 of each fan-out line in which no additional conductive film is provided is also formed.
  • the photoresist 80 is used as a mask layer to protect the additional conductive films 130a and 130b that need to be retained.
  • the etching can be performed by wet etching and after etching.
  • a portion of the additional conductive film 130 is selectively etched without etching the wiring layer 110, which may be specifically achieved by selecting an etching solution or the like.
  • a fan-out line structure including a plurality of fan-out lines as shown in FIG. 1 is formed.
  • the preparation method of the fan-out line structure in the above display panel only needs to adopt a halftone mask, and is completed by one exposure, one ashing, and two etchings.
  • the preparation process is simple and the cost is low. Based on the preparation method of the above fan-out line structure, a corresponding display panel can be manufactured.
  • the method of preparing the fan-out line structure is not limited to the above embodiment.
  • multiple masks, multiple exposures can also be used.
  • the double-layer fan-out structure can be formed by one mask using one mask, and the section without the additional conductive film can be formed by another mask for another exposure, but the process is complicated.
  • the present disclosure also provides an example of a display panel formed based on the fan-out line structure of the embodiment shown in FIG. 1 above, which includes a driving circuit module, a TFT array, and a fan-out line structure between the driving circuit module and the TFT array.
  • the display panel shows good results.
  • the additional conductive film 130 on the wiring layer 110 of the fan-out line 100 of the above embodiment is disposed in a segment, it may also be disposed in the form of three or more segments, and the specific segmentation form is not limited. Sexual.
  • the total length of the additional conductive film 130 By controlling the total length of the additional conductive film 130, the total length of the section in which the additional conductive film is not provided can be controlled, so that the impedance of each of the fan-out lines 100 can be set.

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Abstract

提供一种扇出线结构（10）、显示面板及其制造方法，属于显示技术领域。该扇出线结构（10）包括多条长度不一的扇出线（100）；其中每条扇出线（100）均包括布线层（110）；至少部分扇出线（100）中的每条扇出线（100）的布线层（110）之上设置有与布线层（110）电连接的附加导电膜（130）；并且多条扇出线（100）的阻抗相同。该扇出线结构的多条扇出线之间的阻抗一致性好、制备工艺简单，使得使用该扇出线结构的显示面板的显示效果好。

Description

扇出线结构、显示面板及其制造方法 技术领域
本公开涉及显示技术领域，尤其涉及一种扇出线结构、包括该扇出线结构的显示面板及其制造方法。
背景技术
显示面板包括TFT阵列以及用于驱动TFT阵列的驱动电路模块(例如设置有驱动IC的驱动电路板)。为实现将驱动电路模块的信号输出对应施加在TFT阵列中的相应信号线(例如数据线或栅线)上，需要使用连接导线从驱动电路模块的某一输出引脚对应连接至TFT阵列的某一信号线上。按照常规的驱动电路模块和TFT阵列设置，驱动电路模块的多个输出引脚是相对集中排列而TFT阵列的多条信号线相对分散排列，因此采用以上多条连接导线时会在驱动电路模块与TFT阵列之间形成类似“扇形”结构。因此，通常称该连接导线为“扇出线”，扇出线的设置区域则称为“扇出区(Fan-out Area)”。
然而，从驱动电路模块的输出引脚到TFT阵列的信号线距离是不一致的，必然会导致扇出线的长度相差较大，因此容易导致扇出区的多条扇出线之间的阻抗不均匀，这种阻抗不均匀会影响显示面板的显示效果，是需要尽量避免的。
现有技术中，为实现不同扇出线之间的阻抗尽量均一化，通常对长度较短的扇出线采用绕线设计的方式来增加其阻抗。但是，这种方法需要增加用于绕线的区域，容易导致扇出区的整体宽度的增加，而这种扇出区的整体宽度是会体现在使用该显示面板的显示器的边框尺寸上，因此，扇出区的整体宽度的增加是非常不利于窄边框显示器的开发和设计的。
发明内容
本公开的目的在于，实现扇出线结构的扇出线之间的阻抗均匀化。
为实现以上目的或者其他目的，本公开提供以下技术方案。
按照本公开的一方面，提供一种扇出线结构，其包括多条长度不一的扇出线；其中
每条所述扇出线均包括布线层；
至少部分所述扇出线中的每条扇出线的所述布线层之上设置 有与布线层电连接的附加导电膜；
多条所述扇出线的阻抗相同。
根据本公开的一实施例的扇出线结构，其中，不同长度的所述布线层的阻抗不同。
根据本公开的一实施例的扇出线结构，其中，多条所述扇出线中，除长度最短的布线层外，其余多条所述扇出线中的每条扇出线的布线层均设置有与布线层电连接的附加导电膜。
根据本公开又一实施例的扇出线结构，其中，在多条所述扇出线中，每条所述布线层均设置有与布线层电连接的附加导电膜。
在之前所述实施例的扇出线结构中，所述附加导电膜厚度及宽度一致。
根据本公开还一实施例的扇出线结构，其中，设置有所述附加导电膜的多条扇出线中，设置在不同长度的所述布线层之上的附加导电膜的长度不同。
可选地，所述附加导电膜连续地或分段地设置在所述布线层之上。
可选地，所述附加导电膜材料与所述布线层材料相同。
可选地，所述附加导电膜材料与所述布线层材料不同，且附加导电膜的材料的电阻率小于所述布线层的材料的电阻率。
按照本公开的又一方面，提供一种显示面板，其包括驱动电路模块和TFT阵列，以及以上所述及的任一种扇出线结构，其中所述扇出线结构用于连接驱动电路模块与TFT阵列。
按照本公开的还一方面，提供一种显示面板的制造方法，包括：
提供预设有扇出区的衬底；
在预设的所述扇出区通过沉积形成第一导电层；
在所述第一导电膜表面形成第二导电层；以及
通过刻蚀第一导电层和第二导电层分别形成所述布线层和附加导电膜。
根据本公开又一实施例的制造方法，其中，通过刻蚀第一导电层和第二导电层分别形成所述布线层和附加导电膜包括：
在所述第二导电层上涂覆光刻胶；
通过半色调掩膜板对所述光刻胶曝光显影，以形成光刻胶完全保留区域、光刻胶半保留区域以及光刻胶完全去除区域；
以所述光刻胶完全保留区域和光刻胶半保留区域的光刻胶为掩膜刻蚀所述第一导电层和第二导电层以形成多条布线层；
对所述光刻胶完全保留区域和光刻胶半保留区域的光刻胶同时进行灰化处理以暴露所述光刻胶半保留区域对应第二导电层的部分；
对暴露的所述第二导电层的部分进行刻蚀以形成附加导电膜；以及
去除剩余的光刻胶。
本公开的扇出线结构通过设置附加导电膜来改变长度不一的扇出线的阻抗，使得多条扇出线的阻抗能够相同，阻抗一致性好，制备工艺简单，使用该扇出线结构的显示面板的显示效果好。
附图说明
为了更清楚地说明本公开的实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是按照本公开的一实施例的扇出线结构的示意图。
图2是按照本公开的一实施例的扇出线结构的扇出线的俯视图，图3是图2所示实施例的扇出线的A-A截面结构示意图。
图4至图10示意按照本公开的一实施例的制备方法来制备扇出线结构的过程示意图。
附图标记：
10-扇出线结构；100、1001、1002、1003、1005、1006、1007-扇出线；110’-第一导电层；110-布线层；130’-第二导电层；130、130a、130b-附加导电膜；131-未设置附加导电膜的区段；200-引脚；300-信号线；80-光刻胶；80b-光刻胶完全保留区域；80c-光刻胶半保留区域；80a-光刻胶完全去除区域；90-玻璃衬底。
具体实施方式
下面将结合本公开的实施例中的附图，对本公开的实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本 领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在附图中，为了清楚起见，夸大了层和区域的厚度，并且，由于刻蚀引起的圆润等形状特征未在附图中示意出。
图1图示了按照本公开的一实施例的扇出线结构的示意图。在该实施例中，扇出线结构10设置在驱动电路模块与TFT阵列之间的扇出区中，该扇出线结构10用于将某一驱动电路模块(例如驱动IC)的多个引脚200对应连接至TFT阵列的多条信号线300上，从而，该驱动电路模块可以驱动该TFT阵列的多条信号线对应的区域，以实现显示功能。为方便说明，在图1中示例性地示出了包括7条扇出线100的扇出线结构，即扇出线1001、1002、1003、1004、1005、1006和1007。应当指出，扇出线100的具体条数不是限制性的，可以根据驱动电路模块需要驱动的TFT阵列区域的大小来设置。
在该实施例中，多条扇出线100的长度不一。例如，位于中间的扇出线1004的长度最短，扇出线1004的两侧的其它扇出线的长度依次增加。这样，扇出线1005、扇出线1006和扇出线1007的长度依次增加，扇出线1003、扇出线1002和扇出线1001的长度也依次增加。
对应每条扇出线100，如图1所示，均设置有一布线层110，多条扇出线1001、1002、1003、1004、1005、1006和1007上分别设置的布线层110的长度不一，也即它们的长度不相同。在一实施例中，不同扇出线100的布线层110可以采用相同材料制成，并且它们宽度、厚度也基本相同，因此，不同扇出线100的不同长度的布线层的阻抗不相同。在又一实施例中，即使不同扇出线100的布线层的长度不同，也可以通过对其中若干布线层的宽度或厚度分别进行具体设置，例如，长度越短的布线层的宽度设置越窄，从而使该若干布线层的阻抗大致相同。
在至少部分扇出线100的布线层110之上，设置有附加导电膜130，附加导电膜130是与布线层110电导通的。这样，扇出线100整体也是电导通的。附加导电膜130相对布线层110具有较小的电阻率，因此，在扇出线100的设置有附加导电膜130的区段中，其对应的阻抗能够得到减小，其阻抗减小的大小可以根据附加导电膜130的长度、宽度和/或厚度等条件来确定，尤其是受附加导电膜130的长度影响。
附加导电膜130可以为连续的一段，例如扇出线1001和1007上的附加导电膜130，其是连续地设置在布线层110之上。附加导电膜130也可以被分段设置，例如，扇出线1002、1003、1005和1006上设置的附加导电膜130a和130b，其被分段地设置在布线层110之上。当然，在扇出线结构10中所有设置附加导电膜130的扇出线100中，附加导电膜130可以全部连续地设置，或者可以全部分段地设置，或者如图1所示部分分段地设置、部分连续地设置。
根据每条扇出线100的布线层110的电阻，可以确定每条扇出线100的附加导电膜130的长度(对于多段的附加导电膜130a和130b是指总长度)、宽度和/或厚度等，使得多条扇出线1001、1002、1003、1004、1005、1006和1007之间的阻抗基本相同，也即实现扇出结构10的每条扇出线100的阻抗基本相同。在一实施例中，在设置有附加导电膜130的多条扇出线100中，设置在不同长度的布线层110之上的附加导电膜130的长度不同，这样，可以调节不同长度的扇出线100之间的阻抗一致性。
可选地，将多条扇出线100的阻抗设置为与最短的扇出线的阻抗基本一致，也即其他扇出线以最短扇出线的阻抗为基准来调节设置，使它们与最短扇出线1004的阻抗基本一致。因此，在一实施例中，可以对最短的扇出线1004不设置附加导电膜130，而对于其他的扇出线1001、1002、1003、1005、1006和1007均设置附加导电膜130。也就是说，除长度最短的扇出线1004外，其余多条扇出线中的布线层110之上均设置有与该布线层电连接的附加导电膜130。当然在其他实施例中，也可以在长度较短的几条扇出线的布线层110上不设置附加导电膜130。在长度较短的几条扇出线100之间，可以通过调节长度不一的布线层110的宽度，来使这几条扇出线100的阻抗一致。设置附加导电膜130的扇出线1001、1002、1003、1005、1006和1007的具体结构的实施例在以下描述。
但是，需要说明的是，在其他实施例中，也可以在长度最短的扇出线1004上设置附加导电膜130以减小最短的扇出线1004的阻抗，从而使扇出线结构100的每条扇出线的阻抗进一步一致减小。这样，扇出线结构的所有扇出线的布线层上均设置有附加导电膜。
图2图示了按照本公开的一实施例的扇出线结构的扇出线的俯视 图，图3是图2所示实施例的扇出线的A-A截面结构示意图。
在图2和图3中，扇出线100整体是电导通的，并且可以用来传导从驱动电路模块至TFT阵列的信号线上的驱动信号。扇出线10包括布线层110和堆叠在布线层110上的附加导电膜130，其中，布线层110的电阻率大于附加导电膜130的电阻率。例如，布线层110可以选择电阻率相对较大的ITO(氧化铟锡)材料制成的ITO布线，附加导电膜130可以选择电阻率相对较小的金属材料(例如铝等)制成的金属布线。在一实施例中，布线层110的电阻率可以为附加导电膜130的电阻率的10倍以上，例如100倍。因此，在布线层110和附加导电膜130同时存在情况下，基本以附加导电膜130来导电，这样，附加导电膜130也可以理解为导电工作层。具体地，布线层110和附加导电膜130的布线方向基本相同。需要说明的是，附加导电膜130嵌置在布线层110的表面也可以被理解为附加导电膜130设置在布线层110之上。
如图2和图3所示，在分段设置的附加导电膜130中，附加导电膜130a和附加导电膜130b之间为未设置附加导电膜的区段131。并且，在未设置附加导电膜的区段131处，附加导电膜130a与附加导电膜130b二者自身之间是不能够导电的，必须借助区段131对应的部分布线层110来导电；未设置附加导电膜的区段131的长度为L时，由于长度为L的布线层110的电阻明显大于长度为L的附加导电膜130的电阻，这样，区段131的扇出线部分的阻抗将明显增加，扇出线10的电阻也增加。
需要说明的是，未设置附加导电膜的区段在连续设置的附加导电膜的情形下也是存在的。例如，将附加导电膜130a与附加导电膜130b接合在一起设置，附加导电膜之外的区段即为未设置附加导电膜的区段。
在扇出线100导电工作时，附加导电膜130a和130b对应的区段基本以附加导电膜130a和130b导电(因为其电阻率相对小)，未设置附加导电膜的区段131则完全以布线层110进行导电。区段131的长度L不同时，区段131对应的布线层110的电阻也不同，因此，扇出线100的整体电阻或阻抗大小也不同。未设置附加导电膜的区段131的长度L越长，扇出线100的阻抗越大。
在一实施例中，布线层110的宽度大于附加导电膜130的宽度(如 图1所示)。在又一替换实施例中，布线层110的宽度可以基本等于附加导电膜130的宽度。同一布线层110的分段的附加导电膜130a和附加导电膜130b的厚度和宽度设置为相同；不同布线层110的附加导电膜130的厚度和宽度也可以设置为相同。
在又一实施例中，附加导电膜130也可以与布线层110以相同的材料制成。这样，在对应的设置有附加导电膜130的区段，导电截面积(附加导电膜130与布线层110的截面积之和)增加，其对应的阻抗也下降，从而也可以通过设置附加导电膜130的长度、宽度和/或高度来调节扇出线100的阻抗。
以上实施例的扇出线结构可以实现阻抗均匀一致，因此，应用该扇出线结构形成显示面板时，其显示效果可以得到提高。并且，该扇出线结构的扇出线并不是采用绕线方式，不需要额外增加扇出线结构所需的扇出区的宽度，非常适合应用于窄边框显示器中。
图4至图10图示了按照本公开的一实施例的用来制备扇出线结构的制备方法的过程的示意图。以下结合图4至图10来说明制备图1所示实施例的扇出线结构的过程，其是以某一条扇出线为示例来说明的。应当理解，在其他扇出线的未设置附加导电膜的区段长度L被确定的情况下，其他扇出线也可以同步地被形成。
首先，如图4所示，在玻璃衬底90上沉积形成第一导电层110’，其被构图以形成布线层110，然后在第一导电层110’上沉积并形成第二导电层130’，其被构图以形成附加导电膜130。第一导电层110’和第二导电层130’的厚度可以分别按照欲形成的布线层110和附加导电膜130的厚度来确定。第一导电层110’具体可以但不限于为ITO层，第二导电层130’具体可以但不限于为金属层。
进一步，如图5所示，在第二导电层130’上涂覆光刻胶80。
进一步，如图6所示，采用半色调掩膜板(Half tone mask)对光刻胶80进行曝光，然后在显影去胶后形成光刻胶完全保留区域80b、光刻胶半保留区域80c以及光刻胶完全去除区域80a。以上光刻胶完全保留区域80b、光刻胶半保留区域80c以及光刻胶完全去除区域80a是相对图5中的光刻胶80来定义的。光刻胶半保留区域80c至少用来对应于被构图以形成未设置附加导电膜的区段，其可以根据欲形成的未设置附加导电膜的区段来定义。
进一步，如图7所示，以光刻胶80为掩膜进行刻蚀，也即以光刻胶完全保留区域和光刻胶半保留区域的光刻胶为掩膜对第一导电层110’和附加导电膜130进行刻蚀，从而在玻璃基板90上形成多条包括双层布线的扇出线结构(附加导电膜130此时为连续的)。刻蚀具体可以采用湿法刻蚀被完成，并且在刻蚀后进行清洗。
进一步，如图8所示，对光刻胶完全保留区域和光刻胶半保留区域的光刻胶80同时进行灰化处理。由于光刻胶完全保留区域和光刻胶半保留区域的厚度不一致，较薄的光刻胶半保留区域的光刻胶将先被灰化处理掉，从而暴露光刻胶半保留区域对应的部分布线层130。在光刻胶半保留区域的光刻胶被灰化去除后，灰化过程结束，从而，在布线层130上还会在光刻胶完全保留区域留下相应的光刻胶80，该光刻胶80在后续的刻蚀过程中可以用作掩膜。光刻胶完全保留区域的厚度大于光刻胶半保留区域的厚度，具体地光刻胶半保留区域的厚度为光刻胶完全保留区域的厚度的1/2。
进一步，如图9所示，对暴露的部分附加导电膜130进行刻蚀以形成每条扇出线的分段的附加导电膜130a和130b。同时，每条扇出线的未设置附加导电膜的区段131也被形成。在该步骤中，光刻胶80用作掩膜层以保护需要保留的附加导电膜130a和130b。刻蚀具体可以采用湿法刻蚀完成，并在刻蚀后进行清洗。在对暴露的部分附加导电膜130进行刻蚀的过程中，选择性地刻蚀部分附加导电膜130而不刻蚀布线层110，这具体可以通过选择刻蚀溶液等来实现。
进一步，如图10所示，通过去除光刻胶80和清洗，形成了包括多条如图1所示的扇出线的扇出线结构。
以上显示面板中的扇出线结构的制备方法过程，只需要采用一个半色调掩膜板，并通过一次曝光、一次灰化、两次刻蚀而完成。制备过程简单、成本低。基于以上扇出线结构的制备方法，可以制造相应的显示面板。
应当理解到，扇出线结构的制备方法并不限于以上实施例。在其他实施例中，也可以采用多块掩膜板、多次曝光来制备。例如，双层扇出线结构可以采用一掩膜板进行一次曝光被形成，未设置附加导电膜的区段可以采用另一掩膜板进行另一次曝光被形成，只是相对工艺复杂。
本公开还提供基于以上图1所示实施例的扇出线结构形成的显示面板实例，其包括驱动电路模块、TFT阵列以及驱动电路模块和TFT阵列之间的扇出线结构。该显示面板显示效果好。
需要说明的是，以上实施例的扇出线100的布线层110上的附加导电膜130在分段设置时，其也可以按三段或更多段的形式来设置，其具体分段形式不是限制性的。通过控制附加导电膜130的总长度，即可控制未设置附加导电膜的区段的总长度，从而可以设置每条扇出线100的阻抗。
以上例子主要说明了本公开的扇出线结构、扇出线结构的制备方法以及采用该扇出线结构的显示面板。尽管只对其中一些本公开的实施方式进行了描述，但是本领域普通技术人员应当了解，本公开可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本公开精神及范围的情况下，本公开可能涵盖各种的修改与替换以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种扇出线结构，包括多条长度不一的扇出线；其中，
    每条所述扇出线均包括布线层；
    至少部分所述扇出线中的每条扇出线的所述布线层之上设置有与布线层电连接的附加导电膜；以及
    多条所述扇出线的阻抗相同。
  2. 根据权利要求1所述的扇出线结构，其中，不同长度的所述布线层的阻抗不同。
  3. 根据权利要求2所述的扇出线结构，其中，在多条所述扇出线中，除长度最短的布线层外，其余多条所述扇出线中的每条扇出线的布线层均设置有与布线层电连接的附加导电膜。
  4. 根据权利要求2所述的扇出线结构，其中，在多条所述扇出线中，每条扇出线的所述布线层均设置有与布线层电连接的附加导电膜。
  5. 根据权利要求3或4所述的扇出线结构，其中，所述附加导电膜厚度及宽度一致。
  6. 根据权利要求2所述的扇出线结构，其中，设置有所述附加导电膜的多条扇出线中，设置在不同长度的所述布线层之上的附加导电膜的长度不同。
  7. 根据权利要求1所述的扇出线结构，其中，所述附加导电膜连续地或分段地设置在所述布线层之上。
  8. 根据权利要求1所述的扇出线结构，其中，所述附加导电膜材料与所述布线层的材料相同。
  9. 根据权利要求1所述的扇出线结构，其中，所述附加导电膜材料与所述布线层的材料不同，且附加导电膜的材料的电阻率小于所述布线层的材料的电阻率。
  10. 一种显示面板，包括驱动电路模块和TFT阵列，以及如权利要求1至9任一项所述的扇出线结构，其中所述扇出线结构用于连接驱动电路模块与TFT阵列。
  11. 一种显示面板的制造方法，包括：
    提供预设有扇出区的衬底；
    在预设的所述扇出区通过沉积形成第一导电层；
    在所述第一导电膜表面形成第二导电层；以及
    通过刻蚀第一导电层和第二导电层分别形成所述布线层和附加导电膜。
  12. 根据权利要求11所述的制造方法，其中，通过刻蚀第一导电层和第二导电层分别形成所述布线层和附加导电膜包括：
    在所述第二导电层上涂覆光刻胶；
    通过半色调掩膜板对所述光刻胶曝光显影，以形成光刻胶完全保留区域、光刻胶半保留区域以及光刻胶完全去除区域；
    以所述光刻胶完全保留区域和光刻胶半保留区域的光刻胶为掩膜刻蚀所述第一导电层和第二导电层以形成多条布线层；
    对所述光刻胶完全保留区域和光刻胶半保留区域的光刻胶同时进行灰化处理以暴露所述光刻胶半保留区域对应的第二导电层的部分；
    对暴露的所述第二导电层的部分进行刻蚀以形成附加导电膜；以及
    去除剩余的光刻胶。
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