WO2017166336A1 - 薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板 - Google Patents

薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板 Download PDF

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WO2017166336A1
WO2017166336A1 PCT/CN2016/079247 CN2016079247W WO2017166336A1 WO 2017166336 A1 WO2017166336 A1 WO 2017166336A1 CN 2016079247 W CN2016079247 W CN 2016079247W WO 2017166336 A1 WO2017166336 A1 WO 2017166336A1
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hole
layer
semiconductor layer
disposed
thin film
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French (fr)
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刘勋
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/108,523 priority Critical patent/US10141346B2/en
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
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    • H10D30/67—Thin-film transistors [TFT]
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    • H10D86/01—Manufacture or treatment
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D64/00—Electrodes of devices having potential barriers
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO

Definitions

  • the present invention relates to the field of display, and in particular, to a thin film transistor, a method of fabricating the thin film transistor, and a liquid crystal display panel.
  • a liquid crystal display device for example, a liquid crystal display (LCD) is a commonly used electronic device, which is favored by users because of its low power consumption, small size, and light weight.
  • a liquid crystal display usually includes an array substrate, and the array substrate includes a plurality of thin film transistors (TFTs) distributed in a display shape.
  • TFTs thin film transistors
  • the quality of the thin film transistor directly affects the quality of the liquid crystal display panel.
  • the thin film transistor of the prior art includes an etch barrier layer, and when the etch barrier layer is prepared, it is usually required to deposit an entire layer of an etch barrier material capable of blocking etching, and then the entire etch barrier material is prepared to cover only the mask process.
  • etch stop layer of a portion of the active layer then overlying the etch stop layer, and patterning the metal layer to form a source and a drain, the etch stop layer being capable of preventing subsequent fabrication of the source of the thin film transistor Corrosion of the active layer by the etchant at the time of the drain and the drain.
  • the patterning process of the etch barrier layer requires a mask to be added, so that the process of the thin film transistor is complicated.
  • the invention provides a thin film transistor, the thin film transistor comprising:
  • a gate disposed on a surface of the substrate
  • the etch barrier layer includes a first through hole and a second through hole, wherein the first through hole and the second through hole are disposed corresponding to the semiconductor layer to expose a portion of the semiconductor layer And the first through hole and the second through hole are spaced apart;
  • the passivation layer includes a third through hole and a fourth through hole, wherein the third through hole is disposed corresponding to the first through hole and is connected to the first through hole The fourth through hole is disposed corresponding to the second through hole and communicates with the second through hole;
  • a source disposed on the passivation layer and connected to one end of the semiconductor layer through the first through hole and the third through hole;
  • a drain disposed on the passivation layer, spaced apart from the source, and connected to the other end of the semiconductor layer through the second through hole and the fourth through hole.
  • the thin film transistor further comprises:
  • a pixel electrode is disposed on the passivation layer, the pixel electrode is electrically connected to the drain, and the pixel electrode and the drain are integrated.
  • the thin film transistor further comprises:
  • the passivation layer further includes a fifth through hole, and the fifth through hole is disposed corresponding to the data line to expose a portion of the data line;
  • the data line is electrically connected to the source through the fifth through hole.
  • the first end surface, the second end surface, and the third end surface, the first end surface is disposed on the substrate, the second end surface is opposite to the third end surface, and the second end surface is Intersecting with the first end surface, the third end surface intersects the first end surface, and the third end surface is disposed away from the data line compared to the second end surface, and the data line is adjacent to the first end There is a gap or coplanar between the end face of the three through hole and the second end face of the gate.
  • the data line is disposed on a side of the first through hole away from the second through hole, and the data line is spaced apart from the first through hole, and the fifth through hole is disposed in the The third through hole is away from one side of the fourth through hole, and the fifth through hole is spaced apart from the third through hole.
  • the fifth through hole is disposed corresponding to an end of the data line adjacent to the third through hole.
  • the invention also provides a method for preparing a thin film transistor, the method for preparing the thin film transistor include:
  • Corresponding holes are respectively etched on the etch stop layer and the passivation layer at both ends of the semiconductor layer to expose both ends of the semiconductor layer, and the via holes on the etch stop layer corresponding to the ends of the semiconductor layer are respectively a first through hole and a second through hole, wherein the passivation layer corresponds to the first through hole and communicates with the first through hole as a third through hole, and the passivation layer corresponds to the second through hole a hole communicating with the second through hole is a fourth through hole;
  • the step of “depositing a transparent conductive layer on the surface of the passivation layer away from the etch barrier layer, and patterning the transparent conductive layer to form through the first through hole and the third through hole Connecting a source of one end of the semiconductor layer, and connecting a drain of the other end of the semiconductor layer through the second through hole and the fourth through hole” includes:
  • a transparent conductive layer on a surface of the passivation layer away from the etch stop layer, and patterning the transparent conductive layer to form one end of the semiconductor layer connected through the first through hole and the third through hole a source, a drain connected to the other end of the semiconductor layer through the second through hole and the fourth through hole, and a pixel electrode integrally connected to the drain and electrically connected to the drain.
  • the method for preparing the thin film transistor further includes:
  • the through holes of the end are respectively the first through hole and the second through hole
  • the passivation layer corresponds to the first through hole and communicates with the first through hole as a third through hole
  • the passivation layer corresponds to the
  • the second through hole and the fourth through hole communicating with the second through hole include:
  • Corresponding holes are respectively etched on the etch stop layer and the passivation layer at both ends of the semiconductor layer to expose both ends of the semiconductor layer, and the via holes on the etch stop layer corresponding to the ends of the semiconductor layer are respectively a first through hole and a second through hole, wherein the passivation layer corresponds to the first through hole and communicates with the first through hole as a third through hole, and the passivation layer corresponds to the second through hole a fourth through hole communicating with the second through hole, and a fifth through hole corresponding to the data line in the passivation layer;
  • the step of “depositing a transparent conductive layer on a surface of the passivation layer away from the etch barrier layer, and patterning the transparent conductive layer to form a connection through the first through hole and the third through hole a source of one end of the semiconductor layer, and a drain connected to the other end of the semiconductor layer through the second through hole and the fourth through hole” include:
  • the present invention also provides a liquid crystal display panel comprising the thin film transistor according to any of the above embodiments.
  • the method for fabricating a thin film transistor of the present invention deposits an etch barrier layer on a surface of the semiconductor layer away from the gate insulating layer, and deposits a passivation layer on a surface of the etch barrier layer away from the semiconductor layer, the opposite ends of the corresponding semiconductor layer being in the etch barrier layer and Through holes are respectively etched into the passivation layer to expose both ends of the semiconductor layer.
  • a transparent conductive layer is deposited on the surface of the passivation layer away from the etch barrier layer, and the transparent conductive layer is patterned to form a source and a drain.
  • the method for fabricating the thin film transistor of the present invention does not need to increase the patterning of the etch barrier metal after the etch barrier layer is prepared, thereby simplifying the process of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 3 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • 4 to 11 are schematic views showing corresponding structures in the steps in the flow of the method for fabricating the thin film transistor of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of a thin film transistor according to a preferred embodiment of the present invention.
  • the thin film transistor 10 includes a substrate 110, a gate electrode 120, a gate insulating layer 130, a semiconductor layer 140, an etch barrier layer 150, a passivation layer 170, a source electrode 180a, and a drain electrode 180b.
  • the gate electrode 120 is disposed on a surface of the substrate 110
  • the gate insulating layer 130 covers the gate electrode 120
  • the semiconductor layer 140 is disposed on a surface of the gate insulating layer 130 away from the gate electrode 120. And corresponding to the gate 120.
  • the etch stop layer 150 covers the semiconductor layer 140 , and the etch barrier layer 150 includes a first through hole 151 and a second through hole 152 .
  • the first through hole 151 and the geothermal through hole 152 are disposed corresponding to the semiconductor layer 140 to expose a portion of the semiconductor layer 140, and the first through hole 151 and the second through hole 152 are spaced apart from each other.
  • the passivation layer 170 covers the etch stop layer 150 , and the passivation layer 170 includes a third through hole 171 and a fourth through hole 172 .
  • the third through hole 171 is disposed corresponding to the first through hole 171 and communicates with the first through hole 171
  • the fourth through hole 172 is disposed corresponding to the second through hole 152 and is opposite to the second through hole 152 .
  • the holes 152 are connected.
  • the source 180a is disposed at the passivation One end of the semiconductor layer 140 is connected to the layer 170 through the first through hole 151 and the third through hole 171.
  • the drain electrode 180b is disposed on the passivation layer 170, spaced apart from the source electrode 180a, and connected to the other end of the semiconductor layer 140 through the second through hole 152 and the fourth through hole 172. .
  • the substrate 110 is a transparent substrate, and the material of the substrate 110 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • the material of the gate electrode 120 includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi. In one embodiment, the gate 120 has a thickness of 1500 to 6000 angstroms.
  • the gate insulating layer 130 includes a first sub-insulating layer 131 and a second sub-insulating layer 132.
  • the first sub-insulating layer 131 covers the gate electrode 120
  • the second sub-insulating layer 132 covers the first sub-insulating layer 131 .
  • the first sub-insulating layer 131 comprises a silicon nitride (SiNx) material
  • the second sub-insulating layer 132 comprises a silicon oxide (SiOx) material.
  • the first sub-insulating layer 131 is made of a silicon nitride material, and a hydrogen element (H) can be generated during the preparation of the silicon nitride material for repairing the semiconductor layer 140 for improving the electrical properties of the semiconductor layer 140.
  • the second sub-insulating layer 132 may improve the stress of the semiconductor layer 140 disposed on the second sub-insulating layer 132 to prevent the semiconductor layer 140 from falling off.
  • the insulating layer 130 may have a thickness of 1500 to 4000 angstroms.
  • the semiconductor layer 140 is also referred to as a channel layer or an active layer.
  • the semiconductor layer 140 is a metal oxide semiconductor layer, which may include, but is not limited to, one or more of the following materials: ZnO-based transparent oxide semiconductor material, SnO 2 -based transparent oxidation Semiconductor material, In 2 O 3 based transparent oxide semiconductor material, and the like.
  • the semiconductor layer 140 may be Indium Gallium Zinc Oxide (IGZO).
  • the etch stop layer 150 can be, but is not limited to, a silicon nitride (SiNx) material, a silicon oxide (SiOx) material, or a composite layer of a silicon oxide material and a silicon nitride material.
  • the thin film transistor 10 also includes a data line 160.
  • the data line 160 is disposed between the etch stop layer 150 and the passivation layer 170.
  • the passivation layer 170 further includes a fifth through hole 173 disposed corresponding to the data line 160 to expose a portion of the data line 160.
  • the data line 160 is electrically connected to the source 180a through the fifth through hole 173.
  • the gate 120 includes a first end surface 121 , a second end surface 122 , and a third end surface 123 .
  • the first end surface 121 is disposed on the substrate 110, the second end surface 122 is opposite to the third end surface 123, and the second end surface 122 intersects the first end surface 121, the third end surface
  • the first end surface 121 intersects with the first end surface 121, and the third end surface 123 is disposed away from the data line 160.
  • the data line 160 is adjacent to the end surface of the third through hole 171.
  • the first end surface 121 is disposed on the substrate 110, and the first end surface 121 of the gate 120 is disposed on a surface of the substrate 110 adjacent to the gate 120, and the first end surface 121 is The substrate 110 is coplanar.
  • the data line 160 is adjacent to the end surface of the third through hole 171 and the second end surface 122 of the gate 120 has a gap or is coplanar, between the data line 160 and the gate 120 There is no overlap, and therefore, the parasitic capacitance between the data line 160 and the gate 120 is small, thereby achieving the technical effect of reducing the parasitic capacitance between the data line 160 and the gate 120.
  • the data line 160 is disposed on a side of the first through hole 151 away from the second through hole 152, and the data line 160 is spaced apart from the first through hole 151, the fifth The through hole 173 is disposed on a side of the third through hole 171 away from the fourth through hole 172 , and the fifth through hole 173 is spaced apart from the third through hole 171 .
  • the fifth through hole 173 is disposed adjacent to one end of the data line 160 adjacent to the third through hole 171.
  • the passivation layer 170 may be, but not limited to, a silicon nitride (SiNx) material, a silicon oxide (SiOx) material, or a composite layer of a silicon oxide material and a silicon nitride material.
  • the thin film transistor 10 further includes a pixel electrode 190.
  • the pixel electrode 190 is disposed on the passivation layer 170, the pixel electrode 190 is electrically connected to the drain 180b, and the pixel electrode 190 and the drain electrode 180b are integrated.
  • the pixel electrode 190 has a thickness of 300 to 1000 angstroms.
  • the pixel electrode 190 may be, but not limited to, Indium Tin Oxide (ITO).
  • the etch stop layer 150 of the thin film transistor 10 of the present invention covers the semiconductor layer 140, the passivation layer 170 covers the etch stop layer 150, the source electrode 180a and the drain electrode 180b are disposed on the passivation layer 170, and the semiconductor is connected through the corresponding via hole. Both ends of layer 140.
  • the etch stop layer 150 of the thin film transistor 10 of the present invention covers the semiconductor layer 140, and therefore, there is no need to map the etch stop layer.
  • the source 180a and the drain 180b are overlying the passivation layer 170. Therefore, the source 180a and the drain 180b are relatively far from the etch barrier 150, which can effectively reduce the preparation of the source 180a and the drain 180b.
  • the etching solution etches the semiconductor layer 140 at the time.
  • FIG. 2 is a schematic structural diagram of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • the liquid crystal display panel 1 of the present invention includes an array substrate 2, a color filter substrate 3, and a liquid crystal layer 4.
  • the array substrate 2 is disposed opposite to and spaced apart from the color filter substrate 3, and the liquid crystal layer 4 is interposed between the array substrate 2 and the color filter substrate 3.
  • the array substrate 2 includes a plurality of thin film transistors 10 distributed in an array. For the thin film transistor 10, refer to the foregoing description, and details are not described herein again.
  • FIG. 3 is a flowchart of a method for fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • the method of preparing the thin film transistor includes, but is not limited to, the following steps.
  • a substrate 110 is provided.
  • the material of the substrate 110 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • the material of the first metal layer includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, and MoTi.
  • the gate insulating layer 130 includes, but is not limited to, a silicon nitride (SiNx) material, a silicon oxide (SiOx) material, or the like.
  • the semiconductor material is a metal oxide semiconductor material
  • the semiconductor layer 140 is a metal oxide semiconductor layer
  • the metal oxide semiconductor layer may include but is not limited to the following One or more of the materials: a ZnO-based transparent oxide semiconductor material, a SnO 2 -based transparent oxide semiconductor material, an In 2 O 3 -based transparent oxide semiconductor material, or the like.
  • the semiconductor layer 140 may be Indium Gallium Zinc Oxide (IGZO).
  • the etch barrier layer 150 may be, but not limited to, a silicon nitride (SiNx) material, a silicon oxide (SiOx) material, or a composite layer of a silicon oxide material and a silicon nitride material.
  • the method for preparing the thin film transistor further includes step I, which is described in detail below.
  • Step I depositing a second metal layer on the surface of the etch barrier layer 150 away from the semiconductor layer 140, and patterning the second metal layer to form a data line 160.
  • the material of the second metal layer includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, and MoTi.
  • the passivation layer 170 may be, but not limited to, a silicon nitride (SiNx) material, a silicon oxide (SiOx) material, or a composite layer of a silicon oxide material and a silicon nitride material.
  • a through hole is respectively etched on the etching stopper layer 150 and the passivation layer 170 corresponding to both ends of the semiconductor layer 140 to expose both ends of the semiconductor layer 140, and the etching stopper layer 150 corresponds to the
  • the via holes at the two ends of the semiconductor layer 140 are respectively the first through hole 151 and the second through hole 152, and the passivation layer 170 corresponds to the first through hole 151 and is in communication with the first through hole 151.
  • the hole 171 , the passivation layer 170 corresponding to the second through hole 152 and communicating with the second through hole 152 is a fourth through hole 172 .
  • the step S107 comprises a step II, which is described in detail below.
  • Step II corresponding ends of the semiconductor layer 140 are respectively etched through the etching barrier layer 150 and the passivation layer 170 to expose both ends of the semiconductor layer 140, and the etching barrier layer 150 corresponds to
  • the via holes at the two ends of the semiconductor layer 140 are respectively a first through hole 151 and a second through hole 152.
  • the passivation layer 170 corresponds to the first through hole 151 and is in communication with the first through hole 151.
  • the through hole 171, the passivation layer 170 corresponds to the second through hole 152 and communicates with the second through hole 152 as a fourth through hole 172, and the passivation layer 170 corresponds to the data line 160
  • a fifth through hole 173 is opened.
  • Figure 10 please refer to Figure 10.
  • the step S108 specifically includes: depositing a transparent conductive layer on the surface of the passivation layer 170 away from the etch barrier layer 150, and patterning the transparent conductive layer to form through the first through hole 151
  • the third through hole 171 is connected to the source 180a at one end of the semiconductor layer 140, and the drain 180b at the other end of the semiconductor layer 140 is connected through the second through hole 152 and the fourth through hole 172, and
  • a pixel electrode 190 having an integral structure with the drain 180b and electrically connected to the drain 180b.
  • the step S108 includes the step III, and the step III is described in detail below.
  • Step III depositing a transparent conductive layer on the surface of the passivation layer 170 away from the etch barrier layer 150, and patterning the transparent conductive layer to form through the first through hole 151 and the third through hole 171 is connected to the source 180a at one end of the semiconductor layer 140, and the source 180a is electrically connected to the data line 160 through the fifth through hole 173, and through the second through hole 152 and the fourth
  • the through hole 172 is connected to the drain 180b at the other end of the semiconductor layer 140.
  • Figure 11 depositing a transparent conductive layer on the surface of the passivation layer 170 away from the etch barrier layer 150, and patterning the transparent conductive layer to form through the first through hole 151 and the third through hole 171 is connected to the source 180a at one end of the semiconductor layer 140, and the source 180a is electrically connected to the data line 160 through the fifth through hole 173, and through the second through hole 152 and the fourth
  • the through hole 172 is connected to the drain 180b at the other end of the semiconductor layer 140.
  • the method for fabricating the thin film transistor of the present invention deposits an etch barrier layer 150 on the surface of the semiconductor layer 140 away from the gate insulating layer 130, and a passivation layer 170 on the surface of the etch barrier layer 150 away from the semiconductor layer 140, corresponding to both ends of the semiconductor layer 140. Through holes are respectively etched on the etch stop layer 150 and the passivation layer 170 to expose both ends of the semiconductor layer 140.
  • a transparent conductive layer is deposited on the surface of the passivation layer 170 away from the etch barrier layer 150, and the transparent conductive layer is patterned to form a source and a drain.
  • the method for fabricating the thin film transistor of the present invention does not need to increase the patterning of the etch barrier metal after the etch barrier layer is prepared, thereby simplifying the process of the thin film transistor.

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Abstract

一种薄膜晶体管(10)、液晶显示面板(1)及薄膜晶体管(10)的制备方法。薄膜晶体管(10)包括：基板(110)；栅极(120)，设置在基板(110)的表面；栅极绝缘层(130)，覆盖栅极(120)；半导体层（140），设置在栅极绝缘层（130）远离栅极(120)的表面且对应栅极(120)设置；蚀刻阻挡层(150)，覆盖半导体层(140)，蚀刻阻挡层（150）包括第一贯孔（151）及第二贯孔（152），第一贯孔（151）及第二贯孔（152）对应半导体层（140）设置以显露部分半导体层（140）；钝化层（170），覆盖蚀刻阻挡层（150），钝化层（170）包括第三贯孔（171）及第四贯孔（172），第三贯孔（171）对应第一贯孔（151）设置且与第一贯孔（151）连通，第四贯孔（172）对应第二贯孔（152）设置且与第二贯孔（152）连通；源极（180a），设置在钝化层(170)上且通过第一贯孔(151)及第三贯孔(171）连接半导体层(140)的一端；及漏极(180b)，设置在钝化层(170)上，与源极(180a)间隔设置，且通过第二贯孔(152)及第四贯孔(172)连接半导体层(140)的另一端。

Description

薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板
本发明要求2016年3月28日递交的发明名称为“薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板”的申请号201610182409.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板。
背景技术
液晶显示装置，比如，液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。液晶显示器中通常包括阵列基板，阵列基板包括呈陈列状分布的多个薄膜晶体管(Thin Film Transistor，TFT)，薄膜晶体管的质量好坏直接影响到液晶显示面板的质量。现有技术中的薄膜晶体管包括蚀刻阻挡层，在制备蚀刻阻挡层的时候通常需要沉积整层的能够阻挡蚀刻的蚀刻阻挡材料，接着使用光罩工艺，将整层的蚀刻阻挡材料制备成仅仅覆盖部分有源层的蚀刻阻挡层，接着在蚀刻阻挡层上覆盖金属层，并将所述金属层进行图案化以形成源极和漏极，所述蚀刻阻挡层能够防止在后续制备薄膜晶体管的源极和漏极的时候蚀刻液对所述有源层的腐蚀。但是，现有技术中蚀刻阻挡层的图案化进程需要增加一道光罩，从而使得薄膜晶体管的制程较为复杂。
发明内容
本发明提供一种薄膜晶体管，所述薄膜晶体管包括：
基板；
栅极，设置在所述基板的表面；
栅极绝缘层，覆盖所述栅极；
半导体层，设置在所述栅极绝缘层远离所述栅极的表面且对应所述栅极设 置；
蚀刻阻挡层，覆盖所述半导体层，所述蚀刻阻挡层包括第一贯孔及第二贯孔，所述第一贯孔及第二贯孔对应所述半导体层设置以显露部分所述半导体层，且所述第一贯孔及所述第二贯孔间隔设置；
钝化层，覆盖所述蚀刻阻挡层，所述钝化层包括第三贯孔及第四贯孔，所述第三贯孔对应所述第一贯孔设置且与所述第一贯孔连通，所述第四贯孔对应所述第二贯孔设置且与所述第二贯孔连通；
源极，设置在所述钝化层上且通过所述第一贯孔及所述第三贯孔连接所述半导体层的一端；及
漏极，设置在所述钝化层上，与所述源极间隔设置，且通过所述第二贯孔及所述第四贯孔连接所述半导体层的另一端。
其中，所述薄膜晶体管还包括：
像素电极，设置在所述钝化层上，所述像素电极与所述漏极电连接，且所述像素电极与所述漏极为一体结构。
其中，所述薄膜晶体管还包括：
数据线，设置于所述蚀刻阻挡层与所述钝化层之间；
所述钝化层还包括第五贯孔，所述第五贯孔对应所述数据线设置，以露出部分数据线；
所述数据线通过所述第五贯孔与所述源极电连接。
其中，所述栅极包括第一端面、第二端面及第三端面，所述第一端面设置在所述基板上，所述第二端面与所述第三端面相对设置，所述第二端面与所述第一端面相交，所述第三端面与所述第一端面相交，且所述第三端面相较于所述第二端面远离所述数据线设置，所述数据线邻近所述第三贯孔的端面与所述栅极的第二端面之间存在间隙或者共面。
其中，所述数据线设置于所述第一贯孔远离所述第二贯孔的一侧，且所述数据线与所述第一贯孔间隔设置，所述第五贯孔设置在所述第三贯孔远离所述第四贯孔的一侧，且所述第五贯孔与所述第三贯孔间隔设置。
其中，所述第五贯孔对应所述数据线邻近所述第三贯孔的一端设置。
本发明还提供一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法包 括：
提供基板；
在所述基板的表面沉积第一金属层，并将所述第一金属层进行图案化以形成栅极；
在所述栅极上形成覆盖所述栅极的栅极绝缘层；
在所述栅极绝缘层远离所述栅极的表面沉积一层半导体材料，并将所述半导体材料进行图案化以形成对应所述栅极设置的半导体层；
在所述半导体层远离所述栅极绝缘层的表面沉积蚀刻阻挡层；
在所述蚀刻阻挡层远离所述半导体层的表面沉积钝化层；
对应所述半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端，所述蚀刻阻挡层上对应所述半导体层两端的过孔分别为第一贯孔及第二贯孔，所述钝化层对应所述第一贯孔且与所述第一贯孔连通的为第三贯孔，所述钝化层对应所述第二贯孔且与所述第二贯孔连通的为第四贯孔；
在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极。
其中，所述步骤“在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极”包括：
在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极，以及与所述漏极为一体结构且与所述漏极电连接的像素电极。
其中，在所述步骤“在所述半导体层远离所述栅极绝缘层的表面沉积蚀刻阻挡层”与所述步骤“在所述蚀刻阻挡层远离所述半导体层的表面沉积钝化层”之间，所述薄膜晶体管的制备方法还包括：
在所述蚀刻阻挡层远离所述半导体层的表面沉积第二金属层，图案化所述第二金属层，以形成数据线；
所述步骤“对应所述半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端，所述蚀刻阻挡层上对应所述半导体层两端的过孔分别为第一贯孔及第二贯孔，所述钝化层对应所述第一贯孔且与所述第一贯孔连通的为第三贯孔，所述钝化层对应所述第二贯孔且与所述第二贯孔连通的为第四贯孔”包括：
对应所述半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端，所述蚀刻阻挡层上对应所述半导体层两端的过孔分别为第一贯孔及第二贯孔，所述钝化层对应所述第一贯孔且与所述第一贯孔连通的为第三贯孔，所述钝化层对应所述第二贯孔且与所述第二贯孔连通的为第四贯孔，且在所述钝化层对应所述数据线开设第五贯孔；
所述步骤“在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极”包括：
在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，且所述源极通过所述第五贯孔与所述数据线电连接，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极。
本发明还提供一种液晶显示面板，所述液晶显示面板包括前述任意一实施方式所述的薄膜晶体管。
本发明的薄膜晶体管的制备方法在半导体层远离栅极绝缘层的表面沉积蚀刻阻挡层，在蚀刻阻挡层远离半导体层的表面沉积钝化层，对应半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端。在钝化层远离蚀刻阻挡层的表面沉积透明导电层，并图案化透明导电层以形成源极和漏极。相较于现有技术，本发明的薄膜晶体管的制备方法制备出蚀刻阻挡层之后不需要增加光罩对蚀刻阻挡层金属图案化，从而使得薄膜晶体管的制程简化。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。
图2为本发明一较佳实施方式的液晶显示面板的结构示意图。
图3为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。
图4至图11为本发明薄膜晶体管的制备方法的流程中步骤中对应的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。所述薄膜晶体管10包括基板110、栅极120、栅极绝缘层130、半导体层140、蚀刻阻挡层150、钝化层170、源极180a及漏极180b。所述栅极120设置在所述基板110的表面，所述栅极绝缘层130覆盖所述栅极120，所述半导体层140设置在所述栅极绝缘层130远离所述栅极120的表面且对应所述栅极120设置。所述蚀刻阻挡层150覆盖所述半导体层140，所述蚀刻阻挡层150包括第一贯孔151及第二贯孔152。所述第一贯孔151及所述地热贯孔152对应所述半导体层140设置以显露部分所述半导体层140，且所述第一贯孔151及所述第二贯孔152间隔设置。所述钝化层170覆盖所述蚀刻阻挡层150，所述钝化层170包括第三贯孔171及第四贯孔172。所述第三贯孔171对应所述第一贯孔171设置且与所述第一贯孔171连通，所述第四贯孔172对应所述第二贯孔152设置且与所述第二贯孔152连通。所述源极180a设置在所述钝化 层170上且通过所述第一贯孔151及所述第三贯孔171连接所述半导体层140的一端。所述漏极180b设置在所述钝化层170上，与所述源极180a间隔设置，且通过所述第二贯孔152及所述第四贯孔172连接所述半导体层140的另一端。
所述基板110为透明基板，所述基板110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
所述栅极120的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。在一实施方式中，所述栅极120的厚度为1500～6000埃。
所述栅极绝缘层130包括第一子绝缘层131及第二子绝缘层132。所述第一子绝缘层131覆盖所述栅极120，所述第二子绝缘层132覆盖所述第一子绝缘层131。其中，所述第一子绝缘层131包括氮化硅(SiNx)材料，所述第二子绝缘层132包括氧化硅(SiOx)材料。所述第一子绝缘层131采用氮化硅材料，在制备氮化硅材料的时候能够产生氢元素(H)用来修补所述半导体层140，用于提高所述半导体层140的电性能。所述第二子绝缘层132可以改善设置在所述第二子绝缘层132上的半导体层140的应力，以防止所述半导体层140脱落。在一实施方式中，所述绝缘130的厚度可以为1500～4000埃。
所述半导体层140也称为沟道层或者有源层。优选地，所述半导体层140为金属氧化物半导体层，所述金属氧化物半导体层可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。举例而言，所述半导体层140可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
所述蚀刻阻挡层150可以为但不仅限于为氮化硅(SiNx)材料、氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
所述薄膜晶体管10还包括数据线160。所述数据线160设置于所述蚀刻阻挡层150与所述钝化层170之间。相应地，所述钝化层170还包括第五贯孔173，所述第五贯孔173对应所述数据线160设置，以露出部分数据线160。所述数据线160通过所述第五贯孔173与所述源极180a电连接。
所述栅极120包括第一端面121、第二端面122及第三端面123。所述第一端面121设置在所述基板110上，所述第二端面122与所述第三端面123相对设置，所述第二端面122与所述第一端面121相交，所述第三端面123与所述第一端面121相交，且所述第三端面123相较于所述第二端面122远离所述数据线160设置，所述数据线160邻近所述第三贯孔171的端面与所述栅极120的第二端面122之间存在间隙或者共面。所述第一端面121设置在所述基板110上是指，所述栅极120的第一端面121设置在所述基板110邻近所述栅极120的表面上，且所述第一端面121与所述基板110共面。
由于所述数据线160邻近所述第三贯孔171的端面与所述栅极120的第二端面122之间存在间隙或者共面，因此，所述数据线160与所述栅极120之间没有交叠，因此，所述数据线160与所述栅极120之间的寄生电容较小，从而达到了减小所述数据线160一所述栅极120之间的寄生电容的技术效果。
优选地，所述数据线160设置于所述第一贯孔151远离所述第二贯孔152的一侧，且所述数据线160与所述第一贯孔151间隔设置，所述第五贯孔173设置在所述第三贯孔171远离所述第四贯孔172的一侧，且所述第五贯孔173与所述第三贯孔171间隔设置。
优选地，所述第五贯孔173对应所述数据线160邻近所述第三贯孔171的一端设置。
所述钝化层170可以为但不仅限于为氮化硅(SiNx)材料、氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
所述薄膜晶体管10还包括像素电极190。所述像素电极190设置在所述钝化层170上，所述像素电极190与所述漏极180b电连接，且所述像素电极190与所述漏极180b为一体结构。在一实施方式中，所述像素电极190的厚度为300～1000埃。所述像素电极190可以为但不仅限于为氧化铟锡(Indium Tin Oxide，ITO)。
本发明的薄膜晶体管10的蚀刻阻挡层150覆盖半导体层140，钝化层170覆盖所述蚀刻阻挡层150，源极180a和漏极180b设置在钝化层170上，并通过相应贯孔连接半导体层140的两端。相较于现有技术，本发明的薄膜晶体管10的蚀刻阻挡层150覆盖半导体层140，因此，也不需要对蚀刻阻挡层进行图 案化，且源极180a和漏极180b覆盖在钝化层170上，因此，源极180a和漏极180b离蚀刻阻挡层150相对较远，能够有效减小制备源极180a和漏极180b的时候蚀刻液对半导体层140的腐蚀。
本发明还提供了一种液晶显示面板，请参阅图2，图2为本发明一较佳实施方式的液晶显示面板的结构示意图。本发明的液晶显示面板1包括阵列基板2、彩膜基板3及液晶层4。所述阵列基板2与所述彩膜基板3相对且间隔设置，所述液晶层4夹设在所述阵列基板2与所述彩膜基板3之间。所述阵列基板2包括呈阵列状分布的多个薄膜晶体管10，所述薄膜晶体管10请参阅前述描述，在此不再赘述。
下面结合图1及对图1的描述对本发明的薄膜晶体管的制备方法进行介绍。请一并参阅图3，图3为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。所述薄膜晶体管的制备方法包括但不仅限于以下步骤。
S101，提供基板110。所述基板110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
S102，在所述基板110的表面沉积第一金属层，并将所述第一金属层进行图案化以形成栅极120。具体地，请参阅图4，所述第一金属层的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
S103，在所述栅极120上形成覆盖所述栅极120的栅极绝缘层130。具体地，请参阅图5，所述栅极绝缘层130包括但不仅限于氮化硅(SiNx)材料，氧化硅(SiOx)材料等。
S104，在所述栅极绝缘层130远离所述栅极120的表面沉积一层半导体材料，并将所述半导体材料进行图案化以形成对应所述栅极120设置的半导体层140。具体地，请参阅图6，优选地，半导体材料为金属氧化物半导体材料，则，相应地，所述半导体层140为金属氧化物半导体层，所述金属氧化物半导体层可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。举例而言，所述半导体层140可以为铟镓锌氧化物(Indium Gallium Zinc Oxide， IGZO)。
S105，在所述半导体层140远离所述栅极120绝缘层的表面沉积蚀刻阻挡层150。具体地，请参阅图7，所述蚀刻阻挡层150可以为但不仅限于为氮化硅(SiNx)材料、氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
优选地，在步骤S105和步骤S106之间，所述薄膜晶体管的制备方法还包括步骤I，所述步骤I详细描述如下。
步骤I，在所述蚀刻阻挡层150远离所述半导体层140的表面沉积第二金属层，图案化所述第二金属层，以形成数据线160。具体地，请参阅图8，所述第二金属层的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
S106，在所述蚀刻阻挡层150远离所述半导体层140的表面沉积钝化层170。具体地，请参阅图9，所述钝化层170可以为但不仅限于为氮化硅(SiNx)材料、氧化硅(SiOx)材料、或者氧化硅材料与氮化硅材料的复合层。
S107，对应所述半导体层140的两端在所述蚀刻阻挡层150及钝化层170上分别蚀刻出贯孔以露出所述半导体层140的两端，所述蚀刻阻挡层150上对应所述半导体层140两端的过孔分别为第一贯孔151及第二贯孔152，所述钝化层170对应所述第一贯孔151且与所述第一贯孔151连通的为第三贯孔171，所述钝化层170对应所述第二贯孔152且与所述第二贯孔152连通的为第四贯孔172。
相应地，所述步骤S107包括步骤II，所述步骤II详细描述如下。
步骤II，对应所述半导体层140的两端在所述蚀刻阻挡层150及钝化层170上分别蚀刻出贯孔以露出所述半导体层140的两端，所述蚀刻阻挡层150上对应所述半导体层140两端的过孔分别为第一贯孔151及第二贯孔152，所述钝化层170对应所述第一贯孔151且与所述第一贯孔151连通的为第三贯孔171，所述钝化层170对应所述第二贯孔152且与所述第二贯孔152连通的为第四贯孔172，且在所述钝化层170对应所述数据线160开设第五贯孔173。具体地，请参阅图10。
S108，在所述钝化层170远离所述蚀刻阻挡层150的表面沉积透明导电层， 并图案化所述透明导电层，以形成通过所述第一贯孔151及所述第三贯孔171连接所述半导体层140一端的源极180a，以及通过所述第二贯孔152及所述第四贯孔172连接所述半导体层140另一端的漏极180b。
优选地，所述步骤S108具体包括：在所述钝化层170远离所述蚀刻阻挡层150的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔151及所述第三贯孔171连接所述半导体层140一端的源极180a，通过所述第二贯孔152及所述第四贯孔172连接所述半导体层140另一端的漏极180b，以及与所述漏极180b为一体结构且与所述漏极180b电连接的像素电极190。
相应地，所述步骤S108，包括步骤III，所述步骤III详细描述如下。
步骤III，在所述钝化层170远离所述蚀刻阻挡层150的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔151及所述第三贯孔171连接所述半导体层140一端的源极180a，且所述源极180a通过所述第五贯孔173与所述数据线160电连接，以及通过所述第二贯孔152及所述第四贯孔172连接所述半导体层140另一端的漏极180b。具体地，请参阅图11。
本发明的薄膜晶体管的制备方法在半导体层140远离栅极绝缘层130的表面沉积蚀刻阻挡层150，在蚀刻阻挡层150远离半导体层140的表面沉积钝化层170，对应半导体层140的两端在所述蚀刻阻挡层150及钝化层170上分别蚀刻出贯孔以露出所述半导体层140的两端。在钝化层170远离蚀刻阻挡层150的表面沉积透明导电层，并图案化透明导电层以形成源极和漏极。相较于现有技术，本发明的薄膜晶体管的制备方法制备出蚀刻阻挡层之后不需要增加光罩对蚀刻阻挡层金属图案化，从而使得薄膜晶体管的制程简化。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (15)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    栅极，设置在所述基板的表面；
    栅极绝缘层，覆盖所述栅极；
    半导体层，设置在所述栅极绝缘层远离所述栅极的表面且对应所述栅极设置；
    蚀刻阻挡层，覆盖所述半导体层，所述蚀刻阻挡层包括第一贯孔及第二贯孔，所述第一贯孔及第二贯孔对应所述半导体层设置以显露部分所述半导体层，且所述第一贯孔及所述第二贯孔间隔设置；
    钝化层，覆盖所述蚀刻阻挡层，所述钝化层包括第三贯孔及第四贯孔，所述第三贯孔对应所述第一贯孔设置且与所述第一贯孔连通，所述第四贯孔对应所述第二贯孔设置且与所述第二贯孔连通；
    源极，设置在所述钝化层上且通过所述第一贯孔及所述第三贯孔连接所述半导体层的一端；及
    漏极，设置在所述钝化层上，与所述源极间隔设置，且通过所述第二贯孔及所述第四贯孔连接所述半导体层的另一端。
  2. 如权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    像素电极，设置在所述钝化层上，所述像素电极与所述漏极电连接，且所述像素电极与所述漏极为一体结构。
  3. 如权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    数据线，设置于所述蚀刻阻挡层与所述钝化层之间；
    所述钝化层还包括第五贯孔，所述第五贯孔对应所述数据线设置，以露出部分数据线；
    所述数据线通过所述第五贯孔与所述源极电连接。
  4. 如权利要求3所述的薄膜晶体管，其中，所述栅极包括第一端面、第二端面及第三端面，所述第一端面设置在所述基板上，所述第二端面与所述第三端面相对设置，所述第二端面与所述第一端面相交，所述第三端面与所述第一端面相交，且所述第三端面相较于所述第二端面远离所述数据线设置，所述数据线邻近所述第三贯孔的端面与所述栅极的第二端面之间存在间隙或者共面。
  5. 如权利要求3所述的薄膜晶体管，其中，所述数据线设置于所述第一贯孔远离所述第二贯孔的一侧，且所述数据线与所述第一贯孔间隔设置，所述第五贯孔设置在所述第三贯孔远离所述第四贯孔的一侧，且所述第五贯孔与所述第三贯孔间隔设置。
  6. 如权利要求5所述的薄膜晶体管，其中，所述第五贯孔对应所述数据线邻近所述第三贯孔的一端设置。
  7. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括：
    提供基板；
    在所述基板的表面沉积第一金属层，并将所述第一金属层进行图案化以形成栅极；
    在所述栅极上形成覆盖所述栅极的栅极绝缘层；
    在所述栅极绝缘层远离所述栅极的表面沉积一层半导体材料，并将所述半导体材料进行图案化以形成对应所述栅极设置的半导体层；
    在所述半导体层远离所述栅极绝缘层的表面沉积蚀刻阻挡层；
    在所述蚀刻阻挡层远离所述半导体层的表面沉积钝化层；
    对应所述半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端，所述蚀刻阻挡层上对应所述半导体层两端的过孔分别为第一贯孔及第二贯孔，所述钝化层对应所述第一贯孔且与所述第一贯孔连通的为第三贯孔，所述钝化层对应所述第二贯孔且与所述第二贯孔连通的为第四贯孔；
    在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述 透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极。
  8. 如权利要求7所述的薄膜晶体管的制备方法，其中，所述步骤“在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极”包括：
    在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极，以及与所述漏极为一体结构且与所述漏极电连接的像素电极。
  9. 如权利要求7所述的薄膜晶体管的制备方法，其中，在所述步骤“在所述半导体层远离所述栅极绝缘层的表面沉积蚀刻阻挡层”与所述步骤“在所述蚀刻阻挡层远离所述半导体层的表面沉积钝化层”之间，所述薄膜晶体管的制备方法还包括：
    在所述蚀刻阻挡层远离所述半导体层的表面沉积第二金属层，图案化所述第二金属层，以形成数据线；
    所述步骤“对应所述半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端，所述蚀刻阻挡层上对应所述半导体层两端的过孔分别为第一贯孔及第二贯孔，所述钝化层对应所述第一贯孔且与所述第一贯孔连通的为第三贯孔，所述钝化层对应所述第二贯孔且与所述第二贯孔连通的为第四贯孔”包括：
    对应所述半导体层的两端在所述蚀刻阻挡层及钝化层上分别蚀刻出贯孔以露出所述半导体层的两端，所述蚀刻阻挡层上对应所述半导体层两端的过孔分别为第一贯孔及第二贯孔，所述钝化层对应所述第一贯孔且与所述第一贯孔连通的为第三贯孔，所述钝化层对应所述第二贯孔且与所述第二贯孔连通的为 第四贯孔，且在所述钝化层对应所述数据线开设第五贯孔；
    所述步骤“在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极”包括：
    在所述钝化层远离所述蚀刻阻挡层的表面沉积透明导电层，并图案化所述透明导电层，以形成通过所述第一贯孔及所述第三贯孔连接所述半导体层一端的源极，且所述源极通过所述第五贯孔与所述数据线电连接，以及通过所述第二贯孔及所述第四贯孔连接所述半导体层另一端的漏极。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括薄膜晶体管，所述薄膜晶体管包括：
    基板；
    栅极，设置在所述基板的表面；
    栅极绝缘层，覆盖所述栅极；
    半导体层，设置在所述栅极绝缘层远离所述栅极的表面且对应所述栅极设置；
    蚀刻阻挡层，覆盖所述半导体层，所述蚀刻阻挡层包括第一贯孔及第二贯孔，所述第一贯孔及第二贯孔对应所述半导体层设置以显露部分所述半导体层，且所述第一贯孔及所述第二贯孔间隔设置；
    钝化层，覆盖所述蚀刻阻挡层，所述钝化层包括第三贯孔及第四贯孔，所述第三贯孔对应所述第一贯孔设置且与所述第一贯孔连通，所述第四贯孔对应所述第二贯孔设置且与所述第二贯孔连通；
    源极，设置在所述钝化层上且通过所述第一贯孔及所述第三贯孔连接所述半导体层的一端；及
    漏极，设置在所述钝化层上，与所述源极间隔设置，且通过所述第二贯孔及所述第四贯孔连接所述半导体层的另一端。
  11. 如权利要求10所述的液晶显示面板，其中，所述薄膜晶体管还包括：
    像素电极，设置在所述钝化层上，所述像素电极与所述漏极电连接，且所述像素电极与所述漏极为一体结构。
  12. 如权利要求10所述的液晶显示面板，其中，所述薄膜晶体管还包括：
    数据线，设置于所述蚀刻阻挡层与所述钝化层之间；
    所述钝化层还包括第五贯孔，所述第五贯孔对应所述数据线设置，以露出部分数据线；
    所述数据线通过所述第五贯孔与所述源极电连接。
  13. 如权利要求12所述的液晶显示面板，其中，所述栅极包括第一端面、第二端面及第三端面，所述第一端面设置在所述基板上，所述第二端面与所述第三端面相对设置，所述第二端面与所述第一端面相交，所述第三端面与所述第一端面相交，且所述第三端面相较于所述第二端面远离所述数据线设置，所述数据线邻近所述第三贯孔的端面与所述栅极的第二端面之间存在间隙或者共面。
  14. 如权利要求12所述的液晶显示面板，其中，所述数据线设置于所述第一贯孔远离所述第二贯孔的一侧，且所述数据线与所述第一贯孔间隔设置，所述第五贯孔设置在所述第三贯孔远离所述第四贯孔的一侧，且所述第五贯孔与所述第三贯孔间隔设置。
  15. 如权利要求14所述的液晶显示面板，其中，所述第五贯孔对应所述数据线邻近所述第三贯孔的一端设置。
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