WO2017163890A1 - Appareil d'imagerie à semi-conducteurs, procédé de commande d'appareil d'imagerie à semi-conducteurs et dispositif électronique - Google Patents

Appareil d'imagerie à semi-conducteurs, procédé de commande d'appareil d'imagerie à semi-conducteurs et dispositif électronique Download PDF

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Publication number
WO2017163890A1
WO2017163890A1 PCT/JP2017/009366 JP2017009366W WO2017163890A1 WO 2017163890 A1 WO2017163890 A1 WO 2017163890A1 JP 2017009366 W JP2017009366 W JP 2017009366W WO 2017163890 A1 WO2017163890 A1 WO 2017163890A1
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unit
charge
signal
conversion unit
pixel
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PCT/JP2017/009366
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English (en)
Japanese (ja)
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頼人 坂野
元展 鳥居
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ソニー株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present technology relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, and more particularly, to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device that can expand a dynamic range.
  • a time division method is known in which images are taken in time division with different sensitivities and a plurality of images taken in time division are combined.
  • a space division method in which a light receiving element having different sensitivity is provided and a dynamic range is expanded by combining a plurality of images captured by light receiving elements having different sensitivities (see, for example, Patent Document 1). .
  • the dynamic range can be expanded by increasing the number of divisions.
  • the image quality is deteriorated due to the occurrence of artifacts or a decrease in resolution.
  • the present technology makes it possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.
  • the solid-state imaging device includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels.
  • the first electric charge generated by the first photoelectric conversion unit is converted into the first electric charge.
  • a first data signal stored in the voltage converter, and a second data in the state where the first charge is stored in a region where the potentials of the first charge voltage converter and the second charge voltage converter are combined.
  • the drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. It is possible to control to read out the second reset signal in a state where is reset.
  • the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • a third reset signal in a state where the region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset. Can be controlled.
  • a first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and A signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal can be further provided.
  • the signal processing unit uses the first difference signal as a pixel signal of the unit pixel, and the value of the first difference signal Exceeds the first threshold and the value of the second difference signal is equal to or less than a predetermined second threshold, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal When the value of exceeds the second threshold, the third difference signal can be used as the pixel signal of the unit pixel.
  • the signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal.
  • a pixel signal of the unit pixel can be generated by combining the second difference signal and the third difference signal.
  • the drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge
  • the first reset signal is read out in a state in which the transfer gate portion is turned off, and then the first transfer gate portion is turned on to convert the first charge into the first charge-voltage conversion.
  • the first data signal can be read out in a state where the data is transferred to a part, and then the second data signal can be read out in a state where the third transfer gate part is turned on.
  • the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • the data signal can be controlled to be read out.
  • the unit pixel is formed under a fourth transfer gate unit that transfers charges from the second photoelectric conversion unit to the charge storage unit, and under a gate electrode of the fourth transfer gate unit, An overflow path for transferring charges overflowing from the photoelectric conversion unit to the charge storage unit may be further provided.
  • the second photoelectric conversion unit and the charge storage unit can be connected without a transfer gate unit.
  • the counter electrode of the charge storage unit is connected to a variable voltage power source, and the drive unit has a period of reading a signal based on the charge stored in the charge storage unit in a period of storing charge in the charge storage unit, The voltage applied to the counter electrode of the charge storage portion can be lowered.
  • the driving method of the solid-state imaging device includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels.
  • a second transfer gate unit that couples the potential of the charge storage unit, and a third transfer gate unit that couples the potential of the first charge voltage conversion unit and the second charge voltage conversion unit.
  • the imaging device uses the first charge generated by the first photoelectric conversion unit.
  • the first charge is accumulated in a region where the first data signal accumulated in the first charge-voltage converter and the potentials of the first charge-voltage converter and the second charge-voltage converter are combined.
  • Control is performed to read out the second data signal in the state and the third data signal based on the second charge generated by the second photoelectric conversion unit.
  • An electronic apparatus includes a pixel array unit in which a plurality of unit pixels are arranged, and a drive unit that controls the operation of the unit pixel, and the unit pixel includes a first photoelectric conversion unit.
  • a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, a charge accumulation unit that accumulates charges generated by the second photoelectric conversion unit, a first charge voltage conversion unit, A second charge-voltage converter, a first transfer gate that transfers charges from the first photoelectric converter to the first charge-voltage converter, the second charge-voltage converter, and the charge storage
  • a second transfer gate unit that couples the potentials of the first and second charge gates, and a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter.
  • the first charge generated by the photoelectric conversion unit is accumulated in the first charge voltage conversion unit.
  • a first data signal in a stored state a second data signal in a state in which the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and
  • a solid-state imaging device that controls to read out a third data signal based on the second charge generated by the second photoelectric conversion unit, and a signal processing device that processes a signal from the solid-state imaging device.
  • the first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first data signal, A second data signal in a state where the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and a second data signal generated by the second photoelectric conversion unit.
  • a third data signal based on the charge of 2 is read out.
  • the present technology it is possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.
  • FIG. 1 is a system configuration diagram illustrating an outline of a configuration of a CMOS image sensor to which the present technology is applied. It is a system configuration
  • FIG. 6 is a timing chart for explaining a second operation example at the start of exposure of the unit pixel of FIG. 4.
  • FIG. 5 is a timing chart for explaining a second operation example at the time of reading the unit pixel of FIG. 4.
  • FIG. It is a circuit diagram showing an example of composition of a unit pixel in a 2nd embodiment of this art.
  • 10 is a timing chart for explaining an operation example at the start of exposure of the unit pixel of FIG. 9.
  • 10 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 9.
  • FIG. 13 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 12. It is a circuit diagram showing an example of composition of a unit pixel in a 4th embodiment of this art. 16 is a timing chart for explaining an operation example at the start of exposure of the unit pixel in FIG. 15. 16 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 15. It is an incident light quantity-output characteristic diagram for explanation of signal processing. It is a figure which shows the usage example of a solid-state imaging device. It is a block diagram which shows the structural example of an electronic device. It is a block diagram which shows an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.
  • FIG. 1 is a system configuration diagram showing an outline of the configuration of a solid-state imaging device to which the present technology is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device.
  • the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.
  • a CMOS image sensor 10 includes a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 11. It has a configuration.
  • the peripheral circuit unit includes, for example, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, and a system control unit 15.
  • the CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19.
  • the signal processing unit 18 and the data storage unit 19 may be mounted on the same substrate as the CMOS image sensor 10 or may be disposed on a different substrate from the CMOS image sensor 10.
  • Each processing of the signal processing unit 18 and the data storage unit 19 may be processing by an external signal processing unit provided on a substrate different from the CMOS image sensor 10, for example, a DSP (Digital Signal Processor) circuit or software. Absent.
  • DSP Digital Signal Processor
  • the pixel array unit 11 includes unit pixels (hereinafter also simply referred to as “pixels”) having a photoelectric conversion unit that generates and accumulates charges according to the received light amount in the row direction and the column direction, that is, The configuration is two-dimensionally arranged in a matrix.
  • the row direction refers to the pixel arrangement direction (that is, the horizontal direction) of the pixel row
  • the column direction refers to the pixel arrangement direction (that is, the vertical direction) of the pixel column. Details of the specific circuit configuration and pixel structure of the unit pixel will be described later.
  • the pixel drive lines 16 are wired along the row direction for each pixel row, and the vertical signal lines 17 are wired along the column direction for each pixel column in the matrix pixel array. .
  • the pixel drive line 16 transmits a drive signal for driving when reading a signal from the pixel.
  • the pixel drive line 16 is shown as one wiring, but is not limited to one.
  • One end of the pixel drive line 16 is connected to an output end corresponding to each row of the vertical drive unit 12.
  • the vertical drive unit 12 is configured by a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 11 at the same time or in units of rows. That is, the vertical drive unit 12 constitutes a drive unit that controls the operation of each pixel of the pixel array unit 11 together with the system control unit 15 that controls the vertical drive unit 12.
  • the vertical drive unit 12 is not shown in the figure for its specific configuration, but generally has a configuration having two scanning systems, a reading scanning system and a sweeping scanning system.
  • the readout scanning system selectively scans the unit pixels of the pixel array unit 11 in units of rows in order to read out signals from the unit pixels.
  • the signal read from the unit pixel is an analog signal.
  • the sweep-out scanning system performs sweep-out scanning on the readout line on which readout scanning is performed by the readout scanning system prior to the readout scanning by the exposure time.
  • a so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system.
  • the electronic shutter operation refers to an operation in which the electric charge in the photoelectric conversion unit is discarded and exposure is newly started (charge accumulation is started).
  • the signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation.
  • the period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the charge exposure period in the unit pixel.
  • a signal output from each unit pixel of the pixel row selectively scanned by the vertical driving unit 12 is input to the column processing unit 13 through each of the vertical signal lines 17 for each pixel column.
  • the column processing unit 13 performs predetermined signal processing on signals output from the pixels in the selected row through the vertical signal line 17 for each pixel column of the pixel array unit 11, and temporarily outputs the pixel signals after the signal processing. Hold on.
  • the column processing unit 13 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing as signal processing.
  • CDS Correlated Double Sampling
  • DDS Double Data Sampling
  • the CDS process removes pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel.
  • the column processing unit 13 may have, for example, an AD (analog-digital) conversion function to convert an analog pixel signal into a digital signal and output the digital signal.
  • AD analog-digital
  • the horizontal drive unit 14 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 13. By the selective scanning by the horizontal driving unit 14, pixel signals subjected to signal processing for each unit circuit in the column processing unit 13 are sequentially output.
  • the system control unit 15 includes a timing generator that generates various timing signals, and the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on various timings generated by the timing generator. Drive control is performed.
  • the signal processing unit 18 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing unit 13.
  • the data storage unit 19 temporarily stores data necessary for the signal processing in the signal processing unit 18.
  • CMOS image sensor 10 to which the present technology is applied is not limited to the system configuration described above. Examples of other system configurations include the following system configurations.
  • the data storage unit 19 is arranged at the subsequent stage of the column processing unit 13, and the pixel signal output from the column processing unit 13 is supplied to the signal processing unit 18 via the data storage unit 19.
  • a CMOS image sensor 10A having a system configuration.
  • the column processing unit 13 is provided with an AD conversion function for performing AD conversion for each column or a plurality of columns of the pixel array unit 11, and a data storage unit is provided for the column processing unit 13. 19 and a CMOS image sensor 10B having a system configuration in which the signal processing unit 18 is provided in parallel.
  • FIG. 4 is a circuit diagram illustrating a configuration example of the unit pixel 100A arranged in the pixel array unit 11 of FIGS.
  • the unit pixel 100A includes a first photoelectric conversion unit 101a, a second photoelectric conversion unit 101b, a first transfer gate unit 102a to a fourth transfer gate unit 102d, a reset gate unit 103, a charge storage unit 104, and a first FD (floating diffusion) unit.
  • 105 a a second FD (floating diffusion) portion 105 b, an amplification transistor 106, and a selection transistor 107.
  • a plurality of drive lines are wired for each pixel row as the pixel drive lines 16 in FIGS. 1 to 3 with respect to the unit pixel 100A, for example.
  • Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical drive unit 12 of FIGS. 1 to 3 through a plurality of drive lines. These drive signals are pulses in which each of the transistors of the unit pixel 100A is an NMOS transistor, so that a high level (for example, power supply voltage VDD) is an active state and a low level (for example, a negative potential) is inactive. Signal.
  • VDD power supply voltage
  • the first photoelectric conversion unit 101a is composed of, for example, a PN junction photodiode.
  • the 1st photoelectric conversion part 101a produces
  • the second photoelectric conversion unit 101b is formed of, for example, a PN junction photodiode, similarly to the first photoelectric conversion unit 101a.
  • the second photoelectric conversion unit 101b generates and accumulates charges corresponding to the received light amount.
  • the first photoelectric conversion unit 101a Comparing the first photoelectric conversion unit 101a and the second photoelectric conversion unit 101b, the first photoelectric conversion unit 101a has a larger light receiving surface area and higher sensitivity, and the second photoelectric conversion unit 101b has a light receiving surface area. Is narrow and has low sensitivity.
  • the first transfer gate unit 102a is connected between the first photoelectric conversion unit 101a and the first FD unit 105a.
  • a drive signal TGL is applied to the gate electrode of the first transfer gate portion 102a.
  • the drive signal TGL becomes active, the first transfer gate unit 102a becomes conductive, and the charge accumulated in the first photoelectric conversion unit 101a is transferred to the first FD unit 105a via the first transfer gate unit 102a. Is done.
  • the second transfer gate portion 102b is connected between the charge storage portion 104 and the second FD portion 105b.
  • a drive signal FCG is applied to the gate electrode of the second transfer gate portion 102b.
  • the drive signal FCG becomes active, the second transfer gate portion 102b becomes conductive, and the potentials of the charge storage portion 104 and the second FD portion 105b are coupled.
  • the third transfer gate unit 102c is connected between the first FD unit 105a and the second FD unit 105b.
  • a drive signal FDG is applied to the gate electrode of the third transfer gate portion 102c.
  • the third transfer gate portion 102c becomes conductive, and the potentials of the first FD portion 105a and the second FD portion 105b are coupled.
  • the fourth transfer gate unit 102d is connected between the second photoelectric conversion unit 101b and the charge storage unit 104.
  • a drive signal TGS is applied to the gate electrode of the fourth transfer gate portion 102d.
  • the fourth transfer gate unit 102d becomes conductive, and the charge accumulated in the second photoelectric conversion unit 101b is transferred to the charge accumulation unit 104 via the fourth transfer gate unit 102d. Transferred.
  • the lower part of the gate electrode of the fourth transfer gate portion 102d has a slightly deep potential, and the charge that exceeds the saturation charge amount of the second photoelectric conversion portion 101b and overflows from the second photoelectric conversion portion 101b is stored in the charge storage portion.
  • An overflow path to be transferred to 104 is formed.
  • the overflow path formed below the gate electrode of the fourth transfer gate portion 102d is simply referred to as the overflow path of the fourth transfer gate portion 102d.
  • the reset gate unit 103 is connected between the power supply VDD that supplies the power supply voltage VDD and the second FD unit 105b.
  • a drive signal RST is applied to the gate electrode of the reset gate portion 103.
  • the reset gate unit 103 becomes conductive. Thereby, for example, the potential of the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined, or the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is Reset to the level of voltage VDD.
  • the charge storage unit 104 is made of a capacitor, for example, and the counter electrode of the charge storage unit 104 is connected between the power supply VDD.
  • the charge storage unit 104 stores the charge transferred from the second photoelectric conversion unit 101b.
  • the first FD unit 105a and the second FD unit 105b convert the charge into a voltage signal and output it.
  • the amplification transistor 106 has a gate electrode connected to the first FD unit 105a, a drain electrode connected to the power supply VDD, and a readout circuit that reads out the charge held in the first FD unit 105a, a so-called source follower circuit input unit and Become. That is, the amplification transistor 106 forms a source follower circuit with the constant current source 108 connected to one end of the vertical signal line 17 by connecting the source electrode to the vertical signal line 17 via the selection transistor 107.
  • the selection transistor 107 is connected between the source electrode of the amplification transistor 106 and the vertical signal line 17.
  • a drive signal SEL is applied to the gate electrode of the selection transistor 107.
  • the drive signal SEL becomes active, the selection transistor 107 becomes conductive and the unit pixel 100A becomes selected.
  • the pixel signal output from the amplification transistor 106 is output to the vertical signal line 17 via the selection transistor 107.
  • each drive signal is in an active state, each drive signal is turned on, and each drive signal is in an inactive state, each drive signal is also turned off.
  • each gate portion or each transistor is turned on, each gate portion or each transistor may be turned on, and each gate portion or each transistor is turned off. It is also said that the transistor is turned off.
  • FIG. 5 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.
  • the horizontal synchronization signal XHS is input, and the exposure processing of the unit pixel 100A starts.
  • the drive signals RST and FDG are turned on, and the reset gate unit 103 and the third transfer gate unit 102c are turned on.
  • the potentials of the first FD portion 105a and the second FD portion 105b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.
  • the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on.
  • the electric charge accumulated in the first photoelectric conversion unit 101a is transferred to the region where the potentials of the first FD unit 105a and the second FD unit 105b are coupled via the first transfer gate unit 102a.
  • the unit 101a is reset.
  • the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, accumulation of electric charges in the first photoelectric conversion unit 101a is started, and an exposure period is started.
  • the drive signals TGS and FCG are turned on, and the fourth transfer gate unit 102d and the second transfer gate unit 102b are turned on.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled.
  • the charge accumulated in the second photoelectric conversion unit 101b is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.
  • the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, accumulation of electric charges in the second photoelectric conversion unit 101b is started.
  • the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off.
  • the charge accumulation unit 104 starts accumulating charges that overflow from the second photoelectric conversion unit 101b and are transferred through the overflow path of the fourth transfer gate unit 102d.
  • the drive signals RST and FDG are turned off, and the reset gate unit 103 and the third transfer gate unit 102c are turned off.
  • the horizontal synchronization signal XHS is input.
  • FIG. 6 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.
  • the horizontal synchronization signal XHS is input, and the readout period of the unit pixel 100A starts.
  • the drive signals SEL, RST, and FDG are turned on, and the selection transistor 107, the reset gate unit 103, and the third transfer gate unit 102c are turned on.
  • the unit pixel 100A is selected.
  • the potentials of the first FD portion 105a and the second FD portion 105b are combined, and the potential of the combined region is reset to the level of the power supply voltage VDD.
  • the drive signal RST is turned off, and the reset gate unit 103 is turned off.
  • a signal NH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107.
  • the signal NH2 is a signal based on a potential in a reset state of a region where the potentials of the first FD unit 105a and the second FD unit 105b are combined.
  • the signal NH2 is also referred to as a high-sensitivity reset signal NH2.
  • the drive signal FDG is turned off and the third transfer gate unit 102c is turned off. Thereby, the potential coupling between the first FD part 105a and the second FD part 105b is canceled.
  • the signal NH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107.
  • the signal NH1 is a signal based on the potential in the reset state of the first FD unit 105a.
  • the signal NH1 is also referred to as a high-sensitivity reset signal NH1.
  • the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on. Thereby, the charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is transferred to the first FD unit 105a via the first transfer gate unit 102a.
  • the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, the transfer of charge from the first photoelectric conversion unit 101a to the first FD unit 105a is stopped.
  • a signal SH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107.
  • the signal SH1 is a signal based on the potential of the first FD unit 105a in a state where the electric charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is accumulated in the first FD unit 105a.
  • the signal SH1 is also referred to as a high sensitivity data signal SH1.
  • the drive signals FDG and TGL are turned on, and the third transfer gate unit 102c and the first transfer gate unit 102a are turned on.
  • the potentials of the first FD unit 105a and the second FD unit 105b are combined, and the charge remaining in the first photoelectric conversion unit 101a without being transferred between the time t25 and the time t26 passes through the first transfer gate unit 102a.
  • the high-sensitivity data signal SH1 since the capacity for charge-voltage conversion is small with respect to the amount of charge handled, there is no problem even if charges remain in the first photoelectric conversion unit 101a.
  • the charge remaining in the first photoelectric conversion unit 101a only needs to be transferred when the high-sensitivity data signal SH2 is read, and the charge is not damaged in the first photoelectric conversion unit 101a.
  • the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off.
  • the first transfer gate unit 102a is turned off.
  • transfer of charges from the first photoelectric conversion unit 101a to the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined is stopped.
  • the signal SH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107. Output on line 17.
  • the signal SH2 is generated by the first photoelectric conversion unit 101a during the exposure period, and the accumulated electric charge is accumulated in the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined. It becomes a signal based on.
  • the capacity for charge-voltage conversion at the time of reading the signal SH2 is the capacity of the first FD portion 105a and the second FD portion 105b, and is larger than that at the time of reading the high sensitivity data signal SH1 at time tc.
  • the signal SH2 is also referred to as a high-sensitivity data signal SH2.
  • the drive signal RST is turned on and the reset gate unit 103 is turned on.
  • the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is reset to the level of the power supply voltage VDD.
  • the drive signal SEL is turned off and the selection transistor 107 is turned off.
  • the unit pixel 100A enters a non-selected state.
  • the drive signal RST is turned off, and the reset gate unit 103 is turned off.
  • the drive signals SEL, TGS, and FCG are turned on, and the selection transistor 107, the fourth transfer gate unit 102d, and the second transfer gate unit 102b are turned on.
  • the unit pixel 100A is selected.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges stored in the second photoelectric conversion unit 101b are transferred to the combined region.
  • charges accumulated in the second photoelectric conversion unit 101b and the charge accumulation unit 104 during the exposure period are accumulated in the combined region.
  • the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, the transfer of charge from the second photoelectric conversion unit 101b is stopped.
  • the signal SL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected by the amplification transistor 106 and the selection transistor 106.
  • the signal is output to the vertical signal line 17 through the transistor 107.
  • the signal SL is generated by the second photoelectric conversion unit 101b during the exposure period, and the charges accumulated in the second photoelectric conversion unit 101b and the charge storage unit 104 are converted into the charge storage unit 104, the first FD unit 105a, and the second FD.
  • the signal is based on the potential of the coupled region in the state where the potential of the portion 105b is accumulated in the coupled region. Therefore, the capacity for charge-voltage conversion at the time of reading the signal SL is a total capacity of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b. This capacity is larger than when reading the high sensitivity data signal SH1 at time tc and when reading the high sensitivity data signal SH2 at time td.
  • the signal SL is also referred to as a low-sensitivity data signal SL.
  • the drive signal RST is turned on and the reset gate unit 103 is turned on. Thereby, the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is reset.
  • the drive signals SEL and FCG are turned off, and the selection transistor 107 and the second transfer gate unit 102b are turned off.
  • the unit pixel 100A enters a non-selected state.
  • the potential of the charge storage unit 104 is separated from the potentials of the first FD unit 105a and the second FD unit 105b.
  • the drive signal RST is turned off, and the reset gate unit 103 is turned off.
  • the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potential of the charge storage unit 104 is combined with the potentials of the first FD unit 105a and the second FD unit 105b.
  • the signal NL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected from the amplification transistor 106 and the selection transistor 106.
  • the signal is output to the vertical signal line 17 through the transistor 107.
  • This signal NL is a signal based on a potential in a reset state of a region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined.
  • the signal NL is also referred to as a low-sensitivity reset signal NL.
  • the drive signals SEL, FDG, and FCG are turned off, and the selection transistor 107, the third transfer gate unit 102c, and the second transfer gate unit 102b are turned off.
  • the unit pixel 100A enters a non-selected state. Further, the potential coupling of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b is eliminated.
  • the horizontal synchronization signal XHS is input, and the readout period of the pixel signal of the unit pixel 100A ends.
  • the drive signal RST does not need to be turned on at time t22 as in the example of FIG. 6 because the drive signal RST is kept turned on at the start of exposure. Further, the drive signal RST is kept on after being turned on at time t34.
  • FIG. 9 is a circuit diagram illustrating a configuration example of a unit pixel 100B that is a modification of the unit pixel 100A of FIG.
  • portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d.
  • FIG. 10 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.
  • the drive signal FCG is turned on, and the second transfer gate unit 102b is turned on.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled.
  • the charge accumulated in the charge accumulation unit 104 is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.
  • the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off.
  • the charge accumulation unit 104 starts accumulating the charge transferred from the second photoelectric conversion unit 101b.
  • time t7 and time t8 operations similar to those at time t8 and time t9 in FIG. 5 are performed.
  • FIG. 11 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.
  • the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on.
  • the unit pixel 100A is selected.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges generated in the second photoelectric conversion unit 101b and accumulated in the charge storage unit 104 during the exposure period are Accumulated in the combined area.
  • the fourth transfer gate portion 102d is deleted, the area efficiency of the arrangement of each element constituting the unit pixel 100B is improved. For example, it is possible to increase the area of the light receiving surface of the first photoelectric conversion unit 101a and improve the sensitivity of the first photoelectric conversion unit 101a.
  • FIG. 12 is a circuit diagram illustrating a configuration example of the unit pixel 100C arranged in the pixel array unit 11 of FIGS.
  • portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the connection position of the counter electrode of the charge storage unit 104 is different. That is, the unit pixel 100C is different in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD.
  • the power supply voltage FCVDD of the variable voltage power supply FCVDD is set to, for example, a high level voltage FCH or a low level voltage FCL.
  • the voltage FCH is set to substantially the same level as the power supply voltage VDD
  • the voltage FCL is set to a predetermined intermediate potential.
  • FIG. 13 shows a timing chart of the horizontal synchronization signal XHS, drive signals SEL, RST, FDG, TGL, TGS, FCG, and power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2
  • the state set to the voltage FCH is maintained, and at the time t8, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • FIG. 14 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, FCG, and the power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t38, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • the power supply voltage FCVDD is set to the voltage FCH only at the start of exposure and at the time of reading, and the period in which charges are accumulated in the charge accumulating unit 104 from the start of exposure to the start of reading.
  • the power supply voltage FCVDD is set to the voltage FCL.
  • FIG. 15 is a circuit diagram illustrating a configuration example of the unit pixel 100D arranged in the pixel array unit 11 of FIGS. 1 to 3.
  • portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the unit pixel 100D is different from the unit pixel 100C in FIG. 12 in that the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d. Further, the unit pixel 100D is different from the unit pixel 100B in FIG. 9 in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD.
  • FIG. 16 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2
  • the state set to the voltage FCH is maintained, and at the time t7, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • FIG. 17 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t37, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • the power supply voltage FCVDD is set to the voltage FCL during the period in which charges are accumulated in the charge accumulation unit 104 from the start of exposure to the start of reading.
  • DDS processing that does not remove reset noise but removes fixed pattern noise peculiar to the pixel such as threshold variation of amplification transistors in the pixel.
  • CDS processing is performed to remove pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel.
  • the processing example 1 is an arithmetic processing that does not require the use of a frame memory, there are advantages that the circuit configuration can be simplified and the cost can be reduced.
  • a storage means for example, a frame memory is required. Accordingly, the arithmetic processing of the processing example 2 is performed, for example, by using the data storage unit 19 as a storage unit in the signal processing unit 18 or using a frame memory in an external DSP circuit.
  • the CDS process for removing the fixed pattern noise unique to the pixel such as the reset noise and the threshold variation of the amplification transistor in the pixel is performed for the low-sensitivity signals SL and NL.
  • the signal processing unit 18 sets the ratio of the high sensitivity difference signal SNH2 to the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color, A gain table is generated by calculating as a gain for every specific pixel in the unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the high sensitivity difference signal SNH2 and the gain table as a correction value for the high sensitivity difference signal SNH2.
  • the gain is G1 and the correction value of the high sensitivity difference signal SNH2 (hereinafter referred to as a correction high sensitivity difference signal) is SNH2 ′
  • the gain G and the correction high sensitivity difference signal SNH2 ′ are expressed by the following equation (1): It can be determined based on (2).
  • Cfd1 is a capacitance value of the first FD unit 105a
  • Cfd2 is a capacitance value of the second FD unit 105b. Therefore, the gain G1 is equivalent to the capacitance ratio of charge-voltage conversion when the high sensitivity data signal SH2 and the high sensitivity reset signal NH2 are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.
  • the signal processing unit 18 shares the ratio of the low sensitivity difference signal SNL and the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color.
  • a gain table is generated by calculating as a gain for each specific pixel in a pixel unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the low sensitivity difference signal SNL and the gain table as a correction value for the low sensitivity difference signal SNL.
  • the gain G and the corrected low sensitivity difference signal SNL ′ are expressed by the following equation (3): It can be determined based on (4).
  • Cfc is a capacitance value of the charge storage unit 104. Therefore, the gain G2 is equivalent to the capacitance ratio of charge-voltage conversion when the low sensitivity data signal SL and the low sensitivity reset signal NL are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.
  • the signal processing unit 18 uses predetermined threshold values Vt1 and Vt2 set in advance.
  • the threshold value Vt1 is set in advance in a region where the high sensitivity difference signal SNH1 is saturated and the optical response characteristic is linear in the optical response characteristic.
  • the threshold value Vt2 is set in advance in a region where the high sensitivity difference signal SNH2 is saturated and the light response characteristic is linear in the light response characteristic.
  • FIG. 18 is a graph showing how the pixel signal SN is switched when the high-sensitivity differential signal SNH2 is not used and when it is used.
  • 18A is a graph when the high-sensitivity difference signal SNH2 is not used
  • FIG. 18B is a graph when the high-sensitivity difference signal SNH2 is used.
  • the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL ′).
  • the S / N ratio is greatly reduced and the image quality is deteriorated.
  • the pixel signal SN is switched to the high sensitivity difference signal SNH2 (more precisely, the corrected high sensitivity difference signal SNH2 ′). It is done.
  • the value of the high-sensitivity difference signal SNH2 with respect to the light amount at the time of switching is larger than the value of the low-sensitivity difference signal SNL with respect to the same light amount, so that the decrease in the SN ratio is suppressed and the image quality is kept good.
  • the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL ').
  • the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching is larger than the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching when the high sensitivity difference signal SNH2 is not used, and the decrease in the SN ratio is suppressed. The image quality is kept good.
  • the signal processing unit 18 combines the corrected high-sensitivity difference signal SNH2 ′ and the high-sensitivity difference signal SNH1 at a preset ratio within a predetermined range, and the pixel signal Output as SN. Further, the signal processing unit 18 synthesizes the corrected low-sensitivity difference signal SNL ′ and the corrected high-sensitivity difference signal SNH2 ′ at a preset ratio so that the pixel signal SN Output as.
  • the signal processing unit 18 performs the correction high-sensitivity difference step by step as in the following formulas (5) to (11) within the range before and after the high-sensitivity difference signal SNH1 with the threshold value Vt1 as a reference.
  • the synthesis ratio of the signal SNH2 ′ and the high sensitivity difference signal SNH1 is changed.
  • the signal processing unit 18 uses the threshold value Vt2 as a reference, and the corrected low-sensitivity difference step by step as in the following formulas (11) to (17) within the range before and after the high-sensitivity difference signal SNH2
  • the synthesis ratio of the signal SNL ′ and the corrected high sensitivity difference signal SNH2 ′ is changed.
  • the level at which the low-sensitivity data signal SL is saturated can be raised by providing the charge storage unit 104 for the low-sensitivity second photoelectric conversion unit 101b.
  • the maximum value of the dynamic range can be increased while the minimum value of the dynamic range is maintained, and the dynamic range can be expanded.
  • LED flicker in which a blinking subject such as an LED light source cannot be imaged at the blinking timing.
  • This LED flicker occurs, for example, because the dynamic range of a conventional image sensor is low and it is necessary to adjust the exposure time for each subject.
  • the exposure time is long for low-illuminance subjects and the exposure time is short for high-illuminance subjects. Thereby, it is possible to deal with subjects with various illuminances even in a low dynamic range.
  • the readout speed is constant regardless of the exposure time, when the exposure time is set in a unit shorter than the readout time, light incident on the photoelectric conversion unit other than the exposure time is photoelectrically converted into electric charges. , Discarded without being read.
  • the dynamic range can be expanded as described above, and the exposure time can be set long, so that the occurrence of LED flicker can be suppressed.
  • CMOS image sensors 10, 10A, and 10B as described above, it is possible to prevent the occurrence of artifacts and the reduction in resolution that occur when the number of divisions is increased by the time division method or the space division method.
  • the signal is read twice from the high-sensitivity first photoelectric conversion unit 101a by switching the charge-voltage conversion capacitor, and by using two types of high-sensitivity signals, the SN at the time of signal switching is changed. A decrease in the ratio can be suppressed.
  • the signal may be switched by comparing the low sensitivity difference signal SNL with a threshold value.
  • the charge storage unit may be provided in at least the photoelectric conversion unit having the lowest sensitivity without providing the charge storage unit in the photoelectric conversion unit having the highest sensitivity. Further, it is only necessary to read out a signal to at least the photoelectric conversion unit having the highest sensitivity by switching the charge-voltage conversion capacitor twice. Further, if this condition is satisfied, it is possible to provide two or more photoelectric conversion units having the same sensitivity.
  • the signal readout for the same photoelectric conversion unit may be performed by three or more different charge-voltage conversion capacitors.
  • the high-sensitivity reset signal NH2 the high-sensitivity reset signal NH1, the high-sensitivity data signal SH1, and the high-sensitivity data signal SH2 are read.
  • the reading order of the low sensitivity data signal SL and the low sensitivity reset signal NL can be reversed.
  • the present invention is applied to a CMOS image sensor in which unit pixels are arranged in a matrix.
  • the present technology is not limited to application to a CMOS image sensor. That is, the present technology can be applied to all XY address type solid-state imaging devices in which unit pixels are two-dimensionally arranged in a matrix.
  • the present technology is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but a solid-state that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. Applicable to all imaging devices.
  • the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.
  • FIG. 19 is a diagram illustrating a usage example of the above-described solid-state imaging device.
  • the solid-state imaging device described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
  • Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
  • Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
  • Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
  • Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports, such as action cameras and wearable cameras for sports applications, etc.
  • Equipment used for agriculture such as cameras for monitoring the condition of fields and crops
  • FIG. 20 is a block diagram illustrating a configuration example of an imaging apparatus (camera apparatus) 400 that is an example of an electronic apparatus to which the present technology is applied.
  • the imaging apparatus 400 includes an optical system including a lens group 401, an imaging element 402, a DSP circuit 403 that is a camera signal processing unit, a frame memory 404, a display device 405, a recording device 406, and an operation system 407. And a power supply system 408 and the like.
  • the DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, the operation system 407, and the power supply system 408 are connected to each other via a bus line 409.
  • the lens group 401 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 402.
  • the imaging element 402 converts the amount of incident light imaged on the imaging surface by the lens group 401 into an electrical signal in units of pixels and outputs it as a pixel signal.
  • the display device 405 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 402.
  • the recording device 406 records the moving image or still image captured by the image sensor 402 on a recording medium such as a memory card, a video tape, or a DVD (Digital Versatile Disk).
  • the operation system 407 issues operation commands for various functions of the imaging apparatus 400 under the operation of the user.
  • the power supply system 408 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, and the operation system 407 to these supply targets.
  • Such an imaging apparatus 400 is applied to a camera module for a mobile device such as a video camera, a digital still camera, and a smartphone or a mobile phone.
  • the solid-state imaging apparatus according to each of the above-described embodiments can be used as the imaging element 402. Thereby, the image quality of the imaging device 400 can be improved.
  • the technology according to the present disclosure is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. It may be realized as a device.
  • FIG. 21 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp.
  • the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted.
  • the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image.
  • the vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light.
  • the imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
  • the vehicle interior information detection unit 12040 detects vehicle interior information.
  • a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
  • the microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
  • the sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 22 is a diagram illustrating an example of an installation position of the imaging unit 12031.
  • the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100.
  • the imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100.
  • the forward images acquired by the imaging units 12101 and 12105 are mainly used for detection of a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 22 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100).
  • a predetermined speed for example, 0 km / h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
  • the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles.
  • the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining.
  • the audio image output unit 12052 When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to be superimposed and displayed.
  • voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
  • the technology according to the present disclosure may be applied to the imaging unit 12031, for example.
  • the CMOS image sensor 10 to the CMOS image sensor 10B in FIGS. 1 to 3 can be applied to the imaging unit 12031.
  • the dynamic range of the imaging unit 12031 can be expanded. As a result, for example, generation of LED flicker, generation of artifacts, reduction in resolution, and the like can be suppressed.
  • the present technology can take the following configurations.
  • the unit pixel is A first photoelectric conversion unit;
  • a second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
  • a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
  • the driving unit includes a first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge voltage conversion unit, the first charge voltage conversion unit, and the first charge voltage conversion unit.
  • a second data signal in a state where the first charge is accumulated in a region where the potentials of the two charge-voltage conversion units are combined, and a third charge based on the second charge generated by the second photoelectric conversion unit.
  • a solid-state imaging device that controls to read data signals.
  • the drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined.
  • the solid-state imaging device according to (1) wherein control is performed so as to read a second reset signal in a reset state.
  • the driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • a data signal is read out, and a third reset signal in a state in which a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset is read out.
  • the solid-state imaging device according to (2) A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and The solid-state imaging device according to (3), further including a signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal.
  • the signal processing unit uses the first difference signal as a pixel signal of the unit pixel when the value of the first difference signal is equal to or less than a predetermined first threshold, and the value of the first difference signal is When the first threshold value is exceeded and the value of the second difference signal is less than or equal to a predetermined second threshold value, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal.
  • the signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal,
  • the drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge voltage conversion unit In a state where the transfer gate portion is in a non-conducting state, the first reset signal is read, then the first transfer gate portion is brought into a conducting state, and the first charge is converted into the first charge-voltage converting portion The first data signal is read in the state transferred to, and then the second data signal is read in the state where the third transfer gate portion is turned on.
  • the solid-state imaging device according to any one of (6).
  • the driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • the unit pixel is A fourth transfer gate section for transferring charges from the second photoelectric conversion section to the charge storage section; An overflow path formed under the gate electrode of the fourth transfer gate portion and transferring the charge overflowing from the second photoelectric conversion portion to the charge storage portion;
  • the solid-state imaging device according to any one of the above.
  • the first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit.

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  • Physics & Mathematics (AREA)
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  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention concerne un appareil d'imagerie à semi-conducteurs pouvant étendre la plage dynamique de l'appareil d'imagerie à semi-conducteurs tout en supprimant la détérioration de la qualité d'image, un procédé de commande de l'appareil d'imagerie à semi-conducteurs et un dispositif électronique. L'appareil d'imagerie à semi-conducteurs exécute une commande pour lire : un premier signal de données dans un état dans lequel une première charge générée par une première unité de conversion photoélectrique est mémorisée dans une première unité de conversion de tension de charge ; un deuxième signal de données dans un état dans lequel la première charge est mémorisée dans une zone dans laquelle les potentiels de la première unité de conversion de tension de charge et d'une deuxième unité de conversion de tension de charge sont couplés ; et un troisième signal de données en fonction d'une deuxième charge générée par une deuxième unité de conversion photoélectrique. La présente invention peut être appliquée, par exemple, à un appareil d'imagerie à semi-conducteurs.
PCT/JP2017/009366 2016-03-23 2017-03-09 Appareil d'imagerie à semi-conducteurs, procédé de commande d'appareil d'imagerie à semi-conducteurs et dispositif électronique WO2017163890A1 (fr)

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JP2016058434A JP2017175345A (ja) 2016-03-23 2016-03-23 固体撮像装置、固体撮像装置の駆動方法、及び、電子機器
JP2016-058434 2016-03-23

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111164964A (zh) * 2017-10-27 2020-05-15 索尼半导体解决方案公司 摄像装置和摄像方法
EP4109888A1 (fr) * 2021-06-21 2022-12-28 Samsung Electronics Co., Ltd. Circuit de pixel unitaire et capteur d'image le comprenant

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6474014B1 (ja) 2017-07-05 2019-02-27 パナソニックＩｐマネジメント株式会社 撮像装置
CN115696074B (zh) 2019-12-17 2023-09-15 索尼半导体解决方案公司 光检测装置
JP7064537B2 (ja) 2020-07-29 2022-05-10 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及びこれの制御方法
WO2022172714A1 (fr) * 2021-02-09 2022-08-18 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283573A (ja) * 2009-06-04 2010-12-16 Nikon Corp 電子カメラ
US20130256510A1 (en) * 2012-03-29 2013-10-03 Omnivision Technologies, Inc. Imaging device with floating diffusion switch
JP2014112760A (ja) * 2012-12-05 2014-06-19 Sony Corp 固体撮像装置および電子機器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283573A (ja) * 2009-06-04 2010-12-16 Nikon Corp 電子カメラ
US20130256510A1 (en) * 2012-03-29 2013-10-03 Omnivision Technologies, Inc. Imaging device with floating diffusion switch
JP2014112760A (ja) * 2012-12-05 2014-06-19 Sony Corp 固体撮像装置および電子機器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111164964A (zh) * 2017-10-27 2020-05-15 索尼半导体解决方案公司 摄像装置和摄像方法
CN111164964B (zh) * 2017-10-27 2022-08-16 索尼半导体解决方案公司 摄像装置和摄像方法
EP4109888A1 (fr) * 2021-06-21 2022-12-28 Samsung Electronics Co., Ltd. Circuit de pixel unitaire et capteur d'image le comprenant
US11743610B2 (en) 2021-06-21 2023-08-29 Samsung Electronics Co., Ltd. Pixel and image sensor including the same

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