WO2017156846A1 - 液晶显示装置及其有机发光二极管的补偿电路 - Google Patents

液晶显示装置及其有机发光二极管的补偿电路 Download PDF

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Publication number
WO2017156846A1
WO2017156846A1 PCT/CN2016/081505 CN2016081505W WO2017156846A1 WO 2017156846 A1 WO2017156846 A1 WO 2017156846A1 CN 2016081505 W CN2016081505 W CN 2016081505W WO 2017156846 A1 WO2017156846 A1 WO 2017156846A1
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Prior art keywords
thin film
film transistor
switch unit
emitting diode
organic light
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PCT/CN2016/081505
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English (en)
French (fr)
Inventor
聂诚磊
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/109,877 priority Critical patent/US10204566B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display device and a compensation circuit thereof for the organic light emitting diode.
  • An Organic Light-Emitting Diode is a current light emitting device.
  • the driving circuit of the existing OLED includes two thin film transistors including a switching thin film transistor and a driving thin film transistor, and a driving thin film transistor for controlling the input of the data signal, and the driving thin film transistor for controlling the current passing through the OLED.
  • the positive or negative drift of the threshold voltage of the driving thin film transistor causes different currents to pass through the OLED.
  • the threshold voltage drift of the driving thin film transistor occurs during the use of the thin film transistor, such as illumination in the oxide semiconductor, voltage stress of the source and drain electrodes, and the like, so that the threshold voltage of the driving thin film transistor is shifted, and further The current through the OLED does not reach the required current.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device and a compensation circuit thereof for the organic light emitting diode to solve the above problems.
  • a technical solution adopted by the present invention is to provide a compensation circuit for an organic light emitting diode, which is coupled to an organic light emitting diode, and the compensation circuit includes at least: a first switching unit, the first of the first switching unit The second end of the first switch unit is coupled to the first clock signal, and the second end of the second switch unit is coupled to the third end of the first switch unit, the second switch The second end of the second switch unit is coupled to the organic light emitting diode, the third end of the third switch unit is coupled to the second reference voltage, and the third switch unit is coupled to the second switch unit.
  • the third end is coupled to the organic light emitting diode
  • the fourth end of the third switch unit is coupled to the fourth end of the second switch unit
  • the fourth switch unit is coupled to the data signal by the first end of the fourth switch unit
  • the fourth switch unit The second end of the fourth switch unit is coupled to the second end of the third switch unit; the first switch unit is turned off, When the second switching unit, the third switching unit, and the fourth switching unit are turned on, the compensation circuit drives the organic light emitting diode to emit light, thereby compensating the organic light emitting diode.
  • the current of the organic light emitting diode satisfies the following formula:
  • I is the current of the organic light emitting diode
  • Vdata is the voltage value of the data signal
  • Vpre is the voltage value of the preset voltage
  • the first switching unit includes a first thin film transistor, the first end of the first thin film transistor is connected to the first reference voltage, and the second end of the first thin film transistor is connected to the first clock signal;
  • the second switching unit includes a second thin film transistor and a first capacitor, the first end of the second thin film transistor is connected to the third end of the first thin film transistor, the second end of the second thin film transistor is connected to the preset voltage, and the second thin film transistor is connected The third end is connected to the anode of the organic light emitting diode, and one end of the first capacitor is connected to the first end and the fourth end of the second thin film transistor, and the other end of the first capacitor is grounded.
  • the third switching unit includes a third thin film transistor, the first end of the third thin film transistor is connected to the second reference voltage, the third end of the third thin film transistor is connected to the anode of the organic light emitting diode, and the fourth end of the third thin film transistor is connected. The fourth end of the second thin film transistor.
  • the fourth switching unit includes a fourth thin film transistor and a second capacitor.
  • the first end of the fourth thin film transistor is connected to the data signal
  • the second end of the fourth thin film transistor is connected to the second clock signal
  • the third end of the fourth thin film transistor is connected.
  • one end of the second capacitor is connected to the third end of the fourth thin film transistor and the second end of the third thin film transistor, and the other end of the second capacitor is grounded.
  • the second thin film transistor and the third thin film transistor are double gate thin film transistors
  • the second end of the second thin film transistor is a bottom gate of the double gate thin film transistor
  • the fourth end of the second thin film transistor is a double gate
  • the top gate of the thin film transistor, the second end of the third thin film transistor is a bottom gate of the double gate thin film transistor, and the fourth end of the third thin film transistor is a top gate of the double gate thin film transistor.
  • the first clock signal is at a high level
  • the second clock signal is at a low level
  • the data signal is at a low level
  • the first thin film transistor and the second thin film transistor are turned on
  • the fourth thin film transistor is turned off.
  • the first clock signal is low level
  • the second clock signal is Low level
  • the data signal is low
  • the first thin film transistor is turned off
  • the second thin film transistor is turned on
  • the fourth thin film transistor is turned off.
  • the first clock signal is at a low level
  • the second clock signal is at a high level
  • the data signal is at a high level
  • the first thin film transistor is turned off
  • the second thin film transistor is turned on
  • the third thin film transistor is turned on. Open, the fourth thin film transistor is turned on.
  • a liquid crystal display device including a backlight module and a display panel disposed on a light emitting surface of the backlight module, the backlight module including an organic light emitting diode and a compensation circuit, the compensation circuit is coupled to the organic light emitting diode, and the compensation circuit comprises at least:
  • the first end of the first switching unit is coupled to the first reference voltage, and the second end of the first switching unit is coupled to the first clock signal;
  • the first end of the second switch unit is coupled to the third end of the first switch unit, the second end of the second switch unit is coupled to the preset voltage, and the third end of the second switch unit is coupled to the organic light diode;
  • the first end of the third switching unit is coupled to the second reference voltage
  • the third end of the third switching unit is coupled to the organic light emitting diode
  • the fourth end of the third switching unit is coupled to the second switching unit
  • the first end of the fourth switch unit is coupled to the data signal, the second end of the fourth switch unit is coupled to the second clock signal, and the third end of the fourth switch unit is coupled to the second end of the third switch unit end;
  • the compensation circuit drives the organic light emitting diode to emit light, thereby compensating the organic light emitting diode.
  • the current of the organic light emitting diode satisfies the following formula:
  • I is the current of the organic light emitting diode
  • Vdata is the voltage value of the data signal
  • Vpre is the voltage value of the preset voltage
  • the first switching unit includes a first thin film transistor, the first end of the first thin film transistor is connected to the first reference voltage, and the second end of the first thin film transistor is connected to the first clock signal;
  • the second switching unit includes a second thin film transistor and a first capacitor, and a second thin film transistor One end is connected to the third end of the first thin film transistor, the second end of the second thin film transistor is connected to a preset voltage, and the third end of the second thin film transistor is connected to the positive electrode of the organic light emitting diode, one end of the first capacitor and the second thin film transistor The first end and the fourth end are connected, and the other end of the first capacitor is grounded.
  • the third switching unit includes a third thin film transistor, the first end of the third thin film transistor is connected to the second reference voltage, the third end of the third thin film transistor is connected to the anode of the organic light emitting diode, and the fourth end of the third thin film transistor is connected. The fourth end of the second thin film transistor.
  • the fourth switching unit includes a fourth thin film transistor and a second capacitor.
  • the first end of the fourth thin film transistor is connected to the data signal
  • the second end of the fourth thin film transistor is connected to the second clock signal
  • the third end of the fourth thin film transistor is connected.
  • one end of the second capacitor is connected to the third end of the fourth thin film transistor and the second end of the third thin film transistor, and the other end of the second capacitor is grounded.
  • the second thin film transistor and the third thin film transistor are double gate thin film transistors
  • the second end of the second thin film transistor is a bottom gate of the double gate thin film transistor
  • the fourth end of the second thin film transistor is a double gate
  • the top gate of the thin film transistor, the second end of the third thin film transistor is a bottom gate of the double gate thin film transistor, and the fourth end of the third thin film transistor is a top gate of the double gate thin film transistor.
  • the first clock signal is at a high level
  • the second clock signal is at a low level
  • the data signal is at a low level
  • the first thin film transistor and the second thin film transistor are turned on
  • the fourth thin film transistor is turned off.
  • the first clock signal is low level
  • the second clock signal is low level
  • the data signal is low level
  • the first thin film transistor is turned off
  • the second thin film transistor is turned on
  • the fourth thin film transistor is turned off.
  • the first clock signal is at a low level
  • the second clock signal is at a high level
  • the data signal is at a high level
  • the first thin film transistor is turned off
  • the second thin film transistor is turned on
  • the third thin film transistor is turned on. Open, the fourth thin film transistor is turned on.
  • the invention has the beneficial effects that the compensation circuit drives the organic light emitting diode to emit light when the first switching unit is turned off and the second switching unit, the third switching unit and the fourth switching unit are turned on, which is different from the prior art.
  • the organic light emitting diode is compensated to prevent the current passing through the organic light emitting diode from being affected by the drift of the threshold voltage of the thin film transistor.
  • FIG. 1 is a circuit diagram of a compensation circuit of an organic light emitting diode according to a first embodiment of the present invention
  • FIG. 2 is a timing diagram of the compensation circuit shown in Figure 1;
  • FIG 3 is a schematic structural view of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 1 is a circuit diagram of a compensation circuit of an organic light emitting diode according to a first embodiment of the present invention.
  • the compensation circuit disclosed in this embodiment is applied to an organic light emitting diode.
  • the compensation circuit is coupled to the organic light emitting diode.
  • the compensation circuit includes at least: a first switch unit 11, a second switch unit 12, and a third switch unit. 13 and a fourth switching unit 14.
  • the first end 111 of the first switch unit 11 is coupled to the first reference voltage Vin
  • the second end 112 of the first switch unit 11 is coupled to the first clock signal CK1
  • the first end of the second switch unit 12 is
  • the second end 113 of the second switch unit 12 is coupled to the preset voltage Vpre
  • the third end 123 of the second switch unit 12 is coupled to the organic light emitting diode D.
  • the first end 131 of the third switch unit 13 is coupled to the second reference voltage Vdd
  • the third end 133 of the third switch unit 13 is coupled to the organic light emitting diode D
  • the fourth end 134 of the third switch unit 13 is coupled to the second switch unit.
  • the fourth end 124 of the fourth switch unit 14 is coupled to the data signal Data, the second end 142 of the fourth switch unit 14 is coupled to the second clock signal CK2, and the third end of the fourth switch unit 14 143 is coupled to the second end 132 of the third switch unit 13 .
  • the compensation circuit drives the organic light emitting diode D to emit light, thereby compensating the organic light emitting diode D.
  • the first switching unit 11 includes a first thin film transistor T1.
  • the first end 111 of the first thin film transistor 11 is connected to the first reference voltage Vin, and the second end 112 of the first thin film transistor T1 is connected to the first clock signal CK1.
  • the second switching unit 12 includes a second thin film transistor T2 and a first capacitor C1.
  • the first end 121 of the second thin film transistor T2 is connected to the third end 113 of the first thin film transistor T1, and the second end 122 of the second thin film transistor T2 is connected.
  • the third terminal 123 of the second thin film transistor T2 is connected to the anode of the organic light emitting diode D, and one end of the first capacitor C1 is connected to the first end 121 and the fourth end 124 of the second thin film transistor T2. The other end of C1 is grounded.
  • the third switching unit 13 includes a third thin film transistor T3.
  • the first end 131 of the third thin film transistor T3 is connected to the second reference voltage Vdd, and the third end 133 of the third thin film transistor T3 is connected to the positive electrode of the organic light emitting diode D.
  • the fourth end 134 of the transistor T3 is coupled to the fourth end 124 of the second thin film transistor T2.
  • the fourth switching unit 14 includes a fourth thin film transistor T4 and a second capacitor C2.
  • the first end 111 of the fourth thin film transistor T4 is connected to the data signal Data, and the second end 142 of the fourth thin film transistor T4 is connected to the second clock signal CK2.
  • the third end 143 of the fourth thin film transistor T4 is connected to the second end 132 of the third thin film transistor T3, and one end of the second capacitor C2 is connected to the third end 143 of the fourth thin film transistor T4 and the second end 132 of the third thin film transistor T3.
  • the other end of the second capacitor C2 is grounded, and the second capacitor C2 is used for filtering the data signal Data.
  • the second thin film transistor T2 and the third thin film transistor T3 are both double gate thin film transistors.
  • the first end 121 of the second thin film transistor T2 is the drain of the double gate thin film transistor
  • the second end 122 of the second thin film transistor T2 is the bottom gate BG of the double gate thin film transistor
  • the second thin film transistor T2 The third end 123 is the source of the double gate thin film transistor
  • the fourth end 124 of the second thin film transistor T2 is the top gate TG of the double gate thin film transistor
  • the first end 131 of the third thin film transistor T3 is the double gate
  • the drain of the thin film transistor, the second end 132 of the third thin film transistor T3 is the bottom gate BG of the double gate thin film transistor, and the third end 133 of the third thin film transistor T3 is the source of the double gate thin film transistor
  • the third The fourth terminal 134 of the thin film transistor T3 is the top gate TG of the dual gate thin film transistor.
  • the first end 111 of the first thin film transistor T1 is a drain
  • the second end 112 of the first thin film transistor T1 is a gate
  • the third end 113 of the first thin film transistor T1 is a source
  • the first end of the fourth thin film transistor T4 The terminal 141 is a drain
  • the second end 142 of the fourth thin film transistor T4 is a gate
  • the third end 143 of the fourth thin film transistor T4 is a source.
  • the compensation circuit precharges the organic light emitting diode D, as in the T1-T2 interval in FIG. 2, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the data signal Data is at a low level. .
  • the first thin film transistor T1 is turned on, and the fourth thin film transistor T4 is turned off; the voltage Vbg2 of the second end of the second thin film transistor T2 is a preset voltage Vpre, and the first end 111 and the third end 113 of the first thin film transistor T1 are connected, and the second The first terminal 121 and the fourth terminal 124 of the thin film transistor T2 are connected.
  • the voltage Vtg2 of the fourth terminal 124 of the second thin film transistor T2 is the first reference voltage Vin, and the voltage Vtg3 of the fourth terminal 134 of the third thin film transistor T3. Also for the first reference voltage Vin; the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the organic light emitting diode D emits light. Since the pre-charging time T1-T2 is a few microseconds, and the time during which the organic light-emitting diode D drives the light emission is ten milliseconds, the effect of the organic light-emitting diode D on the pre-charging light emission on the organic light-emitting diode D driving light is very small.
  • the compensation circuit programs the organic light emitting diode D, as in the T2-T3 interval in FIG. 2, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a low level, and the data signal Data is at a low level.
  • the first thin film transistor T1 is turned off, the fourth thin film transistor T4 is turned off; the first end 121 and the fourth end 124 of the second thin film transistor T2 are connected, and the voltage Vtg2 of the fourth end 124 of the second thin film transistor T2 is Vin, and the second thin film transistor is
  • the threshold voltage Vth_t2 of T2 is very small, and the second thin film transistor T2 is turned on.
  • the compensation circuit drives the organic light emitting diode D to emit light, as shown in FIG. 2, it is larger than T3.
  • the first clock signal CK1 is at a low level
  • the second clock signal CK2 is at a high level
  • the data signal Data is at a high level.
  • the first thin film transistor T1 is turned off, the second thin film transistor T2 is turned on, the third thin film transistor T3 is turned on, and the fourth thin film transistor T4 is turned on. Since the voltage Vtg2 of the fourth terminal 124 of the second thin film transistor T2 is maintained by the first capacitor C1 during programming, the threshold voltages of the second thin film transistor T2 and the third thin film transistor T3 are guaranteed to be Vpre-Voled.
  • the second end 132 of the third thin film transistor T3 inputs a preset voltage Data, which is obtained according to the current formula of the thin film transistor:
  • Vbg3 is the voltage Vdata of the second terminal 132 of the fourth thin film transistor T3
  • the threshold voltage of the third thin film transistor T3 is Vpre-Voled into the formula (1):
  • the current of the organic light emitting diode D is only related to the data signal Data and the preset voltage Vpre.
  • the data signal Data and the preset voltage Vpre are constant, the current of the organic light emitting diode D is kept stable. The current through the organic light emitting diode D is prevented from being affected by the drift of the threshold voltage of the thin film transistor.
  • the present invention also provides a liquid crystal display device.
  • the liquid crystal display device disclosed in the present embodiment includes a backlight module 31 and a display panel 32 disposed on a light emitting surface of the backlight module 31, wherein the backlight module
  • the organic light emitting diode D is used to provide the light source for the backlight module 31.
  • the backlight module 31 further includes the compensation circuit described in the above embodiments, and details are not described herein.
  • the current of the organic light emitting diode D of the liquid crystal display device disclosed in the present embodiment is kept stable, and it is possible to prevent the current passing through the organic light emitting diode D from being affected by the drift of the threshold voltage of the thin film transistor, thereby achieving uniform light emission of the display panel 32.
  • the compensation circuit drives the organic light emitting diode to emit light, thereby compensating the organic light emitting diode to avoid passing through the organic light emitting diode.
  • the current is affected by the drift of the threshold voltage of the thin film transistor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶显示装置及其有机发光二极管（D）的补偿电路。补偿电路至少包括第一开关单元（11）、第二开关单元（12）、第三开关单元（13）以及第四开关单元（14）。在第一开关单元（11）关闭，第二开关单元（12）、第三开关单元（13）以及第四开关单元（14）打开时，补偿电路驱动有机发光二极管（D）发光，进而补偿有机发光二极管（D）。补偿电路能够避免通过有机发光二极管（D）的电流受到薄膜晶体管的阈值电压产生漂移的影响。

Description

液晶显示装置及其有机发光二极管的补偿电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示装置及其有机发光二极管的补偿电路。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)是电流发光器件。现有OLED的驱动电路包括两个薄膜晶体管和一个电容，两个薄膜晶体管包括开关薄膜晶体管和驱动薄膜晶体管，开关薄膜晶体管用于控制数据信号的进入，驱动薄膜晶体管用于控制通过OLED的电流。在相同的数据信号的情况下，驱动薄膜晶体管的阈值电压的正向或负向漂移导致不同的电流通过OLED。
目前薄膜晶体管在使用的过程中均会发生驱动薄膜晶体管的阈值电压漂移的现象，例如氧化物半导体中的照光、源漏电极电压应力作用等因素，以使驱动薄膜晶体管的阈值电压产生漂移，进而通过OLED的电流达不到需求的电流。
发明内容
本发明主要解决的技术问题是提供一种液晶显示装置及其有机发光二极管的补偿电路，以解决上述问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种有机发光二极管的补偿电路，其耦接有机发光二极管，该补偿电路至少包括：第一开关单元，第一开关单元的第一端耦接第一参考电压，第一开关单元的第二端耦接第一时钟信号；第二开关单元，第二开关单元的第一端耦接第一开关单元的第三端，第二开关单元的第二端耦接预设电压，第二开关单元的第三端耦接有机发光二极管；第三开关单元，第三开关单元的第一端耦接第二参考电压，第三开关单元的第三端耦接有机发光二极管，第三开关单元的第四端耦接第二开关单元的第四端；第四开关单元，第四开关单元的第一端耦接数据信号，第四开关单元的第二端耦接第二时钟信号，第四开关单元的第三端耦接第三开关单元的第二端；在第一开关单元关闭， 第二开关单元、第三开关单元以及第四开关单元打开时，补偿电路驱动有机发光二极管发光，进而补偿有机发光二极管。
其中，在有机发光二极管发光时，有机发光二极管的电流满足以下公式：
I＝β*(Vdata-Vpre)2
其中，I为有机发光二极管的电流；Vdata为数据信号的电压值；Vpre为预设电压的电压值。
其中，第一开关单元包括第一薄膜晶体管，第一薄膜晶体管的第一端连接第一参考电压，第一薄膜晶体管的第二端连接第一时钟信号；
第二开关单元包括第二薄膜晶体管和第一电容，第二薄膜晶体管的第一端连接第一薄膜晶体管的第三端，第二薄膜晶体管的第二端连接预设电压，第二薄膜晶体管的第三端连接有机发光二极管的正极，第一电容的一端与第二薄膜晶体管的第一端和第四端连接，第一电容的另一端接地。
其中，第三开关单元包括第三薄膜晶体管，第三薄膜晶体管的第一端连接第二参考电压，第三薄膜晶体管的第三端连接有机发光二极管的正极，第三薄膜晶体管的第四端连接第二薄膜晶体管的第四端。
其中，第四开关单元包括第四薄膜晶体管和第二电容，第四薄膜晶体管的第一端连接数据信号，第四薄膜晶体管的第二端连接第二时钟信号，第四薄膜晶体管的第三端连接第三薄膜晶体管的第二端，第二电容的一端与第四薄膜晶体管的第三端和第三薄膜晶体管的第二端连接，第二电容的另一端接地。
其中，第二薄膜晶体管和第三薄膜晶体管均为双栅极薄膜晶体管，第二薄膜晶体管的第二端为双栅极薄膜晶体管的底栅极，第二薄膜晶体管的第四端为双栅极薄膜晶体管的顶栅极，第三薄膜晶体管的第二端为双栅极薄膜晶体管的底栅极，第三薄膜晶体管的第四端为双栅极薄膜晶体管的顶栅极。
其中，补偿电路在预充电时，第一时钟信号为高电平，第二时钟信号为低电平，数据信号为低电平，第一薄膜晶体管和第二薄膜晶体管打开，第四薄膜晶体管关闭。
其中，补偿电路在编程时，第一时钟信号为低电平，第二时钟信号为 低电平，数据信号为低电平，第一薄膜晶体管关闭，第二薄膜晶体管打开，第四薄膜晶体管关闭。
其中，补偿电路在驱动发光时，第一时钟信号为低电平，第二时钟信号为高电平，数据信号为高电平，第一薄膜晶体管关闭，第二薄膜晶体管打开，第三薄膜晶体管打开，第四薄膜晶体管打开。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，其包括背光模组和设置在背光模组的出光面上的显示面板，背光模组包括有机发光二极管和补偿电路，补偿电路耦接有机发光二极管，补偿电路至少包括：
第一开关单元，第一开关单元的第一端耦接第一参考电压，第一开关单元的第二端耦接第一时钟信号；
第二开关单元，第二开关单元的第一端耦接第一开关单元的第三端，第二开关单元的第二端耦接预设电压，第二开关单元的第三端耦接有机发光二极管；
第三开关单元，第三开关单元的第一端耦接第二参考电压，第三开关单元的第三端耦接有机发光二极管，第三开关单元的第四端耦接第二开关单元的第四端；
第四开关单元，第四开关单元的第一端耦接数据信号，第四开关单元的第二端耦接第二时钟信号，第四开关单元的第三端耦接第三开关单元的第二端；
在第一开关单元关闭，第二开关单元、第三开关单元以及第四开关单元打开时，补偿电路驱动有机发光二极管发光，进而补偿有机发光二极管。
其中，在有机发光二极管发光时，有机发光二极管的电流满足以下公式：
I＝β*(Vdata-Vpre)2
其中，I为有机发光二极管的电流；Vdata为数据信号的电压值；Vpre为预设电压的电压值。
其中，第一开关单元包括第一薄膜晶体管，第一薄膜晶体管的第一端连接第一参考电压，第一薄膜晶体管的第二端连接第一时钟信号；
第二开关单元包括第二薄膜晶体管和第一电容，第二薄膜晶体管的第 一端连接第一薄膜晶体管的第三端，第二薄膜晶体管的第二端连接预设电压，第二薄膜晶体管的第三端连接有机发光二极管的正极，第一电容的一端与第二薄膜晶体管的第一端和第四端连接，第一电容的另一端接地。
其中，第三开关单元包括第三薄膜晶体管，第三薄膜晶体管的第一端连接第二参考电压，第三薄膜晶体管的第三端连接有机发光二极管的正极，第三薄膜晶体管的第四端连接第二薄膜晶体管的第四端。
其中，第四开关单元包括第四薄膜晶体管和第二电容，第四薄膜晶体管的第一端连接数据信号，第四薄膜晶体管的第二端连接第二时钟信号，第四薄膜晶体管的第三端连接第三薄膜晶体管的第二端，第二电容的一端与第四薄膜晶体管的第三端和第三薄膜晶体管的第二端连接，第二电容的另一端接地。
其中，第二薄膜晶体管和第三薄膜晶体管均为双栅极薄膜晶体管，第二薄膜晶体管的第二端为双栅极薄膜晶体管的底栅极，第二薄膜晶体管的第四端为双栅极薄膜晶体管的顶栅极，第三薄膜晶体管的第二端为双栅极薄膜晶体管的底栅极，第三薄膜晶体管的第四端为双栅极薄膜晶体管的顶栅极。
其中，补偿电路在预充电时，第一时钟信号为高电平，第二时钟信号为低电平，数据信号为低电平，第一薄膜晶体管和第二薄膜晶体管打开，第四薄膜晶体管关闭。
其中，补偿电路在编程时，第一时钟信号为低电平，第二时钟信号为低电平，数据信号为低电平，第一薄膜晶体管关闭，第二薄膜晶体管打开，第四薄膜晶体管关闭。
其中，补偿电路在驱动发光时，第一时钟信号为低电平，第二时钟信号为高电平，数据信号为高电平，第一薄膜晶体管关闭，第二薄膜晶体管打开，第三薄膜晶体管打开，第四薄膜晶体管打开。
本发明的有益效果是：区别于现有技术的情况，本发明在第一开关单元关闭，第二开关单元、第三开关单元以及第四开关单元打开时，补偿电路驱动有机发光二极管发光，进而补偿有机发光二极管，避免通过有机发光二极管的电流受到薄膜晶体管的阈值电压产生漂移的影响。
附图说明
图1是本发明第一实施例的有机发光二极管的补偿电路的电路图；
图2是图1所示的补偿电路的时序图；
图3是本发明第一实施例的液晶显示装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的有机发光二极管的补偿电路的电路图。本实施例所揭示的补偿电路应用于有机发光二极管，如图1所示，该补偿电路耦接有机发光二极管，补偿电路至少包括：第一开关单元11、第二开关单元12、第三开关单元13以及第四开关单元14。
在本实施例中，第一开关单元11的第一端111耦接第一参考电压Vin，第一开关单元11的第二端112耦接第一时钟信号CK1；第二开关单元12的第一端121耦接第一开关单元11的第三端113，第二开关单元12的第二端122耦接预设电压Vpre，第二开关单元12的第三端123耦接有机发光二极管D；第三开关单元13的第一端131耦接第二参考电压Vdd，第三开关单元13的第三端133耦接有机发光二极管D，第三开关单元13的第四端134耦接第二开关单元12的第四端124；第四开关单元14的第一端141耦接数据信号Data，第四开关单元14的第二端142耦接第二时钟信号CK2，第四开关单元14的第三端143耦接第三开关单元13的第二端132。
其中，在第一开关单元11关闭，第二开关单元12、第三开关单元13以及第四开关单元14打开时，补偿电路驱动有机发光二极管D发光，进而补偿有机发光二极管D。
具体而言，第一开关单元11包括第一薄膜晶体管T1，第一薄膜晶体管11的第一端111连接第一参考电压Vin，第一薄膜晶体管T1的第二端112连接第一时钟信号CK1。
第二开关单元12包括第二薄膜晶体管T2和第一电容C1，第二薄膜晶体管T2的第一端121连接第一薄膜晶体管T1的第三端113，第二薄膜晶体管T2的第二端122连接预设电压Vpre，第二薄膜晶体管T2的第三端123连接有机发光二极管D的正极，第一电容C1的一端与第二薄膜晶体管T2的第一端121和第四端124连接，第一电容C1的另一端接地。
第三开关单元13包括第三薄膜晶体管T3，第三薄膜晶体管T3的第一端131连接第二参考电压Vdd，第三薄膜晶体管T3的第三端133连接有机发光二极管D的正极，第三薄膜晶体管T3的第四端134连接第二薄膜晶体管T2的第四端124。
第四开关单元14包括第四薄膜晶体管T4和第二电容C2，第四薄膜晶体管T4的第一端111连接数据信号Data，第四薄膜晶体管T4的第二端142连接第二时钟信号CK2，第四薄膜晶体管T4的第三端143连接第三薄膜晶体管T3的第二端132，第二电容C2的一端与第四薄膜晶体管T4的第三端143和第三薄膜晶体管T3的第二端132连接，第二电容C2的另一端接地，第二电容C2用于对数据信号Data进行滤波处理。
优选地，第二薄膜晶体管T2和第三薄膜晶体管T3均为双栅极薄膜晶体管。其中，第二薄膜晶体管T2的第一端121为双栅极薄膜晶体管的漏极，第二薄膜晶体管T2的第二端122为双栅极薄膜晶体管的底栅极BG，第二薄膜晶体管T2的第三端123为双栅极薄膜晶体管的源极，第二薄膜晶体管T2的第四端124为双栅极薄膜晶体管的顶栅极TG；第三薄膜晶体管T3的第一端131为双栅极薄膜晶体管的漏极，第三薄膜晶体管T3的第二端132为双栅极薄膜晶体管的底栅极BG，第三薄膜晶体管T3的第三端133为双栅极薄膜晶体管的源极，第三薄膜晶体管T3的第四端134为双栅极薄膜晶体管的顶栅极TG。第一薄膜晶体管T1的第一端111为漏极，第一薄膜晶体管T1的第二端112为栅极，第一薄膜晶体管T1的第三端113为源极；第四薄膜晶体管T4的第一端141为漏极，第四薄膜晶体管T4的第二端142为栅极，第四薄膜晶体管T4的第三端143为源极。
请一并参见图2，根据图2所示的时序图详细描述本实施例的补偿电路的工作原理。
其中，补偿电路对有机发光二极管D进行补偿包括三个部分，分别为 补偿电路对有机发光二极管D进行预充电、补偿电路对有机发光二极管D进行编程以及补偿电路对有机发光二极管D进行驱动发光。
当补偿电路对有机发光二极管D进行预充电时，如图2中的T1-T2区间，第一时钟信号CK1为高电平，第二时钟信号CK2为低电平，数据信号Data为低电平。第一薄膜晶体管T1打开，第四薄膜晶体管T4关闭；第二薄膜晶体管T2的第二端的电压Vbg2为预设电压Vpre，第一薄膜晶体管T1的第一端111和第三端113连接，第二薄膜晶体管T2的第一端121和第四端124连接，此时第二薄膜晶体管T2的第四端124的电压Vtg2为第一参考电压Vin，第三薄膜晶体管T3的第四端134的电压Vtg3也为第一参考电压Vin；第二薄膜晶体管T2和第三薄膜晶体管T3打开，有机发光二极管D发光。由于预充电的时间T1-T2为几微秒，而有机发光二极管D驱动发光的时间为十几毫秒，因此有机发光二极管D在预充电时发光对有机发光二极管D驱动发光的影响非常小。
当补偿电路对有机发光二极管D进行编程时，如图2中的T2-T3区间，第一时钟信号CK1为低电平，第二时钟信号CK2为低电平，数据信号Data为低电平。第一薄膜晶体管T1关闭，第四薄膜晶体管T4关闭；第二薄膜晶体管T2的第一端121和第四端124连接，第二薄膜晶体管T2第四端124的电压Vtg2为Vin，第二薄膜晶体管T2的阈值电压Vth_t2非常小，第二薄膜晶体管T2打开。随着第二薄膜晶体管T2第四端124的电压Vtg2不断减小，第二薄膜晶体管T2的阈值电压Vth_t2不断上升，直到Vbg2-Vs＝Vth_t2时，第二薄膜晶体管T2第四端124的电压Vtg2不再变化，其中Vs为第二薄膜晶体管T2的第三端123的电压。第二薄膜晶体管T2的第四端124的电压Vtg2存储在第一电容C1中，第二薄膜晶体管T2的阈值电压Vth_t2＝Vbg2-Vs＝Vpre-Voled。由于第二薄膜晶体管T2的第四端124与第三薄膜晶体管T3的第四端134连接并且第二薄膜晶体管T2和第三薄膜晶体管T3为镜像薄膜晶体管，因此第三薄膜晶体管T3的阈值电压Vth_t3＝Vth_t2＝Vpre-Voled，第四薄膜晶体管T4打开。由于编程的时间T2-T3为十几微秒，而有机发光二极管D驱动发光的时间为十几毫秒，因此有机发光二极管D在编程时发光对有机发光二极管D驱动发光的影响非常小。
当补偿电路对有机发光二极管D进行驱动发光时，如图2中的大于T3， 第一时钟信号CK1为低电平，第二时钟信号CK2为高电平，数据信号Data为高电平。第一薄膜晶体管T1关闭，第二薄膜晶体管T2打开，第三薄膜晶体管T3打开，第四薄膜晶体管T4打开。由于在进行编程时，第二薄膜晶体管T2的第四端124的电压Vtg2由第一电容C1维持，进而保证第二薄膜晶体管T2和第三薄膜晶体管T3的阈值电压为Vpre-Voled。第三薄膜晶体管T3的第二端132输入预设电压Data，根据薄膜晶体管的电流公式可得：
I＝β(Vbg3-Vth_t3-Vs)2                   (1)
其中，Vbg3为第四薄膜晶体管T3的第二端132的电压Vdata，将第三薄膜晶体管T3的阈值电压为Vpre-Voled代入公式(1)可得：
I＝β[Vdata-(Vpre-Voled)-Voled]2＝β(Vdata-Vpre)2        (2)
根据公式(2)可知，有机发光二极管D的电流仅仅与数据信号Data和预设电压Vpre相关，在数据信号Data和预设电压Vpre不变时，以使有机发光二极管D的电流保持稳定，能够避免通过有机发光二极管D的电流受到薄膜晶体管的阈值电压产生漂移的影响。
本发明还提供一种液晶显示装置，如图3所示，本实施所揭示的液晶显示装置包括：背光模组31和设置在背光模组31的出光面上的显示面板32，其中背光模组31包括上述实施例所描述的有机发光二极管D，该有机发光二极管D用于为背光模组31提供光源，背光模组31进一步包括上述实施例所描述的补偿电路，在此不再赘述。
本实施例所揭示的液晶显示装置的有机发光二极管D的电流保持稳定，能够避免通过有机发光二极管D的电流受到薄膜晶体管的阈值电压产生漂移的影响，实现显示面板32的均匀发光。
综上所述，本发明在第一开关单元关闭，第二开关单元、第三开关单元以及第四开关单元打开时，补偿电路驱动有机发光二极管发光，进而补偿有机发光二极管，避免通过有机发光二极管的电流受到薄膜晶体管的阈值电压产生漂移的影响。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种有机发光二极管的补偿电路，其中，所述补偿电路耦接所述有机发光二极管，所述补偿电路至少包括：
    第一开关单元，所述第一开关单元的第一端耦接第一参考电压，所述第一开关单元的第二端耦接第一时钟信号；
    第二开关单元，所述第二开关单元的第一端耦接所述第一开关单元的第三端，所述第二开关单元的第二端耦接预设电压，所述第二开关单元的第三端耦接所述有机发光二极管；
    第三开关单元，所述第三开关单元的第一端耦接第二参考电压，所述第三开关单元的第三端耦接所述有机发光二极管，所述第三开关单元的第四端耦接所述第二开关单元的第四端；
    第四开关单元，所述第四开关单元的第一端耦接数据信号，所述第四开关单元的第二端耦接第二时钟信号，所述第四开关单元的第三端耦接所述第三开关单元的第二端；
    在所述第一开关单元关闭，所述第二开关单元、第三开关单元以及第四开关单元打开时，所述补偿电路驱动所述有机发光二极管发光，进而补偿所述有机发光二极管。
  2. 根据权利要求1所述的补偿电路，其中，在所述有机发光二极管发光时，所述有机发光二极管的电流满足以下公式：
    I＝β*(Vdata-Vpre)2
    其中，I为所述有机发光二极管的电流；Vdata为所述数据信号的电压值；Vpre为所述预设电压的电压值。
  3. 根据权利要求1所述的补偿电路，其中，所述第一开关单元包括第一薄膜晶体管，所述第一薄膜晶体管的第一端连接所述第一参考电压，所述第一薄膜晶体管的第二端连接所述第一时钟信号；
    所述第二开关单元包括第二薄膜晶体管和第一电容，所述第二薄膜晶体管的第一端连接所述第一薄膜晶体管的第三端，所述第二薄膜晶体管的第二端连接所述预设电压，所述第二薄膜晶体管的第三端连接所述有机发光二极管的正极，所述第一电容的一端与所述第二薄膜晶体管的第一端和 第四端连接，所述第一电容的另一端接地。
  4. 根据权利要求3所述的补偿电路，其中，所述第三开关单元包括第三薄膜晶体管，所述第三薄膜晶体管的第一端连接所述第二参考电压，所述第三薄膜晶体管的第三端连接所述有机发光二极管的正极，所述第三薄膜晶体管的第四端连接所述第二薄膜晶体管的第四端。
  5. 根据权利要求4所述的补偿电路，其中，所述第四开关单元包括第四薄膜晶体管和第二电容，所述第四薄膜晶体管的第一端连接所述数据信号，所述第四薄膜晶体管的第二端连接所述第二时钟信号，所述第四薄膜晶体管的第三端连接所述第三薄膜晶体管的第二端，所述第二电容的一端与所述第四薄膜晶体管的第三端和所述第三薄膜晶体管的第二端连接，所述第二电容的另一端接地。
  6. 根据权利要求5所述的补偿电路，其中，所述第二薄膜晶体管和所述第三薄膜晶体管均为双栅极薄膜晶体管，所述第二薄膜晶体管的第二端为所述双栅极薄膜晶体管的底栅极，所述第二薄膜晶体管的第四端为所述双栅极薄膜晶体管的顶栅极，所述第三薄膜晶体管的第二端为所述双栅极薄膜晶体管的底栅极，所述第三薄膜晶体管的第四端为所述双栅极薄膜晶体管的顶栅极。
  7. 根据权利要求6所述的补偿电路，其中，所述补偿电路在预充电时，所述第一时钟信号为高电平，所述第二时钟信号为低电平，所述数据信号为低电平，所述第一薄膜晶体管和第二薄膜晶体管打开，所述第四薄膜晶体管关闭。
  8. 根据权利要求6所述的补偿电路，其中，所述补偿电路在编程时，所述第一时钟信号为低电平，所述第二时钟信号为低电平，所述数据信号为低电平，所述第一薄膜晶体管关闭，所述第二薄膜晶体管打开，所述第四薄膜晶体管关闭。
  9. 根据权利要求6所述的补偿电路，其中，所述补偿电路在驱动发光时，所述第一时钟信号为低电平，所述第二时钟信号为高电平，所述数据信号为高电平，所述第一薄膜晶体管关闭，所述第二薄膜晶体管打开，所述第三薄膜晶体管打开，所述第四薄膜晶体管打开。
  10. 一种液晶显示装置，其中，所述液晶显示装置包括背光模组和设置 在所述背光模组的出光面上的显示面板，所述背光模组包括有机发光二极管和补偿电路，所述补偿电路耦接所述有机发光二极管，所述补偿电路至少包括：
    第一开关单元，所述第一开关单元的第一端耦接第一参考电压，所述第一开关单元的第二端耦接第一时钟信号；
    第二开关单元，所述第二开关单元的第一端耦接所述第一开关单元的第三端，所述第二开关单元的第二端耦接预设电压，所述第二开关单元的第三端耦接所述有机发光二极管；
    第三开关单元，所述第三开关单元的第一端耦接第二参考电压，所述第三开关单元的第三端耦接所述有机发光二极管，所述第三开关单元的第四端耦接所述第二开关单元的第四端；
    第四开关单元，所述第四开关单元的第一端耦接数据信号，所述第四开关单元的第二端耦接第二时钟信号，所述第四开关单元的第三端耦接所述第三开关单元的第二端；
    在所述第一开关单元关闭，所述第二开关单元、第三开关单元以及第四开关单元打开时，所述补偿电路驱动所述有机发光二极管发光，进而补偿所述有机发光二极管。
  11. 根据权利要求10所述的液晶显示装置，其中，在所述有机发光二极管发光时，所述有机发光二极管的电流满足以下公式：
    I＝β*(Vdata-Vpre)2
    其中，I为所述有机发光二极管的电流；Vdata为所述数据信号的电压值；Vpre为所述预设电压的电压值。
  12. 根据权利要求10所述的液晶显示装置，其中，所述第一开关单元包括第一薄膜晶体管，所述第一薄膜晶体管的第一端连接所述第一参考电压，所述第一薄膜晶体管的第二端连接所述第一时钟信号；
    所述第二开关单元包括第二薄膜晶体管和第一电容，所述第二薄膜晶体管的第一端连接所述第一薄膜晶体管的第三端，所述第二薄膜晶体管的第二端连接所述预设电压，所述第二薄膜晶体管的第三端连接所述有机发光二极管的正极，所述第一电容的一端与所述第二薄膜晶体管的第一端和第四端连接，所述第一电容的另一端接地。
  13. 根据权利要求12所述的液晶显示装置，其中，所述第三开关单元包括第三薄膜晶体管，所述第三薄膜晶体管的第一端连接所述第二参考电压，所述第三薄膜晶体管的第三端连接所述有机发光二极管的正极，所述第三薄膜晶体管的第四端连接所述第二薄膜晶体管的第四端。
  14. 根据权利要求13所述的液晶显示装置，其中，所述第四开关单元包括第四薄膜晶体管和第二电容，所述第四薄膜晶体管的第一端连接所述数据信号，所述第四薄膜晶体管的第二端连接所述第二时钟信号，所述第四薄膜晶体管的第三端连接所述第三薄膜晶体管的第二端，所述第二电容的一端与所述第四薄膜晶体管的第三端和所述第三薄膜晶体管的第二端连接，所述第二电容的另一端接地。
  15. 根据权利要求14所述的液晶显示装置，其中，所述第二薄膜晶体管和所述第三薄膜晶体管均为双栅极薄膜晶体管，所述第二薄膜晶体管的第二端为所述双栅极薄膜晶体管的底栅极，所述第二薄膜晶体管的第四端为所述双栅极薄膜晶体管的顶栅极，所述第三薄膜晶体管的第二端为所述双栅极薄膜晶体管的底栅极，所述第三薄膜晶体管的第四端为所述双栅极薄膜晶体管的顶栅极。
  16. 根据权利要求15所述的液晶显示装置，其中，所述补偿电路在预充电时，所述第一时钟信号为高电平，所述第二时钟信号为低电平，所述数据信号为低电平，所述第一薄膜晶体管和第二薄膜晶体管打开，所述第四薄膜晶体管关闭。
  17. 根据权利要求15所述的液晶显示装置，其中，所述补偿电路在编程时，所述第一时钟信号为低电平，所述第二时钟信号为低电平，所述数据信号为低电平，所述第一薄膜晶体管关闭，所述第二薄膜晶体管打开，所述第四薄膜晶体管关闭。
  18. 根据权利要求15所述的液晶显示装置，其中，所述补偿电路在驱动发光时，所述第一时钟信号为低电平，所述第二时钟信号为高电平，所述数据信号为高电平，所述第一薄膜晶体管关闭，所述第二薄膜晶体管打开，所述第三薄膜晶体管打开，所述第四薄膜晶体管打开。
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