WO2017148362A1 - 一种ddr系统的控制系统及控制方法 - Google Patents

一种ddr系统的控制系统及控制方法 Download PDF

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Publication number
WO2017148362A1
WO2017148362A1 PCT/CN2017/075117 CN2017075117W WO2017148362A1 WO 2017148362 A1 WO2017148362 A1 WO 2017148362A1 CN 2017075117 W CN2017075117 W CN 2017075117W WO 2017148362 A1 WO2017148362 A1 WO 2017148362A1
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Prior art keywords
target value
ddr
parameter
clock
ddr system
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PCT/CN2017/075117
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English (en)
French (fr)
Inventor
曹友铭
姚琮
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华为技术有限公司
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Priority to EP17759213.6A priority Critical patent/EP3413162B1/en
Priority to BR112018067462A priority patent/BR112018067462A2/pt
Publication of WO2017148362A1 publication Critical patent/WO2017148362A1/zh
Priority to US16/116,352 priority patent/US10915158B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a control system and a control method for a DDR system.
  • DDR Double Rate Synchronous Dynamic Random Access Memory
  • ISP Internet Service Provider, Internet Service Provider
  • the system, display system, etc. share a power domain with the DDR system.
  • the power supply voltage and the clock frequency of the DDR system are often set to a fixed value that satisfies the requirements of all functional modules, so that the functional systems can be guaranteed to work normally. But it also brings the power consumption of the DDR system.
  • Embodiments of the present invention provide a control system and a control method for a DDR system, which can reduce power consumption of a DDR system.
  • Embodiments of the present invention provide a control system for a DDR system, including a monitoring unit and a control unit, where:
  • the monitoring unit monitors the working states of the functional systems sharing the power domain with the DDR system, and determines the power parameter target value and the clock parameter target value of the DDR system according to the monitored working states of the functional systems;
  • the control unit controls the power parameter and the clock parameter of the DDR system according to the power parameter target value and the clock parameter target value of the DDR system determined by the monitoring unit.
  • the power parameter may be a power supply voltage
  • the clock parameter may be a clock frequency
  • the monitoring unit may specifically determine the power supply voltage target value and the clock frequency target value of the DDR system according to the monitored operating states of the functional systems;
  • the control unit may specifically control the power voltage and the clock frequency of the DDR system according to the power voltage target value and the clock frequency target value of the DDR system determined by the monitoring unit.
  • the monitoring unit can determine the clock frequency demand value of each function system according to the monitored working state of each functional system; and then determine the power voltage target value and the clock frequency target of the DDR system according to the clock frequency demand value of each functional system. value.
  • the monitoring unit may determine the maximum value as the clock frequency target value of the DDR system in the clock frequency demand value of each functional system; and then determine the DDR system according to the clock frequency target value of the DDR system. Power supply voltage target value.
  • the DDR system is in a self-refresh state during the control unit controlling the power parameter and the clock parameter change of the DDR system; at this time, the control system of the DDR system further includes a delay buffer unit.
  • the delay buffer unit acts as a data storage buffer for each functional system.
  • control unit determines that the amount of data in the delay buffer unit reaches a preset amount of data before controlling the power parameter and the clock parameter change of the DDR system.
  • control unit can control the DDR system to enter the corresponding working mode according to the changed power parameter or the clock parameter after controlling the power parameter and the clock parameter of the DDR system.
  • the embodiment of the invention further provides a control method for a DDR system, including:
  • the power parameters and clock parameters of the DDR system are controlled according to the power parameter target value of the DDR system and the clock parameter target value.
  • the power parameter may be a power supply voltage
  • the clock parameter may be a clock frequency
  • determining the power parameter target value and the clock parameter target value of the DDR system according to the working state of each functional system may specifically include: determining a power supply voltage target value and a clock frequency target value of the DDR system according to working states of the functional systems;
  • the power parameter and the clock parameter of the DDR system are controlled according to the power parameter target value and the clock parameter target value of the DDR system, and specifically, the power voltage and the clock of the DDR system are controlled according to the power voltage target value of the DDR system and the clock frequency target value. frequency.
  • determining the power supply voltage target value and the clock frequency target value of the DDR system according to the working state of each functional system may include:
  • the power supply voltage target value and the clock frequency target value of the DDR system are determined according to the clock frequency demand value of each functional system.
  • determining a power supply voltage target value and a clock frequency target value of the DDR system according to a clock frequency requirement value of each function system may include:
  • the maximum value is determined as the clock frequency target value of the DDR system in the clock frequency demand value of each functional system
  • the power supply voltage target value of the DDR system is determined according to the clock frequency target value of the DDR system.
  • the DDR system is in a self-refresh state; preferably, before controlling the power parameter and the clock parameter of the DDR system, The method includes: determining that the amount of data in the delay buffer unit reaches a preset data amount; wherein the delay buffer unit is used as a data storage buffer of each functional system when the DDR system is in a self-refresh state.
  • the DDR system can be controlled to enter the corresponding working mode according to the changed power parameter or the clock parameter.
  • the power parameters and clock parameters of the DDR system are controlled according to the working states of the functional systems sharing the power domain with the DDR system, that is, the power parameters of the DDR system and
  • the clock parameters are related to the working state of each functional system, which can ensure the normal operation of each functional system and reduce the power consumption of the DDR system.
  • FIG. 1 is a schematic structural diagram of a control system of a DDR system according to an embodiment of the present invention
  • FIG. 2 is a second schematic structural diagram of a control system of a DDR system according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of execution of a control unit in a control system of a DDR system according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of execution of a DDR controller in a DDR system according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart diagram of a method for controlling a DDR system according to an embodiment of the present invention.
  • an embodiment of the present invention provides a control system and a control method for the DDR system.
  • the preferred embodiments of the present invention are described below with reference to the accompanying drawings, which should be understood. The preferred embodiments are only intended to illustrate and explain the present invention and are not intended to limit the invention. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
  • the embodiment of the present invention provides a control system for a DDR system, as shown in FIG. 1 , which may specifically include the following units:
  • the monitoring unit 101 is configured to monitor an operating state of each functional system sharing a power domain with the DDR system; and determine a power parameter target value and a clock parameter target value of the DDR system according to the monitored working states of the functional systems.
  • the working state of the function system may specifically include, but is not limited to, a load state including a function system, an operation scenario, and the like.
  • the control unit 102 is configured to control the power parameter and the clock parameter of the DDR system according to the power parameter target value and the clock parameter target value of the DDR system determined by the monitoring unit 101.
  • the power parameter and the clock parameter of the DDR system have a one-to-one correspondence, so when the power parameter target value of the DDR system is the same as the current value of the power parameter of the DDR system, the clock parameter target value of the DDR system and the clock parameter of the DDR system.
  • the current value is also the same; when the power parameter target value of the DDR system is different from the current value of the power parameter of the DDR system, the clock parameter target value of the DDR system is different from the current value of the clock parameter of the DDR system.
  • the control unit 102 may first determine whether the power parameter target value of the DDR system is different from the current value of the power parameter of the DDR system; when the power parameter target value of the DDR system is the same as the current value of the power parameter of the DDR system, the control The unit 102 does not output the parameter adjustment instruction. At this time, the power parameter and the clock parameter of the DDR system are unchanged; when the power parameter target value of the DDR system is different from the current value of the power parameter of the DDR system, the control unit 102 outputs a parameter adjustment instruction. Control the power parameter of the DDR system to change to the power parameter target value, and control the clock parameter of the DDR system to change to the clock parameter target value.
  • control system of the DDR system provided by the embodiment of the present invention, the power parameter and the clock parameter of the DDR system are related to the working states of the functional systems, and are no longer fixed values, so that the functional systems can be guaranteed to work normally and can be reduced. Power consumption of DDR systems.
  • the power parameter may be a power supply voltage
  • the clock parameter may be a clock frequency
  • the monitoring unit 101 determines the power supply voltage target value and the clock frequency target value of the DDR system according to the monitored operating states of the functional systems.
  • the control unit 102 specifically determines the power supply voltage target value of the DDR system according to the monitoring unit 101.
  • the clock frequency target value controls the power supply voltage and clock frequency of the DDR system.
  • the monitoring unit 101 may first determine a clock frequency demand value of each function system according to the monitored working state of each functional system; and then determine a power supply voltage target value and a clock of the DDR system according to the clock frequency demand value of each functional system. Frequency target value. According to the power supply voltage target value and the clock frequency target value of the DDR system determined by the clock frequency demand value of each functional system, the normal operation of each functional system can be ensured.
  • the monitoring unit 101 may determine the maximum value as the clock frequency target value of the DDR system in the clock frequency demand value of each functional system; and then determine the DDR system according to the clock frequency target value of the DDR system.
  • the target value of the power supply voltage may be determined the maximum value as the clock frequency target value of the DDR system in the clock frequency demand value of each functional system.
  • the foregoing specific embodiment is only a preferred example, and the method for the monitoring unit 101 to determine the power supply voltage target value and the clock frequency target value of the DDR system is simple and straightforward, high in efficiency, and easy to implement.
  • the monitoring unit 101 may also determine the power supply voltage target value and the clock frequency target value of the DDR system according to the clock frequency demand value of each functional system. Since the power parameters and the clock parameters of the functional systems are also in a one-to-one correspondence, in a specific embodiment of the present invention, the monitoring unit 101 can determine the power voltage of each functional system according to the clock frequency requirement value of each functional system.
  • the demand value determines the maximum value in the power supply voltage demand value of each functional system as the power supply voltage target value of the DDR system, and then determine the clock frequency target value of the DDR system according to the power supply voltage target value of the DDR system, of course, the same
  • the maximum value is directly determined as the clock frequency target value of the DDR system in the clock frequency demand value of each functional system.
  • the monitoring unit 101 can determine the power supply voltage target value and the clock frequency target value of the DDR system according to the clock frequency demand value of each functional system in other manners, which will not be described in detail herein.
  • the DDR system is in a self-refresh state during the control unit 102 controlling the power supply parameters and clock parameter changes of the DDR system.
  • control system includes the monitoring unit 101 and the control unit 102, as shown in FIG. 2, including:
  • the delay buffer unit 103 is configured as a data storage buffer of each functional system when the DDR system is in a self-refresh state.
  • control unit 102 can also determine that the amount of data in the delay buffer unit 103 reaches a preset data amount before controlling the power parameter and the clock parameter change of the DDR system.
  • each function system can no longer read data from the DDR system, and can only read data from the delay buffer unit 103, if the delay buffer unit The amount of data in 103 is too small, and if the data is too late to be sent to the functional system, an exception is thrown.
  • the control unit 102 determines that the amount of data in the delay buffer unit 103 is not less than the data requirement of each functional system in the power supply parameter and the clock parameter change process of the DDR system, that is, It is determined that the amount of data in the delay buffer unit 103 reaches a preset amount of data, and it is possible to avoid causing an abnormality.
  • the control unit 102 controls the power supply voltage and the clock frequency of the DDR system according to the power supply voltage target value and the clock frequency target value of the DDR system determined by the monitoring unit 101. Specifically, as shown in FIG. 3, the following steps are performed:
  • Step 301 Determine whether the power supply voltage target value of the DDR system is different from the current value of the power supply voltage of the DDR system.
  • this step 301 is cyclically executed.
  • Step 302 Determine whether the amount of data in the delay buffer unit 103 reaches a preset data amount.
  • step 303 When the amount of data in the delay buffer unit 103 reaches the preset amount of data, proceeds to step 303;
  • Step 303 Output a parameter adjustment instruction, control a power supply voltage of the DDR system to change to a power supply voltage target value, and control a clock frequency of the DDR system to change to a clock frequency target value.
  • the DDR system includes a DDR controller and a DDR PHY (Physical Layer).
  • the parameter adjustment command output by the control unit 102 can be input to the DDR controller of the DDR system, and the DDR controller receives the parameter.
  • the DDR PHY is controlled to enter a self-refresh state even if the DDR system is in a self-refresh state.
  • the DDR controller can change the power supply voltage of the DDR system after controlling the DDR PHY to enter the self-refresh state.
  • the parameter adjustment instruction output by the control unit 102 also needs to be input to the clock generation unit, and the clock generation unit generates a corresponding clock frequency according to the clock frequency target value to input the DDR controller and the DDR PHY of the DDR system. To achieve a change in the clock frequency of the DDR system.
  • the control unit 102 may further adjust the power parameter or the changed clock parameter, that is, the power parameter target.
  • Value or clock parameter target value control the DDR system to enter the corresponding working mode; in different working modes, the number of specific circuits opened in the DDR PHY of the DDR system is different, so the power consumption of the DDR system is also different, so according to the changed power supply
  • the parameter or the changed clock parameter controls the DDR system to enter the corresponding working mode, which can further reduce the power consumption of the DDR system.
  • the DDR controller can control the DDR PHY to leave the self-refresh state, even if the DDR system leaves the self-refresh state and resumes normal operation.
  • the working mode indication information may be carried in the parameter adjustment instruction and sent by the control unit 102 to the DDR controller.
  • the working mode of the DDR system includes a low-power low-voltage mode and a high-energy high-voltage mode, and the DDR controller in the DDR system can specifically execute the flow of FIG. , including the following steps:
  • Step 401 Determine whether a parameter adjustment instruction is received.
  • this step 401 is executed cyclically.
  • Step 402 Control the DDR PHY to enter a self-refresh state, and then control a power supply voltage change of the DDR system.
  • the clock frequency of the DDR system also changes.
  • Step 403 whether the power supply voltage and the clock frequency have stabilized.
  • step 404 When the power supply voltage and the clock frequency have stabilized, proceed to step 404;
  • this week's step 403 is performed cyclically.
  • Step 404 Determine whether it is a low voltage mode.
  • Step 405 controlling the DDR PHY to enter the low voltage mode, and then proceeding to step 407.
  • Step 406 Control the DDR PHY to enter the high voltage mode, and then proceed to step 407.
  • Step 407 Control the DDR PHY to leave the self-refresh state.
  • control system of the DDR system provided by the embodiment of the present invention can reduce the power consumption of the DDR system and save a lot of resources.
  • the embodiment of the invention further provides a mobile terminal, comprising the control system of the above DDR system.
  • control system of the DDR system according to the above embodiment of the present invention, correspondingly, the embodiment of the present invention further provides a control method for the DDR system, as shown in FIG. 5, which may specifically include the following steps:
  • Step 501 Monitor an operating state of each functional system in the power domain shared with the DDR system.
  • the working state of the functional system may be specifically, but not limited to, including a load state of the functional system, an operation scenario, and the like.
  • Step 502 Determine a power parameter target value and a clock parameter target value of the DDR system according to working states of the functional systems.
  • Step 503 Control a power parameter and a clock parameter of the DDR system according to a power parameter target value of the DDR system and a clock parameter target value.
  • control method of the DDR system provided by the embodiment of the present invention, the power supply parameter and the clock parameter of the DDR system are related to the working state of each functional system, and are no longer fixed values, thereby ensuring normal operation of each functional system and reducing Power consumption of DDR systems.
  • the power parameter may be a power supply voltage
  • the clock parameter may be a clock frequency
  • step 502 determining the power parameter target value and the clock parameter target value of the DDR system according to the working state of each functional system, which may include: determining the power voltage target value and the clock of the DDR system according to the working state of each functional system. Frequency target value;
  • Step 503 Control the power parameter and the clock parameter of the DDR system according to the power parameter target value of the DDR system and the target value of the clock parameter, and specifically include: controlling the power of the DDR system according to the power voltage target value of the DDR system and the clock frequency target value. Voltage and clock frequency.
  • determining the power supply voltage target value and the clock frequency target value of the DDR system according to the working state of each functional system may include: determining a clock frequency demand value of each functional system according to an operating state of each functional system; The clock frequency demand value of the function system determines the power supply voltage target value and the clock frequency target value of the DDR system, so as to ensure the normal operation of each functional system.
  • determining the power supply voltage target value and the clock frequency target value of the DDR system according to the clock frequency requirement value of each functional system may specifically include: determining a clock frequency demand value of each functional system. The maximum value is taken as the clock frequency target value of the DDR system; the power supply voltage target value of the DDR system is determined according to the clock frequency target value of the DDR system.
  • determining the power supply voltage target value and the clock frequency target value of the DDR system according to the clock frequency requirement value of each functional system may also be implemented in other manners, which will not be described in detail herein.
  • the DDR system in the process of controlling the power parameter and the clock parameter change of the DDR system, the DDR system is in a self-refresh state; preferably, before controlling the power parameter and the clock parameter change of the DDR system, the method further includes: determining The amount of data in the delay buffer unit reaches a preset data amount; wherein the delay buffer unit is used as a data storage buffer of each functional system when the DDR system is in a self-refresh state.
  • the DDR system can be controlled to enter the corresponding working mode according to the changed power parameter or the clock parameter, thereby further reducing the power consumption of the DDR system.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements a particular function in a block or blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing a particular function in a block or blocks of a flow or a flow and/or block diagram of a flowchart.

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Abstract

一种DDR系统的控制系统及控制方法，能够减小DDR系统的功耗。该系统包括：监测单元，用于监测与DDR系统共用电源域的各功能系统的工作状态；根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值；控制单元，用于根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。

Description

一种DDR系统的控制系统及控制方法
本申请要求在2016年02月29日提交中国专利局、申请号为201610113635.1、发明名称为“一种DDR系统的控制系统及控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及计算机技术领域，特别涉及一种DDR系统的控制系统及控制方法。
背景技术
随着计算机技术的发展，目前的很多通信设备中都会设置DDR(Double Data Rate，双倍速率同步动态随机存储器)系统，通常，设备中的一些功能系统如ISP(Internet Service Provider，互联网服务提供商)系统、显示系统等会和DDR系统共用一个电源域。
现有技术中，当多个功能系统和DDR系统共用一个电源域时，DDR系统的电源电压和时钟频率往往被设置为能满足所有功能模块需求的固定值，这样虽然能够保证各功能系统正常工作，但同时也带来了DDR系统的功耗问题。
发明内容
本发明实施例提供一种DDR系统的控制系统及控制方法，能够减小DDR系统的功耗。
本发明实施例提供了一种DDR系统的控制系统，包括监测单元和控制单元，其中：
监测单元监测与DDR系统共用电源域的各功能系统的工作状态，并根据监测到的各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值；
控制单元根据监测单元确定的DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。
其中，电源参数具体可以为电源电压，时钟参数具体可以为时钟频率。
即，监测单元具体可以根据监测到的各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值；
控制单元具体可以根据监测单元确定的DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时钟频率。
具体的，监测单元可以根据监测到的各功能系统的工作状态，确定各功能系统的时钟频率需求值；然后根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值。
在本发明的一个具体实施例中，监测单元可以在各功能系统的时钟频率需求值中确定出最大值作为DDR系统的时钟频率目标值；然后根据DDR系统的时钟频率目标值，确定DDR系统的电源电压目标值。
进一步的，在本发明实施例中，在控制单元控制DDR系统的电源参数和时钟参数变化的过程中，DDR系统处于自刷新状态；此时，上述DDR系统的控制系统，还包括延迟缓冲单元，在DDR系统处于自刷新状态时，延迟缓冲单元作为各功能系统的数据存储缓存。
较佳的，控制单元可以在控制DDR系统的电源参数和时钟参数变化之前，确定延迟缓冲单元中的数据量达到预设数据量。
较佳的，控制单元可以在控制DDR系统的电源参数和时钟参数变化之后，根据变化后的电源参数或时钟参数，控制DDR系统进入相应的工作模式。
本发明实施例还提供了一种DDR系统的控制方法，包括：
监测与DDR系统共用电源域的各功能系统的工作状态；
根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值；
根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。
其中，电源参数具体可以为电源电压，时钟参数具体可以为时钟频率。
即，根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值，具体可以包括：根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值；
根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数，具体可以包括：根据DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时钟频率。
具体的，根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值，可以包括：
根据各功能系统的工作状态，确定各功能系统的时钟频率需求值；
根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值。
在本发明的一个具体实施例中，根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值，具体可以包括：
在各功能系统的时钟频率需求值中确定出最大值作为DDR系统的时钟频率目标值；
根据DDR系统的时钟频率目标值，确定DDR系统的电源电压目标值。
进一步的，在本发明实施例中，在控制DDR系统的电源参数和时钟参数变化的过程中，DDR系统处于自刷新状态；较佳的，在控制DDR系统的电源参数和时钟参数变化之前，还包括：确定延迟缓冲单元中的数据量达到预设数据量；其中，延迟缓冲单元，在DDR系统处于自刷新状态时作为各功能系统的数据存储缓存。
较佳的，在控制DDR系统的电源参数和时钟参数变化之后，还可以根据变化后的电源参数或时钟参数，控制DDR系统进入相应的工作模式。
根据本发明实施例提供的DDR系统的控制系统及控制方法，根据与DDR系统共用电源域的各功能系统的工作状态，对DDR系统的电源参数和时钟参数进行控制，即DDR系统的电源参数和时钟参数与各功能系统的工作状态有关，既能够保证各功能系统正常工作，又减小了DDR系统的功耗。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中：
图1为本发明实施例提供的DDR系统的控制系统的结构示意图之一；
图2为本发明实施例提供的DDR系统的控制系统的结构示意图之二；
图3为本发明实施例提供的DDR系统的控制系统中的控制单元执行的流程示意图；
图4为本发明实施例提供的DDR系统中的DDR控制器执行的流程示意图；
图5为本发明实施例提供的DDR系统的控制方法的流程示意图。
具体实施方式
为了给出减小DDR系统功耗的实现方案，本发明实施例提供了一种DDR系统的控制系统及控制方法，以下结合说明书附图对本发明的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本发明实施例提供了一种DDR系统的控制系统，如图1所示，具体可以包括如下单元：
监测单元101，用于监测与DDR系统共用电源域的各功能系统的工作状态；根据监测到的各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值。其中，功能系统的工作状态具体可以但不限于包括功能系统的负载状态、运行场景等。
控制单元102，用于根据监测单元101确定的DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。
通常，DDR系统的电源参数和时钟参数是一一对应的关系，因此当DDR系统的电源参数目标值与DDR系统的电源参数当前值相同时，DDR系统的时钟参数目标值与DDR系统的时钟参数当前值也相同；当DDR系统的电源参数目标值与DDR系统的电源参数当前值不相同时，DDR系统的时钟参数目标值与DDR系统的时钟参数当前值也不相同。
因此实际实施时，控制单元102可以先判断DDR系统的电源参数目标值与DDR系统的电源参数当前值是否不相同；在DDR系统的电源参数目标值与DDR系统的电源参数当前值相同时，控制单元102不输出参数调整指令，此时，DDR系统的电源参数和时钟参数不变；在DDR系统的电源参数目标值与DDR系统的电源参数当前值不相同时，控制单元102输出参数调整指令，控制DDR系统的电源参数变化至电源参数目标值，控制DDR系统的时钟参数变化至时钟参数目标值。
即本发明实施例提供的DDR系统的控制系统，DDR系统的电源参数和时钟参数与各功能系统的工作状态有关，不再为固定值，这样既能够保证各功能系统正常工作，又能够减小DDR系统的功耗。
在本发明实施例中，上述电源参数具体可以为电源电压，时钟参数具体可以为时钟频率。
此时，监测单元101具体根据监测到的各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值；控制单元102具体根据监测单元101确定的DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时钟频率。
具体的，监测单元101可以根据监测到的各功能系统的工作状态，先确定各功能系统的时钟频率需求值；然后根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值。根据各功能系统的时钟频率需求值确定的DDR系统的电源电压目标值和时钟频率目标值，能够保证各功能系统的正常工作。
在本发明的一个具体实施例中，监测单元101可以在各功能系统的时钟频率需求值中确定出最大值作为DDR系统的时钟频率目标值；然后根据DDR系统的时钟频率目标值，确定DDR系统的电源电压目标值。
需要说明的是，上述具体实施例仅为一个较佳示例，监测单元101确定DDR系统的电源电压目标值和时钟频率目标值的方法简单直接，效率较高，且易于实现。
在本发明的其它具体实施例中，监测单元101也可以采用其它方式根据各功能系统的时钟频率需求值确定DDR系统的电源电压目标值和时钟频率目标值。由于各功能系统的电源参数和时钟参数也是一一对应的关系，因此，在本发明的一个具体实施例中，监测单元101可以根据各功能系统的时钟频率需求值，确定各功能系统的电源电压需求值，然后在各功能系统的电源电压需求值中确定出最大值作为DDR系统的电源电压目标值，然后根据DDR系统的电源电压目标值，确定DDR系统的时钟频率目标值，当然也可以同前述具体实施例，在各功能系统的时钟频率需求值中直接确定出最大值作为DDR系统的时钟频率目标值。
当然，监测单元101还可以采用其它方式根据各功能系统的时钟频率需求值确定DDR系统的电源电压目标值和时钟频率目标值，在此不再举例详述。
在本发明实施例中，在控制单元102控制DDR系统的电源参数和时钟参数变化的过程中，DDR系统处于自刷新状态。
因此，实际实施时，控制系统除了包括监测单元101、控制单元102，还可以如图2所示，包括：
延迟缓冲单元103，用于在DDR系统处于自刷新状态时作为各功能系统的数据存储缓存。
较佳的，控制单元102，还可以在控制DDR系统的电源参数和时钟参数变化之前，确定延迟缓冲单元103中的数据量达到预设数据量。
在DDR系统的电源参数和时钟参数变化过程中，DDR系统处于自刷新状态时，各功能系统无法再从DDR系统中读取数据，只能从延迟缓冲单元103中读取数据，若延迟缓冲单元103中的数据量过少，数据来不及送入功能系统，则会引发异常。
因此，控制单元102在控制DDR系统的电源参数和时钟参数变化之前，确定延迟缓冲单元103中的数据量不少于DDR系统的电源参数和时钟参数变化过程中各功能系统的数据需求量，即确定延迟缓冲单元103中的数据量达到预设数据量，能够避免引发异常。
即当电源参数具体为电源电压，时钟参数具体为时钟频率，控制单元102在根据监测单元101确定的DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时钟频率时，具体可以如图3所示，执行下述步骤：
步骤301、判断DDR系统的电源电压目标值与DDR系统的电源电压当前值是否不相同。
当DDR系统的电源电压目标值与DDR系统的电源电压当前值不相同时，进入步骤302；
当DDR系统的电源电压目标值与DDR系统的电源电压当前值相同时，循环执行本步骤301。
步骤302、判断延迟缓冲单元103中的数据量是否达到预设数据量。
当延迟缓冲单元103中的数据量达到预设数据量时，进入步骤303；
当延迟缓冲单元103中的数据量未达到预设数据量时，返回执行步骤301。
步骤303、输出参数调整指令，控制DDR系统的电源电压变化至电源电压目标值，控制DDR系统的时钟频率变化至时钟频率目标值。
如图2中所示，DDR系统中包括DDR控制器以及DDR PHY(Physical Layer，物理层)，控制单元102输出的参数调整指令可以输入至DDR系统的DDR控制器，DDR控制器在接收到参数调整指令后控制DDR PHY进入自刷新状态，即使DDR系统处于自刷新状态。
当电源参数具体为电源电压时，DDR控制器可以在控制DDR PHY进入自刷新状态后进行DDR系统的电源电压的变化。
当时钟参数具体为时钟频率时，控制单元102输出的参数调整指令还需要输入至时钟产生单元，由时钟产生单元根据时钟频率目标值产生相应的时钟频率输入至DDR系统的DDR控制器和DDR PHY，实现DDR系统的时钟频率的变化。
较佳的，控制单元102在控制DDR系统的电源参数变化至电源参数目标值、时钟参数变化至时钟参数目标值之后，还可以根据变化后的电源参数或变化后的时钟参数，即电源参数目标值或时钟参数目标值，控制DDR系统进入相应的工作模式；不同的工作模式下，DDR系统的DDR PHY中开启的具体电路数量不同，因此DDR系统的功耗也不同，所以根据变化后的电源参数或变化后的时钟参数，控制DDR系统进入相应的工作模式，能够进一步减小DDR系统的功耗。之后，DDR控制器可以控制DDR PHY离开自刷新状态，即使DDR系统离开自刷新状态，恢复正常工作状态。
实际实施时，工作模式指示信息可以携带在参数调整指令，由控制单元102发送至DDR控制器。
当电源参数具体为电源电压，时钟参数具体为时钟频率时，假设，DDR系统的工作模式包括低能耗的低压模式和高能耗的高压模式，那么DDR系统中的DDR控制器具体可以执行图4流程，包括下述步骤：
步骤401、判断是否接收到参数调整指令。
当接收到参数调整指令时，进入步骤402；
当未接收到参数调整指令时，循环执行本步骤401。
步骤402、控制DDR PHY进入自刷新状态，然后控制DDR系统的电源电压变化。
在DDR PHY进入自刷新状态后，DDR系统的时钟频率也发生变化。
步骤403、电源电压和时钟频率是否已经稳定。
当电源电压和时钟频率已经稳定时，进入步骤404；
当电源电压和时钟频率未稳定时，循环执行本周步骤403。
步骤404、判断是否为低压模式。
当确定为低压模式时，进入步骤405；
当确定不为低压模式时，进入步骤406。
步骤405、控制DDR PHY进入低压模式，而后进入步骤407。
步骤406、控制DDR PHY进入高压模式，而后进入步骤407。
步骤407、控制DDR PHY离开自刷新状态。
综上，采用本发明实施例提供的DDR系统的控制系统，能够减小DDR系统的功耗，节省大量资源。
本发明实施例还提供了一种移动终端，包括上述DDR系统的控制系统。
基于同一发明构思，根据本发明上述实施例提供的DDR系统的控制系统，相应地，本发明实施例还提供一种DDR系统的控制方法，如图5所示，具体可以包括如下步骤：
步骤501、监测与DDR系统共用电源域的各功能系统的工作状态；其中，功能系统的工作状态具体可以但不限于包括功能系统的负载状态、运行场景等。
步骤502、根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值。
步骤503、根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。
即本发明实施例提供的DDR系统的控制方法，DDR系统的电源参数和时钟参数与各功能系统的工作状态有关，不再为固定值，这样既能够保证各功能系统正常工作，又能够减小DDR系统的功耗。
在本发明实施例中，上述电源参数具体可以为电源电压，时钟参数具体可以为时钟频率。
此时，步骤502、根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值，具体可以包括：根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值；
步骤503、根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数，具体可以包括：根据DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时钟频率。
具体的，上述根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值，可以包括：根据各功能系统的工作状态，确定各功能系统的时钟频率需求值；然后根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值，这样能够保证各功能系统的正常工作。
在本发明的一个具体实施例中，上述根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值，具体可以包括：在各功能系统的时钟频率需求值中确定出最大值作为DDR系统的时钟频率目标值；根据DDR系统的时钟频率目标值，确定DDR系统的电源电压目标值。
在本发明的其它具体实施例中，根据各功能系统的时钟频率需求值确定DDR系统的电源电压目标值和时钟频率目标值还可以采用其它方式实现，在此不再举例详述。
在本发明实施例中，在控制DDR系统的电源参数和时钟参数变化的过程中，DDR系统处于自刷新状态；较佳的，在控制DDR系统的电源参数和时钟参数变化之前，还包括：确定延迟缓冲单元中的数据量达到预设数据量；其中，延迟缓冲单元，在DDR系统处于自刷新状态时作为各功能系统的数据存储缓存。
较佳的，在控制DDR系统的电源参数和时钟参数变化之后，还可以根据变化后的电源参数或时钟参数，控制DDR系统进入相应的工作模式，能够进一步减小DDR系统的功耗。
上述各步骤可以可对应于图1、图2所示结构中的相应单元功能，在此不再赘述。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中特定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中特定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中特定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (13)

  1. 一种DDR系统的控制系统，其特征在于，包括：
    监测单元，用于监测与DDR系统共用电源域的各功能系统的工作状态；根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值；
    控制单元，用于根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。
  2. 如权利要求1所述的控制系统，其特征在于，
    所述监测单元，具体用于根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值；
    所述控制单元，具体用于根据DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时钟频率。
  3. 如权利要求2所述的控制系统，其特征在于，所述监测单元，具体用于根据各功能系统的工作状态，确定各功能系统的时钟频率需求值；根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值。
  4. 如权利要求3所述的控制系统，其特征在于，所述监测单元，具体用于在各功能系统的时钟频率需求值中确定出最大值作为DDR系统的时钟频率目标值；根据DDR系统的时钟频率目标值，确定DDR系统的电源电压目标值。
  5. 如权利要求1-4任一所述的控制系统，其特征在于，在所述控制单元控制DDR系统的电源参数和时钟参数变化的过程中，DDR系统处于自刷新状态；
    所述控制系统，还包括：
    延迟缓冲单元，用于在DDR系统处于自刷新状态时作为各功能系统的数据存储缓存。
  6. 如权利要求5所述的控制系统，其特征在于，所述控制单元，还用于在控制DDR系统的电源参数和时钟参数变化之前，确定所述延迟缓冲单元中的数据量达到预设数据量。
  7. 如权利要求1-6任一所述的控制系统，其特征在于，所述控制单元，还用于在控制DDR系统的电源参数和时钟参数变化之后，根据变化后的电源参数或时钟参数，控制DDR系统进入相应的工作模式。
  8. 一种DDR系统的控制方法，其特征在于，包括：
    监测与DDR系统共用电源域的各功能系统的工作状态；
    根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值；
    根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数。
  9. 如权利要求8所述的控制方法，其特征在于，
    根据各功能系统的工作状态，确定DDR系统的电源参数目标值和时钟参数目标值，具体包括：
    根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值；
    根据DDR系统的电源参数目标值和时钟参数目标值，控制DDR系统的电源参数和时钟参数，具体包括：
    根据DDR系统的电源电压目标值和时钟频率目标值，控制DDR系统的电源电压和时 钟频率。
  10. 如权利要求9所述的控制方法，其特征在于，根据各功能系统的工作状态，确定DDR系统的电源电压目标值和时钟频率目标值，具体包括：
    根据各功能系统的工作状态，确定各功能系统的时钟频率需求值；
    根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值。
  11. 如权利要求10所述的控制方法，其特征在于，根据各功能系统的时钟频率需求值，确定DDR系统的电源电压目标值和时钟频率目标值，具体包括：
    在各功能系统的时钟频率需求值中确定出最大值作为DDR系统的时钟频率目标值；
    根据DDR系统的时钟频率目标值，确定DDR系统的电源电压目标值。
  12. 如权利要求8-11任一所述的控制方法，其特征在于，在控制DDR系统的电源参数和时钟参数变化的过程中，DDR系统处于自刷新状态；
    在控制DDR系统的电源参数和时钟参数变化之前，还包括：确定延迟缓冲单元中的数据量达到预设数据量；其中，所述延迟缓冲单元，在DDR系统处于自刷新状态时作为各功能系统的数据存储缓存。
  13. 如权利要求8-12任一所述的控制方法，其特征在于，在控制DDR系统的电源参数和时钟参数变化之后，还包括：根据变化后的电源参数或时钟参数，控制DDR系统进入相应的工作模式。
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