WO2017148240A1

WO2017148240A1 - Loss-of-lock detection system and method for phase-locked loop

Info

Publication number: WO2017148240A1
Application number: PCT/CN2017/072902
Authority: WO
Inventors: 顾春杰; 陈永铭; 王仁巧; 杨硕
Original assignee: 中兴通讯股份有限公司
Priority date: 2016-03-03
Filing date: 2017-02-04
Publication date: 2017-09-08
Also published as: CN107154800A; CN107154800B

Abstract

A loss-of-lock detection system for a phase-locked loop. An input clock frequency of the phase-locked loop is smaller than an output clock frequency of the phase-locked loop. The system comprises a frequency divider, a trigger, and a counter. The frequency divider uses an output clock of the phase-locked loop as a clock signal, and an output end of the frequency divider is connected to a data end of the trigger. The trigger uses an input clock of the phase-locked loop as a sampling clock, and an output end of the trigger is separately connected to a reset end of the frequency divider and a reset end of the counter. The counter uses the input clock of the phase-locked loop as a counting clock, and an output end of the counter outputs an indication signal indicating lock or loss of lock.

Description

Detection system and detection method for phase locked loop loss of lock

Technical field

The present disclosure relates to the field of phase locked loops, for example, to a detection system and a detection method for a phase locked loop loss of lock.

Background technique

Two types of phase-locked loop loss detection methods are usually used: the first is to directly use the lock-lock signal reported by the phase-locked loop chip, and the second is to count the phase-locked loop input clock and the phase-locked loop output clock in the logic unit. Detection, each phase-locked loop input clock cycle counts with the phase-locked loop output clock, and detects whether the count value is equal to the ratio of the phase-locked loop output clock to the input clock frequency.

The disadvantage of the first method is that the reference source is interfered by the line or the internal locking standard of the phase-locked loop chip is too strict, so that the phase-locked loop chip often reports the loss-of-lock alarm that the system does not care about, and the detection is too strict; the disadvantage of the second method is that There is an error in the count value, and each count cycle counter is cleared to recalculation, no phase accumulation, resulting in failure to detect even if the phase locked loop is lost, and the detection is too loose.

Summary of the invention

The present disclosure provides a detection system and a detection method for a phase locked loop loss lock, and flexibly sets a lockout detection standard for a phase locked loop.

The present disclosure provides a detection system for a phase locked loop loss of lock, the input clock frequency of the phase locked loop is less than the output clock frequency of the phase locked loop; the system includes:

Frequency dividers, flip-flops and counters;

The frequency divider uses the output clock of the phase locked loop as a clock signal, and the output end is connected to the data end of the flip-flop;

The flip-flop takes an input clock of the phase-locked loop as a sampling clock, and an output terminal is respectively connected to a clear end of the frequency divider and a clear end of the counter;

The counter uses the input clock of the phase locked loop as a counting clock, and the output terminal outputs an indication signal indicating locking or loss of lock.

Optionally, the frequency divider is configured to divide an output signal of the phase locked loop, generate a periodic pulse signal of the same frequency as the input clock of the phase locked loop, and output.

Optionally, the flip-flop samples a periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop, when the frequency divider outputs a positive pulse and the sampling value is low. Normally, an output signal indicating a clear operation is generated, or when the frequency divider outputs a negative pulse and the sample value is a high level, an output signal indicating a clear operation is generated;

The frequency divider is cleared when the clear terminal receives the output signal indicating the clear operation and generates a half-width pulse output;

The counter is cleared when the clear terminal receives the output signal indicating the clear operation, and outputs an indication signal indicating that the lock is lost.

Optionally, the counter counts on each rising edge or each falling edge of the input clock of the phase locked loop; and no longer accumulates when the count value reaches a predetermined count overflow value, and outputs an indication signal indicating the lock.

Optionally, the periodic pulse signal generated by the frequency divider is a positive pulse or a negative pulse; and the frequency divider and the counter are synchronously cleared or asynchronously cleared.

The present disclosure also provides a method for detecting a phase locked loop loss of lock, the method comprising:

The frequency divider uses the output clock of the phase locked loop as a clock signal, and sends the output signal to the data end of the trigger;

The flip-flop uses an input clock of the phase-locked loop as a sampling clock, and sends an output signal to a clear end of the frequency divider and a clear end of the counter;

The counter uses the input clock of the phase locked loop as a count clock, and outputs an indication signal indicating lock or loss of lock.

Optionally, the method further includes:

The frequency divider divides the output signal of the phase locked loop to generate a periodic pulse signal of the same frequency as the input clock of the phase locked loop and outputs the same.

Optionally, the method further includes:

The flip-flop samples a periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop, and generates a representation when the frequency divider outputs a positive pulse and the sampling value is a low level. Clearing the output signal of the operation, or when the frequency divider outputs a negative pulse and the sample value is high level, generating an output signal indicating a clear operation;

Optionally, the method further includes:

The counter counts on each rising edge or each falling edge of the input clock of the phase locked loop; and no longer accumulates when the count value reaches a predetermined count overflow value, and outputs an indication signal indicating the lock.

Optionally, the periodic pulse signal generated by the frequency divider is a positive pulse or a negative pulse; and the frequency divider and the counter are synchronously cleared or asynchronously cleared. The above solution can set different frequency divider output pulse width according to different scenarios, different phase-locked loops, select different counter overflow values, and realize adjustable phase-locked loop loss detection. The above technical solution can not only avoid the interference of the reference source signal or the unnecessary lockout alarm caused by the strict internal locking standard of the phase locked loop chip, but also avoid the false lock indication caused by the traditional counting detection being too loose.

DRAWINGS

1 is a schematic structural view of a detection system for a phase locked loop loss lock in the first embodiment;

2 is a first schematic diagram of a detection system for a phase locked loop loss lock in the second embodiment;

3 is a second schematic diagram of a detection system for phase-locked loop loss of lock in the second embodiment;

4 is a schematic diagram of a detection system for phase-locked loop loss of lock in the third embodiment;

FIG. 5 is a flow chart of a method for detecting a loss of a phase locked loop in the fourth embodiment.

detailed description

In order to make the technical solutions of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.

Embodiment 1

As shown in FIG. 1 , the embodiment provides a detection system for a phase locked loop loss lock. The input clock frequency of the phase locked loop is smaller than the output clock frequency of the phase locked loop. The system includes:

Frequency divider 11, flip-flop 12 and counter 13.

The frequency divider 11 uses the output clock of the phase locked loop as a clock signal, and the output end is connected to the data end of the flip-flop 12.

The flip-flop 12 uses the input clock of the phase-locked loop as a sampling clock, and the output terminal is respectively connected to the clearing end of the frequency divider 11 and the clearing end of the counter 13.

The counter 13 uses the input clock of the phase locked loop as a count clock, and the output terminal outputs an indication signal indicating lock or loss of lock.

Optionally, the frequency divider 11 is configured to divide an output signal of the phase locked loop to generate a periodic pulse signal of the same frequency as the input clock of the phase locked loop and output the same.

Optionally, the flip-flop 12 samples a periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop, when the frequency divider outputs a positive pulse and the sampling value is low. At the level, an output signal indicating a clear operation is generated, or when the frequency divider outputs a negative pulse and the sample value is a high level, an output signal indicating a clear operation is generated;

The frequency divider 11 is cleared and generates a half-width pulse output when the clear terminal receives the output signal indicating the clear operation;

The counter 13 is cleared when the clear terminal receives the output signal indicating the clear operation, and outputs an indication signal indicating that the lock is lost.

Optionally, the counter 13 counts on each rising edge or each falling edge of the input clock of the phase locked loop; and no longer accumulates when the count value reaches a predetermined count overflow value, and outputs an indication signal indicating the lock .

Optionally, the periodic pulse signal generated by the frequency divider 11 is a positive pulse or a negative pulse; and the frequency divider 11 and the counter 12 are synchronously cleared or asynchronously cleared.

Embodiment 2

As shown in Figure 2, the external reference source is connected to a logic unit (such as a logic circuit) including a frequency divider, a flip-flop, and a counter. The external reference can be directly outputted inside the logic unit, or can be output to the lower stage after being divided. The phase-locked loop, the external reference source can also be directly output to the phase-locked loop outside the logic unit. The phase-locked loop locks the external reference source and generates a clock output to the logic unit for phase-lock detection.

As shown in Figure 3, the phase-locked loop output is connected to a frequency divider, and the appropriate frequency division number can be set. The divided clock frequency is equal to the clock frequency of the phase-locked loop input. The clock output from the divider is a periodic pulse signal. The polarity and width of the pulse are adjustable. When the divider is cleared, a half-width pulse output is generated.

The divider output is connected to the data terminal of the flip-flop. The trigger uses the phase-locked loop input clock sampling, and the trigger data output terminal is connected to the clearing end of the frequency divider and the counter.

The flip-flop samples the periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop.

When the frequency divider outputs a positive pulse and the sample value is low, an output signal indicating a clear operation is generated. Alternatively, when the frequency divider outputs a negative pulse and the sample value is high, an output signal indicating a clear operation is generated. If an output signal indicating a clear operation is generated, a clear operation is performed, that is, the divider is cleared and a half-width pulse is generated, and the counter is cleared.

When the divider outputs a positive pulse and the sample value is high, no output signal indicating a clear operation is generated. Alternatively, when the frequency divider outputs a negative pulse and the sample value is low level, an output signal indicating a clear operation is not generated. If an output signal indicating a clear operation is not generated, the frequency divider outputs a periodic pulse in accordance with the frequency division number while the counter is accumulated until overflow.

The counter uses the phase-locked loop input clock as the count clock. When the counter is cleared, the count value is cleared. When the counter is not cleared, the count value period is accumulated. When the count value overflows, the lock indication signal is no longer accumulated and output. In this embodiment, the count overflow value is adjustable. The count overflow value cannot be set too small. If the setting is too small, when the phase-locked loop loses lock, when the counter is not cleared, the counter overflow value will be generated and a false lock indication will be generated. The count overflow value cannot be set too large. If the setting is too large, the lock will be delayed after the phase locked loop is normally locked.

Embodiment 3

In the scenario of the third embodiment, the phase-locked loop input clock is 8 kHz, and the phase-locked loop output clock is 50 MHz. This scenario allows the reference source to have a phase jump of 1 us without generating a lock-out alarm. The phase-locked loop input clock and the phase-locked loop output clock can be set as needed, which is not limited in this disclosure.

The input clock of the frequency divider is 50MHz, the output clock frequency of the frequency divider is 8KHz, and the positive pulse width is 2us, that is, the phase-locked loop input clock has a phase jump redundancy of about 1us. When the divider is cleared, the count value is cleared to 50, and the divider output is set to high level 1. When the count reaches 100, the divider output is set to low level 0. When the count is up to 6250, the count value is automatically cleared to 0. At the same time, the divider output is set to a high level of 1.

Assume that the phase-locked loop loses lock, the frequency offset between the input clock and the output clock of the phase-locked loop is 1ppm. When the trigger is sampled to the output clock of the divider, the divider is cleared, and the divider output is 1us. A positive pulse of width, the counter is cleared, and the lockout indication 0 is output. The flip-flop is sampled once every 125us, the sampling value is high level, the frequency divider is normally divided by the clearing operation, and the counter is added in sequence but not overflowing still outputs the loss of lock indication 0. After 8000 consecutive samples are high, the frequency is divided. The cumulative phase drift of the output clock relative to the phase-locked loop input clock is 125us*8000*10 ^-6 =1us. The frequency divider output clock is relative to the phase-locked loop input clock. The accumulated phase drifts 1us to the left or 1us to the right. The next trigger sampling will sample low.

As shown in Figure 4, the dotted line in the output of the divider shows the output of the divider when it is not cleared. The trigger is sampled low, the divider is cleared, and the divider outputs a positive pulse of 1us width. Cleared and outputs the lockout indication 0. The divider and counter are cleared once every 8000 samples. If the counter overflow value is set to 9000, the counter will never overflow and the output loss lock indication will be maintained.

When the phase-locked loop is locked, the frequency synchronization between the input clock and the output clock of the phase-locked loop is achieved. After the initial clear operation, the phase difference between the phase-locked loop input clock and the divider output clock is stable at 1us, and 9000 consecutive samples are used. If it is high, the divider and counter do not clear operation, and the counter overflows. The count value is stable at 9000, no longer accumulate, and the output lock indication is 1. Even if the reference source is disturbed and the phase jumps, the output lock indication 1 is stabilized within ±1us.

It should be noted that, in the embodiment of the present disclosure, the count overflow value may be set according to the selected phase locked loop and the application scenario. For example, if the selected phase-locked loop is allowed to change to Xus in this scenario, the width of the positive and negative pulses generated by the divider can be set to 2Xus (1Xus respectively), and if the phase-locked loop loses lock, The frequency offset between the input clock and the output clock of the phase-locked loop is Yppm (1ppm=10 ^-6 ). The phase-locked loop input clock, that is, the sampling clock frequency of the flip-flop is F KHz, then when the phase-locked loop loses lock After the sampling is required N times, the frequency divider and the counter generate a clear operation.

Taking the third embodiment as an example, F=8, X=1, Y=1,

Calculated at this time

That is to say, the counter overflow value is slightly larger than 8000, for example, 9000.

The above technical solution according to different application scenarios, different phase-locked loop chips set different pulse widths of the frequency divider output, can prevent unnecessary loss of lock alarm under the allowed interference conditions, and can prevent the system from being caused by the reference source interference. The fault of the phase-locked loop lost lock has not occurred yet. In addition, according to different application scenarios, different phase-locked loop chips set the counter overflow value of the counter, and the overflow value cannot be too small, and when the phase-locked loop loses lock, the counter has reached the overflow value and is incorrectly locked when the counter is not cleared. Indicates that the overflow value cannot be too large to prevent the lock from being displayed after the normal lock is prevented.

In the embodiment of the present disclosure, the phase-locked loop input clock frequency is less than the phase-locked loop output clock frequency. Optionally, the phase-locked loop input clock frequency is less than 10 times and above the phase-locked loop output clock frequency.

Meanwhile, the technical solution of the embodiment of the present disclosure does not limit whether the sampling clock of the frequency divider, the flip-flop, and the counter in the logic unit adopts a rising edge or a falling edge, and does not limit whether the frequency divider and the counter adopt synchronous clearing or asynchronous clearing.

Embodiment 4

As shown in FIG. 5, the embodiment provides a method for detecting a phase-locked loop loss lock, which is applied to the phase-locked loop loss-of-lock detection system according to any one of embodiments 1 to 3.

In step 110, the frequency divider sends the output signal to the data end of the flip-flop with the output clock of the phase-locked loop as a clock signal.

In step 120, the flip-flop uses the input clock of the phase-locked loop as a sampling clock, and sends an output signal to the clearing end of the frequency divider and the clearing end of the counter.

In step 130, the counter uses the input clock of the phase locked loop as a count clock, and outputs an indication signal indicating lock or loss of lock.

Optionally, the method further includes:

The method further includes:

The flip-flop samples a periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop, and generates a representation when the frequency divider outputs a positive pulse and the sampling value is a low level. Clearing the output signal of the operation, or when the divider outputs a negative pulse and the sample value is high Generating an output signal indicative of a clearing operation;

Optionally, the method further includes:

The counter counts on each rising edge or each falling edge of the input clock of the phase locked loop; and no longer accumulates when the count value reaches a predetermined count overflow value, and outputs an indication signal indicating the lock. Optionally, the periodic pulse signal generated by the frequency divider is a positive pulse or a negative pulse; and the frequency divider and the counter are synchronously cleared or asynchronously cleared. The above description is only an alternative embodiment of the present disclosure. One of ordinary skill in the art will appreciate that all or a portion of the steps described above can be accomplished by a program that instructs the associated hardware, such as a read-only memory, a magnetic or optical disk, and the like. Optionally, all or part of the steps of the foregoing embodiments may also be implemented by using one or more integrated circuits. Accordingly, the modules in the foregoing embodiments may be implemented in the form of hardware, and may be implemented in the form of software functional modules. It can be implemented in a combination of software and hardware.

Industrial applicability

The detection system and the detection method of the phase locked loop loss lock provided by the embodiment of the present disclosure flexibly adjust the lockout detection of the phase locked loop, and avoid the unnecessary loss caused by the interference of the reference source signal or the strict internal locking standard of the phase locked loop chip. The lock alarm can also avoid the mis-locking indication caused by the traditional counting detection being too loose.

Claims

A detection system for locking a phase locked loop, wherein an input clock frequency of the phase locked loop is smaller than an output clock frequency of the phase locked loop; the system includes:

Frequency dividers, flip-flops, and counters; among them,

The frequency divider uses the output clock of the phase locked loop as a clock signal, and the output end is connected to the data end of the flip-flop;

The flip-flop takes an input clock of the phase-locked loop as a sampling clock, and an output terminal is respectively connected to a clear end of the frequency divider and a clear end of the counter;

The counter uses the input clock of the phase locked loop as a counting clock, and the output terminal outputs an indication signal indicating locking or loss of lock.
The system of claim 1 wherein:

The frequency divider is configured to divide an output signal of the phase locked loop to generate a periodic pulse signal of the same frequency as the input clock of the phase locked loop and output the same.
The system of claim 1 wherein:

The flip-flop samples a periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop, and generates a representation when the frequency divider outputs a positive pulse and the sampling value is a low level. Clearing the output signal of the operation, or when the frequency divider outputs a negative pulse and the sample value is high level, generating an output signal indicating a clear operation;

The frequency divider is cleared when the clear terminal receives the output signal indicating the clear operation and generates a half-width pulse output;

The counter is cleared when the clear terminal receives the output signal indicating the clear operation, and outputs an indication signal indicating that the lock is lost.
The system of claim 3 wherein:

The counter counts on each rising edge or each falling edge of the input clock of the phase locked loop; And when the count value reaches the predetermined count overflow value, it is no longer accumulated, and an indication signal indicating the lock is output.
The system of claim 1 wherein:

The periodic pulse signal generated by the frequency divider is a positive pulse or a negative pulse; and the frequency divider and the counter are synchronously cleared or asynchronously cleared.
A method for detecting a lockout of a phase locked loop, the method for detecting a phase locked loop loss of lock according to any one of claims 1 to 5, the method comprising:

The frequency divider uses the output clock of the phase locked loop as a clock signal, and sends the output signal to the data end of the trigger;

The flip-flop uses an input clock of the phase-locked loop as a sampling clock, and sends an output signal to a clear end of the frequency divider and a clear end of the counter;

The counter uses the input clock of the phase locked loop as a count clock, and outputs an indication signal indicating lock or loss of lock.
The method of claim 6 wherein said method further comprises:

The frequency divider divides the output signal of the phase locked loop to generate a periodic pulse signal of the same frequency as the input clock of the phase locked loop and outputs the same.
The method of claim 6 further comprising:

The flip-flop samples a periodic pulse signal output by the frequency divider on each rising edge or every falling edge of the input clock of the phase locked loop, and generates a representation when the frequency divider outputs a positive pulse and the sampling value is a low level. Clearing the output signal of the operation, or when the frequency divider outputs a negative pulse and the sample value is high level, generating an output signal indicating a clear operation;

The frequency divider is cleared when the clear terminal receives the output signal indicating the clear operation and generates a half-width pulse output;

The counter is cleared when the clear terminal receives the output signal indicating the clear operation, and the output indicates Loss of lock indication signal.
The method of claim 8 further comprising:

The counter counts on each rising edge or each falling edge of the input clock of the phase locked loop; and no longer accumulates when the count value reaches a predetermined count overflow value, and outputs an indication signal indicating the lock.
The method of claim 6 wherein:

The periodic pulse signal generated by the frequency divider is a positive pulse or a negative pulse; and the frequency divider and the counter are synchronously cleared or asynchronously cleared.