WO2017134808A1 - Method for producing semiconductor device - Google Patents

Method for producing semiconductor device Download PDF

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Publication number
WO2017134808A1
WO2017134808A1 PCT/JP2016/053459 JP2016053459W WO2017134808A1 WO 2017134808 A1 WO2017134808 A1 WO 2017134808A1 JP 2016053459 W JP2016053459 W JP 2016053459W WO 2017134808 A1 WO2017134808 A1 WO 2017134808A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
range
semiconductor wafer
solvent
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PCT/JP2016/053459
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French (fr)
Japanese (ja)
Inventor
小笠原　淳
浩二 伊東
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新電元工業株式会社
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Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to PCT/JP2016/053459 priority Critical patent/WO2017134808A1/en
Priority to CN201780000314.3A priority patent/CN107533972B/en
Priority to PCT/JP2017/002218 priority patent/WO2017135094A1/en
Priority to JP2017523009A priority patent/JP6235190B1/en
Priority to TW106103485A priority patent/TWI612567B/en
Publication of WO2017134808A1 publication Critical patent/WO2017134808A1/en

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    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
    • C03C8/02—Frit compositions, i.e. in a powdered or comminuted form
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
    • C03C8/02—Frit compositions, i.e. in a powdered or comminuted form
    • C03C8/04—Frit compositions, i.e. in a powdered or comminuted form containing zinc
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • a method of manufacturing a semiconductor device including a glass film forming step of forming a glass film on the surface of a semiconductor wafer is known (for example, Japanese Patent Laid-Open Nos. 63-22457 and 60-94729, No. 57-143832).
  • lead-free glass fine particles not containing lead are deposited on a mesa groove of a semiconductor wafer by electrophoretic deposition (EPD), and then the lead-free glass deposited in the mesa groove.
  • the passivation film of the semiconductor device is formed by firing the fine particles to vitrify.
  • a suspension in which lead-free glass fine particles are suspended in a solvent is used in the glass film forming step by electrophoretic deposition. And the characteristic of the electrolyte added to this suspension is not necessarily constant.
  • the adhesion of lead-free glass particles to the semiconductor wafer by the electrophoretic deposition method is not stable, and the thickness of the lead-free glass particles deposited in the mesa groove is accurately determined to a predetermined thickness.
  • it cannot be controlled it does not adhere until the thickness of the deposit of lead-free glass fine particles reaches a predetermined thickness).
  • the semiconductor device cut and separated from the semiconductor wafer As a result, the insulation properties (reverse characteristics) of the passivation film vary and the reliability of the semiconductor device is lowered.
  • the lead-free glass fine particle semiconductor by the electrophoretic deposition method due to the variation in the characteristics of the electrolyte added to the suspension.
  • the adhesion to the wafer is not stable and the thickness of the lead-free glass fine particles deposited in the mesa groove cannot be accurately controlled to a predetermined thickness.
  • an object of the present invention is to provide a method of manufacturing a semiconductor device capable of accurately controlling the thickness of the lead-free glass fine particles deposited in the mesa groove to a predetermined thickness.
  • a method for manufacturing a semiconductor device includes: A semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass coating formation surface, and a suspension in which lead-free glass fine particles are suspended in a solvent, the first electrode plate and the second electrode plate are A state in which the semiconductor wafer is placed between the first electrode plate and the second electrode plate while facing each other while being immersed in the suspension, and the glass film forming surface faces the first electrode plate side A glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition, and a method for manufacturing a semiconductor device,
  • the suspension used in the glass coating forming step is controlled by adding a surfactant, water, and an electrolyte to the solvent after controlling the dielectric constant of the solvent containing the lead-free glass fine particles to the first range.
  • the suspension is characterized in that its electric conductivity is controlled in the second range.
  • the electrical conductivity of the suspension is controlled in the second range by adjusting at least one of the surfactant, the water, and the electrolyte.
  • the first range of the dielectric constant of the solvent is in the range of 5 to 11.
  • the second range of the electrical conductivity of the suspension is characterized by being in the range of 200 nS / cm to 400 nS / cm.
  • the electrolyte Prior to being added to the solvent, the electrolyte has a conductivity controlled to a third range;
  • the third range of the electric conductivity of the electrolyte is 90 ⁇ S / cm to 130 ⁇ S / cm.
  • the electrolyte is a mixed solution containing an organic solvent and nitric acid.
  • the organic solvent is isopropyl alcohol or ethyl acetate.
  • the electrical conductivity of the electrolyte is controlled to the third range by adjusting a ratio of the nitric acid in the mixed solution.
  • the solvent is a mixed solvent of isopropyl alcohol and ethyl acetate.
  • the dielectric constant of the solvent is controlled to the first range by adjusting a ratio of the ethyl acetate in the mixed solvent.
  • the lead-free glass fine particles are lead-free glass fine particles containing at least one of SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , and BaO.
  • the surfactant is a nonionic surfactant.
  • the surfactant is polyethylene glycol.
  • the semiconductor wafer preparation step includes a step of preparing a semiconductor wafer having a pn junction parallel to the main surface; Forming an exposed portion of the pn junction on the inner surface of the groove by forming a groove having a depth exceeding the pn junction from one surface of the semiconductor wafer; And a step of forming a base insulating film on the inner surface of the groove so as to cover the exposed portion of the pn junction.
  • the semiconductor wafer preparation step A step of forming an exposed portion of a pn junction on the surface of the semiconductor wafer; and a step of forming a base insulating film on the surface of the semiconductor wafer so as to cover the exposed portion of the pn junction.
  • a method of manufacturing a semiconductor device includes a semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass film forming surface, and a suspension in which lead-free glass fine particles are suspended in a solvent.
  • the first electrode plate and the second electrode plate are placed facing each other in a state where the first electrode plate and the second electrode plate are immersed in the suspension.
  • the suspension used in the glass film forming step is a method in which the dielectric constant of the solvent containing glass fine particles is controlled within the first range, and then the surfactant, water is added to the solvent whose dielectric constant is controlled within the first range. , And an electrolyte, and the electric conductivity is controlled to a second range. Then, the electrical conductivity of the suspension is controlled within the second range by adjusting at least one of the surfactant, water, and the electrolyte.
  • the dielectric constant of the solvent containing lead-free glass fine particles is controlled within the first range, and then the dielectric constant is controlled within the first range.
  • a surfactant, water, and an electrolyte are added to the lead-free glass particles in the suspension by electrophoretic deposition using a suspension in which the electrical conductivity is controlled to the second range. Deposit in mesa groove.
  • the thickness of the lead-free glass fine particles deposited in the mesa groove formed on the semiconductor wafer can be accurately controlled to a predetermined thickness.
  • the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness
  • the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
  • FIG. 1 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 1.
  • FIG. 3 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 2.
  • FIG. 4 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 3.
  • FIG. 5 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 4.
  • FIG. 6 is a diagram illustrating steps in the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 5.
  • FIG. 5 is a diagram illustrating steps in the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 5.
  • FIG. 7 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 6.
  • FIG. 8 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 7.
  • FIG. 9 is a cross-sectional view of the glass film forming apparatus 1 as seen from the lateral direction.
  • FIG. 10 is a diagram illustrating an example of the composition of the suspension 12 used in the electrophoretic deposition method of the semiconductor device manufacturing method according to the first embodiment.
  • FIG. 11 is a view showing the upper surface of a semiconductor wafer in which lead-free glass fine particles are deposited in the mesa groove by the semiconductor device manufacturing method according to the comparative example.
  • FIG. 12 is a view of a semiconductor wafer in which lead-free glass particles are deposited in mesa grooves by the method for manufacturing a semiconductor device according to the first embodiment.
  • the method of manufacturing a semiconductor device according to the first embodiment includes a “semiconductor wafer preparation step”, a “glass film formation step”, an “oxide film removal step”, and a “roughened region”.
  • the “forming process”, “electrode forming process”, and “semiconductor wafer cutting process” are performed in this order.
  • the semiconductor device manufacturing method according to the embodiment will be described below in the order of steps.
  • a p + type diffusion layer 112 is formed by diffusion of p type impurities from one surface of an n ⁇ type semiconductor wafer (for example, an n ⁇ type silicon wafer having a diameter of 4 inches) 110,
  • An n + -type diffusion layer 114 is formed by diffusion of n-type impurities from the other surface to prepare a semiconductor wafer in which a pn junction parallel to the main surface is formed (FIG. 1).
  • oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (FIG. 1).
  • a predetermined opening is formed in a predetermined portion of the oxide film 116 by a photoetching method.
  • the semiconductor wafer is subsequently etched to form a groove (mesa groove) 120 having a depth exceeding the pn junction from one surface of the semiconductor wafer (FIG. 2).
  • the exposed portion A of the pn junction is formed on the inner surface of the groove 120. That is, an exposed portion of the pn junction is formed on the surface of the semiconductor wafer.
  • a base insulating film 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (FIG. 3). That is, the base insulating film 121 is formed on the surface of the semiconductor wafer (the inner surface of the groove 120) so as to cover the exposed portion A of the pn junction.
  • DryO 2 dry oxygen
  • the thickness of the base insulating film 121 is, for example, in the range of 5 nm to 60 nm (for example, 20 nm).
  • the base insulating film 121 is formed by placing the semiconductor wafer in a diffusion furnace and then treating it at a temperature of 900 ° C. for 10 minutes while flowing an oxygen gas. If the thickness of the base insulating film 121 is less than 5 nm, the effect of reducing the BT resistance may not be obtained. On the other hand, if the thickness of the base insulating film 121 exceeds 60 nm, it may not be possible to form a glass film by electrophoretic deposition in the next glass film forming process.
  • a semiconductor wafer having a mesa groove formed on the glass film forming surface is prepared.
  • a glass film forming apparatus having the following configuration, that is, a tank 10 for storing the suspension 12 in which the lead-free glass fine particles are suspended, and in a state facing each other.
  • the first electrode plate 14 and the second electrode plate 16 installed in the tank 10 are installed between the first electrode plate 14 and the second electrode plate 16 to dispose the semiconductor wafer W at a predetermined position.
  • a glass film forming apparatus including a semiconductor wafer placement jig (not shown) and a power supply device 20 for applying a potential to the first electrode plate 14 and the second electrode plate 16 is used (FIG. 9).
  • the first electrode plate 14 connected to the plus terminal and the first terminal connected to the minus terminal are inside the tank 10 storing the suspension 12 in which the lead-free glass particles are suspended.
  • the two electrode plates 16 are placed facing each other while being immersed in the suspension 12, and the semiconductor wafer W is formed between the first electrode plate 14 and the second electrode plate 16 on the surface on which the glass film is to be formed (FIG. 9).
  • the glass coating 124 is formed on the surface on which the glass coating is to be formed by electrophoretic deposition in a state where the inner surface of the groove is arranged in a posture facing the first electrode plate 14 side.
  • a voltage applied between the first electrode plate 14 and the second electrode plate 16 a voltage of 10V to 800V (for example, 400V) is applied.
  • the suspension 12 used in this glass film forming step is controlled in the first range of the dielectric constant of the solvent (1) containing the lead-free glass fine particles, and then the electrolyte (2 ), Water (3), and surfactant (4) are added, and the electrical conductivity (EC: Electro Conductivity) is controlled within the second range (see FIG. 10).
  • the lead-free glass particles made of lead-free glass include, for example, at least one of the following glass particles, that is, SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , BaO. And lead-free glass particles prepared from a melt obtained by melting a raw material containing substantially no Pb.
  • the solvent (1) is a mixed solvent of isopropyl alcohol and ethyl acetate.
  • the dielectric constant of the solvent (1) is controlled to the first range described above by adjusting the ratio of ethyl acetate in the mixed solvent.
  • the first range of the dielectric constant of the solvent (1) is in the range of 5 to 11 (more preferably 5 to 8).
  • the electrolyte (2) is a mixed solution of an organic solvent (isopropyl alcohol (IPA)) and nitric acid (HNO 3 ).
  • the volume ratio of the organic solvent and nitric acid in this mixed solution is, for example, 1000: 1 to 5.
  • the organic solvent may be ethyl acetate.
  • the electrical conductivity of the suspension 12 is adjusted to the second described above. Control to the range.
  • the second range of the electric conductivity of the suspension 12 is in the range of 200 nS / cm to 400 nS / cm.
  • the electrical conductivity (conductivity) of the suspension in which the lead glass powder is suspended is 150. ⁇ 50 ⁇ S / cm (see the above-mentioned JP-A-63-22457).
  • the condition of the electrical conductivity of the conventional suspension is greatly different from that of the second range of the electrical conductivity of the suspension 12 described above. And it has been confirmed that the lead-free glass applied in the present embodiment cannot be deposited in the mesa groove of the semiconductor element by the electrophoretic deposition method under the condition of the electrical conductivity of the conventional suspension.
  • the electric conductivity of the electrolyte (2) is controlled within the third range.
  • the electrical conductivity of the electrolyte (2) is controlled to the third range described above by adjusting the ratio of nitric acid in the mixed solution.
  • the third range of the electric conductivity of the electrolyte (2) is in the range of 90 ⁇ S / cm to 130 ⁇ S / cm.
  • the electrolyte (2) is about 30 to 40 cc
  • the surfactant (3) is about 30 to 40 cc
  • the water (4) is about 20 cc.
  • the surfactant (4) described above is more preferably a nonionic surfactant.
  • the surfactant (4) is polyethylene glycol.
  • volume ratio of isopropyl alcohol to the surfactant in the suspension 12 is, for example, 100: 1.
  • the dielectric constant of the solvent containing the lead-free glass fine particles is controlled within the first range (5 to 11), and then the dielectric constant is changed to the first dielectric constant.
  • the electrolyte (2), water (3), and surfactant (4) are added to the solvent controlled to the range (mixed solvent of isopropyl alcohol (IPA) and ethyl acetate), and the electric conductivity is adjusted to the second range.
  • the lead-free glass particles in the suspension are deposited on the mesa grooves of the semiconductor wafer by electrophoretic deposition using a suspension controlled at (200 nS / cm to 400 nS / cm).
  • the electric conductivity of the electrolyte (2) is controlled within the third range (90 ⁇ S / cm to 130 ⁇ S / cm).
  • the thickness of the lead-free glass fine particles deposited in the mesa groove formed in the semiconductor wafer can be accurately controlled to a predetermined thickness.
  • the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness
  • the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
  • Electrode forming step Ni plating is performed on the semiconductor wafer to form the anode electrode 134 on the roughened region 132 and the cathode electrode 136 is formed on the other surface of the semiconductor wafer (FIG. 7).
  • the semiconductor device (mesa type pn diode) 100 can be manufactured.
  • FIG. 11 is a view showing the upper surface of a semiconductor wafer in which lead-free glass fine particles are deposited in the mesa groove by the semiconductor device manufacturing method according to the comparative example.
  • FIG. 12 is a view of a semiconductor wafer in which lead-free glass fine particles are deposited in mesa grooves by the method for manufacturing a semiconductor device according to the first embodiment.
  • the electrical conductivity EC of the electrolyte is about 30 ⁇ S / cm.
  • the third range of the electrical conductivity EC of the electrolyte (2) is in the range of 100 ⁇ S / cm to 130 ⁇ S / cm.
  • the voltage between the electrodes during EPD is 150V.
  • the adhesion amount of the lead-free glass particles is only 22 mg, and the adhesion of the lead-free glass particles to the semiconductor wafer is stabilized. Therefore, the thickness of the lead-free glass fine particles deposited in the mesa groove cannot be accurately controlled to a predetermined thickness.
  • the adhesion amount of lead-free glass particles is 45 mg (electrical conductivity EC
  • the third range is 95 ⁇ S / cm) and 50 mg (the third range of electrical conductivity EC is 125 ⁇ S / cm), and the adhesion of lead-free glass particles to the semiconductor wafer is stable and deposited in the mesa groove.
  • the thickness of the lead-free glass fine particle deposit can be controlled to a predetermined thickness with high accuracy.
  • a method for manufacturing a semiconductor device includes a semiconductor wafer preparation step of preparing a semiconductor wafer having a mesa groove formed on a glass film forming surface, and suspending lead-free glass fine particles in a solvent.
  • the first electrode plate and the second electrode plate are placed opposite to each other in a state where the first electrode plate and the second electrode plate are immersed in the suspension, and the semiconductor wafer is glass between the first electrode plate and the second electrode plate.
  • a glass film forming step of forming a glass film on the glass film forming surface by an electrophoretic deposition method with the film forming surface facing the first electrode plate.
  • the suspension used in the glass film forming step is a method in which the dielectric constant of the solvent containing glass fine particles is controlled within the first range, and then the surfactant, water is added to the solvent whose dielectric constant is controlled within the first range. , And an electrolyte, and the electric conductivity is controlled to a second range. Then, the electrical conductivity of the suspension is controlled within the second range by adjusting at least one of the surfactant, water, and the electrolyte.
  • the dielectric constant of the solvent containing lead-free glass fine particles is controlled within the first range, and then the dielectric constant is controlled within the first range.
  • the mixed solvent of isopropyl alcohol and ethyl acetate is added with a surfactant, water, and an electrolyte, and the suspension is subjected to electrophoretic deposition using a suspension whose electric conductivity is controlled in the second range.
  • Lead-free glass particles in the liquid are deposited on the mesa groove of the semiconductor wafer.
  • the thickness of the lead-free glass fine particles deposited in the mesa groove formed on the semiconductor wafer can be accurately controlled to a predetermined thickness.
  • the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness
  • the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
  • a semiconductor wafer plate made of silicon is used as the semiconductor wafer, but the present invention is not limited to this.
  • a semiconductor wafer made of SiC, GaN, GaO or the like can be used.

Abstract

This method for producing a semiconductor device includes: a semiconductor wafer preparation step in which a semiconductor wafer that has a mesa groove formed on a glass coating formation surface is prepared; and a glass coating formation step in which a first electrode plate and a second electrode plate are installed facing each other in a suspension, which is formed by suspending lead-free glass fine particles in a solvent, with said electrode plates immersed in the suspension, and a glass coating is formed on the glass coating formation surface by means of electrophoretic deposition with the semiconductor wafer disposed between the first electrode plate and the second electrode plate such that the glass coating formation surface faces the first electrode plate side.

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体装置の製造方法に関する発明である。 The present invention relates to a method for manufacturing a semiconductor device.
　従来、半導体ウェーハの表面にガラス被膜を形成するガラス被膜形成工程を含む半導体装置の製造方法が知られている（例えば、特開昭６３－２２４５７号公報、特開昭６０－９４７２９号公報、特開昭５７－１４３８３２号公報参照）。 Conventionally, a method of manufacturing a semiconductor device including a glass film forming step of forming a glass film on the surface of a semiconductor wafer is known (for example, Japanese Patent Laid-Open Nos. 63-22457 and 60-94729, No. 57-143832).
　この半導体装置の製造方法においては、電気泳動堆積法（ＥＰＤ：Ｅｌｅｃｔｒｏｐｈｏｒｅｔｉｃ　Ｄｅｐｏｓｉｔｉｏｎ）により、鉛を含まない鉛フリーガラス微粒子を半導体ウェーハのメサ溝に堆積させ、その後、当該メサ溝に堆積した鉛フリーガラス微粒子を焼成して、ガラス化することで、半導体装置のパッシベーション膜を形成する。 In this method of manufacturing a semiconductor device, lead-free glass fine particles not containing lead are deposited on a mesa groove of a semiconductor wafer by electrophoretic deposition (EPD), and then the lead-free glass deposited in the mesa groove. The passivation film of the semiconductor device is formed by firing the fine particles to vitrify.
　上述の従来の半導体装置の製造方法では、電気泳動堆積法によるガラス被膜形成工程において、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液を用いる。そして、この懸濁液に添加する電解質の特性は、必ずしも一定では無い。 In the conventional method for manufacturing a semiconductor device described above, a suspension in which lead-free glass fine particles are suspended in a solvent is used in the glass film forming step by electrophoretic deposition. And the characteristic of the electrolyte added to this suspension is not necessarily constant.
　この電解質の特性のばらつきにより、電気泳動堆積法による鉛フリーガラス微粒子の半導体ウェーハに対する付着性が安定せず、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができない（鉛フリーガラス微粒子の堆積物の厚さが所定の厚さになるまで付着しない）問題があった。 Due to the variation in the characteristics of the electrolyte, the adhesion of lead-free glass particles to the semiconductor wafer by the electrophoretic deposition method is not stable, and the thickness of the lead-free glass particles deposited in the mesa groove is accurately determined to a predetermined thickness. However, there is a problem that it cannot be controlled (it does not adhere until the thickness of the deposit of lead-free glass fine particles reaches a predetermined thickness).
　そして、例えば、この鉛フリーガラス微粒子の堆積物の厚さのばらつきにより、この堆積物を焼成してガラス化したパッシベーション膜の膜厚もばらつくこととなるため、半導体ウェーハから切断分離された半導体装置のパッシベーション膜の絶縁性（逆方向特性）がばらついて当該半導体装置の信頼性が低下してしまうこととなる。 And, for example, because the thickness of the passivation film obtained by baking this deposit and vitrifying it due to the variation in the thickness of the deposit of the lead-free glass fine particles varies, the semiconductor device cut and separated from the semiconductor wafer As a result, the insulation properties (reverse characteristics) of the passivation film vary and the reliability of the semiconductor device is lowered.
　上述のように、従来の半導体装置の製造方法では、電気泳動堆積法によるガラス被膜形成工程において、懸濁液に添加される電解質の特性のばらつきにより、電気泳動堆積法による鉛フリーガラス微粒子の半導体ウェーハに対する付着性が安定せず、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができない問題がある。 As described above, in the conventional semiconductor device manufacturing method, in the glass film forming step by the electrophoretic deposition method, the lead-free glass fine particle semiconductor by the electrophoretic deposition method due to the variation in the characteristics of the electrolyte added to the suspension. There is a problem that the adhesion to the wafer is not stable and the thickness of the lead-free glass fine particles deposited in the mesa groove cannot be accurately controlled to a predetermined thickness.
　そこで、本発明では、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することが可能な半導体装置の製造方法を提供することを目的とする。 Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of accurately controlling the thickness of the lead-free glass fine particles deposited in the mesa groove to a predetermined thickness.
　本発明の一態様に係る実施形態に従った半導体装置の製造方法は、　　　
　ガラス被膜形成面にメサ溝が形成された半導体ウェーハを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第１電極板と第２電極板とを前記懸濁液に浸漬した状態で対向して設置するとともに、前記第１電極板と前記第２電極板との間に前記半導体ウェーハを前記ガラス被膜形成面が前記第１電極板側に向いた状態で、電気泳動堆積法により前記ガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む半導体装置の製造方法であって、
　前記ガラス被膜形成工程で用いられる前記懸濁液は、前記鉛フリーガラス微粒子を含む前記溶媒の誘電率を第１の範囲に制御した後、当該溶媒に、界面活性剤、水、及び電解質を加えて、その電気伝導度を第２の範囲に制御した懸濁液である
　ことを特徴とする。 A method for manufacturing a semiconductor device according to an embodiment of one aspect of the present invention includes:
A semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass coating formation surface, and a suspension in which lead-free glass fine particles are suspended in a solvent, the first electrode plate and the second electrode plate are A state in which the semiconductor wafer is placed between the first electrode plate and the second electrode plate while facing each other while being immersed in the suspension, and the glass film forming surface faces the first electrode plate side A glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition, and a method for manufacturing a semiconductor device,
The suspension used in the glass coating forming step is controlled by adding a surfactant, water, and an electrolyte to the solvent after controlling the dielectric constant of the solvent containing the lead-free glass fine particles to the first range. The suspension is characterized in that its electric conductivity is controlled in the second range.
　前記半導体装置の製造方法において、
　前記界面活性剤、前記水及び前記電解質の少なくとも何れか１つを調整することで、前記懸濁液の前記電気伝導度を前記第２の範囲に制御することを特徴とする。 In the method for manufacturing the semiconductor device,
The electrical conductivity of the suspension is controlled in the second range by adjusting at least one of the surfactant, the water, and the electrolyte.
　前記半導体装置の製造方法において、　　　
　前記溶媒の誘電率の前記第１の範囲は、５～１１の範囲であることを特徴とする。 In the method for manufacturing the semiconductor device,
The first range of the dielectric constant of the solvent is in the range of 5 to 11.
　前記半導体装置の製造方法において、
　前記懸濁液の電気伝導度の前記第２の範囲は、２００ｎＳ/ｃｍ～４００ｎＳ/ｃｍの範囲であることを特徴とする。 In the method for manufacturing the semiconductor device,
The second range of the electrical conductivity of the suspension is characterized by being in the range of 200 nS / cm to 400 nS / cm.
　前記半導体装置の製造方法において、
　前記溶媒に加えられる前に、前記電解質は、電気伝導度が第３の範囲に制御されており、
　前記電解質の電気伝導度の前記第３の範囲は、９０μＳ/ｃｍ～１３０μＳ/ｃｍの範囲であることを特徴とする。 In the method for manufacturing the semiconductor device,
Prior to being added to the solvent, the electrolyte has a conductivity controlled to a third range;
The third range of the electric conductivity of the electrolyte is 90 μS / cm to 130 μS / cm.
　前記半導体装置の製造方法において、
　前記電解質は、有機溶剤と硝酸とを含む混合液であることを特徴とする請求項５に記載の半導体装置の製造方法。 In the method for manufacturing the semiconductor device,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the electrolyte is a mixed solution containing an organic solvent and nitric acid.
　前記半導体装置の製造方法において、
　前記有機溶剤は、イソプロピルアルコール又は酢酸エチルである。 In the method for manufacturing the semiconductor device,
The organic solvent is isopropyl alcohol or ethyl acetate.
　前記半導体装置の製造方法において、
　前記電解質の前記電気伝導度を、前記混合液における前記硝酸の割合を調整することにより、前記第３の範囲に制御することを特徴とする。 In the method for manufacturing the semiconductor device,
The electrical conductivity of the electrolyte is controlled to the third range by adjusting a ratio of the nitric acid in the mixed solution.
　前記半導体装置の製造方法において、
　前記溶媒は、イソプロピルアルコールと酢酸エチルとの混合溶媒であることを特徴とする。 In the method for manufacturing the semiconductor device,
The solvent is a mixed solvent of isopropyl alcohol and ethyl acetate.
　前記半導体装置の製造方法において、
　前記溶媒の誘電率を、前記混合溶媒における前記酢酸エチルの割合を調整することにより、前記第１の範囲に制御する
　ことを特徴とする。 In the method for manufacturing the semiconductor device,
The dielectric constant of the solvent is controlled to the first range by adjusting a ratio of the ethyl acetate in the mixed solvent.
　前記半導体装置の製造方法において、
　前記鉛フリーガラス微粒子は、ＳｉＯ２、Ａｌ２Ｏ３、ＣａＯ、ＭｇＯ、ＺｎＯ、Ｂ２Ｏ３、ＢａＯの少なくとも何れか１つを含む鉛フリーガラス微粒子である
　ことを特徴とする。 In the method for manufacturing the semiconductor device,
The lead-free glass fine particles are lead-free glass fine particles containing at least one of SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , and BaO.
　前記半導体装置の製造方法において、
　前記界面活性剤は、非イオン系界面活性剤であることを特徴とする。 In the method for manufacturing the semiconductor device,
The surfactant is a nonionic surfactant.
　前記半導体装置の製造方法において、
　前記界面活性剤は、ポリエチレングリコールであることを特徴とする。 In the method for manufacturing the semiconductor device,
The surfactant is polyethylene glycol.
　前記半導体装置の製造方法において、
　前記半導体ウェーハ準備工程は、主面に平行なｐｎ接合を備える半導体ウェーハを準備する工程と、
　前記半導体ウェーハの一方の表面から前記ｐｎ接合を超える深さの溝を形成することにより、前記溝の内面に前記ｐｎ接合の露出部を形成する工程と、
　前記ｐｎ接合の露出部を覆うように前記溝の内面に下地絶縁膜を形成する工程と、を含む
　ことを特徴とする。 In the method for manufacturing the semiconductor device,
The semiconductor wafer preparation step includes a step of preparing a semiconductor wafer having a pn junction parallel to the main surface;
Forming an exposed portion of the pn junction on the inner surface of the groove by forming a groove having a depth exceeding the pn junction from one surface of the semiconductor wafer;
And a step of forming a base insulating film on the inner surface of the groove so as to cover the exposed portion of the pn junction.
　前記半導体装置の製造方法において、
　前記半導体ウェーハ準備工程は、
　半導体ウェーハの表面にｐｎ接合の露出部を形成する工程と、前記ｐｎ接合の露出部を覆うように前記半導体ウェーハの表面に下地絶縁膜を形成する工程と、を含む
　ことを特徴とする。 In the method for manufacturing the semiconductor device,
The semiconductor wafer preparation step
A step of forming an exposed portion of a pn junction on the surface of the semiconductor wafer; and a step of forming a base insulating film on the surface of the semiconductor wafer so as to cover the exposed portion of the pn junction.
　本発明の一態様に係る半導体装置の製造方法は、ガラス被膜形成面にメサ溝が形成された半導体ウェーハを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第１電極板と第２電極板とを懸濁液に浸漬した状態で対向して設置するとともに、第１電極板と第２電極板との間に半導体ウェーハをガラス被膜形成面が第１電極板側に向いた状態で、電気泳動堆積法によりガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む。そして、ガラス被膜形成工程で用いられる懸濁液は、ガラス微粒子を含む溶媒の誘電率を第１の範囲に制御した後、誘電率を第１の範囲に制御した溶媒に、界面活性剤、水、及び電解質を加えて、その電気伝導度を第２の範囲に制御した懸濁液である。そして、界面活性剤、水及び電解質の少なくとも何れかを調整することで、懸濁液の電気伝導度を第２の範囲に制御する。 A method of manufacturing a semiconductor device according to an aspect of the present invention includes a semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass film forming surface, and a suspension in which lead-free glass fine particles are suspended in a solvent. In addition, the first electrode plate and the second electrode plate are placed facing each other in a state where the first electrode plate and the second electrode plate are immersed in the suspension. And a glass film forming step of forming a glass film on the glass film forming surface by an electrophoretic deposition method in a state facing the one electrode plate side. The suspension used in the glass film forming step is a method in which the dielectric constant of the solvent containing glass fine particles is controlled within the first range, and then the surfactant, water is added to the solvent whose dielectric constant is controlled within the first range. , And an electrolyte, and the electric conductivity is controlled to a second range. Then, the electrical conductivity of the suspension is controlled within the second range by adjusting at least one of the surfactant, water, and the electrolyte.
　すなわち、本発明の一態様に係る半導体装置の製造方法においては、先ず鉛フリーガラス微粒子を含む溶媒の誘電率を第１の範囲に制御し、次に誘電率を第１の範囲に制御した溶媒に、界面活性剤、水、及び電解質を加えて、電気伝導度を第２の範囲に制御した懸濁液を用いる電気泳動堆積法により、当該懸濁液中の鉛フリーガラス微粒子を半導体ウェーハのメサ溝に堆積させる。 That is, in the method for manufacturing a semiconductor device according to one embodiment of the present invention, first, the dielectric constant of the solvent containing lead-free glass fine particles is controlled within the first range, and then the dielectric constant is controlled within the first range. In addition, a surfactant, water, and an electrolyte are added to the lead-free glass particles in the suspension by electrophoretic deposition using a suspension in which the electrical conductivity is controlled to the second range. Deposit in mesa groove.
　これにより、半導体ウェーハに形成されたメサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができる。 Thereby, the thickness of the lead-free glass fine particles deposited in the mesa groove formed on the semiconductor wafer can be accurately controlled to a predetermined thickness.
　特に、鉛フリーガラス微粒子の堆積物の厚さが所定の厚さに制御されるため、この堆積物を焼成してガラス化したパッシベーション膜の膜厚も所定の膜厚に制御されることとなり、半導体ウェーハから切断分離された半導体装置のパッシベーション膜の絶縁性（逆方向特性）のばらつきを低減して当該半導体装置の信頼性を向上ことが可能となる。 In particular, since the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness, the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
図１は、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 1 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to the first embodiment. 図２は、図１に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 2 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 1. 図３は、図２に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 3 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 2. 図４は、図３に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 4 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 3. 図５は、図４に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 5 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 4. 図６は、図５に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 6 is a diagram illustrating steps in the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 5. 図７は、図６に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 7 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 6. 図８は、図７に続く、第１の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 8 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 7. 図９は、ガラス被膜形成装置１を横方向から見た断面図である。FIG. 9 is a cross-sectional view of the glass film forming apparatus 1 as seen from the lateral direction. 図１０は、第１の実施形態に係る半導体装置の製造方法の電気泳動堆積法で用いられる懸濁液１２の組成の一例を示す図である。FIG. 10 is a diagram illustrating an example of the composition of the suspension 12 used in the electrophoretic deposition method of the semiconductor device manufacturing method according to the first embodiment. 図１１は、比較例に係る半導体装置の製造方法により、鉛フリーガラス微粒子をメサ溝に堆積させた半導体ウェーハの上面を示す図である。FIG. 11 is a view showing the upper surface of a semiconductor wafer in which lead-free glass fine particles are deposited in the mesa groove by the semiconductor device manufacturing method according to the comparative example. 図１２は、第１の実施形態に係る半導体装置の製造方法により、鉛フリーガラス微粒子をメサ溝に堆積させた半導体ウェーハの図である。FIG. 12 is a view of a semiconductor wafer in which lead-free glass particles are deposited in mesa grooves by the method for manufacturing a semiconductor device according to the first embodiment.
　以下、本発明に係る実施形態について図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１の実施形態First embodiment
　第１の実施形態に係る半導体装置の製造方法は、図１ないし図８に示すように、「半導体ウェーハ準備工程」、「ガラス被膜形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体ウェーハ切断工程」をこの順序で実施する。以下、実施形態に係る半導体装置の製造方法を工程順に説明する。 As shown in FIGS. 1 to 8, the method of manufacturing a semiconductor device according to the first embodiment includes a “semiconductor wafer preparation step”, a “glass film formation step”, an “oxide film removal step”, and a “roughened region”. The “forming process”, “electrode forming process”, and “semiconductor wafer cutting process” are performed in this order. The semiconductor device manufacturing method according to the embodiment will be described below in the order of steps.
（ａ）半導体ウェーハ準備工程
　まず、ｎ－型半導体ウェーハ（例えば、直径４インチのｎ－型シリコンウェーハ）１１０の一方の表面からのｐ型不純物の拡散によりｐ＋型拡散層１１２を形成するとともに、他方の表面からのｎ型不純物の拡散によりｎ＋型拡散層１１４を形成して、主面に平行なｐｎ接合が形成された半導体ウェーハを準備する（図１）。 (A) Semiconductor wafer preparation step First, a p + type diffusion layer 112 is formed by diffusion of p type impurities from one surface of an n− type semiconductor wafer (for example, an n− type silicon wafer having a diameter of 4 inches) 110, An n + -type diffusion layer 114 is formed by diffusion of n-type impurities from the other surface to prepare a semiconductor wafer in which a pn junction parallel to the main surface is formed (FIG. 1).
　その後、熱酸化によりｐ＋型拡散層１１２及びｎ＋型拡散層１１４の表面に酸化膜１１６、１１８を形成する（図１）。 Thereafter, oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (FIG. 1).
　次に、フォトエッチング法によって、酸化膜１１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体ウェーハのエッチングを行い、半導体ウェーハの一方の表面からｐｎ接合を超える深さの溝（メサ溝）１２０を形成する（図２）。このとき、溝１２０の内面にｐｎ接合の露出部Ａが形成される。すなわち、半導体ウェーハの表面にｐｎ接合の露出部を形成する。 Next, a predetermined opening is formed in a predetermined portion of the oxide film 116 by a photoetching method. After etching the oxide film, the semiconductor wafer is subsequently etched to form a groove (mesa groove) 120 having a depth exceeding the pn junction from one surface of the semiconductor wafer (FIG. 2). At this time, the exposed portion A of the pn junction is formed on the inner surface of the groove 120. That is, an exposed portion of the pn junction is formed on the surface of the semiconductor wafer.
　次に、ドライ酸素（ＤｒｙＯ２）を用いた熱酸化法によって、溝１２０の内面にシリコン酸化膜からなる下地絶縁膜１２１を形成する（図３）。すなわち、ｐｎ接合の露出部Ａを覆うように半導体ウェーハの表面（溝１２０の内面）に下地絶縁膜１２１を形成する。 Next, a base insulating film 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (FIG. 3). That is, the base insulating film 121 is formed on the surface of the semiconductor wafer (the inner surface of the groove 120) so as to cover the exposed portion A of the pn junction.
　なお、下地絶縁膜１２１の厚さは、例えば、５ｎｍ～６０ｎｍの範囲内（例えば２０ｎｍ）とする。下地絶縁膜１２１の形成は、半導体ウェーハを拡散炉に入れた後、酸素ガスを流しながら９００℃の温度で１０分処理することにより行う。下地絶縁膜１２１の厚さが５ｎｍ未満であるとＢＴ耐量低減の効果が得られなくなる場合がある。一方、下地絶縁膜１２１の厚さが６０ｎｍを超えると次のガラス被膜形成工程で電気泳動堆積法によりガラス被膜を形成することができなくなる場合がある。 Note that the thickness of the base insulating film 121 is, for example, in the range of 5 nm to 60 nm (for example, 20 nm). The base insulating film 121 is formed by placing the semiconductor wafer in a diffusion furnace and then treating it at a temperature of 900 ° C. for 10 minutes while flowing an oxygen gas. If the thickness of the base insulating film 121 is less than 5 nm, the effect of reducing the BT resistance may not be obtained. On the other hand, if the thickness of the base insulating film 121 exceeds 60 nm, it may not be possible to form a glass film by electrophoretic deposition in the next glass film forming process.
　以上のようにして、ガラス被膜形成面にメサ溝が形成された半導体ウェーハが準備される。 As described above, a semiconductor wafer having a mesa groove formed on the glass film forming surface is prepared.
　（ｂ）ガラス被膜形成工程
　次に、電気泳動堆積法により溝１２０の内面及びその近傍の半導体ウェーハ表面にガラス被膜１２４を形成するとともに、当該ガラス被膜１２４を焼成することにより、当該ガラス被膜１２４を緻密化する（図４）。 (B) Glass film formation step Next, the glass film 124 is formed on the inner surface of the groove 120 and the surface of the semiconductor wafer in the vicinity thereof by electrophoretic deposition, and the glass film 124 is baked to form the glass film 124. Densification (FIG. 4).
　このガラス被膜形成工程を実施するにあたっては、以下の構成を備えるガラス被膜形成装置、すなわち、鉛フリーガラス微粒子を懸濁させた懸濁液１２を貯留するための槽１０と、互いに対向した状態で槽１０の中に設置された第１電極板１４及び第２電極板１６と、第１電極板１４と第２電極板１６との間に設置され、所定位置に半導体ウェーハＷを配設するための半導体ウェーハ配設治具（図示せず。）と、第１電極板１４および第２電極板１６に電位を与える電源装置２０と、を備えるガラス被膜形成装置を用いる（図９）。 In carrying out this glass film forming step, a glass film forming apparatus having the following configuration, that is, a tank 10 for storing the suspension 12 in which the lead-free glass fine particles are suspended, and in a state facing each other. The first electrode plate 14 and the second electrode plate 16 installed in the tank 10 are installed between the first electrode plate 14 and the second electrode plate 16 to dispose the semiconductor wafer W at a predetermined position. A glass film forming apparatus including a semiconductor wafer placement jig (not shown) and a power supply device 20 for applying a potential to the first electrode plate 14 and the second electrode plate 16 is used (FIG. 9).
　そして、図９に示すように、鉛フリーガラス微粒子を懸濁させた懸濁液１２を貯留した槽１０の内部に、プラス端子に接続された第１電極板１４とマイナス端子に接続された第２電極板１６とを懸濁液１２に浸漬した状態で対向して設置するとともに、これら第１電極板１４と第２電極板１６との間に半導体ウェーハＷをガラス被膜形成予定面（図９では溝の内面）が第１電極板１４側に向いた姿勢で配置した状態で、電気泳動堆積法によりガラス被膜形成予定面にガラス被膜１２４を形成する。なお、第１電極板１４と第２電極板１６との間に印加する電圧としては、１０Ｖ～８００Ｖ（例えば４００Ｖ）の電圧を与える。 Then, as shown in FIG. 9, the first electrode plate 14 connected to the plus terminal and the first terminal connected to the minus terminal are inside the tank 10 storing the suspension 12 in which the lead-free glass particles are suspended. The two electrode plates 16 are placed facing each other while being immersed in the suspension 12, and the semiconductor wafer W is formed between the first electrode plate 14 and the second electrode plate 16 on the surface on which the glass film is to be formed (FIG. 9). Then, the glass coating 124 is formed on the surface on which the glass coating is to be formed by electrophoretic deposition in a state where the inner surface of the groove is arranged in a posture facing the first electrode plate 14 side. As a voltage applied between the first electrode plate 14 and the second electrode plate 16, a voltage of 10V to 800V (for example, 400V) is applied.
　ここで、このガラス被膜形成工程で用いられる懸濁液１２は、鉛フリーガラス微粒子を含む溶媒（１）の誘電率を第１の範囲に制御した後、当該溶媒（１）に、電解質（２）、水（３）、及び界面活性剤（４）を加えて、その電気伝導度（ＥＣ：Ｅｌｅｃｔｒｏ　Ｃｏｎｄｕｃｔｉｖｉｔｙ）を第２の範囲に制御した懸濁液である（図１０参照）。 Here, the suspension 12 used in this glass film forming step is controlled in the first range of the dielectric constant of the solvent (1) containing the lead-free glass fine particles, and then the electrolyte (2 ), Water (3), and surfactant (4) are added, and the electrical conductivity (EC: Electro Conductivity) is controlled within the second range (see FIG. 10).
　なお、鉛フリーガラスからなる鉛フリーガラス微粒子として、例えば、次のようなガラス微粒子、すなわち、ＳｉＯ２、Ａｌ２Ｏ３、ＣａＯ、ＭｇＯ、ＺｎＯ、Ｂ２Ｏ３、ＢａＯの少なくとも何れか１つを含有し、かつ、Ｐｂを実質的に含有しない原料を溶融させて得られる融液から作製された鉛フリーガラス微粒子を用いる。 The lead-free glass particles made of lead-free glass include, for example, at least one of the following glass particles, that is, SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , BaO. And lead-free glass particles prepared from a melt obtained by melting a raw material containing substantially no Pb.
　そして、溶媒（１）は、イソプロピルアルコールと酢酸エチルとの混合溶媒である。この溶媒（１）の誘電率を、混合溶媒における酢酸エチルの割合を調整することにより、既述の第１の範囲に制御する。例えば、溶媒（１）の誘電率の第１の範囲は、５～１１（より好ましくは５～８）の範囲である。 The solvent (1) is a mixed solvent of isopropyl alcohol and ethyl acetate. The dielectric constant of the solvent (1) is controlled to the first range described above by adjusting the ratio of ethyl acetate in the mixed solvent. For example, the first range of the dielectric constant of the solvent (1) is in the range of 5 to 11 (more preferably 5 to 8).
　また、電解質（２）は、有機溶剤（イソプロピルアルコール（ＩＰＡ））と硝酸（ＨＮＯ３）との混合液である。この混合液の有機溶剤と硝酸との体積比は、例えば、１０００：１～５である。なお、有機溶剤は、酢酸エチルであってもよい。 The electrolyte (2) is a mixed solution of an organic solvent (isopropyl alcohol (IPA)) and nitric acid (HNO 3 ). The volume ratio of the organic solvent and nitric acid in this mixed solution is, for example, 1000: 1 to 5. The organic solvent may be ethyl acetate.
　ここで、本実施形態では、電解質（２）、水（３）及び界面活性剤（４）の少なくとも何れか１つを調整することで、懸濁液１２の電気伝導度を既述の第２の範囲に制御する。この懸濁液１２の電気伝導度の第２の範囲は、２００ｎＳ/ｃｍ～４００ｎＳ/ｃｍの範囲である。 Here, in this embodiment, by adjusting at least one of the electrolyte (2), water (3), and surfactant (4), the electrical conductivity of the suspension 12 is adjusted to the second described above. Control to the range. The second range of the electric conductivity of the suspension 12 is in the range of 200 nS / cm to 400 nS / cm.
　なお、従来の鉛を含有させた鉛ガラス粉末を電気泳動堆積法により半導体素子のメサ溝に堆積させる場合、鉛ガラス粉末を懸濁させた懸濁液の電気伝導度（導電率）は、１５０±５０μＳ/ｃｍである（既述の特開昭６３－２２４５７号公報参照）。この従来の懸濁液の電気伝導度の条件は、上述の懸濁液１２の電気伝導度の第２の範囲と比較して大きく異なる。そして、この従来の懸濁液の電気伝導度の条件では、本実施形態で適用する鉛フリーガラスを電気泳動堆積法により半導体素子のメサ溝に堆積させることができないことが確認されている。 When the conventional lead glass powder containing lead is deposited on the mesa groove of the semiconductor element by electrophoretic deposition, the electrical conductivity (conductivity) of the suspension in which the lead glass powder is suspended is 150. ± 50 μS / cm (see the above-mentioned JP-A-63-22457). The condition of the electrical conductivity of the conventional suspension is greatly different from that of the second range of the electrical conductivity of the suspension 12 described above. And it has been confirmed that the lead-free glass applied in the present embodiment cannot be deposited in the mesa groove of the semiconductor element by the electrophoretic deposition method under the condition of the electrical conductivity of the conventional suspension.
　さらに、本実施形態では、既述の溶媒（１）に加えられる前に、電解質（２）は、電気伝導度が第３の範囲に制御される。例えば、電解質（２）の電気伝導度を、混合液における硝酸の割合を調整することにより、既述の第３の範囲に制御する。この電解質（２）の電気伝導度の第３の範囲は、９０μＳ/ｃｍ～１３０μＳ/ｃｍの範囲である。 Furthermore, in this embodiment, before the electrolyte (2) is added to the above-described solvent (1), the electric conductivity of the electrolyte (2) is controlled within the third range. For example, the electrical conductivity of the electrolyte (2) is controlled to the third range described above by adjusting the ratio of nitric acid in the mixed solution. The third range of the electric conductivity of the electrolyte (2) is in the range of 90 μS / cm to 130 μS / cm.
　なお、溶媒（１）の体積を、例えば、７Ｌ程度とした場合、電解質（２）は３０～４０ｃｃ程度であり、界面活性剤（３）は３０～４０ｃｃ程度であり、水（４）は２０～５０ｃｃ程度である。 When the volume of the solvent (1) is about 7 L, for example, the electrolyte (2) is about 30 to 40 cc, the surfactant (3) is about 30 to 40 cc, and the water (4) is about 20 cc. About 50cc.
　なお、既述の界面活性剤（４）は、より好ましくは、非イオン系界面活性剤である。特に、界面活性剤（４）は、ポリエチレングリコールである。 The surfactant (4) described above is more preferably a nonionic surfactant. In particular, the surfactant (4) is polyethylene glycol.
　なお、懸濁液１２における、イソプロピルアルコールと界面活性剤との体積比は、例えば、１００：１である。 Note that the volume ratio of isopropyl alcohol to the surfactant in the suspension 12 is, for example, 100: 1.
　このように、本実施形態に係る半導体装置の製造方法においては、先ず鉛フリーガラス微粒子を含む溶媒の誘電率を第１の範囲（５～１１）に制御し、次に誘電率を第１の範囲に制御した溶媒（イソプロピルアルコール（ＩＰＡ）と酢酸エチルとの混合溶媒）に、電解質（２）、水（３）、及び界面活性剤（４）を加えて、電気伝導度を第２の範囲（２００ｎＳ/ｃｍ～４００ｎＳ/ｃｍ）に制御した懸濁液を用いる電気泳動堆積法により、当該懸濁液中の鉛フリーガラス微粒子を半導体ウェーハのメサ溝に堆積させる。特に、本実施形態では、既述の溶媒（１）に加えられる前に、電解質（２）は、電気伝導度が第３の範囲（９０μＳ/ｃｍ～１３０μＳ/ｃｍ）に制御される。 As described above, in the method of manufacturing a semiconductor device according to the present embodiment, first, the dielectric constant of the solvent containing the lead-free glass fine particles is controlled within the first range (5 to 11), and then the dielectric constant is changed to the first dielectric constant. The electrolyte (2), water (3), and surfactant (4) are added to the solvent controlled to the range (mixed solvent of isopropyl alcohol (IPA) and ethyl acetate), and the electric conductivity is adjusted to the second range. The lead-free glass particles in the suspension are deposited on the mesa grooves of the semiconductor wafer by electrophoretic deposition using a suspension controlled at (200 nS / cm to 400 nS / cm). In particular, in this embodiment, before the electrolyte (2) is added to the solvent (1) described above, the electric conductivity of the electrolyte (2) is controlled within the third range (90 μS / cm to 130 μS / cm).
　これにより、後述のように、半導体ウェーハに形成されたメサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができる。 Thereby, as will be described later, the thickness of the lead-free glass fine particles deposited in the mesa groove formed in the semiconductor wafer can be accurately controlled to a predetermined thickness.
　特に、鉛フリーガラス微粒子の堆積物の厚さが所定の厚さに制御されるため、この堆積物を焼成してガラス化したパッシベーション膜の膜厚も所定の膜厚に制御されることとなり、半導体ウェーハから切断分離された半導体装置のパッシベーション膜の絶縁性（逆方向特性）のばらつきを低減して当該半導体装置の信頼性を向上ことが可能となる。 In particular, since the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness, the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
　（ｃ）酸化膜除去工程
　次に、ガラス被膜１２４の表面を覆うようにフォトレジスト１２６を形成した後、当該フォトレジスト１２６をマスクとして酸化膜１１６のエッチングを行い、Ｎｉめっき電極膜を形成する部位１３０における酸化膜１１６を除去する（図５）。 (C) Oxide Film Removal Step Next, a photoresist 126 is formed so as to cover the surface of the glass coating 124, and then the oxide film 116 is etched using the photoresist 126 as a mask to form a Ni plating electrode film. The oxide film 116 in 130 is removed (FIG. 5).
　（ｄ）粗面化領域形成工程
　次に、Ｎｉめっき電極膜を形成する部位１３０における半導体ウェーハ表面の粗面化処理を行い、Ｎｉめっき電極と半導体ウェーハとの密着性を高くするための粗面化領域１３２を形成する（図６）。 (D) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni plated electrode and the semiconductor wafer by performing a roughening process on the surface of the semiconductor wafer in the portion 130 where the Ni plated electrode film is to be formed. The formation region 132 is formed (FIG. 6).
　（ｅ）電極形成工程
　次に、半導体ウェーハにＮｉめっきを行い、粗面化領域１３２上にアノード電極１３４を形成するとともに、半導体ウェーハの他方の表面にカソード電極１３６を形成する（図７）。 (E) Electrode forming step Next, Ni plating is performed on the semiconductor wafer to form the anode electrode 134 on the roughened region 132 and the cathode electrode 136 is formed on the other surface of the semiconductor wafer (FIG. 7).
　（ｆ）半導体ウェーハ切断工程
　次に、ダイシング等により、ガラス被膜１２４の中央部において半導体ウェーハを切断して半導体ウェーハをチップ化して、半導体装置（メサ型のｐｎダイオード）１００を製造する（図８）。 (F) Semiconductor Wafer Cutting Process Next, the semiconductor wafer is cut into chips by dicing or the like at the center of the glass coating 124 to produce a semiconductor device (mesa pn diode) 100 (FIG. 8). ).
　以上のようにして、半導体装置（メサ型のｐｎダイオード）１００を製造することができる。 As described above, the semiconductor device (mesa type pn diode) 100 can be manufactured.
　ここで、上述の第１の実施形態に係る半導体装置の製造方法の効果を説明する。図１１は、比較例に係る半導体装置の製造方法により、鉛フリーガラス微粒子をメサ溝に堆積させた半導体ウェーハの上面を示す図である。また、図１２は、第１の実施形態に係る半導体装置の製造方法により、鉛フリーガラス微粒子をメサ溝に堆積させた半導体ウェーハの図である。なお、図１１の比較例では、電解質の電気伝導度ＥＣは、約３０μＳ/ｃｍである。また、図１２の実施形態では、電解質（２）の電気伝導度ＥＣの第３の範囲が１００μＳ/ｃｍ～１３０μＳ/ｃｍの範囲である。また、図１１の比較例及び図１２に示す実施形態において、ＥＰＤ時の電極間の電圧は、１５０Ｖである。 Here, the effect of the semiconductor device manufacturing method according to the first embodiment will be described. FIG. 11 is a view showing the upper surface of a semiconductor wafer in which lead-free glass fine particles are deposited in the mesa groove by the semiconductor device manufacturing method according to the comparative example. FIG. 12 is a view of a semiconductor wafer in which lead-free glass fine particles are deposited in mesa grooves by the method for manufacturing a semiconductor device according to the first embodiment. In the comparative example of FIG. 11, the electrical conductivity EC of the electrolyte is about 30 μS / cm. In the embodiment of FIG. 12, the third range of the electrical conductivity EC of the electrolyte (2) is in the range of 100 μS / cm to 130 μS / cm. In the comparative example of FIG. 11 and the embodiment shown in FIG. 12, the voltage between the electrodes during EPD is 150V.
　図１１に示すように、比較例では、電気泳動堆積法による堆積時間が２分では、鉛フリーガラス微粒子の付着量が２２ｍｇしか付着せず、鉛フリーガラス微粒子の半導体ウェーハに対する付着性が安定せず、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができない。 As shown in FIG. 11, in the comparative example, when the deposition time by the electrophoretic deposition method is 2 minutes, the adhesion amount of the lead-free glass particles is only 22 mg, and the adhesion of the lead-free glass particles to the semiconductor wafer is stabilized. Therefore, the thickness of the lead-free glass fine particles deposited in the mesa groove cannot be accurately controlled to a predetermined thickness.
　一方、図１２に示すように、第１の実施形態に係る半導体装置の製造方法においては、電気泳動堆積法による堆積時間を２分では、鉛フリーガラス微粒子の付着量が４５ｍｇ（電気伝導度ＥＣの第３の範囲が９５μＳ/ｃｍ）、５０ｍｇ（電気伝導度ＥＣの第３の範囲が１２５μＳ/ｃｍ）付着し、鉛フリーガラス微粒子の半導体ウェーハに対する付着性が安定して、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができる。 On the other hand, as shown in FIG. 12, in the manufacturing method of the semiconductor device according to the first embodiment, when the deposition time by the electrophoretic deposition method is 2 minutes, the adhesion amount of lead-free glass particles is 45 mg (electrical conductivity EC The third range is 95 μS / cm) and 50 mg (the third range of electrical conductivity EC is 125 μS / cm), and the adhesion of lead-free glass particles to the semiconductor wafer is stable and deposited in the mesa groove. The thickness of the lead-free glass fine particle deposit can be controlled to a predetermined thickness with high accuracy.
　以上のように、本発明の一態様に係る半導体装置の製造方法は、ガラス被膜形成面にメサ溝が形成された半導体ウェーハを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第１電極板と第２電極板とを懸濁液に浸漬した状態で対向して設置するとともに、第１電極板と第２電極板との間に半導体ウェーハをガラス被膜形成面が第１電極板側に向いた状態で、電気泳動堆積法によりガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む。そして、ガラス被膜形成工程で用いられる懸濁液は、ガラス微粒子を含む溶媒の誘電率を第１の範囲に制御した後、誘電率を第１の範囲に制御した溶媒に、界面活性剤、水、及び電解質を加えて、その電気伝導度を第２の範囲に制御した懸濁液である。そして、界面活性剤、水及び電解質の少なくとも何れかを調整することで、懸濁液の電気伝導度を第２の範囲に制御する。 As described above, a method for manufacturing a semiconductor device according to an aspect of the present invention includes a semiconductor wafer preparation step of preparing a semiconductor wafer having a mesa groove formed on a glass film forming surface, and suspending lead-free glass fine particles in a solvent. The first electrode plate and the second electrode plate are placed opposite to each other in a state where the first electrode plate and the second electrode plate are immersed in the suspension, and the semiconductor wafer is glass between the first electrode plate and the second electrode plate. And a glass film forming step of forming a glass film on the glass film forming surface by an electrophoretic deposition method with the film forming surface facing the first electrode plate. The suspension used in the glass film forming step is a method in which the dielectric constant of the solvent containing glass fine particles is controlled within the first range, and then the surfactant, water is added to the solvent whose dielectric constant is controlled within the first range. , And an electrolyte, and the electric conductivity is controlled to a second range. Then, the electrical conductivity of the suspension is controlled within the second range by adjusting at least one of the surfactant, water, and the electrolyte.
　すなわち、本発明の一態様に係る半導体装置の製造方法においては、先ず鉛フリーガラス微粒子を含む溶媒の誘電率を第１の範囲に制御し、次に誘電率を第１の範囲に制御した溶媒（イソプロピルアルコールと酢酸エチルとの混合溶媒）に、界面活性剤、水、及び電解質を加えて、電気伝導度を第２の範囲に制御した懸濁液を用いる電気泳動堆積法により、当該懸濁液中の鉛フリーガラス微粒子を半導体ウェーハのメサ溝に堆積させる。 That is, in the method for manufacturing a semiconductor device according to one embodiment of the present invention, first, the dielectric constant of the solvent containing lead-free glass fine particles is controlled within the first range, and then the dielectric constant is controlled within the first range. (The mixed solvent of isopropyl alcohol and ethyl acetate) is added with a surfactant, water, and an electrolyte, and the suspension is subjected to electrophoretic deposition using a suspension whose electric conductivity is controlled in the second range. Lead-free glass particles in the liquid are deposited on the mesa groove of the semiconductor wafer.
　これにより、半導体ウェーハに形成されたメサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができる。 Thereby, the thickness of the lead-free glass fine particles deposited in the mesa groove formed on the semiconductor wafer can be accurately controlled to a predetermined thickness.
　特に、鉛フリーガラス微粒子の堆積物の厚さが所定の厚さに制御されるため、この堆積物を焼成してガラス化したパッシベーション膜の膜厚も所定の膜厚に制御されることとなり、半導体ウェーハから切断分離された半導体装置のパッシベーション膜の絶縁性（逆方向特性）のばらつきを低減して当該半導体装置の信頼性を向上ことが可能となる。 In particular, since the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness, the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
　なお、上記実施形態においては、半導体ウェーハとしてシリコンからなる半導体ウェーハ板を用いたが、本発明はこれに限定されるものではない。例えば、ＳｉＣ、ＧａＮ、ＧａＯなどからなる半導体ウェーハを用いることもできる。 In the above embodiment, a semiconductor wafer plate made of silicon is used as the semiconductor wafer, but the present invention is not limited to this. For example, a semiconductor wafer made of SiC, GaN, GaO or the like can be used.
　本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。 Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.
１　ガラス被膜形成装置　
１０　槽　
１２　懸濁液　
１４　第１電極板　
１６　第２電極板　
２０　電源装置　
１００　半導体装置
１１０　ｎ－型半導体基板
１１２　ｐ＋型拡散層
１１４　ｎ－型拡散層
１１６，１１８　酸化膜
１２０　溝（メサ溝）
１２１　下地絶縁膜
１２４　ガラス被膜
１２６　フォトレジスト
１３０　Ｎｉめっき電極膜を形成する部位
１３２　粗面化領域
１３４　アノード電極
１３６　カソード電極
Ｖ１　第１電極板の電位
Ｖ２　第２電極板の電位 1 Glass film forming equipment
10 tanks
12 Suspension
14 First electrode plate
16 Second electrode plate
20 Power supply
100 Semiconductor device 110 n− type semiconductor substrate 112 p + type diffusion layer 114 n− type diffusion layers 116 and 118 Oxide film 120 groove (mesa groove)
121 Substrate insulating film 124 Glass coating 126 Photoresist 130 Ni plating electrode film forming portion 132 Roughened region 134 Anode electrode 136 Cathode electrode V1 Potential of first electrode plate V2 Potential of second electrode plate

Claims (15)

  1. 　ガラス被膜形成面にメサ溝が形成された半導体ウェーハを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第１電極板と第２電極板とを前記懸濁液に浸漬した状態で対向して設置するとともに、前記第１電極板と前記第２電極板との間に前記半導体ウェーハを前記ガラス被膜形成面が前記第１電極板側に向いた状態で、電気泳動堆積法により前記ガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む半導体装置の製造方法であって、
    　前記ガラス被膜形成工程で用いられる前記懸濁液は、前記鉛フリーガラス微粒子を含む前記溶媒の誘電率を第１の範囲に制御した後、当該溶媒に、界面活性剤、水、及び電解質を加えて、その電気伝導度を第２の範囲に制御した懸濁液である
    　ことを特徴とする半導体装置の製造方法。     A semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass coating formation surface, and a suspension in which lead-free glass fine particles are suspended in a solvent, the first electrode plate and the second electrode plate are A state in which the semiconductor wafer is placed between the first electrode plate and the second electrode plate while facing each other while being immersed in the suspension, and the glass film forming surface faces the first electrode plate side A glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition, and a method for manufacturing a semiconductor device,
    The suspension used in the glass coating forming step is controlled by adding a surfactant, water, and an electrolyte to the solvent after controlling the dielectric constant of the solvent containing the lead-free glass fine particles to the first range. A method of manufacturing a semiconductor device, characterized in that the electrical conductivity is a suspension whose second range is controlled.
  2. 　前記界面活性剤、前記水及び前記電解質の少なくとも何れか１つを調整することで、前記懸濁液の前記電気伝導度を前記第２の範囲に制御する
    　ことを特徴とする請求項１に記載の半導体装置の製造方法。     The electrical conductivity of the suspension is controlled to the second range by adjusting at least one of the surfactant, the water, and the electrolyte. Semiconductor device manufacturing method.
  3. 　前記溶媒の誘電率の前記第１の範囲は、５～１１の範囲であることを特徴とする請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein the first range of the dielectric constant of the solvent is in the range of 5 to 11.
  4. 　前記懸濁液の電気伝導度の前記第２の範囲は、２００ｎＳ/ｃｍ～４００ｎＳ/ｃｍの範囲であることを特徴とする請求項３に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 3, wherein the second range of electric conductivity of the suspension is in a range of 200 nS / cm to 400 nS / cm.
  5. 　前記溶媒に加えられる前に、前記電解質は、電気伝導度が第３の範囲に制御されており、
    　前記電解質の電気伝導度の前記第３の範囲は、９０μＳ/ｃｍ～１３０μＳ/ｃｍの範囲であることを特徴とする請求項４に記載の半導体装置の製造方法。     Prior to being added to the solvent, the electrolyte has a conductivity controlled to a third range;
    5. The method of manufacturing a semiconductor device according to claim 4, wherein the third range of the electric conductivity of the electrolyte is in a range of 90 μS / cm to 130 μS / cm.
  6. 　前記電解質は、有機溶剤と硝酸とを含む混合液であることを特徴とする請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein the electrolyte is a mixed solution containing an organic solvent and nitric acid.
  7. 　前記有機溶剤は、イソプロピルアルコール又は酢酸エチルであることを特徴とする請求項６に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 6, wherein the organic solvent is isopropyl alcohol or ethyl acetate.
  8. 　前記電解質の前記電気伝導度を、前記混合液における前記硝酸の割合を調整することにより、前記第３の範囲に制御することを特徴とする請求項７に記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 7, wherein the electrical conductivity of the electrolyte is controlled to the third range by adjusting a ratio of the nitric acid in the mixed solution.
  9. 　前記溶媒は、イソプロピルアルコールと酢酸エチルとを含む混合溶媒であることを特徴とする請求項３に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 3, wherein the solvent is a mixed solvent containing isopropyl alcohol and ethyl acetate.
  10. 　前記溶媒の誘電率を、前記混合溶媒における前記酢酸エチルの割合を調整することにより、前記第１の範囲に制御する
    　ことを特徴とする請求項９に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 9, wherein the dielectric constant of the solvent is controlled within the first range by adjusting a ratio of the ethyl acetate in the mixed solvent.
  11. 　前記鉛フリーガラス微粒子は、ＳｉＯ２、Ａｌ２Ｏ３、ＣａＯ、ＭｇＯ、ＺｎＯ、Ｂ２Ｏ３、ＢａＯの少なくとも何れか１つを含む鉛フリーガラス微粒子である
    　ことを特徴とする請求項２に記載の半導体装置の製造方法。     The lead-free glass fine particles are lead-free glass fine particles containing at least one of SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , and BaO. The manufacturing method of the semiconductor device of description.
  12. 　前記界面活性剤は、非イオン系界面活性剤であることを特徴とする請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein the surfactant is a nonionic surfactant.
  13. 　前記界面活性剤は、ポリエチレングリコールであることを特徴とする請求項１２に記載の半導体装置の製造方法。 13. The method of manufacturing a semiconductor device according to claim 12, wherein the surfactant is polyethylene glycol.
  14. 　前記半導体ウェーハ準備工程は、主面に平行なｐｎ接合を備える半導体ウェーハを準備する工程と、
    　前記半導体ウェーハの一方の表面から前記ｐｎ接合を超える深さの溝を形成することにより、前記溝の内面に前記ｐｎ接合の露出部を形成する工程と、
    　前記ｐｎ接合の露出部を覆うように前記溝の内面に下地絶縁膜を形成する工程と、を含む
    　ことを特徴とする請求項２に記載の半導体装置の製造方法。     The semiconductor wafer preparation step includes a step of preparing a semiconductor wafer having a pn junction parallel to the main surface;
    Forming an exposed portion of the pn junction on the inner surface of the groove by forming a groove having a depth exceeding the pn junction from one surface of the semiconductor wafer;
    The method for manufacturing a semiconductor device according to claim 2, further comprising: forming a base insulating film on an inner surface of the groove so as to cover the exposed portion of the pn junction.
  15. 　前記半導体ウェーハ準備工程は、
    　半導体ウェーハの表面にｐｎ接合の露出部を形成する工程と、前記ｐｎ接合の露出部を覆うように前記半導体ウェーハの表面に下地絶縁膜を形成する工程と、を含む
    　ことを特徴とする請求項２に記載の半導体装置の製造方法。     The semiconductor wafer preparation step
    And forming a base insulating film on the surface of the semiconductor wafer to cover the exposed portion of the pn junction. 3. A method for manufacturing a semiconductor device according to 2.
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