WO2017124878A1 - 倒装led芯片的键合电极结构及制作方法 - Google Patents

倒装led芯片的键合电极结构及制作方法 Download PDF

Info

Publication number
WO2017124878A1
WO2017124878A1 PCT/CN2016/111662 CN2016111662W WO2017124878A1 WO 2017124878 A1 WO2017124878 A1 WO 2017124878A1 CN 2016111662 W CN2016111662 W CN 2016111662W WO 2017124878 A1 WO2017124878 A1 WO 2017124878A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
flip
led chip
layer
chip
Prior art date
Application number
PCT/CN2016/111662
Other languages
English (en)
French (fr)
Inventor
钟志白
杨力勋
郑锦坚
李佳恩
徐宸科
康俊勇
Original Assignee
厦门市三安光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 厦门市三安光电科技有限公司 filed Critical 厦门市三安光电科技有限公司
Publication of WO2017124878A1 publication Critical patent/WO2017124878A1/zh
Priority to US15/859,543 priority Critical patent/US10276750B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/13578—Plural coating layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/13686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present invention belongs to the field of optoelectronic technology, and particularly relates to a bonded electrode structure of a flip-chip LED chip and a manufacturing method thereof.
  • LEDs Light-emitting diodes
  • FC-LED chip flip-chip bonding structure
  • An object of the present invention is to provide a bonded electrode structure and a manufacturing method of a flip-chip LED chip, which solves the problem that a conventional flip-chip LED chip structure is prone to short-circuit or leakage during package soldering.
  • a bonded electrode structure of a flip-chip LED chip characterized in that: the bonding electrode structure is divided into a bottom layer and an upper surface layer in a vertical direction from bottom to top.
  • the sidewall of the bonding electrode underlayer structure forms an oxide layer for flip-chip LED package, because the adhesion to the surface of the solder paste is poor, and the surface tension is large, so that the solder paste is downwardly packaged.
  • the electrode is extended to prevent the solder paste from diffusing toward the LED chip end, thereby avoiding chip leakage and short circuit, and improving reliability;
  • the upper surface layer of the main contact portion is used for contact conduction and heat dissipation;
  • the sidewall of the bottom portion structure of the grid-shaped partial electrode forms an oxide layer having a barrier effect as a retaining wall for solder paste for packaging;
  • the number of the grating partial electrodes is at least four;
  • the grid partial electrode pattern includes a rectangle or a square or a circle or an ellipse or a triangle or a polygon or a cross or a combination of the foregoing;
  • the grating portion is distributed around a certain side or each side of the main contact portion; [0011] further, the non-oxidizable metal is selected from A1 or Ag or Cu or one of any combination of the foregoing;
  • the oxidizable metal is selected from Cr or Pt or Au or one of any combination of the foregoing.
  • a method for fabricating a bonded electrode structure of a flip-chip LED chip includes:
  • a metal laminate including a bottom layer and an upper surface layer in a vertical direction from bottom to top, wherein the bottom layer is an easily oxidizable metal, and the upper surface layer is a metal that is not easily oxidized; the main contact portion is divided into a main contact portion and a gate surrounding the main contact portion in a horizontal direction.
  • the metal laminate is subjected to oxygen plasma pretreatment, the upper surface layer is not easily oxidized, the oxygen plasma forms a clean surface layer, and the surface activity is increased to form a good contact, and the bottom layer is an easily oxidizable metal, an oxygen ion body. Treatment will cause the sidewalls of the underlayer to form an oxide layer.
  • the oxide layer formed on the sidewall of the bonding electrode underlayer structure is used for flip-chip LED package, because the adhesion to the solder paste surface is poor, and the surface tension is large, so that the solder paste is downwardly
  • the package electrode is extended to prevent the solder paste from diffusing toward the LED chip end, thereby avoiding chip leakage and short circuit, and improving reliability;
  • an upper surface layer of the main contact portion is used for contact conduction and heat dissipation
  • the sidewall of the bottom portion structure of the grid-shaped partial electrode forms an oxide layer having a barrier effect as a retaining wall for solder paste for packaging;
  • the number of the grating partial electrodes is at least four;
  • the grating partial electrode pattern is rectangular or square or circular or elliptical or triangular or polygonal or cross or a combination of the foregoing;
  • the grating portion is distributed around a certain side or each side of the main contact portion; [0022] further, the oxidizable metal is selected from A1 or Ag or Cu or one of any combination of the foregoing; [0023] Further, the non-oxidizable metal is selected from Cr or Pt or Au or one of any combination of the foregoing.
  • a flip-chip LED chip comprising: a light-emitting epitaxial layer composed of a first semiconductor layer, a second semiconductor layer, and a quantum well layer sandwiched between two layers, and located at The P electrode on the second semiconductor layer and the N electrode on the first semiconductor layer are characterized in that: the P electrode and the N electrode structure in the flip chip LED chip structure are provided as the bonding electrode structure.
  • a distance between the P electrode and the N electrode is greater than a cross distance of the P electrode or the N electrode.
  • the P electrode and the N electrode have a cross-sectional distance of less than 100 ⁇ m.
  • the distance between the ⁇ electrode and the ⁇ electrode is greater than 100 ⁇ m.
  • the flip-chip LED chip electrode structure design of the present invention includes at least the following technical effects:
  • the sidewall of the grid-shaped partial electrode underlayer structure forms an oxide layer having a barrier effect, as a solder paste for encapsulation Retaining wall
  • the distance between the P electrode and the N electrode in the bonded electrode structure is larger than the cross-sectional distance of the P electrode or the N electrode, the electrode cross-sectional distance is small, and the electrode material is saved, and is used for flip-chip LED package.
  • the solder paste has a small chance of overflow; and the spacing is large, and the chance of the mutual diffusion of the solder paste on both sides of the P electrode and the N electrode is reduced, and short circuit or leakage is not easily generated.
  • FIG. 3 are schematic cross-sectional views showing the structure of a flip-chip LED chip fabricated according to an embodiment of the present invention
  • FIG. 3 is a schematic view of the structure of the flip-chip LED chip of FIG. Top view.
  • FIG. 4 is a cross-sectional view of a flip chip LED chip structure for a solder paste package according to an embodiment of the invention. [0034] FIG.
  • FIG. 5 is a schematic top view showing a schematic view of a gate portion electrode referred to in the present invention.
  • Each reference numeral in the drawing indicates: 100: substrate; 101: luminescent epitaxial layer; 102: P electrode; 103: N electrode; 1021A: underlying structure of the main contact portion of the N electrode; 1022A: above the main contact portion of the N electrode Surface layer; 1021B: bottom structure of N-electrode grid portion; 1022B: surface layer above N-gate grid portion; 103: P electrode; 104: oxide layer; 105: solder paste; 106: package electrode; 107: package substrate; W1 : electrode spacing; W2: cross-sectional distance.
  • the present invention proposes a bonding electrode design suitable for flip-chip LED chips, and solves the problem that the conventional flip-chip LED chip structure is prone to short-circuit or leakage during package soldering without changing the package substrate.
  • the following embodiments will be used to illustrate the bonded electrode structure and flip chip LED chip of the present invention.
  • the flip-chip LED chip provided in this embodiment includes: a substrate 100; a light-emitting epitaxial layer 101 composed of an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer, which is located in the lining Above the bottom 100; an N electrode 102 on the N-type semiconductor layer of the light-emitting epitaxial layer 101; and a P-electrode 103 on the P-type semiconductor layer of the light-emitting epitaxial layer 101.
  • the substrate 100 may be selected from a substrate suitable for epitaxial growth such as sapphire or silicon carbide or silicon or gallium nitride or aluminum nitride or zinc oxide.
  • a substrate suitable for epitaxial growth such as sapphire or silicon carbide or silicon or gallium nitride or aluminum nitride or zinc oxide.
  • sapphire is preferred;
  • the light-emitting epitaxial layer 101 is nitrogen.
  • Gallium (GaN) series materials but not limited thereto;
  • P electrode 103, N electrode 102 as a bonding electrode structure, divided vertically from bottom to top into a metal stack composed of a bottom layer and an upper surface layer, wherein the underlying structure It is an oxidizable metal and an oxide layer is formed on the sidewall, and the upper surface layer is a metal that is not easily oxidized;
  • the touch portion and the grid portion surrounding the main contact portion is selected from a substrate suitable for epitaxial growth such as sapphire or silicon carbide or silicon or gallium
  • the areas of the P and N electrodes may be equivalent and the positions are symmetrical.
  • the N electrode is divided into the bottom layer (1021A, 1021B) and the upper surface layer (1022A, 1022B) in the vertical direction, and is divided into a main contact portion (1021A, 1022A) and a grid portion (1021B, 1022B) in the horizontal direction.
  • the oxidizable metal which can be used for the underlying structure is selected from A1 or Ag or Cu or one of the foregoing combinations, and has a thickness of 2000 A-50000A.
  • the oxidized metal sidewall forms an oxide layer 104, and the upper surface layer is selected to be non-oxidizable metal including Cr.
  • the grid portion electrode pattern is square, the number is at least 4, and this embodiment is preferably 8 layers are distributed on both sides of the main contact layer;
  • the sidewall of the grid-shaped partial electrode bottom layer structure forms an oxide layer 104 having a retaining wall effect, and is used as a retaining wall for the package solder paste 105 for flip-chip LED package, due to The adhesion to the surface of the solder paste 105 is poor, and the surface tension is large, so that the solder paste spreads down the package electrode 106 (above the package substrate 107) to block the solder paste 105. Diffusing the LED chip end, so as to avoid leakage and short circuit chip to improve reliability.
  • the gate portion electrode pattern (eg, 1022B) may be changed according to the actual chip design, including rectangular or square or circular or elliptical or A triangle or a polygon or a cross or a combination of the foregoing is as shown in FIG. 5.
  • the grid-shaped partial electrode distribution surrounds the two sides of the main contact portion, it is to be understood that the grid-shaped partial electrode may also be distributed around each side of the main contact portion as needed, not to 2 Or 4 sides are limited.
  • the distance W1 between the P electrode and the N electrode of the embodiment is greater than 100 ⁇ m
  • the cross-sectional distance W2 of the germanium electrode and the germanium electrode is less than 100 ⁇ m, that is, the distance between the germanium electrode and the germanium electrode is greater than that of the germanium electrode or the germanium electrode.
  • the cross-sectional distance is such that the electrode cross-section distance is small, the electrode material is saved, and the chance of overflowing the solder paste for the flip-chip LED package is small; and the pitch is large, and the solder paste on both sides of the P electrode and the N electrode is reduced. Diffusion meets the probability that it is not prone to short circuit or leakage.
  • the method for fabricating the flip-chip LED chip bonding electrode structure of the above embodiment includes the following steps;
  • a metal laminate is formed, which is sequentially vapor-deposited or sputtered with an easily oxidizable metal Al, and is not easily oxidized by metal Cr, Pt, and Au.
  • the oxidizable metal is a bottom layer, and the metal is not easily oxidized to the upper surface layer; in the horizontal direction, The yellow light mask process is divided into a main contact portion and a grid portion surrounding the main contact portion;
  • the above metal layer is subjected to oxygen plasma (0 2 Plasma) pretreatment, and the upper surface layer metal is not easily oxidized, and the plasma can form a clean surface and improve surface activity, so that the upper surface layer forms a good contact, and the bottom layer is formed.
  • the metal of the sidewall is easily formed by the action of an oxygen ion, and the oxide layer A1 2 0 3 is easily formed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

一种倒装LED芯片的键合电极结构及制作方法，包括：衬底（100）；发光外延层（101），位于衬底之上；键合电极（102，103），位于发光外延层之上；键合电极结构，在垂直方向从下至上划分为由底层（1021A，1021B）和上表层（1022A，1022B）组成的金属叠层，其中底层结构为易氧化金属且侧壁形成氧化层（104），上表层为不易氧化金属；在水平方向划分为主接触部分（1021A，1022A）以及围绕主接触部分的栅状部分（1021B，1022B）。该键合电极结构及制作方法解决了习知倒装LED芯片结构在封装焊接时容易发生短路或者漏电的问题。

Description

说明书 发明名称：倒装 LED芯片的键合电极结构及制作方法 技术领域
[0001] 本发明属于光电技术领域， 具体涉及倒装 LED芯片的键合电极结构及制作方法 背景技术
[0002] 发光二极管 （LED) 具有寿命长、 节能环保等显著优点， 被认为是继白炽灯、 荧光灯之后又一次照明技术的革命， 是目前国际上半导体和照明领域研发和产 业关注的焦点， 拥有巨大的应用前景。 以蓝宝石、 A1N等作为绝缘衬底的 LED芯 片， 由于衬底导热率比较低， 因此横向结构的 LED的 PN结的温度比较高。 为了 解决散热的问题， 芯片的倒装焊结构 （FC-LED) 被提出， 发光效率和散热效果 都有了改进。 但是倒装芯片设计， 由于 P、 N金属电极的大小、 位置受限， 倒装 芯片贴片回流焊已经成为一种产业化的封装方式， 在封装吋常采用锡膏焊接的 作业方式， 易造成锡膏涂布不均、 锡膏溢流出焊盘区域， 若遇到芯片电极焊料 挤压就会发生电路不良、 漏电等异常。
技术问题
问题的解决方案
技术解决方案
[0003] 发明的目的在于： 提供一种倒装 LED芯片的键合电极结构及制作方法， 解决习 知倒装 LED芯片结构在封装焊接吋容易发生短路或者漏电的问题。
[0004] 根据本发明的第一方面， 提供一种倒装 LED芯片的键合电极结构， 其特征在于 ： 所述键合电极结构， 在垂直方向从下至上划分为由底层和上表层组成的金属 叠层， 其中底层结构为易氧化金属且侧壁形成氧化层， 上表层为不易氧化金属 ； 在水平方向划分为主接触部分以及围绕主接触部分的栅状部分。
[0005] 进一步地， 所述键合电极底层结构的侧壁形成氧化层， 用于倒装 LED封装吋， 由于与锡膏表面附着性很差， 表面张力大， 使得锡膏向下沿着封装电极扩展， 以阻止锡膏往 LED芯片端扩散， 从而避免芯片漏电和短路， 提高可靠性； [0006] 进一步地， 所述主接触部分的上表层用于接触导电和散热；
[0007] 进一步地， 所述栅状部分电极底层结构的侧壁形成氧化层具有挡墙效果， 作为 封装用锡膏的挡墙；
[0008] 进一步地， 所述栅状部分电极数目至少 4个；
[0009] 进一步地， 所述栅状部分电极图形包括长方形或者正方形或圆形或椭圆形或三 角形或多边形或十字形或前述组合；
[0010] 进一步地， 所述栅状部分分布围绕在主接触部分的某个侧面或者各个侧面； [0011] 进一步地， 所述不易氧化金属选用 A1或 Ag或 Cu或前述任意组合之一；
[0012] 进一步地， 所述易氧化金属选用 Cr或 Pt或 Au或前述任意组合之一。
[0013] 根据本发明的第二方面， 提供一种倒装 LED芯片的键合电极结构的制作方法， 包括：
[0014] 先制作金属叠层， 在垂直方向从下至上包括底层和上表层， 其中底层为易氧化 金属， 上表层为不易氧化金属； 在水平方向划分为主接触部分以及围绕主接触 部分的栅状部分；
[0015] 再对所述金属叠层进行氧等离子体预处理， 上表层不易氧化， 氧等离子体对上 表层形成清洁， 提高表面活性， 以形成良好的接触， 底层为易氧化金属， 氧离 子体处理会使底层的侧壁形成氧化层。
[0016] 进一步地， 所述键合电极底层结构的侧壁形成的氧化层， 用于倒装 LED封装吋 ， 由于与锡膏表面附着性很差， 表面张力大， 使得锡膏向下沿着封装电极扩展 ， 以阻止锡膏往 LED芯片端扩散， 从而避免芯片漏电和短路， 提高可靠性；
[0017] 进一步地， 所述主接触部分的上表层， 用于接触导电和散热；
[0018] 进一步地， 所述栅状部分电极底层结构的侧壁形成氧化层具有挡墙效果， 作为 封装用锡膏的挡墙；
[0019] 进一步地， 所述栅状部分电极数目至少 4个；
[0020] 进一步地， 所述栅状部分电极图形长方形或者正方形或圆形或椭圆形或三角形 或多边形或十字形或前述组合；
[0021] 进一步地， 所述栅状部分分布围绕在主接触部分的某个侧面或者各个侧面； [0022] 进一步地， 所述易氧化金属选用 A1或 Ag或 Cu或前述任意组合之一； [0023] 进一步地， 所述不易氧化金属选用 Cr或 Pt或 Au或前述任意组合之一。
[0024] 根据本发明的第三方面， 提供一种倒装 LED芯片， 包括： 由第一半导体层、 第 二半导体层及夹在两层之间的量子阱层组成的发光外延层， 以及位于第二半导 体层上的 P电极、 位于第一半导体层上的 N电极， 其特征在于： 所述倒装 LED芯 片结构中所述 P电极、 N电极结构设置为上述键合电极结构。
[0025] 进一步地， 所述 P电极与 N电极的间距大于 P电极或 N电极的横截距离。
[0026] 进一步地， 所述 P电极、 N电极的横截距离小于 100μηι。
[0027] 进一步地， 所述 Ρ电极与 Ν电极的间距大于 100μηι。
发明的有益效果
有益效果
[0028] 与现有技术相比， 本发明的倒装 LED芯片电极结构设计， 至少包括以下技术效 果：
[0029] (1) 藉由键合电极结构的主接触部分的上表层， 用于接触导电和散热， 栅状 部分电极底层结构的侧壁形成氧化层具有挡墙效果， 作为封装用锡膏的挡墙；
[0030] (2) 藉由键合电极底层结构的侧壁通过氧等离子体预处理形成氧化层， 用于 倒装 LED封装吋， 由于与锡膏表面附着性很差， 表面张力大， 使得锡膏向下沿着 封装电极扩展， 以阻止锡膏往 LED芯片端扩散， 从而避免芯片漏电和短路， 提高 可靠性；
[0031] (3) 藉由键合电极结构中的 P电极与 N电极的间距大于 P电极或 N电极的横截距 离， 电极横截距离较小， 节省电极材料， 用于倒装 LED封装吋锡膏溢出机会小； 而间距较大， 减少位于 P电极与 N电极两侧的锡膏相互扩散会合几率， 不容易产 生短路或者漏电。
对附图的简要说明
附图说明
[0032] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0033] 图 1~图3为本发明实施例制作的倒装 LED芯片结构的剖视示意图， 图 3为图 2的 俯视图。
[0034] 图 4为本发明实施例的倒装 LED芯片结构用于锡膏封装吋的剖视示意图。
[0035] 图 5为本发明中提及的栅极部分电极水平俯视示意图举例。
[0036] 图中各标号表示： 100: 衬底； 101 : 发光外延层； 102: P电极； 103: N电极 ； 1021A: N电极主接触部分之底层结构； 1022A: N电极主接触部分之上表层； 1021B: N电极栅状部分之底层结构； 1022B: N电极栅状部分之上表层； 103: P 电极； 104: 氧化层； 105: 锡膏； 106： 封装电极； 107: 封装基板； W1 : 电极 间距； W2: 横截距离。
本发明的实施方式
[0037] 为了能彻底地了解本发明， 将在下列的描述中提出详尽的步骤及其组成， 另外 ， 众所周知的组成或步骤并未描述于细节中， 以避免造成本发明不必要之限制 。 本发明的较佳实施例会详细描述如下， 然而除了这些详细描述之外， 本发明 还可以广泛地施行在其它的实施例中， 且本发明的范围不受限定， 以专利权利 范围为准。
[0038] 本发明提出一适用于倒装 LED芯片之键合电极设计， 在不改变封装基板的前提 下， 解决习知倒装 LED芯片结构在封装焊接吋容易发生短路或者漏电的问题。 下 面实施例将配合图示说明本发明的键合电极结构及倒装 LED芯片。
具体实施例
[0039] 请参考图 1〜图 3， 本实施例提供的倒装 LED芯片， 包括： 衬底 100; 由 N型半导 体层、 量子阱层和 P型半导体层组成的发光外延层 101， 位于衬底 100之上； N电 极 102， 位于发光外延层 101之 N型半导体层上； P电极 103， 位于发光外延层 101 之 P型半导体层上。
[0040] 具体来说， 上述衬底 100可以选择蓝宝石或碳化硅或硅或氮化镓或氮化铝或氧 化锌等适合外延生长的衬底， 本实施例优选蓝宝石； 发光外延层 101为氮化镓 （ GaN) 系列材料， 但不以此为限； P电极 103、 N电极 102作为键合电极结构， 在 垂直方向从下至上划分为由底层和上表层组成的金属叠层， 其中底层结构为易 氧化金属且侧壁形成氧化层， 上表层为不易氧化金属； 在水平方向划分为主接 触部分以及围绕主接触部分的栅状部分。
[0041] 请参考图 4， P、 N电极的面积可以相当， 且位置对称。 以 N电极为例， 在垂直 方向上划分为底层 （1021A、 1021B) 和上表层 （1022A、 1022B) ， 在水平方向 上划分为主接触部分 （1021A、 1022A) 和栅状部分 （1021B、 1022B) ， 其中底 层结构可选用的易氧化金属选用 A1或 Ag或 Cu或前述任意组合之一， 厚度为 2000 A-50000A, 易氧化金属侧壁形成氧化层 104， 上表层可选用的不易氧化金属包 括 Cr或 Pt或 Au或前述任意组合之一， 厚度为 50人~5000人； 主接触部分的上表层 用于接触导电和散热； 栅状部分电极图形为正方形， 数目至少 4个， 本实施例优 选为 8个， 分布于主接触层的两侧； 栅状部分电极底层结构的侧壁形成氧化层 10 4具有挡墙效果， 作为封装用锡膏 105的挡墙， 用于倒装 LED封装吋， 由于与锡膏 105表面附着性很差， 表面张力大， 使得锡膏向下沿着封装电极 106 (位于封装 基板 107之上） 扩展， 以阻止锡膏 105往 LED芯片端扩散， 从而避免芯片漏电和短 路， 提高可靠性。
[0042] 为进一步提高栅极部分电极底层结构的侧壁氧化层的挡墙效果， 可以根据实际 芯片设计， 改变栅极部分电极图形 （如 1022B) ， 包括长方形或者正方形或圆形 或椭圆形或三角形或多边形或十字形或前述组合， 如参考图 5所示。 此外， 本实 施例虽然示出了栅状部分电极分布围绕在主接触部分的 2个侧面， 需要知晓的是 栅状部分电极还可以根据需要， 分布围绕在主接触部分的各个侧面， 不以 2个或 者 4个侧面为限。
[0043] 请参考图 3， 本实施例的 P电极与 N电极的间距 W1大于 100μηι， Ρ电极、 Ν电极 的横截距离 W2小于 100μηι， 即 Ρ电极与 Ν电极的间距大于 Ρ电极或 Ν电极的横截距 离， 如此则由于电极横截距离较小， 节省电极材料， 用于倒装 LED封装吋锡膏溢 出机会小； 而间距较大， 减少位于 P电极与 N电极两侧的锡膏相互扩散会合几率 ， 不容易产生短路或者漏电。
[0044] 上述实施例的倒装 LED芯片键合电极结构制作方法， 包括以下步骤；
[0045] 先制作金属叠层， 依次蒸镀或溅镀易氧化金属 Al、 不易氧化金属 Cr、 Pt和 Au， 其中易氧化金属为底层， 不易氧化金属为上表层； 在水平方向上， 可以通过黄 光光罩工艺划分为主接触部分以及围绕主接触部分的栅状部分； [0046] 再对上述金属叠层进行氧等离子体 （0 2 Plasma) 预处理， 上表层金属不易氧 化， 等离子体可以对表面形成清洁， 提高表面活性， 如此则上表层会形成良好 的接触， 底层的侧壁的金属在氧离子体作用下， 容易形成氧化层 A1 20 3。
[0047] 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明书中 变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。

Claims

权利要求书
倒装 LED芯片的键合电极结构， 其特征在于： 所述键合电极结构， 在 垂直方向从下至上划分为由底层和上表层组成的金属叠层， 其中底层 结构为易氧化金属且侧壁形成氧化层， 上表层为不易氧化金属； 在水 平方向划分为主接触部分以及围绕主接触部分的栅状部分。
根据权利要求 1所述的倒装 LED芯片的键合电极结构， 其特征在于： 所述键合电极底层结构的侧壁形成氧化层， 用于倒装 LED封装吋， 由 于与锡膏表面附着性很差， 表面张力大， 使得锡膏向下沿着封装电极 扩展， 以阻止锡膏往 LED芯片端扩散， 从而避免芯片漏电和短路， 提 高可靠性。
根据权利要求 1所述的倒装 LED芯片的键合电极结构， 其特征在于： 所述主接触部分的上表层用于接触导电和散热， 所述栅状部分电极底 层结构的侧壁形成氧化层具有挡墙效果。
根据权利要求 1所述的倒装 LED芯片的键合电极结构， 其特征在于： 所述栅状部分电极数目至少 4个。
根据权利要求 1所述的倒装 LED芯片的键合电极结构， 其特征在于： 所述栅状部分电极图形包括长方形或者正方形或圆形或椭圆形或三角 形或多边形或十字形或前述组合。
倒装 LED芯片的键合电极结构的制作方法， 包括：
先制作金属叠层， 在垂直方向从下至上包括底层和上表层， 其中底层 为易氧化金属， 上表层为不易氧化金属； 在水平方向划分为主接触部 分以及围绕主接触部分的栅状部分；
再对所述金属叠层进行氧等离子体预处理， 上表层不易氧化， 氧等离 子体对上表层形成清洁， 提高表面活性， 以形成良好的接触， 底层为 易氧化金属， 氧离子体处理会使底层的侧壁形成氧化层。
根据权利要求 6所述的倒装 LED芯片的键合电极结构的制作方法， 其 特征在于： 所述键合电极底层结构的侧壁形成的氧化层， 用于倒装 L ED封装吋， 氧化层与锡膏表面附着性很差， 表面张力大， 使得锡膏 向下沿着封装电极扩展， 以阻止锡膏往 LED芯片端扩散， 从而避免芯 片漏电和短路， 提高可靠性。
[权利要求 8] 根据权利要求 6所述的倒装 LED芯片的键合电极结构的制作方法， 其 特征在于： 所述主接触部分的上表层用于接触导电和散热， 所述栅状 部分电极底层结构的侧壁形成氧化层具有挡墙效果。
[权利要求 9] 根据权利要求 6所述的倒装 LED芯片的键合电极结构的制作方法， 其 特征在于： 所述栅状部分电极数目至少 4个。
[权利要求 10] 根据权利要求 6所述的倒装 LED芯片的键合电极结构的制作方法， 其 特征在于： 所述栅状部分电极图形包括长方形或者正方形或圆形或椭 圆形或三角形或多边形或十字形或前述组合。
[权利要求 11] 倒装 LED芯片结构， 包括： 由第一半导体层、 第二半导体层及夹在两 层之间的量子阱层组成的发光外延层， 以及位于第二半导体层上的 P 电极、 位于第一半导体层上的 N电极， 其特征在于： 所述倒装 LED芯 片结构中所述 P电极、 N电极结构设置为权利要求 1~4中任一项所述的 键合电极结构。
[权利要求 12] 根据权利要求 11所述的倒装 LED芯片结构， 其特征在于： 所述 P电极 与 N电极的间距大于 P电极或 N电极的横截距离。
PCT/CN2016/111662 2016-01-18 2016-12-23 倒装led芯片的键合电极结构及制作方法 WO2017124878A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/859,543 US10276750B2 (en) 2016-01-18 2017-12-31 Bonding electrode structure of flip-chip led chip and fabrication method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610030189.8 2016-01-18
CN201610030189.8A CN105489727B (zh) 2016-01-18 2016-01-18 倒装led芯片的键合电极结构及制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/859,543 Continuation US10276750B2 (en) 2016-01-18 2017-12-31 Bonding electrode structure of flip-chip led chip and fabrication method

Publications (1)

Publication Number Publication Date
WO2017124878A1 true WO2017124878A1 (zh) 2017-07-27

Family

ID=55676586

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/111662 WO2017124878A1 (zh) 2016-01-18 2016-12-23 倒装led芯片的键合电极结构及制作方法

Country Status (3)

Country Link
US (1) US10276750B2 (zh)
CN (1) CN105489727B (zh)
WO (1) WO2017124878A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489727B (zh) * 2016-01-18 2018-06-19 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法
CN110416243B (zh) * 2019-07-26 2021-11-12 成都辰显光电有限公司 一种显示面板及其制作方法
CN110707186A (zh) 2019-10-21 2020-01-17 深圳市华星光电半导体显示技术有限公司 Led显示面板的制备方法
CN113690267B (zh) * 2021-06-30 2023-01-17 河源市众拓光电科技有限公司 一种贴片式hemt-led的单片集成方法
CN114038877A (zh) * 2021-08-09 2022-02-11 重庆康佳光电技术研究院有限公司 发光芯片及其制作方法和发光组件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243709A (ja) * 2002-02-15 2003-08-29 Matsushita Electric Works Ltd 半導体発光素子
CN102683535A (zh) * 2011-03-17 2012-09-19 斯坦雷电气株式会社 发光元件、发光元件模块及车辆用灯具
CN103493225A (zh) * 2011-07-06 2014-01-01 松下电器产业株式会社 氮化物半导体发光元件及其制造方法
CN104576858A (zh) * 2013-10-15 2015-04-29 上海工程技术大学 一种新型倒装led芯片结构及其制作方法
CN105489727A (zh) * 2016-01-18 2016-04-13 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192782A (ja) * 2007-02-05 2008-08-21 Toyota Central R&D Labs Inc 電極及びそれを有するｉｉｉ族窒化物系化合物半導体発光素子
TW200929591A (en) * 2007-12-19 2009-07-01 Chi Mei Lighting Technologycorporation Light-emitting diode device with thermally conductive base
US8631855B2 (en) * 2008-08-15 2014-01-21 Lighting Science Group Corporation System for dissipating heat energy
US8058669B2 (en) * 2008-08-28 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitting diode integration scheme
JP2010141262A (ja) * 2008-12-15 2010-06-24 Showa Denko Kk 半導体発光素子、電極構造、半導体発光素子の製造方法、電極構造の製造方法
CN101859861A (zh) * 2010-05-13 2010-10-13 厦门市三安光电科技有限公司 具有双反射层的氮化镓基倒装发光二极管及其制备方法
CN102437063A (zh) * 2011-11-25 2012-05-02 北京大学深圳研究生院 一种液态凸点倒装芯片的制作方法
CN103325905B (zh) * 2012-03-20 2016-01-06 山东浪潮华光光电子股份有限公司 一种具有电流阻挡结构的GaN基发光二极管芯片及其制作方法
CN204088359U (zh) * 2014-08-13 2015-01-07 扬州乾照光电有限公司 全覆盖式扩展电极结构的发光二极管

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243709A (ja) * 2002-02-15 2003-08-29 Matsushita Electric Works Ltd 半導体発光素子
CN102683535A (zh) * 2011-03-17 2012-09-19 斯坦雷电气株式会社 发光元件、发光元件模块及车辆用灯具
CN103493225A (zh) * 2011-07-06 2014-01-01 松下电器产业株式会社 氮化物半导体发光元件及其制造方法
CN104576858A (zh) * 2013-10-15 2015-04-29 上海工程技术大学 一种新型倒装led芯片结构及其制作方法
CN105489727A (zh) * 2016-01-18 2016-04-13 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法

Also Published As

Publication number Publication date
US20180145220A1 (en) 2018-05-24
US10276750B2 (en) 2019-04-30
CN105489727A (zh) 2016-04-13
CN105489727B (zh) 2018-06-19

Similar Documents

Publication Publication Date Title
US6649437B1 (en) Method of manufacturing high-power light emitting diodes
WO2017124878A1 (zh) 倒装led芯片的键合电极结构及制作方法
CN101897046B (zh) 半导体发光器件及其制造方法
TWI453948B (zh) The structure of the press - fit type flip - chip light emitting element and its making method
US10490701B2 (en) Light emitting diode chip
WO2014036803A1 (zh) 一种改善出光率的发光二极管倒装芯片及其制备方法
TWM484188U (zh) 發光元件
CN101359704B (zh) 发光元件及其制造方法
CN109449271B (zh) 一种具有焊料电极的led芯片及其制作方法
CN102593304B (zh) 一种使用陶瓷散热的高功率led灯具
TWI575769B (zh) 發光二極體晶片、發光裝置以及發光二極體的晶圓級結構
CN100414704C (zh) 平面倒装led集成芯片及制造方法
CN203521454U (zh) 一种倒装led芯片的欧姆接触电极结构及倒装led芯片
CN104733600A (zh) 一种倒装led芯片及其制备方法
CN105336829A (zh) 倒装发光二极管结构及其制作方法
CN102569586A (zh) 整面压合式倒装led及其制备方法
CN1780002A (zh) 倒装氮化镓基发光二极管芯片的制作方法
CN211555926U (zh) 防短接led芯片结构
CN210692539U (zh) 一种倒装GaN基HEMT-LED集成器件
CN103904182A (zh) 一种衬底图形化的倒装led芯片及其制备方法
CN207116465U (zh) 一种易封装易散热倒装高压led芯片
CN103367579B (zh) 一种半导体发光器件的电流阻挡层及其制备方法
CN209691782U (zh) 一种半导体器件
CN201266609Y (zh) 带静电保护功能的led芯片
CN203536474U (zh) Led芯片

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16886138

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16886138

Country of ref document: EP

Kind code of ref document: A1