WO2017113266A1

WO2017113266A1 - Finfet doping method

Info

Publication number: WO2017113266A1
Application number: PCT/CN2015/100058
Authority: WO
Inventors: 洪俊华; 陈炯; 金光耀; 张劲; 何川
Original assignee: 上海凯世通半导体有限公司
Priority date: 2015-12-31
Filing date: 2015-12-31
Publication date: 2017-07-06
Also published as: TW201724206A; CN108431928B; TWI567797B; CN108431928A

Abstract

A FinFET doping method. The FinFET comprises a substrate (1) and Fins (21, 22) located on the substrate (1) and arranged in parallel at an interval, wherein each Fin (21, 22) comprises a top face, and an opposite first side wall and second side wall. The doping method comprises: forming a dielectric layer (31, 32) on the surface of each Fin (21, 22), wherein the dielectric layer (31, 32) covers the top face, the first side wall and the second side wall of the Fin (21, 22); respectively injecting a doping element into the Fin (21, 22) from a first side wall side and a second side wall side; and performing a heat treatment so that the doping element is diffused into the Fin (21, 22) and is activated, wherein the thickness of the dielectric layer (31, 32) is at least 1 nm, and the injection energy of the doping element is 2 keV or below. By covering the top and the side walls of the Fins (21, 22) with the dielectric layer (31, 32) instead of directly injecting the doping element into the Fins (21, 22), the doped element is prevented from directly entering the Fins (21, 22); and by performing a heat treatment to form doping of the Fins (21, 22), a doping dosage of the top and the side walls is controlled and the Fins (21, 22) are protected from direct ion bombardment.

Description

FinFET doping method

Technical field

The present invention relates to a doping method, and more particularly to a doping method of a FinFET.

Background technique

As integrated circuits move from smaller 22nm technology nodes to smaller sizes, the process uses FinFET (Fin Field Effect Transistor, Fin is a fin, FinFET named according to the shape of the transistor and the fin similarity) structure, designed to reduce Channeling has an absolute advantage in suppressing subthreshold currents and gate leakage currents. As integration increases, it will be an inevitable trend for FinFET devices to replace traditional planar devices.

In terms of device structure, with the development of processes below 14 nm, the aspect ratio of the FinFET structure (the ratio of the height of Fin to the distance between two Fin) increases, the angle of ion implantation (injection direction and The angle of the Fin top normal is getting smaller and smaller, so the ions injected into the top will be more than the ions injected into the sidewall, and for each complete injection of the top and the two sidewalls. Since it is not vertical injection, there is only one ion implantation per sidewall, and the top surface has undergone two ion implantations, which undoubtedly exacerbates the severe unevenness of the doping dose of the top of Fin and the sidewall of Fin. At present, this non-uniformity is extremely significant, even reaching a ratio of top to side doping dose of 20:1, and optimally, reaching 10:1. That is to say, the doping amount of the top is much larger than that of the sidewall, and this unevenness is extremely disadvantageous for the optimization of device performance.

Furthermore, the energy of high-dose ion implantation is generally higher, and the bombardment of the Fin by the ions after the higher-energy ion implantation may destroy the single crystal structure of Fin to cause a problem of amorphization.

In terms of process, the existing process steps are complicated, and a hard mask must be introduced during doping, which further complicates the entire process. IBM has published a patent application this year (US20150079773) which involves a method of doping FinFETs in order to form NFETs (N-type field effect transistors) and PFETs (P-type field effect transistors) on a substrate. The following processes:

a covering the surface of all Fin oxide layers;

b covering the photoresist on the Fin forming the PFET;

c removing the oxide layer overlying the Fin of the NFET to be formed while removing the photoresist;

d integrally depositing an N-type dopant;

e diffusing an N-type dopant into Fin to form an NFET;

f removing the remaining N-type dopant and the oxide layer on the Fin of the PFET to be formed;

g again forming an oxide layer to cover the NFET and the undoped Fin (ie, the Fin of the PFET to be formed);

h forming a photoresist on the NFET;

i removing the oxide layer on the undoped Fin while removing the photoresist;

j integrally depositing a P-type dopant;

k diffuses a P-type dopant into Fin to form a PFET;

l Remove the remaining P-type dopant and the oxide layer on the NFET.

In order to form FETs of different doping types, it is necessary to form a mask to protect the portion that does not need to be doped. Due to the high temperature of the diffusion doping process, the mask must be able to withstand high temperatures, mostly oxide layers. This is a kind of hard mask, and its formation process and removal process itself are complicated and the steps are very complicated.

Summary of the invention

The technical problem to be solved by the present invention is to overcome the defects of severe unevenness of the doping amount of the top and side walls of Fin in the prior art, the amorphization of Fin in the doping process, and the hard masking in the doping process. The defects of the film and the process are complicated, and a FinFET doping method is provided. The doping element is not directly injected into the Fin, but the dielectric layer is covered on the top and sidewall of the Fin to block the doping element from directly entering the Fin and passing through The heat treatment after ion implantation forms a doping of Fin to control the doping amount of the top and sidewalls and protect Fin from direct bombardment of ions.

The present invention solves the above technical problems by the following technical solutions:

A FinFET doping method, the FinFET includes a substrate and a plurality of Fins disposed in parallel on the substrate, each Fin including a top surface, opposite first sidewalls and second sidewalls, characterized by The plurality of Fins includes a first Fin for forming an NFET and a second Fin for forming a PFET, and the doping method includes the following steps:

S1: forming a dielectric layer on a surface of the first Fin and a surface of the second Fin, the dielectric layer covering a top surface of the first Fin, a first sidewall and a second sidewall, and a top surface, the first side covering the second Fin a wall and a second side wall;

S2: forming a photoresist on the dielectric layer corresponding to the second Fin;

S3: performing N-type doping element implantation on the first Fin from the first sidewall side of the first Fin and the second sidewall side of the first Fin, respectively, and then removing the photoresist on the dielectric layer corresponding to the second Fin;

S4: forming a photoresist on the dielectric layer corresponding to the first Fin;

S5: performing P-type doping element implantation on the second Fin from the first sidewall side of the second Fin and the second sidewall side of the second Fin, respectively, and then removing the photoresist on the dielectric layer corresponding to the first Fin;

S6: heat treatment causes the N-type doping element to diffuse into the first Fin and be activated and cause the P-type doping element to diffuse into the second Fin and be activated,

Wherein the dielectric layer has a thickness of at least 1 nm, and the implantation energy of the N-type element and the P-type element is 2 keV or less.

Because of the three-dimensional structure of Fin, if the sidewall of Fin is doped, the direction of ion implantation will be at an angle to the top surface, so that the top surface will undergo two dopings, and each sidewall will be doped. Only one doping is experienced; in addition, as the degree of integration increases, the injection angle is relatively small, and the projected dose of the top surface will be much larger than the projected dose of the sidewall. In the technical solution of the present invention, due to the existence of the dielectric layer, the doping element does not directly bombard the Fin, and a part of the doping element stays in the dielectric layer, so that the doping element can be uniformly distributed after the heat treatment. Fin's top surface and two side walls.

The process steps of the present invention are significantly reduced compared to the IBM process. In the IBM process, due to the diffusion doping method, in order to form different doping types, for example, when forming an NFET, the PFET portion must be covered with a hard mask (because the photoresist is not resistant to diffusion doping). The high temperature required, so only a hard mask of silicon oxide or silicon nitride can be used. When forming a PFET, the portion of the NFET must also be covered with a hard mask to protect the NFET that has been doped. However, the steps of forming a hard mask and removing the hard mask itself are very complicated, which increases the difficulty of the entire process. Degree and uncertainty. Comparing the steps of the present invention, it can be seen that the present invention at least omits the step of forming a hard mask and removing the hard mask at a time; and further, because ion implantation is used as a doping means, even a photoresist which is not resistant to high temperature can be used as The mask blocks areas that do not need to be implanted.

Preferably, the implanting of each doping element comprises the steps of: doping element implantation on a dielectric layer covering the first sidewall and the top surface of the Fin at a first implantation angle, the first implantation angle being an injection direction and The angle formed by the normal of the top surface;

Doping the dielectric layer covering the second sidewall and the top surface of the Fin at a second implantation angle, the second implantation angle being an angle between the injection direction and the normal of the top surface.

The first injection angle and/or the second injection angle is greater than 0° and less than or equal to 45°.

Preferably, the thickness of the dielectric layer overlying the top surface is greater than the thickness of the dielectric layer overlying the first and second sidewalls.

Preferably, the implantation energy of the doping element in step S3 or step S5 is 1 keV or less, and preferably, the implantation energy of the doping element in step S3 or step S5 is 800 eV or less.

Preferably, the dose of the implanted doping element is at least 3e15/cm ² , preferably, the dose of the implanted doping element is 1e16-1e17/cm ² .

Preferably, the dielectric layer has a thickness of from 1 nm to 10 nm. Preferably, the dielectric layer covering the top surface has a thickness of 3 nm to 5 nm, and the dielectric layer covering the sidewall has a thickness of 2 nm to 3 nm.

Preferably, the dielectric layer is a nitride or an oxide or a carbide, preferably the dielectric layer is silicon nitride or silicon dioxide or aluminum oxide.

Preferably, the heat treatment in step S6 is performed by RTA (rapid thermal annealing), and/or the heat treatment temperature in step S6 is 950 ° C - 1200 ° C.

The present invention also provides a method of doping a FinFET, the FinFET comprising a substrate and Fin disposed in parallel on the substrate, each Fin comprising a top surface, an opposite first sidewall and a second sidewall, wherein the FinFET is characterized in that The doping method comprises the following steps:

S1: forming a dielectric layer on a surface of each Fin, the dielectric layer covering a top surface, a first sidewall and a second sidewall of the Fin;

S2: implanting a doping element into the Fin from the first sidewall side at a first implantation angle, where The first injection angle is an angle formed by the injection direction and the normal of the top surface;

S3: implanting a doping element into the Fin from the second sidewall side at a second implantation angle, where the second implantation angle is an angle between the injection direction and a normal of the top surface;

S4: heat treatment causes the doping element to diffuse into the Fin and be activated,

The dielectric layer has a thickness of at least 1 nm, and the implantation energy of the doping element is 2 keV or less.

In addition to optimizing the doping uniformity of Fin and improving the degree of amorphization, the present invention can use a combination of an ion implantation process and a dielectric layer to block a region that does not need to be doped, and omits at least one conventional diffusion process. A step of forming a hard mask and removing the hard mask.

Preferably, the first injection angle and/or the second injection angle is greater than 0° and less than or equal to 45°.

Preferably, the implantation energy of the doping element in step S2 or step S3 is 1 keV or less, and preferably, the implantation energy of the doping element in step S2 or step S3 is 800 eV or less.

Preferably, the heat treatment in step S4 employs RTA, and/or the heat treatment temperature in step S4 is 950 ° C - 1200 ° C.

S2: performing plasma doping on Fin;

S3: heat treatment causes the doping element to diffuse into the Fin and be activated,

Wherein the dielectric layer has a thickness of at least 1 nm.

Preferably, the dielectric layer is a nitride or oxide or carbide of the dielectric layer, preferably the dielectric layer is silicon nitride or silicon dioxide or aluminum oxide.

Preferably, the heat treatment in step S3 employs RTA, and/or the heat treatment temperature in step S3 is 950 ° C - 1200 ° C. .

Based on the common knowledge in the art, the above various preferred conditions can be arbitrarily combined to obtain preferred embodiments of the present invention.

The positive effects of the present invention are:

1. In the doping method of the present invention, the doping element is not directly injected into the Fin, but a lower energy implantation is used, and a different selection of the thickness of the dielectric layer can be achieved: a part of the doping element stays in the dielectric In the layer, another part of the doping element enters the Fin, and the top surface and the sidewall of the Fin actually after the heat treatment are uniformly distributed, thereby improving the doping uniformity of the top surface and the sidewall of the Fin.

2. In the scheme of ion implantation, since Fin is not directly bombarded, it will not cause great damage to Fin, so that the seed layer can be well preserved in Fin, which effectively alleviates the problem of Fin amorphization.

3. The combination of doping the dielectric layer and thermal diffusion eliminates the step of forming the hard mask at least once and removing the hard mask at least once. The photoresist can be used to cover the portion that is not doped, simplifying the overall process.

DRAWINGS

FIG. 1 is a schematic structural view of Fin when undoped in Embodiment 1 of the present invention.

2 is a schematic view showing the formation of a dielectric layer in Embodiment 1 of the present invention.

3 is a schematic view showing that a PFET is blocked by a photoresist in Embodiment 1 of the present invention.

4 is a schematic view showing the injection of an N-type element from the first sidewall side in Embodiment 1 of the present invention.

Fig. 5 is a schematic view showing the injection of an N-type element from the side of the second side wall in the first embodiment of the present invention.

FIG. 6 is a schematic view showing the NFET blocked by the photoresist in Embodiment 1 of the present invention.

Fig. 7 is a schematic view showing the injection of a P-type element from the side of the first side wall in the first embodiment of the present invention.

Figure 8 is a schematic view showing the injection of a P-type element from the second sidewall side in Embodiment 1 of the present invention.

FIG. 9 is a schematic view showing formation of an N-type doped region and a P-type doped region in Embodiment 1 of the present invention.

FIG. 10 is a schematic structural view of Fin after removing a dielectric layer in Embodiment 1 of the present invention.

Figure 11 is a schematic view showing the structure of Fin when undoped in Example 2 of the present invention.

Figure 12 is a schematic view showing the formation of a dielectric layer in Embodiment 2 of the present invention.

Figure 13 is a schematic view showing the implantation of a doping element from the first sidewall side in Embodiment 2 of the present invention.

Figure 14 is a schematic view showing the implantation of a doping element from the second sidewall side in Embodiment 2 of the present invention.

Figure 15 is a schematic view showing the formation of a doped region in Embodiment 2 of the present invention.

FIG. 16 is a schematic structural view of Fin after removing a dielectric layer in Embodiment 2 of the present invention.

Fig. 17 is a simulation diagram showing the distribution of boron element implantation in Fin covering a 5 nm dielectric layer.

Fig. 18 is a simulation diagram showing the distribution of boron element implantation in Fin covering a 3 nm dielectric layer.

detailed description

The invention is further illustrated by the following examples, which are not intended to limit the invention. The experimental methods in the following examples which do not specify the specific conditions are selected according to conventional methods and conditions, or according to the product specifications.

Example 1

Referring to FIGS. 1 to 10, the FinFET includes a substrate 1 and a plurality of Fins disposed in parallel on the substrate. In this embodiment, two Fins are shown, each of which includes a top surface, an opposite first sidewall, and a first Two sidewalls, the plurality of Fins including a first Fin 21 for forming an NFET and a second Fin 22 for forming a PFET, the doping method comprising the steps of:

Referring to FIG. 2, a dielectric layer, such as silicon nitride, is first formed on the surface of Fin, the silicon nitride covers the top surface and both sidewalls of all Fins, and the silicon nitride covering the top surface is indicated by 31, covering the sidewalls. The silicon nitride is represented by 32, and the thickness of the silicon nitride on the top surface (for example, 5 nm) is larger than the thickness of the silicon nitride (2 nm) on the sidewall.

Referring to Figure 3, the second Fin is protected with photoresist 4. Referring to FIG. 4, an N-type element is implanted from the first sidewall side (for example, the right side) of the first Fin, the implantation direction is 10° from the first Fin top normal, and the implantation energy is 500 eV. Due to the protection of the photoresist 4, the second Fin is not affected. Next, referring to FIG. 5, an N-type element is implanted from the second sidewall side (for example, the left side) of the first Fin, and the angle of the injection direction to the first Fin top normal is also 10°, and the implantation energy is 500 eV. Since the implantation energy is low, a part of the N-type element stays in the silicon nitride, and only another part of the N-type element is injected into the first Fin. The photoresist overlying the second Fin is then removed.

Referring to Figure 6, a photoresist (also denoted by reference numeral 4) is overlaid on the silicon nitride on the first Fin to protect the structure that has been implanted. Referring to FIGS. 7-8, P-type elements are implanted from the right side and the left side, respectively, with an implantation angle of 10° and an implantation energy of 300 eV. Such a portion of the P-type element stays in the silicon nitride overlying the second Fin, and another portion of the P-type element is implanted in the second Fin.

Referring to FIG. 9, after the photoresist 4 is removed, the structure shown in FIG. 9 is heat-treated, so that the N-type element and the P-type element in the silicon nitride enter the first Fin and the second Fin, respectively, and are activated, and additionally injected into Doping elements in the first Fin and the second Fin are also activated. Referring to Figure 10, the silicon nitride is subsequently removed.

In the present embodiment, the doping of the NFET and the PFET can be completed by forming only one dielectric layer and removing the primary dielectric layer, and the steps are greatly reduced compared to the IBM process, and the process is greatly simplified.

Furthermore, due to the three-dimensional structure of Fin, the injection must be at an angle to the top surface. In order to ensure that the two sidewalls of Fin are doped, the top surface of Fin must be implanted twice. The injection angle is relatively small, and the projection dose of the top surface is much larger than the projection dose of the side surface, which is the fundamental reason why the doping uniformity of Fin is very poor. In this embodiment, the doping element is not directly implanted into the Fin, but the dielectric layer is first formed and then injected and combined with the heat treatment to diffuse the doping element to the Fin. In this way, the doping difference between the top surface and the sidewall of the Fin after the heat treatment is greatly reduced.

Moreover, just because the doping element does not directly bombard Fin, but directly bombards the dielectric layer, the seed layer is well preserved in Fin, thereby alleviating the problem of amorphization.

Example 2

Referring to Figures 11-16, the FinFET includes a substrate 100 and Fin 200 disposed in parallel spaced apart on the substrate, each Fin including a top surface 201, opposing first and second sidewalls (where the sidewalls are each indicated at 202) The doping method comprises the following steps:

Referring to FIG. 12, a dielectric layer is formed on the surface of each Fin, the dielectric layer covering the top surface of the Fin, the first sidewall and the second sidewall, and the substrate between adjacent Fins, which is covered by 300a in FIG. The top dielectric layer, 300b, represents the dielectric layer overlying the first sidewall and the second sidewall. The dielectric layer has a thickness of at least 2 nm.

Referring to FIG. 13, the first sidewall (for example, the right side) and the top surface of Fin are implanted with a doping element at a first implantation angle, and the first implantation angle is an angle between the injection direction and the normal of the top surface. ;

With continued reference to FIG. 14, the second sidewall (left side) and the top surface of Fin are implanted with a doping element at a second implantation angle, which is an angle between the injection direction and the normal of the top surface. In the present embodiment, the injection angle is 10°. Wherein, the implantation energy of the doping element is 500 eV or less, such that a part of the doping element stays in the dielectric layer and the other part enters the Fin.

Referring to Fig. 15, heat treatment of the structure obtained in Fig. 14 causes the doping element implanted into the dielectric layer to enter Fin and be activated, and the doping element injected into Fin is also activated, thereby being on the top of Fin and Fin Doped regions are formed on both sidewalls, denoted by 41 and 42, respectively. The dielectric layer is then removed. Referring to Figure 16, the doped structure of Fin is obtained, and the doping of the top and sidewalls of Fin is completed.

Since there is no direct bombardment of Fin and a part of the doping element remains in the dielectric layer after ion implantation, the problem of Fin amorphization is greatly alleviated. Furthermore, the doped regions of the top and sidewalls of Fin are obtained by the diffusion of heat treatment, so the doping region obtained by the doping method of the present invention is relatively uniform compared to the direct ion implantation of Fin. .

Example 3

The basic principle of Embodiment 3 is the same as that of Embodiment 1, except that:

The thickness of the dielectric layer covering the top surface is greater than the thickness of the dielectric covering the first sidewall and the second sidewall. For example, the dielectric layer covering the top surface of the Fin has a thickness of 5 nm and covers both sidewalls of the Fin. The dielectric layer has a thickness of 3 nm.

Simulation experiment

Simulation of ion implantation into the dielectric layer

Referring to Figure 17 and Figure 18, 300eV boron ion implantation is used as an example (simulated by the simulation software TRIM), using silicon nitride and silicon dioxide as dielectric layers, respectively, and the injection angle is still 10° (ie for the top surface of Fin) For example, the angle between the injection direction and the top normal is 10°; for the sidewall of Fin, the angle between the injection direction and the sidewall normal is 80°, respectively, and the dielectric layer thickness is 5 nm ( The results are shown in Fig. 17) and the case where the dielectric layer was 3 nm (see Fig. 18 for the results). Wherein, the abscissa indicates the injection depth (in nm), and the ordinate indicates the atomic concentration (unit cm ^-3 )

In the case where the dielectric layer is 5 nm, for the top surface, silicon nitride is used in the case where the atomic concentration of boron in the final silicon nitride is 2.8e16/cm ³ and the atomic concentration in the Si is 1.7e13/cm. ³ . In the case of using silica, the atomic concentration in the silica was 2.7 e16/cm ³ and the atomic concentration in the Si was 1.1e15/cm ³ .

In the case where the dielectric layer is 3 nm, for the top surface, silicon nitride is used: the atomic concentration of boron in the final silicon nitride is 2.5e15/cm ³ , and the atomic concentration into the Si is 1.3e13/cm. ³ . In the case of using silica, the atomic concentration in the silica was 2.3e15/cm ³ and the atomic concentration in the Si was 1.6e14/cm ³ .

In order to clearly show the Fin and the dielectric layer and the doped regions, the dimensions of the various portions described above are not to scale, and those skilled in the art will understand that the proportions in the drawings are not limiting of the invention.

While the invention has been described with respect to the preferred embodiments of the present invention, it is understood that the scope of the invention is defined by the appended claims. Ben A person skilled in the art can make various changes or modifications to the embodiments without departing from the spirit and scope of the invention, and such changes and modifications fall within the scope of the invention.

Claims

A FinFET doping method, the FinFET comprising a substrate and a plurality of Fins disposed in parallel on the substrate, each Fin including a top surface, opposite first sidewalls and second sidewalls, wherein The plurality of Fins includes a first Fin for forming an NFET and a second Fin for forming a PFET, and the doping method includes the following steps:

S1: forming a dielectric layer on a surface of the first Fin and a surface of the second Fin, the dielectric layer covering a top surface of the first Fin, a first sidewall and a second sidewall, and a top surface, the first side covering the second Fin a wall and a second side wall;

S2: forming a photoresist on the dielectric layer corresponding to the second Fin;

S3: performing N-type doping element implantation on the first Fin from the first sidewall side of the first Fin and the second sidewall side of the first Fin, respectively, to remove the photoresist on the dielectric layer corresponding to the second Fin;

S4: forming a photoresist on the dielectric layer corresponding to the first Fin;

S5: performing P-type doping element implantation on the second Fin from the first sidewall side of the second Fin and the second sidewall side of the second Fin, respectively, to remove the photoresist on the dielectric layer corresponding to the first Fin;

S6: heat treatment causes the N-type doping element to diffuse into the first Fin and be activated and cause the P-type doping element to diffuse into the second Fin and be activated,

Wherein the dielectric layer has a thickness of at least 1 nm, and the implantation energy of the N-type element and the P-type element is 2 keV or less.
The method of doping a FinFET according to claim 1, wherein the implanting of each doping element comprises the step of: covering the dielectric layer covering the first sidewall and the top surface of the Fin at a first implantation angle. Doping element implantation, the first injection angle is an angle between the injection direction and the normal of the top surface;

Doping the dielectric layer covering the second sidewall and the top surface of the Fin at a second implantation angle, the second implantation angle being an angle between the injection direction and the normal of the top surface.

The first injection angle and/or the second injection angle is greater than 0° and less than or equal to 45°.
The method of doping a FinFET according to claim 1, wherein the thickness of the dielectric layer covering the top surface is greater than the thickness of the dielectric layer overlying the first sidewall and the second sidewall.
The method of doping a FinFET according to claim 1, wherein the implantation energy of the doping element in step S3 or step S5 is 1 keV or less, preferably, the implantation energy of the doping element in step S3 or step S5 is 800 eV. the following.
A method of doping a FinFET according to claim 1, wherein the dose of the implanted doping element is at least 3e15/cm 2 , and preferably, the dose of the implanted doping element is 1e16-1e17/cm 2 .
The method of doping a FinFET according to claim 1, wherein the dielectric layer has a thickness of from 1 nm to 10 nm.
The method of doping a FinFET according to claim 1, wherein the dielectric layer is a nitride or an oxide or a carbide, and preferably the dielectric layer is silicon nitride or silicon dioxide or aluminum oxide.
The method of doping a FinFET according to claim 1, wherein the heat treatment in step S6 is performed by using RTA, and/or the heat treatment temperature in step S6 is from 950 ° C to 1200 ° C.
A FinFET doping method, the FinFET comprising a substrate and Fin disposed in parallel on the substrate, each Fin comprising a top surface, an opposite first sidewall and a second sidewall, characterized in that the doping The method includes the following steps:

S1: forming a dielectric layer on a surface of each Fin, the dielectric layer covering a top surface, a first sidewall and a second sidewall of the Fin;

S2: implanting a doping element from the first sidewall side to the Fin at a first implantation angle, where the first implantation angle is an angle between the injection direction and a normal of the top surface;

S3: implanting a doping element into the Fin from the second sidewall side at a second implantation angle, where the second implantation angle is an angle between the injection direction and a normal of the top surface;

S4: heat treatment causes the doping element to diffuse into the Fin and be activated,

The dielectric layer has a thickness of at least 1 nm, and the implantation energy of the doping element is 2 keV or less.
The method of doping a FinFET according to claim 9, wherein the first implantation angle and/or the second implantation angle is greater than 0° and less than or equal to 45°.
A method of doping a FinFET according to claim 9, wherein the method is covered The thickness of the dielectric layer of the face is greater than the thickness of the dielectric layer overlying the first and second sidewalls.
The method of doping a FinFET according to claim 9, wherein the implantation energy of the doping element in step S2 or step S3 is 1 keV or less, preferably, the implantation energy of the doping element in step S2 or step S3 is 800 eV. the following.
A method of doping a FinFET according to claim 9, wherein the dose of the implanted doping element is at least 3e15/cm 2 , and preferably, the dose of the implanted doping element is 1e16-1e17/cm 2 .
The method of doping a FinFET according to claim 9, wherein the dielectric layer has a thickness of from 1 nm to 10 nm.
The method of doping a FinFET according to claim 9, wherein the dielectric layer is a nitride or an oxide or a carbide, and preferably the dielectric layer is silicon nitride or silicon dioxide or aluminum oxide.
The method of doping a FinFET according to claim 9, wherein the heat treatment in step S4 is performed by using RTA, and/or the heat treatment temperature in step S4 is from 950 ° C to 1200 ° C.
A FinFET doping method, the FinFET comprising a substrate and Fin disposed in parallel on the substrate, each Fin comprising a top surface, an opposite first sidewall and a second sidewall, characterized in that the doping The method includes the following steps:

S1: forming a dielectric layer on a surface of each Fin, the dielectric layer covering a top surface, a first sidewall and a second sidewall of the Fin;

S2: performing plasma doping on Fin;

S3: heat treatment causes the doping element to diffuse into the Fin and be activated,

Wherein the dielectric layer has a thickness of at least 1 nm.
The method of doping a FinFET according to claim 17, wherein the thickness of the dielectric layer covering the top surface is greater than the thickness of the dielectric layer overlying the first sidewall and the second sidewall.
The method of doping a FinFET according to claim 17, wherein the dielectric layer has a thickness of from 1 nm to 10 nm.
A method of doping a FinFET according to claim 17, wherein the dielectric The layer is such that the dielectric layer is a nitride or an oxide or a carbide, preferably the dielectric layer is silicon nitride or silicon dioxide or aluminum oxide.
The method of doping a FinFET according to claim 17, wherein the heat treatment in step S3 is performed by using RTA, and/or the heat treatment temperature in step S3 is from 950 ° C to 1200 ° C.