WO2017111803A1 - Techniques permettant de former des éléments électro-conducteurs à alignement et réduction de capacité améliorés - Google Patents

Techniques permettant de former des éléments électro-conducteurs à alignement et réduction de capacité améliorés Download PDF

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Publication number
WO2017111803A1
WO2017111803A1 PCT/US2015/000341 US2015000341W WO2017111803A1 WO 2017111803 A1 WO2017111803 A1 WO 2017111803A1 US 2015000341 W US2015000341 W US 2015000341W WO 2017111803 A1 WO2017111803 A1 WO 2017111803A1
Authority
WO
WIPO (PCT)
Prior art keywords
hardmask
electrically conductive
layer
barrier layer
conductive features
Prior art date
Application number
PCT/US2015/000341
Other languages
English (en)
Inventor
Kevin Lin
Richard E. SCHENKER
Manish Chandhok
Jefferey BIELEFELD
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/000341 priority Critical patent/WO2017111803A1/fr
Priority to TW105138462A priority patent/TW201735303A/zh
Publication of WO2017111803A1 publication Critical patent/WO2017111803A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

Definitions

  • Figure 10 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.
  • Figure 19 illustrates a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.
  • Figures 20-28 illustrate a process flow of fabricating an IC in accordance with another embodiment of the present disclosure.
  • dielectric layer 104 may be formed from a nitride, such as silicon nitride (Si 3 N 4 ), or an oxynitride, such as silicon oxynitride (SiON), a carbide, such as silicon carbide (SiC), or an oxycarbonitride, such as silicon oxycarbonitride (SiOCN).
  • dielectric layer 104 may be formed from a combination of any of the aforementioned materials.
  • dielectric layer 104 may have a thickness, for example, in the range of about 50-150 nm (e.g., about 50-100 nm, about 100— 150 nm, or any other sub-range in the range of about 50-150 nm).
  • a thickness for example, in the range of about 50-150 nm (e.g., about 50-100 nm, about 100— 150 nm, or any other sub-range in the range of about 50-150 nm).
  • Other suitable materials, formation techniques, and configurations for dielectric layer 104 will depend on a given application and will be apparent in light of this disclosure.
  • dielectric layer 104 may be formed as a multi-layer structure (e.g., bi-layer, tri-layer, or other quantity of constituent layers), wherein the constituent layers are of different material composition, at least one of which is configured to serve as an etch stop layer.
  • a multi-layer structure e.g., bi-layer, tri-layer, or other quantity of constituent layers
  • the constituent layers are of different material composition, at least one of which is configured to serve as an etch stop layer.
  • a given hardmask body may be configured as a generally helmet-like (or otherwise cap-like) portion disposed over the topography provided by underlying portion(s) of barrier layer 108 and conductive feature(s) 106.
  • a given constituent hardmask body of hardmask layer 1 10 may be of generally rectangular or square cross-sectional geometry.
  • a given constituent hardmask body of hardmask layer 1 10 may be of generally trapezoidal cross- sectional geometry.
  • a given constituent hardmask body of hardmask layer 1 10 may have one or more curvilinear surfaces (top, sidewalls, or other).
  • a given constituent hardmask body of hardmask layer 1 10 may have angled or tapered sidewalls, whereas in some other instances, a given constituent hardmask body of hardmask layer 1 10 may have substantially straight, vertical sidewalls.
  • IC 102 after recessing conductive features 106 as in Figure 8, IC 102 optionally may undergo one or more additional fabrication processes.
  • Figure 9 which illustrates a cross-sectional view of an IC 102 after forming a hardmask layer 1 16, in accordance with an embodiment of the present disclosure.
  • hardmask layer 1 16 may be formed within any one or more desired features 1 14a and 1 14b, over conductive features 106, in accordance with some embodiments.
  • hardmask layer 1 16 may be formed with any of the example materials, techniques, and configurations discussed above, for instance, with respect to hardmask layer 1 10, in accordance with some embodiments.
  • hardmask layer 1 16 and hardmask layer 1 10 may differ in material composition, providing for etch selectivity with respect to one another.
  • dielectric layer 1 18 may be patterned with one or more features 1 18a, the dimensions and geometry of which may be customized, as desired for a given target application or end-use.
  • a given feature 1 18a may be formed so as to land, at least in part, over a portion of hardmask layer 1 16 and underlying conductive feature 106.
  • a portion of the underlying hardmask layer 1 16 may be selectively removed (e.g., selectively etched away), exposing the underlying conductive feature 106 hosted, for instance, by a feature 1 14b.
  • hardmask layer 1 10 e.g., one or more hardmask bodies, discussed above
  • hardmask layer 1 10 may be disposed over and in direct contact with the top surfaces of conductive features 106, as well as the ends of portions of barrier layer 108 alongside conductive features 106, in accordance with an embodiment. Compare this with the hardmask layer 1 10 in Figure 4, discussed above, which instead resides over and in direct contact with portions of barrier layer 108 conformal to the top surfaces of conductive features 106, in accordance with an embodiment.
  • barrier layer 1 12 may be disposed over portions of barrier layer 108 and hardmask layer 1 10, along sidewalls of conductive features 106.
  • it may be desirable to remove portions that deposit over hardmask layer 1 10, to ensure that the upper surfaces of the constituent hardmask bodies of hardmask layer 1 10 remain exposed. Also, it may be desirable to remove portions of barrier layer 1 12 that deposit over portions of barrier layer 108 between neighboring conductive features 106.
  • IC 105 after filling all (or some sub-set) of features 1 14a, IC 105 optionally may undergo a recessing process in which conductive feature(s) 106 are recessed to below the height of barrier layer 1 12 and hardmask layer 1 10.
  • a recessing process in which conductive feature(s) 106 are recessed to below the height of barrier layer 1 12 and hardmask layer 1 10.
  • Figure 25 illustrates a cross-sectional view of an IC 105 configured in accordance with an embodiment of the present disclosure. Recessing of conductive feature(s) 106 may be performed via any suitable standard, custom, or proprietary etch-and-clean technique(s), as will be apparent in light of this disclosure.
  • hardmask layer 1 10 e.g., the helmet-like hardmask bodies
  • hardmask layer 1 16 may exhibit etch selectivity, in accordance with some embodiments.
  • the communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 1000 may include a plurality of communication chips 1006.
  • Example 3 includes the subject matter of Example 2, wherein a pitch of the first and second electrically conductive features is about one-half of a pitch of the first and third electrically conductive features.
  • Example 7 includes the subject matter of Example 2 and further includes a second hardmask layer disposed over a top surface of the third electrically conductive feature, wherein the first and second hardmask layers are physically separated by the second barrier layer.
  • Example 8 includes the subject matter of Example 7, wherein the first and second hardmask layers are of different material composition, such that they exhibit etch selectivity with respect to one another.
  • Example 17 includes the subject matter of any of Examples 16 and 18-30, wherein forming the first hardmask layer involves at least one of a physical vapor deposition (PVD) process and a chemical vapor deposition (CVD) process.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • Example 18 includes the subject matter of any of Examples 16-17 and 19-30 and further includes forming a third electrically conductive feature over the substrate, between the first and second electrically conductive features.
  • Example 28 includes the subject matter of any of Examples 16-27 and 29-30, wherein at least one of the first and second hardmask bodies is configured to prevent electrical leakage therethrough.
  • Example 30 includes the subject matter of any of Examples 16-29, wherein the substrate is configured as at least one of a bulk semiconductor substrate, a semiconductor-on-insulator structure, a semiconductor wafer, and a multi-layered structure.
  • Example 37 includes the subject matter of Example 36, wherein at least one constituent electrically conductive feature of at least one of the first plurality and the second plurality extends into the dielectric layer.
  • Example 38 includes the subject matter of any of Examples 31-37 and 39 ⁇ 43, wherein the first barrier layer is further disposed between the at least one constituent electrically conductive feature of the first plurality and the at least one hardmask body of the first hardmask layer disposed there over.
  • Example 39 includes the subject matter of any of Examples 31-38 and 40—43, wherein: the first hardmask layer includes at least one of titanium nitride (TiN), silicon nitride (Si 3 N 4 ), silicon dioxide (S1O 2 ), silicon carbonitride (SiCN), and silicon oxynitride (SiO x N y ); and the at least one hardmask body of the first hardmask layer has a thickness in the range of about 5- 20 nm.
  • TiN titanium nitride
  • Si 3 N 4 silicon dioxide
  • SiCN silicon carbonitride
  • SiO x N y silicon oxynitride

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne des techniques permettant de former des éléments électro-conducteurs à alignement et réduction de capacité améliorés. Selon certains modes de réalisation, des éléments conducteurs individuels peuvent être formés sur un substrat semi-conducteur par un procédé soustractif (par exemple, par formation soustractive de motifs). Pour un élément donné, des première et seconde couches barrières (conformes ou non) peuvent être disposées le long des parois latérales de celui-ci, et un corps de masque dur en forme de casque peut être disposé sur une surface supérieure de celui-ci. Des éléments conducteurs supplémentaires peuvent être formées entre des éléments existants, en utilisant les couches barrières comme espaceurs d'alignement, pour ainsi réduire de moitié (ou réduire autrement) le pas de l'élément. Une couche d'un autre matériau de masque dur peut être disposée sur les éléments supplémentaires formés. Cette couche et les corps de masque dur en forme de casque peuvent avoir des compositions de matériau différentes, pour permettre une sélectivité pour l'un ou l'autre au moment de la gravure. La ou les couches supplémentaires peuvent être formées sur la topographie résultante, en exploitant la sélectivité de gravure des masques durs lors de la formation d'interconnexions pour des couches adjacentes de circuit intégré.
PCT/US2015/000341 2015-12-24 2015-12-24 Techniques permettant de former des éléments électro-conducteurs à alignement et réduction de capacité améliorés WO2017111803A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2015/000341 WO2017111803A1 (fr) 2015-12-24 2015-12-24 Techniques permettant de former des éléments électro-conducteurs à alignement et réduction de capacité améliorés
TW105138462A TW201735303A (zh) 2015-12-24 2016-11-23 用於形成具有改善的調正及電容降低之導電特徵的技術

Applications Claiming Priority (1)

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PCT/US2015/000341 WO2017111803A1 (fr) 2015-12-24 2015-12-24 Techniques permettant de former des éléments électro-conducteurs à alignement et réduction de capacité améliorés

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809002A (zh) * 2021-09-13 2021-12-17 长江存储科技有限责任公司 半导体器件及其制作方法
US11398545B2 (en) 2018-06-25 2022-07-26 Intel Corporation Single-mask, high-q performance metal-insulator-metal capacitor (MIMCAP)
EP4145498A1 (fr) * 2021-09-07 2023-03-08 Imec VZW Structure d'interconnexion étagé

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI755722B (zh) * 2020-05-05 2022-02-21 力晶積成電子製造股份有限公司 半導體結構及其製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077627A1 (en) * 2003-10-10 2005-04-14 Chen-Hua Yu Copper wiring with high temperature superconductor (HTS) layer
US20060234497A1 (en) * 2005-04-15 2006-10-19 Chih-Chao Yang Interconnect structure and method of fabrication of same
US20090017616A1 (en) * 2007-07-10 2009-01-15 Stephan Grunow Method for forming conductive structures
US20130043556A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
US20150263131A1 (en) * 2014-03-11 2015-09-17 Tokyo Electron Limited Method of Forming Self-Aligned Contacts Using a Replacement Metal Gate Process in a Semiconductor Device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077627A1 (en) * 2003-10-10 2005-04-14 Chen-Hua Yu Copper wiring with high temperature superconductor (HTS) layer
US20060234497A1 (en) * 2005-04-15 2006-10-19 Chih-Chao Yang Interconnect structure and method of fabrication of same
US20090017616A1 (en) * 2007-07-10 2009-01-15 Stephan Grunow Method for forming conductive structures
US20130043556A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
US20150263131A1 (en) * 2014-03-11 2015-09-17 Tokyo Electron Limited Method of Forming Self-Aligned Contacts Using a Replacement Metal Gate Process in a Semiconductor Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11398545B2 (en) 2018-06-25 2022-07-26 Intel Corporation Single-mask, high-q performance metal-insulator-metal capacitor (MIMCAP)
EP4145498A1 (fr) * 2021-09-07 2023-03-08 Imec VZW Structure d'interconnexion étagé
CN113809002A (zh) * 2021-09-13 2021-12-17 长江存储科技有限责任公司 半导体器件及其制作方法

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