WO2017111801A1 - Techniques d'intégration de diodes électroluminescentes pour systèmes de matériaux iii-v - Google Patents

Techniques d'intégration de diodes électroluminescentes pour systèmes de matériaux iii-v Download PDF

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Publication number
WO2017111801A1
WO2017111801A1 PCT/US2015/000332 US2015000332W WO2017111801A1 WO 2017111801 A1 WO2017111801 A1 WO 2017111801A1 US 2015000332 W US2015000332 W US 2015000332W WO 2017111801 A1 WO2017111801 A1 WO 2017111801A1
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led
substrate
core
layer
trench
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PCT/US2015/000332
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English (en)
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Sansaptak DASGUPTA
Peter Chang
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Intel Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256

Definitions

  • LEDs Light emitting diodes
  • LEDs are used for any of a variety of lighting applications, from automobile headlights to household lighting to computer displays (whether for mobile or stationary computing devices).
  • Advantages of LEDs, whether used for illumination or display technology include high reliability, relatively high energy efficiency (compared to, for example, thermal or fluorescent lighting technologies), and mechanical durability.
  • Most LEDs, typically approximately from 0.5 millimeter (mm) to approximately 1 mm in size, are fabricated by placing an n-doped semiconductor and a p-doped semiconductor in intimate contact, thus forming a p-n junction.
  • holes from the p-doped semiconductor and electrons from the n-doped semiconductor migrate to a recombination region disposed about the interface at which the two semiconductors meet.
  • Photons are emitted upon recombination of the electrons and holes.
  • the color emitted by an LED is a function of the band gaps of the n-type semiconductor and the p-type semiconductor forming the p-n junction.
  • the color emitted by each LED can be tailored through material selection and/or manipulation of the band gap of the each material used.
  • FIG. 1A illustrates a cross-section view of an example LED capable of emitting
  • FIG. IB illustrates a cross-section view of an example LED capable of emitting either blue light or green light.
  • FIG. 2A illustrates a plan view of an LED system that includes an array of LEDs, CMOS LED driver circuits, and CMOS LED control circuits all of which are monolithically formed on a single substrate, in accordance with an embodiment of the present disclosure.
  • FIG. 2B illustrates a cross-section view of an LED pixel of FIG. 2A that includes a red- light emitting LED, a blue light emitting LED, and a green light emitting LED, in accordance with an embodiment of the present disclosure.
  • FIGS. 3A through 3C are perspective and cross-section views illustrating a method for forming an LED configured to emit red-light, in accordance with an embodiment of the present disclosure.
  • FIG. 3D is a schematic illustration of a device cross-section of an alternative architecture of a micro-LED configured to emit red-light, in accordance with an embodiment of the present disclosure.
  • FIG. 4A is a cross-section view of two LEDs, one of which is configured to emit blue light and one of which is configured to emit green light, in accordance with an embodiment of the present disclosure.
  • FIG. 4B illustrates LEDs in which each core is deposited as a nanowire, in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a method flow diagram illustrating a method for fabricating a monolithic LED integrated circuit configured to emit one of blue light or green light, in accordance with an embodiment of the present disclosure.
  • FIGS. 6A-D illustrate various aspects of integrating an LED array with a display panel, in accordance with an embodiment of the present disclosure.
  • FIG. 7 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure.
  • the LEDs can be further monolithically formed with CMOS control and driver circuitry on a common substrate.
  • the techniques are particularly useful for fabricating so-called "micro-LEDs" that are on the order of 100 nm to 10 microns in size.
  • the techniques can scale to smaller or larger size ranges as desired.
  • reference to micro- LEDs herein is not intended to limit the present disclosure to a particular size range or range of manufacturing nodes; rather, the monolithically formed LED integrated circuits can be any size suitable for a given application.
  • Some example embodiments include LED systems that use and/or control arrays of LEDs, such as high resolution displays.
  • the LEDs are fabricated in groups (or "pixels") that include one each of a red LED, a blue LED, and a green LED.
  • the individual LEDs are square or rectangular in shape. The size of each LED may vary from one embodiment to the next, but in some example cases support a pixel density in the range of approximately 50,000 to several hundred thousand pixels per square millimeter. This density enables high resolution displays. Because LED systems according to some embodiments provided herein include red, blue, and green LEDs, control circuits, and driver circuits, all monolithically fabricated on the same substrate, significant resolution improvements, reduced power consumption, and fabrication efficiencies are achieved.
  • Fabrication of LEDs is usually performed on a substrate with a crystal structure that is compatible with the crystal structure of the materials used for the p-n junction.
  • III- N type materials often used for blue and green LEDs are usually fabricated on a sapphire- structure (e.g., alumina) substrate because the hexagonal crystal III-N materials can be grown on the crystallographically compatible R-plane of the hexagonal sapphire crystal substrate.
  • Layers of a red-light emitting LED which are usually fabricated from materials with a cubic crystal structure, are often epitaxially grown on a cubic crystal of gallium arsenide (GaAs).
  • each LED configured to emit a different color of light is fabricated separately on a different substrate, and then these distinct substrates are combined through bonding techniques onto a single substrate.
  • red, blue, and green LEDs can be combined in a single device, or in a single pixel in a display, to produce a range of colored-light, including white light.
  • Red- light emitting LEDs such as the red-light emitting LED 100
  • GaAs substrates such as GaAs substrate 104.
  • GaAs gallium arsenide
  • GaAs is often selected as a substrate because its crystal structure is compatible with the crystal structures of the other layers used to fabricate the red-light emitting LED despite slight differences in lattice parameters.
  • An indium gallium phosphide (InGaP) buffer layer 108 can, in some examples, be disposed between the GaAs substrate 104 and the other layers of the red-light emitting LED because the InGaP lattice constants are between those of GaAs and the other layers of the LED. Thus, the InGaP layer provides a transition between lattice constants of adjacent layers, thereby reducing crystal defects caused by strain from mismatched lattice constants.
  • An n-doped semiconductor layer 1 12, such as aluminum indium phosphide (AllnP) doped with silicon (Si) is disposed on the InGaP layer 108 to contribute electrons to the recombination region of the p-n junction.
  • AlGalnP aluminum gallium indium phosphide
  • the AlGalnP layer 1 16 is configured as multiple layers of quantum wells, each of which is from approximately lnm to approximately 10 nm thick. These quantum wells confine charge carriers to nanoscale regions, which increases the rate of recombination. The quantum wells may also impose boundary conditions on the charge carrier waveforms, thus tailoring the emitted wavelength of light.
  • a p-doped semiconductor layer 120 such as aluminum indium phosphide (AllnP) doped with zinc is disposed on a p-side of the p-n junction (i.e., on a side of the active layer 1 16 opposite that of the n- doped layer 1 12) of the red LED 100.
  • the p-doped semiconductor layer 120 contributes holes to the active layer 1 16 that, when recombined with electrons, emits light.
  • a transparent p-type electrode 124 is disposed on the p-type layer 120 to provide good electrical contact with an externally applied voltage while permitting the light emitted by the active layer 1 16 to be visible.
  • FIG. IB illustrates an LED 130 configured to emit either blue or green light.
  • the hexagonal crystal structure of gallium nitride commonly used on a host for an n-type dopant in blue or green light-emitting LEDs, is grown on the crystallographically compatible R-plane of a hexagonal sapphire substrate 134.
  • a layer of an undoped buffer layer and undoped GaN 138 is deposited on the substrate 134 to reduce defects generated by lattice mismatch between layers.
  • On top of the buffer layer 138 is deposited an n-doped GaN layer 142.
  • This n-doped layer 142 contributes electrons to the recombination region 146.
  • the recombination layer 146 in this case is a plurality of quantum well layers approximately from 1 nanometer (nm) to approximately 10 nm thick that are deposited in a blanket layer so as to be disposed between the n-doped and p-doped layers. As explained above, the quantum well layers confine charge carriers to sub-regions within the recombination layer 146, thus improving emission efficiency of the LED.
  • a p-doped layer 150 such as magnesium doped GaN is deposited on top of the blanket layers of the recombination layer 146 to contribute holes to the recombination layer 146.
  • An n-type electrode 144 and a p-type electrode provide electrical contact to their respective layers so that a voltage can be applied to the LED 130.
  • the LEDs 100 and 130 can be bonded to a common substrate, to accommodate color mixing applications.
  • Control circuits and driver circuits embodied in separately fabricated complementary metal oxide semiconductor (CMOS) devices may be further connected to the LEDs via a motherboard or similar interconnection. Note that the resulting integrated circuit is not monolithic, in that multiple separately fabricated sub-circuits are employed and joined to a common substrate through a bonding process.
  • CMOS complementary metal oxide semiconductor
  • fabrication of high-density LED devices using LED architectures such as those shown in FIGS. 1 A and IB would generally be inoperable due to crystal defects (e.g., slip dislocations) created, in some cases, by differences in lattice constants of crystals of materials adjacent to one another within the LED.
  • crystal defects e.g., slip dislocations
  • Such crystal defects upon migrating to a recombination region of the LED, disrupt electron-hole recombination, and thus decrease light emission from the LED.
  • Disruption of electron-hole recombination is less problematic in LEDs which are on the order of 1 mm in size (or larger) because the area of the recombination region is large compared to the area affected by the dislocation.
  • any decrease in illumination efficiency from crystal defects for millimeter-scale LEDs may be negligible. But because the size of the interface in some of the embodiments of LEDs described below is much smaller than millimeter scale devices, the effect of dislocations on illumination efficiency is more pronounced.
  • LEDs are fabricated with III— V semiconductor material on group IV material semiconductor substrates so that crystal defects that would otherwise migrate to a recombination region of the p-n junction and inhibit carrier recombination (and therefore light emission) are trapped in areas of the LED away from the recombination region.
  • each LED is fabricated by first etching a trench through an insulation layer on a substrate. The trenches are configured so that a core of the LED traps defects at locations away from the recombination region of the p-n junction.
  • red LED structures are etched with a shape and aspect ratio that traps defects within the ⁇ 11 1 ⁇ planes at locations away from the recombination region in the red LED.
  • blue and green LEDs are also configured with respect to the crystallographic planes of trie material system used for blue and green LEDs.
  • some embodiments of the present disclosure include LEDs with a recombination region that is not merely planar, but which follows contours of a three dimensional device. This increases the surface area of each LED, thus improving the intensity of light produced per unit area.
  • each of a red, blue, and green LED monolithically formed and disposed on a common substrate may be detected.
  • Control circuits and driver circuits may also be formed and disposed on the same substrate as the red, blue, and green LEDs so as to provide an overall monolithic structure, and may also be detected.
  • Distinct material systems such as group IV semiconductor materials (e.g., silicon, germanium, and silicon germanium) implementing CMOS control and driver circuits, and III-V semiconductor materials (e.g., gallium nitride, indium nitride, and aluminum nitride, and alloys thereof) implementing LEDs of an array, may be further detectable in such analysis.
  • group IV semiconductor materials e.g., silicon, germanium, and silicon germanium
  • III-V semiconductor materials e.g., gallium nitride, indium nitride, and aluminum nitride, and alloys thereof
  • the common substrate upon which these distinct materials systems are provisioned is a silicon-containing substrate (e.g., bulk silicon or silicon-on- insulator).
  • the configuration of the LED cores and their disposition within a trench tailored to trap defects away from a corresponding p-n junction recombination region could also be detected.
  • inventions of the present disclosure include, for example, system on a chip (SoC) lighting devices that can be applied to any lighting application.
  • SoC system on a chip
  • some embodiments of the present disclosure can be applied to display technology for mobile computing devices, computer displays (mobile or stationary), televisions, household lighting, automotive lighting, industrial lighting, and others. Numerous configurations and variations will be apparent in light of this disclosure.
  • FIG. 2A illustrates plan-view of an LED system 200 configured according to an embodiment of the present disclosure.
  • the system 200 includes a substrate 202 and an MxN array of LED pixels 204 formed thereon, one of which is highlighted within a dotted box in FIG. 2A.
  • each pixel 204 includes a red-light emitting LED 208, a blue-light emitting LED 212, and a green-light emitting LED 216.
  • the system 200 also includes CMOS control circuits 220 and CMOS LED driver circuits 224, also formed on the substrate 202.
  • the MxN array of pixels along with the CMOS control circuits 220 and CMOS LED driver circuits 224, is, in this embodiment a monolithic structure formed on a common substrate 202.
  • the LEDs 208, 212, and 216 (and the pixels 204 formed by the LEDs 208, 212, and 216) can be controlled to produce white light as well as any mixture of red, blue, and green lights.
  • the substrate 202 is a bulk silicon substrate.
  • the silicon substrate can have (100), (1 10) or (1 1 1) orientation and may have offcut ranging from 0-10 deg. Because silicon is used as the substrate 202 in this example embodiment, the CMOS control circuits 220 and CMOS LED driver circuits 224 may be readily fabricated thereon by way of standard processing.
  • substrate 202 may be a multilayer structure, such as a silicon layer on an insulation layer.
  • the array of pixels 204 is also fabricated on substrate 202. However, because the pixels 204 are implemented with a III-V material system, the lattice mismatch between the silicon substrate 202 and the pixels 204 has to be taken into consideration.
  • substrate 202 can be any substrate suitable for growing thereon low defect density LED materials for each individual LED color desired, wherein lattice mismatch between the diverse material systems (e.g., group IV and III-V materials systems) is controlled with defect trapping mechanisms, as variously provided herein.
  • an isolation layer may be formed on the substrate 202, as will be discussed in turn with respect to 205 in Figure 2B.
  • dimensions of a pixel 204 are described by identifying a length of individual LEDs (dimension “a"), and identifying a sum (dimension "c") of the widths of each of the three LEDs (each of which corresponds to dimension "b") plus a spacing between the three LEDs (dimensions "d” and/or “e”).
  • the pixel 204 is roughly square, but it will be appreciated in light of this disclosure that the configuration of the pixels and the individual LEDs is not so limited.
  • each individual LED is 500 nm in an "a” dimension and 100 nm in a "b” dimension.
  • either or both of these dimensions can range, for instance, from approximately 100 nm to approximately 10 microns.
  • a spacing "d” and “e” between pixels in this example is approximately from 500 nm to approximately 1 micron in some embodiments, but can range from 100 nm to 10 microns in still other example embodiments.
  • Some embodiments of the present disclosure include a display that includes a pixel density from approximately 50,000 pixels to 57,000 pixels per square millimeter (mm ) for square pixels in which each LED is a square with each side approximately 100 nm long and a spacing between LEDs and between pixels of 1 micron. Still other embodiments may have a pixel density in the range of hundreds of thousands of pixels by, for example, reducing spacing between the LEDs (to 500nm or less) or reducing the LED size and spacing (to 50 nm or less). The integration techniques provided herein readily scale into such smaller dimensions. It will be appreciated that pixel density will vary in other embodiments as a function of the sizes and shapes of the LEDs and spacing between pixels.
  • the control logic circuits 220 determine the pixels and LEDs illuminated at any given time.
  • the control logic circuits 220 receive instructions (e.g., to display a still image, a moving image, an interactive user interface) regarding the image to display and converts the received instructions into a pattern of illuminated pixels.
  • the control logic circuits 220 also determine the mix of color and intensity of light to be emitted by each pixel 204.
  • the CMOS control circuits 220 are CMOS circuits fabricated using standard forming techniques, as normally done or otherwise desired.
  • CMOS circuitry 220 if pixels 204 are formed prior to the CMOS circuitry 220, then masking or passivation can be used to protect the pixel array during the CMOS forming processes. Likewise, that if the CMOS circuitry 220 is formed prior to pixels 204, then masking or passivation can be used to protect the CMOS circuitry 220 during the pixel array forming processes.
  • the LED driver circuits 224 also fabricated on the same substrate 202 on which the LEDs are fabricated, supply and regulate power to the various individual LEDs and corresponding pixels.
  • LED driver circuits 224 in operative communication with the control logic circuits 220 and the electrodes of the various pixels 204, facilitate the generation of charge carriers and their migration to the recombination region.
  • the CMOS LED driver circuits 224 can be fabricated using standard CMOS processing techniques as normally done, or otherwise desired. However, any formed portions of the pixel array can be protected with masking or passivation, as previously explained.
  • high temperature processing associated with forming the III-V material based pixels 204 is carried out prior to CMOS processing used to form the control circuits 220 and LED driver circuits 224.
  • FIG. 2B illustrates one example embodiment of a cross-section of an LED pixel 204 that includes a red-light emitting LED 208, a blue light emitting LED 212, and a green light emitting LED 216.
  • Each individual LED of this example embodiment includes a core (210, 214, 218) disposed through a shallow trench isolation (STI) layer 205 provided on the substrate 202.
  • Each individual LED also includes at least one recombination layer (219, 220, 222) and an outer layer (224, 226, 228).
  • STI shallow trench isolation
  • a high level description of the pixel architecture follows in the context of FIG. 2B, with a more detailed description of example LED compositions and configurations presented in the context of FIGS. 3A, 3B, 3C, 3D, 4A, and 4B.
  • the core 210, 214, 218 of each LED 208, 212, and 216 is a semiconductor doped with one of an n-type dopant or a p-type dopant.
  • each of the cores (210, 214, 218) shown in FIG. 2B includes features to trap defects away from a corresponding recombination region (layers 219, 220, 222, to be discussed in turn) within the LED.
  • the angled bottom and an aspect ratio of core 210 of LED 208 traps crystal defects in locations away from the recombination region for cubic crystals (e.g., for materials commonly used for red-light emitting LEDs).
  • Cores 214 and 218 of blue-light emitting LED 212 and green-light emitting LED 216, respectively, are epitaxially overgrown onto a surface of the STI 205 to trap crystal defects in locations away from the corresponding recombination regions for hexagonal crystals (e.g., for materials used for blue-light emitting and green-light emitting LEDs).
  • each core 210, 214, 218 is at least one conformal recombination layer 219, 220, 222 that functions as a recombination region in the p-n junction.
  • the recombination layers 219, 220, 222 can be embodied, in some examples, as at least one quantum well.
  • each quantum well layer can be, for instance, from approximately 1 nm to approximately 10 nm thick.
  • the number of layers of quantum wells is from 1 to approximately 10. In some examples, four, five, or six layers are used.
  • Quantum wells confine the charge carriers to a quantum-scale area, improving the rate at which the carriers recombine and thus the quantity of light emitted per unit time and per unit area. Quantum wells can also impose boundary conditions on the charge carrier wavelengths, and thus can change the wavelength(s) of emitted light.
  • each recombination layer 219, 220, 222 is a corresponding conformal outer layer 224, 226, 228 of the p-n junction that has a dopant that contributes charged charge carriers to the recombination layer(s) having opposite charges to the charge carriers contributed by the core dopant.
  • the conformal outer layer 224, 226, 228 injects carriers into the recombination layer 219, 220, 222 having charges opposite those injected by the core 210, 214, and 218. These oppositely charged carriers recombine in the recombination region, resulting in the emission of light.
  • each LED 208, 212, and 216 follows in the context of FIGS. 3 A, 3B, 3C, 3D, 4A, and 4B.
  • a specific example composition and doping of each layer is presented for the example embodiments of FIGS. 3A, 3B, 3C, 3D, 4A, and 4B.
  • the example cores 210, 214, and 218 are presented below as n-doped and outer layers 224, 226, and 228 are presented below as p-doped.
  • the doping and/or compositions can be changed so that the materials and dopants presented below for the outer layers 224, 226, and 228 are used for the core, and the materials and dopants presented below for the cores 210, 214, and 218 are used for the outer layers.
  • the specific material systems presented below are for convenience of explanation and that other materials systems may be used as alternatives while still embodying aspects of the present disclosure. Numerous such configurations and variations will be apparent in light of this disclosure.
  • FIGS. 3A, 3B, 3C, 3D, 4A, and 4B illustrate example embodiments of individual LEDs.
  • FIGS. 3A-C illustrate structures of one embodiment of a red-light emitting LED.
  • FIG. 3D illustrates an alternative embodiment of a red-light emitting LED.
  • FIG. 4A illustrates example embodiments of blue-light and green-light emitting LEDs.
  • FIG. 4B illustrates a nanowire embodiment of an example pixel of the present disclosure that includes a red-light emitting, a blue-light emitting and a green-light emitting LED.
  • FIG. 3A is a perspective view illustrating a patterned STI layer 205 and substrate 202, in accordance with an embodiment of the present disclosure.
  • a number of trenches 304 are etched through the STI layer 205, and in at least some instances (such as for the red LEDs 208) into the underlying substrate 202.
  • FIG. 3B shows a cross-section view of a given trench 304, according to one such embodiment.
  • the trench 304 passes through the STI layer 205, and a portion of trench 304 is formed in the underlying semiconductor substrate 202 and has faceted or otherwise tapered sidewalls 308.
  • Some elements of a red-light emitting LED are deposited in the trench 304 with tapered sidewalls 308 at a bottom of the trench 304 that traps defects away from a recombination region of the LED, as is explained below in more detail.
  • the trench 304 of FIG. 3B has an aspect ratio in which a height of the trench H (measured from a top surface of the STI layer 205 to the lowest point of the trench 304 in the substrate 202) is at least two times greater than a width W of the trench (measured at an any point in the STI layer 205).
  • the aspect ratio and the tapered sidewall 308 are configured to trap defects within the red-light emitting LED 208 away from light-emitting portions (a recombination region) of the LED 208. By trapping defects away from the light-emitting portions of the LED 208 (through mechanisms explained below in the context of FIG. 3C), the operation of the LED is improved.
  • the significant improvement enabled by the aspect ratio and tapered sidewall 308 facilitates useful illumination intensities from the LEDs, according to some embodiments.
  • the cross-section of the trench 304 can be square.
  • the tapered sidewalls 308 include four sidewalls in a pyramidal configuration. Other cross-sections are also possible, as will be appreciated in light of this disclosure.
  • FIG. 3C continues the illustration of the red-light emitting LED 208 presented above.
  • the red-light emitting LED 208 includes an n-doped core 312 that includes a tapered point disposed within tapered sidewalls 308. At least one slip dislocation 316 is disposed within the core 312.
  • the red-light emitting LED also includes a recombination layer 320 and a p-doped layer 324.
  • the n-doped core 312 is gallium arsenide (GaAs) doped with silicon, although other compositions of both core and dopant may also be used for the fabrication of a red-light emitting micro-LED, such as gallium arsenide doped with germanium.
  • GaAs gallium arsenide
  • Another example core 312 composition includes indium gallium phosphide.
  • III-V materials can be used as well, as will be appreciated in light of this disclosure.
  • dislocations 316 are formed within the n-doped gallium arsenide core 312 due to a lattice mismatch (approximately 4%) between lattice the constants of the silicon in the semiconducting substrate 202 and the gallium arsenide core 312. While deposition of the n-doped gallium arsenide core (or other materials having a cubic crystal system) is generally epitaxial with the semiconducting substrate 202, occasional atomic misalignments, deposition-induced defects, or other sources of strain at the interface of the n- doped gallium arsenide core 312 and the substrate 202 are possible.
  • strain at the interface can generate one or more dislocations 316, such as slip dislocations, within the n-doped gallium arsenide core 312. These dislocations, upon migration to a recombination layer in an LED, degrade illumination efficiency as explained above.
  • the red-light emitting LED 208 is configured to trap dislocations in a portion of the core 312 away from the recombination region 320 using a portion of the core 312 disposed within the tapered sidewalls 308 at a bottom portion of the trench that is disposed in the substrate 202.
  • This example configuration angles the sidewalls of the portion of the core 312 at approximately 55° with respect to the ⁇ 100 ⁇ family of planes of the GaAs single crystal core 312 grown in the [100] direction.
  • This configuration along with a height to width ratio (i.e., aspect ratio) of 2 to 1 of the trench 304, facilitates the trapping of dislocations in the bottom portion of the core 312.
  • the sidewall 308 is angled approximately 55° with respect to the ⁇ 100 ⁇ planes to correspond to the ⁇ 1 1 1 ⁇ family of planes in the cubic crystal system of gallium arsenide. Slip dislocations in the cubic crystal structure of GaAs are mobile within planes of the ⁇ 111 ⁇ family.
  • any dislocations created at an interface between the core 312 and the semiconducting substrate 202 are unable to migrate to the recombination region and therefore cannot degrade illumination efficiency of the LED.
  • a recombination layer 320 is conformally deposited over the n-doped core 312.
  • the recombination layer 320 functions, in part, as a recombination region in which electrons and holes combine to emit a photon.
  • the recombination layer 320 can include at least one quantum well. Examples of quantum wells include one or more layers of aluminum gallium indium phosphide, each of which is from approximately lnm thick to approximately 10 nm thick, according to some embodiments. In some example such embodiments, 3, 4, or 5, quantum well layers are used as the recombination layer 320.
  • a p-doped layer 324 is conformally deposited on the recombination layer 320, thus completing fabrication of the p-n junction.
  • the p-doped layer is used to inject holes into the recombination region (i.e., recombination layer 320) for recombination with electrons and subsequent emission of a photon.
  • the p-doped layer 324 is aluminum indium phosphide that is doped with magnesium, although other p-type dopants may also be used.
  • FIG. 3D depicts an alternative embodiment of a red-light emitting LED 350.
  • the STI or other insulation layer 205 and semiconducting substrate 202 are etched to include sidewalls 308, as described above.
  • An n-doped GaAs layer 354 is deposited in the pyramidal bottom of the trench disposed within the semiconducting layer of substrate 202.
  • a layer of n-doped aluminum indium phosphide 358 is deposited from approximately a boundary between the insulation layer 205 and the substrate 202 to a height above the insulation layer 205.
  • This second portion of the n-doped aluminum indium phosphide layer 358 extending above a surface of the insulation layer 205 is then covered by a conforming recombination layer 362.
  • the recombination layer 362 includes at least one quantum well of alternating layers of aluminum gallium indium phosphide and gallium phosphide.
  • a p-doped conformal layer of aluminum indium phosphide 366 is then deposited on the recombination layer 362 to complete fabrication of the LED.
  • electrical connections to, for example, driver circuits 224 and control circuits 220, disposed elsewhere on the substrate 202 are omitted for clarity.
  • the blue-light emitting micro-LED 212 and the green-light emitting LED 216 include structures designed to confine slip dislocations to areas of the core away from the recombination region (the recombination layers 416 and 420).
  • the core material used for both of the blue-light emitting micro-LED 212 and the green-light emitting LED 216 in this embodiment has a different crystal structure than the gallium arsenide used to fabricate the core the red-light emitting LED 208, the structural configuration of the blue-light emitting LED 212 and the green-light emitting micro-LED 216 is different from that of the red-light emitting LED 208.
  • the blue-light emitting LED 212 and the green-light emitting LED 216 each include an n-doped core 408, a first portion of which is disposed in trench 404. Slip dislocations 412 are shown within both of the blue-light emitting LED 212 and the green-light emitting LED 216.
  • the blue-light emitting LED 212 includes a blue-light recombination layer 416
  • the green-light emitting LED 216 includes a green-light recombination layer 420.
  • Each of the recombination layers can be embodied as at least one quantum well.
  • the recombination layers of the blue-light emitting LED and the green-light emitting LED are, in this example, both fabricated from indium gallium nitride (InGaN).
  • the ratio of indium to gallium in the recombination layer is different depending on the color of light to be emitted. For example, to emit blue light the ratio of indium to gallium is from approximately 1 to approximately 9; to emit green light the ratio of indium to gallium is approximately from 1 to 4 or 1 to 5.
  • Both LEDs 212 and 216 include p-doped outer layer 424, in this example embodiment.
  • the n-doped core 408 is any semiconducting compound from the III-N system, and in this example is gallium nitride (GaN). Any n-type dopants can be used to contribute electrons to the gallium nitride, but in this case the GaN is doped with silicon. In other embodiments, the GaN is doped with germanium. Other n-type dopants may also be applied for this GaN core or for other core compositions. As shown, a first portion of the n- doped core 408 is disposed within a trench 404 through the insulation layer 205 and in contact with the semiconducting substrate 202.
  • GaN gallium nitride
  • a second portion of the n-doped core 408 is laterally "overgrown" on top of the insulation layer 205 and beyond the perimeter of the trench 404 using lateral epitaxial growth.
  • the sidewalls of the trenches for the blue-light emitting micro-LED 212 and the green-light emitting micro-LED 216 are approximately parallel to the ⁇ 0001 ⁇ family of planes in the hexagonal single crystal of the core 408 grown in the [0001] direction.
  • This overgrowth provides defect free regions of the core 408 because migrating slip dislocations are pinned within the first portion within the trench 404 at the boundary between the trench 404 and the insulation layer 205, and thus cannot migrate to the recombination layers 416 and 420. In this way, the operation of the LED is not impaired by dislocations interfering with carrier recombination at the recombination region.
  • FIG. 4B illustrates an embodiment of the present disclosure in which the cores of each
  • the LED are fabricated as nanowires.
  • the nanowires shown in FIG. 4B can be from approximately 30 nm to approximately 500 nm in cross-sectional diameter where the cross-section is in a plane that is parallel to the interface between the insulation layer 205 and the substrate 202 as shown in FIG. 4B.
  • the term "diameter” encompasses a longest straight line distance from points on an outer perimeter of a core and through a center of the above-indicated cross-section regardless of geometry.
  • the term "diameter” as used herein encompasses a longest straight line distance from points on an outer perimeter of a core through a center in any number of cross-sectional shapes.
  • cores may have cross-sections of any number of geometries, including that of a square (for cubic single crystals associated with red-light emitting LEDs) and that of a hexagon (for hexagonal single crystals associated with blue-light or green-light emitting LEDs).
  • embodiments of the cores of the LEDs may not have a cross-section of a regular polygon due to variations caused by fabrication processes, variations in crystal growth, asymmetries caused intentionally through fabrication methods, or through other mechanisms.
  • the term "diameter” is used to characterize the longest straight line distance from points on an outer perimeter of a core and through a center of the core despite any irregularities in the shape of the above-identified cross-section.
  • diameters of the cores illustrated in FIG. 4B can be from 30nm to 400nm, 30nm to 300nm, 30nm to 200nm, and 30nm to lOOnm.
  • the nanowires may have a cross-sectional thickness of less than 30nm (e.g., 20nm or less) or greater than 500nm (e.g., lOOOnm).
  • a nanowire configuration for a LED core defect densities can be decreased even further thus improving the resolution and performance of LEDs and LED displays.
  • an n- type GaN and buffer layers 468 are deposited in a trench in the insulation layer 205 on the substrate 202.
  • a subsequent insulation layer 472 is deposited.
  • Two trenches, one for each of a blue-light emitting 474 LED and a green-light emitting 476 LED, are etched through the subsequent insulation layer 472.
  • One n-doped GaN nanowire core is deposited in each trench, one for a blue-light emitting LED and one for a green-light emitting LED. Unlike the embodiments described above, no lateral epitaxial overgrowth is employed in this embodiment, although this technique may optionally be used.
  • at least one recombination layer e.g., a quantum well layer
  • outer layers are deposited using methods and compositions described above, the blue-light emitting and green-light emitting devices are protected with a mask.
  • the trench for the red-light emitting LED is then etched and a red-light emitting nanowire 478 is deposited having dimensions of from approximately 30 nm to approximately 500 nm in diameter.
  • the red-light emitting micro-LED nanowire core 478 is deposited using methods and compositions described above.
  • FIG. 5 illustrates an example method 500 for fabricating LEDs, according to an embodiment of the present disclosure.
  • An insulation layer is deposited 504 on a semiconductor substrate, as described above.
  • the semiconducting layer or substrate is silicon.
  • the semiconducting layer or substrate is any type of semiconductor (e.g., II- VI, III-V, and others).
  • the insulating layer deposited 504 is any one of silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide.
  • Photolithographic masking is applied 508 to areas of the substrate corresponding to red- light emitting LEDs and any areas that do not correspond to the trenches of the blue-light emitting and green-light emitting LEDS. By applying the mask, these areas of the substrate are protected from the etching processes used to fabricate the trenches for the blue-light emitting and green-light emitting LEDS.
  • Trenches corresponding to blue and green LEDs are etched 512 through the insulating layer.
  • etchant processes used for the etching 512 include, for instance, reactive ion etching (RIE), and plasma etching. In other examples, depending on the chemical composition of the insulation layer, a wet-chemical etch is used.
  • the single crystal cores of the blue-light emitting and green-light emitting LEDs are then deposited 516 in the etched trenches using any of, for example, chemical vapor deposition (CVD), metal oxide chemical vapor deposition (MOCVD), and molecular beam epitaxy (MBE).
  • the single crystal cores in this example are deposited so as to be oriented in the [0001] direction.
  • the cores, once deposited, are also doped 516.
  • the cores of blue-light emitting and green-light emitting LEDs can be doped 516 either with an n-type dopant or a p- type dopant. Examples of n-type dopants include silicon and germanium. Examples of p-type dopants include magnesium.
  • dopants are incorporated during epitaxial deposition.
  • Fabrication of the blue-light emitting and green-light emitting LEDs continues by depositing 520 the recombination layer, which can include one or more quantum well layers conformal to the deposited core using one of the deposition methods indicated above for the deposition of the core. These techniques include, but are not limited to, CVD, MOCVD, and MBE, according to some embodiments.
  • a conformal outer layer is then deposited 524 on the recombination layer.
  • the conformal outer layer is doped with a dopant having a charge opposite that of the core to complete the p-n junction of the LED.
  • This deposition and doping 524 are performed using any of the deposition techniques already described.
  • a mask is then applied 528 to any areas not corresponding to red- light emitting LEDs to protect the structures corresponding to the blue-light emitting and green- light emitting LEDs during fabrication of red-light emitting LEDs.
  • Trenches corresponding to red LEDs are then etched 532 using any of the etch processes described above for the etching 512 of trenches for the blue-light emitting and green-light emitting LEDs.
  • Tapered sidewalls are etched 536 in the bottom of the trenches corresponding to the red-light emitting LEDs in a separate wet etch process using a mixture tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), and sodium hydroxide (NaOH).
  • TMAH mixture tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • NaOH sodium hydroxide
  • this etch 536 naturally produces the tapered or faceted sidewalls at a trench bottom described above in the context of FIGS. 3A-D.
  • Cores are deposited 540 within the trenches using any one or more of deposition techniques described above in the context of depositing 516.
  • the core is in some embodiments GaAs that is subsequently doped 540 with an n-type dopant. In other embodiments, the core is AllnP that is subsequently doped 540 with a p-type dopant.
  • At least one conformal recombination layer that can include at least one quantum well is deposited 544 on the core using techniques described above in the depositing 520.
  • An outer layer is deposited 548 on the recombination layer and doped with a dopant opposite that of the core. For example, if the core in n-doped GaAs, then the deposited 548 outer layer is, in one example, p-doped AllnP. In another example, if the core is p-doped AllnP, then the outer layer is n-doped GaAs.
  • CMOS control circuits and driver circuits are fabricated 552 using standard CMOS processing (e.g., photolithography, material deposition and planarization, and implantation techniques).
  • CMOS processing e.g., photolithography, material deposition and planarization, and implantation techniques.
  • the p-doped outer shell of each LED is connected to a drain of a corresponding driver and/or control circuit.
  • n-doped cores are connected together through the substrate.
  • the outer-layer is n-doped
  • the outer shell of each LED is connected to a source of a corresponding driver and/or control circuit.
  • p-doped cores are connected together through the substrate.
  • FIGS. 6A-D illustrate stages of integrating an LED array with a display panel, in accordance with an embodiment of the present disclosure.
  • FIG. 6A illustrates an LED system 600 that includes a micro-LED array 602 of pixels 604, 608, and 612. The pixels are disposed between a substrate 616, which in this example is n-doped silicon, and a p-type electrical contact 620.
  • the p-type electrical contact in the embodiment shown as well as any of the other embodiments disclosed herein, is a transparent conductor such as indium tin oxide, gallium indium tin oxide, zinc oxide, and others as will be appreciated.
  • the LED system 600 also includes CMOS control circuits, driver circuits, and other wiring used for the proper functioning of the system 600 and the array 602, as described above but not shown in FIGS. 6A-6D for clarity of explanation.
  • the integration of the system 600 begins by removal of a portion of the substrate 616, as shown in FIG. 6B.
  • the removal of excess material from a backside of the substrate i.e., a side opposite that on which the array 602 is disposed
  • the backside of the substrate is also implanted with hydrogen. This hydrogen implantation disrupts the crystallinity of the substrate, which facilitates removal of the partially or entirely amorphous portion of the substrate. This facilitates fabrication of a thin substrate.
  • the backside face of the silicon substrate is attached to a backplane of a display 624 (e.g., a transparent touchscreen of a mobile computing device or a transparent screen of a monitor or television) using known techniques.
  • a backplane of a display 624 e.g., a transparent touchscreen of a mobile computing device or a transparent screen of a monitor or television
  • n- type electrical contacts 628 are made between the display backplane to the substrate 616 to each individual micro-LED of each pixel (only one of which is shown for clarity of explanation). This configuration enables the electrically active elements of the display backplane 624 to contribute to the illumination and control of the array 602.
  • FIG. 7 illustrates a computing system implemented with LEDs in accordance with an embodiment of the present disclosure.
  • the computing system 700 houses a motherboard 702.
  • the motherboard 702 may include a number of components, including, but not limited to, a processor 704 and at least one communication chip 706, each of which can be physically and electrically coupled to the motherboard 702, or otherwise integrated therein.
  • the motherboard 702 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 700, etc.
  • computing system 700 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 702.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • graphics processor e.g., a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • Any display included in computing system 700 may include one or more integrated circuit structures or devices formed using the techniques disclosed herein, according to some embodiments.
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 706 can be part of or otherwise integrated into the processor 704).
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing system 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 700 may include a plurality of communication chips 706.
  • a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing system 700 includes an integrated circuit die packaged within the processor 704.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also may include an integrated circuit die packaged within the communication chip 706.
  • multi-standard wireless capability may be integrated directly into the processor 704 (e.g., where functionality of any chips 706 is integrated into processor 704, rather than having separate communication chips).
  • processor 704 may be a chip set having such wireless capability.
  • any number of processor 704 and/or communication chips 706 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing device 700 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that employs one or more integrated circuit structures or devices, as variously described herein.
  • PDA personal digital assistant
  • Example 1 is an integrated circuit comprising, a single semiconductor substrate , the substrate comprising silicon, an insulation layer disposed on the substrate, an array of light emitting diodes (LEDs) disposed on a first region of the substrate and at least partially within one or more trenches of the insulation layer, each of the LEDs implemented at least in part with III-V semiconductor material.
  • LEDs light emitting diodes
  • Example 2 includes the subject matter of Example 1 and further includes a complementary metal oxide semiconductor (CMOS) circuit disposed on second region of the substrate and at least partially within one or more additional trenches of the insulation layer, the CMOS circuit configured to at least one of control and drive the LEDs, the CMOS circuit implemented at least in part with silicon.
  • CMOS complementary metal oxide semiconductor
  • Example 3 includes the subject matter of any of Examples 1 and 2, wherein at least some of the -LEDs are at least partially formed in a trench of the substrate, the trench having a faceted bottom.
  • Example 4 includes the subject matter of any of Examples 1-3, wherein at least some of the LEDs include features that trap crystal defects away from a recombination layer within the LED.
  • Example 5 includes the subject matter of any of Examples 1 -4, wherein each LED of the array is from approximately 50 nm to 500 nm in a first dimension and from 50 nm to 500 nm in a second dimension.
  • Example 6 includes the subject matter of any of Examples 1-5, wherein the LED array is comprised of a plurality of pixels, each pixel comprising a red LED, a blue LED, and a green LED, each pixel from approximately 2.3 microns to approximately 30 microns in a first dimension.
  • Example 7 includes the subject matter of any of Examples 1-6, wherein the LED array is comprised of a plurality of pixels, each pixel comprising a red LED, a blue LED, and a green LED.
  • Example 8 includes the subject matter of Example 7, wherein each red LED of the LED array includes a core having a first portion and a second portion, the first portion disposed below a surface of the insulation layer and into the substrate, the second portion disposed above the surface of the insulation layer of the substrate, a recombination layer conformally disposed on the second portion of the core, and an outer layer conformally disposed over the recombination layer.
  • Example 9 includes the subject matter of Example 8, wherein the core is n-doped gallium arsenide.
  • Example 10 includes the subject matter of Example 9, wherein the n-type dopant comprises silicon.
  • Example 1 1 includes the subject matter of Example 9, wherein the n-type dopant is germanium.
  • Example 12 includes the subject matter of any of Examples 9-1 1 , wherein the outer layer is p-doped indium phosphide.
  • Example 13 includes the subject matter of any of Examples 9-12, wherein the recombination layer comprises at least one quantum well of aluminum gallium indium phosphide.
  • Example 14 includes the subject matter of any of Examples 1-13, wherein a first set of trenches of the one or more trenches is disposed in both the insulator layer and the substrate, the first set corresponding to a plurality of red-light emitting LEDs, each trench of the first set having a height at least twice a width.
  • Example 15 includes the subject matter of any of Examples 1 -14, wherein the first set of trenches has a bottom with at least one sidewall oriented parallel to a ⁇ 1 1 1 ⁇ family of planes in a cubic crystal system of the substrate.
  • Example 16 includes the subject matter of any of Examples 1-15, wherein the array includes green and blue LEDs, each green and blue LED includes a gallium nitride core doped with a first dopant, the gallium nitride core having a first portion and a second portion, the first portion disposed below a surface of the insulation layer and the second portion disposed above the surface of the insulation layer, the second portion laterally extending over a portion of the surface of the insulation layer, a recombination layer conformally disposed on the second portion of the gallium nitride core, and an outer gallium nitride layer having a second dopant conformally disposed over the at least one quantum well layer.
  • each green and blue LED includes a gallium nitride core doped with a first dopant, the gallium nitride core having a first portion and a second portion, the first portion disposed below a surface of the insulation layer and the second portion disposed above the surface of the insulation layer, the second portion laterally
  • Example 17 includes the subject matter of Example 16, wherein the first dopant is an n- type dopant.
  • Example 18 includes the subject matter of any of Examples 16-17, wherein the second dopant is a p-type dopant.
  • Example 19 includes the subject matter of any of Examples 16-18, wherein the recombination layer is a plurality of quantum well layers that comprise at least one indium gallium nitride layer alternating with at least one gallium nitride layer.
  • Example 20 includes the subject matter of any of Examples 16-19, wherein some of the trenches defined in the insulation layer correspond to the plurality of green and blue LEDs, each such trench having a sidewall oriented parallel to a ⁇ 0001 ⁇ family of planes of a hexagonal single crystal grown in a (0001) direction.
  • Example 21 is a light emitting diode (LED) device that includes a single semiconductor substrate, an insulation layer disposed on the single semiconductor substrate, at least one pixel comprising at least one red-light emitting LED, each red-light emitting LED including a first trench defined by the single semiconductor substrate and the insulation layer, the first trench including a height at least twice a width and further including a faceted bottom disposed in the single semiconductor substrate, a core having (1) a first portion disposed within the first trench and below a surface of the insulation layer and (2) a second portion disposed above the surface of the substrate, the core fabricated from a semiconductor doped with a first dopant, a recombination layer conformally disposed over the second portion of the core, and an outer layer having a second dopant, the outer layer conformally disposed over the recombination layer.
  • LED light emitting diode
  • Example 22 includes the subject matter of Example 21 , wherein the substrate is a single crystal of silicon grown in one of a (100) or a (1 10) direction and the faceted bottom comprises at least one sidewall parallel to ⁇ 1 1 1 ⁇ planes of a single crystal of silicon.
  • Example 23 includes the subject matter of any of Examples 21-22, wherein the at least one pixel further includes at least one blue-light or green-light emitting LED that in turn include a second trench defined by the insulation layer, a gallium nitride core doped with a first dopant, the gallium nitride core having a first portion and a second portion, the first portion disposed below a surface of the insulation layer and the second portion disposed above the surface of the insulation layer, the first portion in contact with the substrate below the second trench and the second portion laterally extending over a portion of the surface of the insulation layer, a recombination layer conformally disposed on the second portion of the gallium nitride core, andan outer gallium nitride layer having a second dopant conformally disposed over the at least one quantum well layer.
  • the at least one pixel further includes at least one blue-light or green-light emitting LED that in turn include a second trench defined by the insulation layer, a gallium nitride core
  • Example 24 includes the subject matter of any of Examples 21-23, wherein the second portion of the core has a diameter greater than the first portion of the core.
  • Example 25 includes the subject matter of any of Examples 21-23, wherein the core is n- doped gallium arsenide.
  • Example 26 includes the subject matter of claim 25, wherein the dopant is silicon.
  • Example 27 includes the subject matter of any of Examples 21 -26, and further includes a complementary metal oxide semiconductor (CMOS) circuit disposed at least one of on and in the single semiconductor substrate and at least partially within one or more additional trenches of the insulation layer, the CMOS circuit configured to at least one of control and drive the LEDs, the CMOS circuit implemented at least in part with silicon.
  • CMOS complementary metal oxide semiconductor
  • Example 28 is a method for fabricating micron-scale light emitting diodes, the method including etching a first set of trenches in a single semiconducting substrate and through an insulation layer on the single semiconducting substrate, etching a second set of trenches through the insulation layer and up to the single semiconducting substrate, depositing a semiconducting core in each trench of the first set of the second set of trenches, depositing a conformal recombination layer on each semiconducting core, depositing an outer layer on each of the conformal recombination layers, and fabricating at least one of a control circuit and a driver circuit on the substrate.
  • Example 29 includes the subject matter of Example 28, wherein each trench of the first set of trenches has a height at least twice a width.
  • Example 30 includes the subject matter of any of Examples 28-29, wherein each trench of the first set of trenches has a pyramidal bottom.
  • Example 31 includes the subject matter of any of Examples 28-30, and further includes etching a bottom of each trench of the first set to expose ⁇ 1 1 1 ⁇ planes of the substrate, in which the substrate is a single crystal of silicon grown in one of the (100) or (110) directions.
  • Example 32 includes the subject matter of any of Examples 28-31, wherein depositing the semiconducting core in each trench of the first set includes depositing a first portion of the core in the trench having a first diameter approximately equal to a diameter of the trench, and depositing a second portion of the core connected to the first portion and above the trench, the second portion having a second diameter greater than the first diameter.
  • Example 33 includes the subject matter of any of Examples 28-32, wherein depositing the semiconducting core in each trench of the second set comprises depositing a single crystal of gallium nitride in a (0001 ) direction.
  • Example 34 includes the subject matter of any of Examples 28-33, wherein each trench of the first set and the second set is from approximately 100 nm to approximately 1 micron in a first dimension.
  • Example 35 includes the subject matter of any of Examples 28-34, wherein each trench of the first set and the second set is from approximately 100 nm to approximately 1 micron in a second dimension.

Abstract

L'invention concerne des techniques de fabrication de diodes électroluminescentes (DEL) rouges, bleues et vertes monolithiques à l'aide de matériaux III-V à faible densité de défauts. Dans certains modes de réalisation, les DEL peuvent en outre être formées de manière monolithique avec des circuits de commande et d'attaque CMOS sur un substrat commun (par exemple, un substrat contenant du silicium). Les techniques sont particulièrement utiles pour fabriquer des DEL d'une taille de l'ordre de 50 nm à 10 µm. Les DEL comprennent des éléments qui piègent les défauts cristallins à distance d'une couche de recombinaison dans la DEL, facilitant le bon fonctionnement et l'efficacité d'éclairage des DEL. Des systèmes à DEL selon certains modes de réalisation comprennent des DEL rouges, bleues et vertes, ainsi que des circuits de commande et/ou d'attaque, tous fabriqués de manière monolithique sur le même substrat. Des matrices de DEL ainsi formées peuvent être utilisées dans un grand nombre d'applications, telles que des écrans à haute résolution.
PCT/US2015/000332 2015-12-24 2015-12-24 Techniques d'intégration de diodes électroluminescentes pour systèmes de matériaux iii-v WO2017111801A1 (fr)

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