WO2017110808A1

WO2017110808A1 - Wiring structure, method for manufacturing same, and electronic device

Info

Publication number: WO2017110808A1
Application number: PCT/JP2016/087954
Authority: WO
Inventors: 細田　哲史; 正古川; 亮古堅; 綾子古瀬; 鉄兵外田; 絢子有吉
Original assignee: 大日本印刷株式会社
Priority date: 2015-12-24
Filing date: 2016-12-20
Publication date: 2017-06-29
Also published as: TW201728235A

Abstract

The purpose of the present invention is to provide an exceptionally reliable wiring structure, a method for easily manufacturing a wiring structure of such description, and an electronic device in which the wiring structure is used. According to one embodiment of the present invention, there is provided a wiring structure having: a first insulation layer that has a concave portion in a first surface; a first conductor layer positioned in the concave portion, the first conductor layer protruding from the first surface; a conductor barrier layer interposed between the first conductor layer and the first insulation layer; and a second insulation layer positioned on the first surface.

Description

Wiring structure, method of manufacturing the same, and electronic device

The present invention relates to a wiring structure, a manufacturing method thereof, and an electronic device. In particular, the present invention relates to a wiring structure including interlayer connection vias and wiring, a method for manufacturing the wiring structure, and an electronic device using the wiring structure.

For example, a multilayer wiring structure in which upper and lower desired wirings are connected via interlayer connection vias uses, for example, an epoxy-based photocurable insulating resist, An insulating layer having a through hole for forming an interlayer connection via and a recess for forming a wiring is formed on the lower wiring, and a diffusion suppression layer for preventing copper diffusion is formed on the insulating layer, Next, a metal thin film layer is formed, and using this metal thin film layer as a seed electrode layer, copper is deposited in the through holes and the recesses by electroplating to form a conductive layer, and then the conductive layer located on the insulating layer is CMP ( It is manufactured by repeating the process of allowing copper to exist only in the recesses by polishing and flattening with Chemical Mechanical Polishing (Patent Documents 1 to 3).

JP 2000-236145 A Japanese Patent Laid-Open No. 2001-15517 JP 2006-66517 A

However, when the conductive layer protruding on the insulating layer is polished and flattened, it is difficult to stop the polishing accurately when the conductive layer is polished and becomes flush with the insulating layer. Will be. For this reason, there was a problem that a desired thickness could not be secured in the insulating layer, and insulation reliability was lowered.
In addition, there may be insufficient adhesion between the pad portion and wiring of the lower wiring structure formed by planarizing the conductive layer located on the insulating layer by CMP and the insulating layer of the upper wiring structure. In such a case, there is a problem that copper easily diffuses in a portion having insufficient adhesion, and a short circuit occurs between adjacent wirings of the same wiring structure or between the wirings and the pads. In addition, there is a problem of inducing a connection failure between the lower pad portion and the upper interlayer connection via.
A short circuit between wirings or between a wiring and a pad can be suppressed by increasing the distance between wirings or between a wiring and a pad, but it is against the demand for higher density due to a narrow pitch. In addition, after performing planarization by CMP, the surface of the pad portion and the wiring existing in the concave portion of the insulating layer is roughened, so that the pad portion and the wiring of the lower wiring structure and the upper wiring structure Adhesion with the insulating layer can be improved. However, such roughening causes a problem that the rough surface continues along the longitudinal direction of the wiring and the high-frequency characteristics of the wiring deteriorate. The present invention has been made in view of the above-described circumstances, and has a highly reliable wiring structure, a method for easily manufacturing such a wiring structure, and an electronic device using the wiring structure. The purpose is to provide.

According to one embodiment of the present invention, a first insulating layer having a recess on a first surface, a first conductor layer located in the recess and protruding from the first surface, and a first conductor layer, There is provided a wiring structure having a conductor barrier layer interposed between the first insulating layer and the first insulating layer.

According to one embodiment of the present invention, a first insulating layer having a recess on a first surface, a first conductor layer located in the recess and protruding from the first surface, and a first conductor layer, There is provided a wiring structure having a conductor barrier layer interposed between the first insulating layer and an alloy anchor layer located on the first conductor layer exposed on the first surface.

A base material located on the second surface opposite to the first surface may be further included.

A second insulating layer located on the first surface may be further included.

In the first surface, the height of the first conductor layer in the stacking direction may be higher than the height of the conductor barrier layer.

The first conductor layer may be copper, and the conductor barrier layer may be either a chromium / titanium composite layer or a molybdenum alloy layer.

The conductor barrier layer may have a thickness in the range of 50 to 100 nm.

A silane coupling agent layer may be further provided on the alloy anchor layer.

The alloy anchor layer may be a copper tin alloy layer or a copper tin nickel alloy layer.

The alloy anchor layer may have a thickness in the range of 50 to 100 nm.

A first through hole penetrating the first insulating layer and connected to the concave portion; a second through hole penetrating the second insulating layer and connected to the concave portion; and the second through hole, A second conductor layer electrically connected to the first conductor layer, wherein the first conductor layer is located in the recess and the first through hole, and the conductor barrier layer includes the first conductor layer and It may be interposed between the first insulating layer and the first insulating layer.

An electronic device including a wiring structure, a core substrate that is electrically connected to the first conductor layer, and a semiconductor element that is electrically connected to the second conductor layer may be used.

According to one embodiment of the present invention, an insulating layer forming step of forming an insulating layer having a recess on the first surface on a substrate, and forming a conductor barrier layer on the first surface including the inner wall surface of the recess. A conductor barrier layer forming step, a conductor layer forming step of forming a seed electrode layer so as to cover at least the conductor barrier layer, and forming a conductor layer on the seed electrode layer by electroplating; and a conductor barrier on the first surface A method for manufacturing a wiring structure is provided, which includes a polishing step of polishing a conductor layer using a layer as a stopper, and a removal step of removing a conductor barrier layer on a first surface.

After the removing step, an alloy anchor layer forming step of forming an alloy anchor layer on the conductor layer by immersing the first surface in the displacement plating solution may be further included.

In the alloy anchor layer forming step, the alloy anchor layer may be a copper tin alloy layer or a copper tin nickel alloy layer.

After the alloy anchor layer forming step, the silane coupling agent layer forming step of forming a silane coupling agent layer on the alloy anchor layer by bringing the silane coupling agent into contact with the first surface and then washing is further performed. May be included.

In the insulating layer forming step, the recess may be formed using an imprint method.

In the insulating layer forming step, the recess may be formed using a photolithography method.

In the polishing step, the conductor layer may be chemically polished.

In the polishing step, after the conductor layer is chemically polished, chemical mechanical polishing may be further performed.

In the polishing step, chemical polishing with higher selectivity of the conductor layer than the conductor barrier layer may be performed.

In the polishing process, the conductor layer may be subjected to chemical mechanical polishing.

The conductor barrier layer may have a hardness greater than the hardness of the conductor layer.

In the conductor barrier layer forming step, the conductor barrier layer is either a chromium / titanium composite layer or a molybdenum alloy layer, and in the conductor layer forming step, the conductor layer may be copper.

The wiring structure of the present invention is excellent in insulation reliability and high-frequency characteristics of the wiring, can reduce the pitch of the wiring, and is excellent in adhesion between the wiring structures.
The method for manufacturing a wiring structure according to the present invention is excellent in insulation reliability and high-frequency characteristics of the wiring, enables a wiring pitch to be narrowed, and enables manufacturing of a wiring structure having excellent adhesion between wiring structures. is there.
The electronic device of the present invention is excellent in high-frequency characteristics of the wiring, enables high-density wiring, and has excellent adhesion between the wiring structures constituting the structure, and has high reliability.

FIG. 1 is a schematic partial sectional view showing an embodiment of a wiring structure according to the present invention. FIG. 2 is a schematic partial sectional view showing an embodiment of a wiring structure having a three-layer structure. FIG. 3A is a process diagram for explaining an embodiment of a method for producing a wiring structure according to the present invention. FIG. 3B is a process diagram for explaining an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 3C is a process diagram for explaining an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 4A is a process diagram for explaining an embodiment of a method for producing a wiring structure according to the present invention. FIG. 4B is a process diagram for explaining an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 4C is a process diagram for describing an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 5A is a process diagram for explaining an embodiment of a method for producing a wiring structure according to the present invention. FIG. 5B is a process diagram for describing an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 5C is a process diagram for describing an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 6 is an enlarged view of a portion surrounded by a chain line circle in FIG. 5A. FIG. 7 is an enlarged view of a portion surrounded by a chain line circle in FIG. 5B. FIG. 8 is an enlarged view of a portion surrounded by a chain line circle in FIG. 5C. FIG. 9A is a process diagram for explaining an embodiment of a method for producing a wiring structure according to the present invention. FIG. 9B is a process diagram for describing an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 9C is a process diagram for describing an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 10 is a schematic partial cross-sectional view showing an embodiment of the electronic device of the present invention. FIG. 11 is an enlarged cross-sectional view of a portion surrounded by a circle in FIG. FIG. 12 is a schematic partial cross-sectional view corresponding to FIG. 11 showing another embodiment of the electronic device of the present invention. FIG. 13 is a partial plan view showing an embodiment of a wiring structure according to the present invention. 14 is an enlarged partial sectional view taken along line II of the wiring structure shown in FIG. FIG. 15 is a partial enlarged cross-sectional view of the wiring structure shown in FIG. FIG. 16 is a partial perspective view showing an insulating layer constituting the wiring structure. FIG. 17 is a schematic partial cross-sectional view showing an embodiment of a wiring structure having a three-layer structure. FIG. 18 is a schematic partial cross-sectional view showing another embodiment of the wiring structure of the present invention. FIG. 19 is a partial perspective view showing an insulating layer constituting the wiring structure shown in FIG. FIG. 20A is a process diagram for describing an embodiment of a method for producing a wiring structure according to the present invention. FIG. 20B is a process diagram for describing one embodiment of a method for producing a wiring structure according to the present invention. FIG. 20C is a process diagram for describing an embodiment of a method for manufacturing a wiring structure according to the present invention. FIG. 21 is a schematic partial cross-sectional view showing an embodiment of the electronic device of the present invention. FIG. 22 is an enlarged cross-sectional view of a portion surrounded by a circle in FIG. FIG. 23 is a schematic partial cross-sectional view corresponding to FIG. 22 showing another embodiment of the electronic device of the present invention. FIG. 24 is a schematic partial cross-sectional view showing another embodiment of the electronic device of the present invention. FIG. 25 is a schematic partial cross-sectional view showing another embodiment of the electronic device of the present invention. FIG. 26 is a schematic partial cross-sectional view showing another embodiment of the electronic device of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that the drawings are schematic or conceptual, and the dimensions of each member, the ratio of sizes between the members, etc. are not necessarily the same as the actual ones, and represent the same members. However, in some cases, the dimensions and ratios may be different depending on the drawing. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

<Embodiment 1>
[Wiring structure]
FIG. 1 is a schematic partial sectional view showing an embodiment of a wiring structure according to the present invention. In FIG. 1, a wiring structure 1 includes an insulating layer 3 positioned on a base material 2, and a recess 4 and a pad portion for wiring formation positioned on the surface 3 a side opposite to the base material 2 of the insulating layer 3. A recess 5 for forming, a through hole 6 for forming an interlayer connection via located in the recess 5, a wiring 14 positioned in the recess 4 of the insulating layer 3, a pad portion 15 positioned in the recess 5, A wiring layer 11 including an interlayer connection via 16 integrated with the pad portion 15 and positioned in the through hole 6 is provided. The surface 14 a of the wiring 14 opposite to the substrate 2 and the surface 15 a of the pad portion 15 opposite to the substrate 2 are in a state protruding from the surface 3 a of the insulating layer 3. A conductor barrier layer 18 is interposed between the wiring 14, the pad portion 15, the interlayer connection via 16, and the insulating layer 3. That is, the conductor barrier layer 18 is disposed on the inner surface of the recess 4 for forming the wiring, the recess 5 for forming the pad portion, and the through hole 6 for forming the interlayer connection via located in the insulating layer 3. The wiring 14, the pad portion 15, and the interlayer connection via 16 are in contact with the conductor barrier layer 18. In the illustrated example, the conductor barrier layer 18 is indicated by a bold line. An end 18 a opposite to the substrate 2 in the stacking direction of the conductor barrier layer 18 is exposed on the surface 3 a side of the insulating layer 3. The end 18a of the conductor barrier layer 18 is at the same height as the surface 3a of the insulating layer 3 or is in a depressed state. That is, the surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the end portion 18 a of the conductor barrier layer 18.
The base material 2 may have desired wiring and pad portions. However, in the illustrated example, the base material 2 is described as a substrate shape for convenience.

The insulating layer 3 ensures electrical insulation between the wirings 14 or between the wirings 14 and the pad portions 15, and when the wiring structures are laminated to form a multilayer structure. For example, an epoxy-based material, a benzocyclobutene-based material, a polybenzoxazole-based material, a polyimide-based material, a fluorine-based material, a maleimide-based material, or the like is preferable. The insulating layer 3 preferably has a thickness t in the range of about 2 to 8 μm, for example, immediately below the wiring 14 and immediately below the pad portion 15.
The wiring 14 can be set as appropriate within a range of, for example, a width of 0.5 to 10 μm and a thickness of 0.5 to 10 μm. Further, when the planar view shape of the pad portion 15 is circular, it can be appropriately set within a range of, for example, a diameter of 5 to 20 μm and a thickness of 0.5 to 10 μm. Further, the shape of the interlayer connection via 16 is, for example, a columnar shape, a frustoconical shape, etc., and the diameter can be appropriately set in the range of 2 to 12 μm, and the thickness is equal to the thickness t of the insulating layer 3 described above. It will be compatible. The conductor constituting the wiring 14, the pad portion 15, and the interlayer connection via 16 is preferably made of a material having a surface resistance of 1Ω / □ or less such as copper, nickel, nickel chrome alloy or the like. Further, the height h at which the surface 14a of the wiring 14 and the surface 15a of the pad portion 15 protrude from the surface 3a of the insulating layer 3 can be, for example, about 50 to 120 nm, preferably about 60 to 100 nm. The height at which the surface 14a of the wiring 14 and the surface 15a of the pad portion 15 protrude from the end portion 18a of the conductor barrier layer 18 may be h or more.

The conductor barrier layer 18 suppresses the diffusion of the conductor components constituting the wiring 14, the pad portion 15, and the interlayer connection via 16 into the insulating layer 3. For example, Cr / Ti is laminated from the insulating layer 3 side. And a composite alloy, a molybdenum alloy, a titanium alloy such as TiN, a tungsten alloy, a silicon alloy such as SiN, a nickel alloy such as NiP, a cobalt alloy such as CoWP, and a tantalum alloy such as TaN. Among these, wet etching using a desired etching solution, oxidation resistance to dilute sulfuric acid and hydrochloric acid, copper thermal diffusion prevention, moisture resistance, surface resistance is several tens of Ω / □ or less, and cracks In particular, a Cr / Ti composite layer or a molybdenum alloy is particularly suitable as a material that does not easily cause the occurrence of the problem and has excellent adhesion to the insulating layer 3.

The thickness of the conductor barrier layer 18 can be appropriately set depending on the material used. Here, the thickness of the conductor barrier layer 18 indicates the thickness in the direction perpendicular to the contact surface between the insulating layer 3 and the conductor barrier layer 18. For example, when a Cr / Ti composite layer is used as the conductor barrier layer 18, the insulating layer 3, the Cr layer, and the Ti layer are arranged in this order so that the Cr layer is in contact with the insulating layer 3 and the Ti layer is in contact with the Cr layer. . The thickness of the Cr layer located on the insulating layer 3 side can be in the range of 10 to 20 nm, for example, and the thickness of the Ti layer can be in the range of 40 to 100 nm, for example. When the thickness of the Cr layer is less than 10 nm, the adhesion with the insulating layer 3 is insufficient, and when it exceeds 20 nm, the front and back conductivity of the conductor barrier layer 18 is lowered and the conduction function of the interlayer connection via is insufficient. Absent. Further, if the thickness of the Ti layer is less than 40 nm, the effect of suppressing the diffusion of the conductor becomes insufficient, and if it exceeds 100 nm, the internal stress increases and the adhesion with the Cr layer is lowered, which is not preferable. When a molybdenum alloy is used as the conductor barrier layer 18, for example, the thickness can be in the range of 50 to 100 nm. When the thickness of the conductor barrier layer 18 made of molybdenum alloy is less than 50 nm, the effect of suppressing the diffusion of the conductor becomes insufficient. When the thickness exceeds 100 nm, the internal stress increases and the adhesion to the insulating layer 3 decreases, The front and back conductivity of the conductor barrier layer 18 is undesirably lowered. As will be described later, in the wiring structure according to the present invention, the conductor barrier layer 18 and the conductor layer 10 are formed on the surface 3a of the insulating layer 3, and the conductor layer 10 is polished using the conductor barrier layer 18 as a stopper. The conductor barrier layer 18 on the surface 3a of the insulating layer 3 is removed by performing flash etching. Therefore, the height h at which the surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 protrude from the surface 3 a of the insulating layer 3 corresponds to the thickness of the conductor barrier layer 18.

By adopting such a configuration, when the wiring structure 1 is laminated to form a multilayer structure, electrical insulation of the upper and lower wirings by the insulating layer 3 can be reliably obtained, and the upper and lower wiring structures can be obtained. The adhesion strength is high. FIG. 2 is a schematic partial cross-sectional view illustrating an example of a three-layer wiring structure including a wiring structure 1A including a wiring layer 11A, a wiring structure 1B including a wiring layer 11B, and a wiring structure 1C including a wiring layer 11C. It is. As shown in FIG. 2, in the wiring structure _1ML having a three-layer structure, since the wiring layer 11A provided in the wiring structure 1A protrudes from the insulating layer 3A, the wiring structure positioned on the wiring structure 1A. The insulating layer 3B of 1B and the wiring layer 11A are engaged. Similarly, since the wiring layer 11B provided in the wiring structure 1B protrudes from the insulating layer 3B, the insulating layer 3C of the wiring structure 1C located on the wiring structure 1B and the wiring layer 11B are engaged with each other. It has become. Therefore, the adhesion strength of the insulating layer 3B to the wiring layer 11A and the adhesion strength of the insulating layer 3C to the wiring layer 11B are high, and the three-layer wiring structure _1ML is excellent in insulation reliability, and also has a wiring structure. Excellent mutual adhesion. Unlike the conventional wiring structure in which the surface of the wiring and the surface of the pad portion are roughened in order to improve the adhesion between the wiring structures, the high frequency characteristics of the wiring are excellent.
In the above description, the wiring structure having a three-layer structure is taken as an example, but the number of constituent layers of the wiring structure having a multilayer structure is not particularly limited.

The above-described embodiment of the wiring structure is an example, and the present invention is not limited to this embodiment. For example, in the above-described embodiment, the wiring structure includes one type of wiring having a cross-sectional shape, but may include two or more types of wiring having a cross-sectional shape.
Further, among the plurality of pad portions 15, there may be one connected to the wiring 14 and one separated from the wiring 14. The pad portion 15 that is separated from the wiring 14 becomes a dummy pad portion, but in order to ensure the strength uniformity in the plane of the wiring structure, the presence of the dummy pad portion that is separated from the wiring 14 exists. Is advantageous.

[Method for manufacturing wiring structure]
3 to 5 are process diagrams for explaining an embodiment of a method for manufacturing a wiring structure according to the present invention, and show an example of manufacturing the wiring structure 1 described above. 6 to 8 are enlarged sectional views showing a part of the process drawings.
In this embodiment, first, in the insulating layer forming step, an insulating layer having a recess for forming a pad portion, a through hole for forming an interlayer connection via located in the recess, and a recess for forming a wiring is used as a base. Form on the material. The present embodiment is an example in which an insulating layer is formed by using an imprint method. Here, a recess for forming a pad portion and a through hole for forming an interlayer connection via located in the recess are formed on the insulating layer. And a mold 51 for forming an insulating layer having a recess for forming a wiring by an imprint method is prepared (FIG. 3A). The mold 51 includes a mold base 52 and a concavo-convex structure 53 located on the main surface 52 a of the mold base 52. The concavo-convex structure 53 of the mold 51 includes a convex portion 54 having a linear shape in plan view and a convex portion 55 having a circular shape in plan view. The convex portion 54 having a linear shape in plan view is a convex portion for forming a concave portion for forming a wiring in the insulating layer. On the other hand, the convex part 55 having a circular shape in plan view is a convex part for forming a concave part for forming the pad part in the insulating layer, and a light shielding is provided at a substantially central part of the top flat surface 55a of the convex part 55. Layer 56 is located. In addition, from the desired convex-shaped part 55, the linear convex-shaped part 54 is pulled out. However, some of the plurality of convex portions 55 may be separated from the linear convex portion 54.

Next, a photocurable insulating resist is supplied onto the base material 2, the base material 2 and the mold 51 are brought close to each other, and the photocurable insulating resist is developed between the base material 2 and the mold 51 to be photocurable. An insulating resist layer 3 ′ is formed (FIG. 3B). In the illustrated example, the base material 2 is described in a substrate shape for convenience, but may have a desired wiring and pad portion. Examples of the photo-curable insulating resist used include epoxy-based, benzocyclobutene-based, polybenzoxazole-based, polyimide-based, fluorine-based, and maleimide-based resists.
Next, light irradiation is performed from the back surface 52b side of the mold base 52 of the mold 51 to cure the photocurable insulating resist layer 3 'to the insulating material layer 3 ", and the light shielding layer 56 of the mold 51 and the base material. The photo-curable insulating resist layer 3 ′ located between the two layers 2 is left uncured (FIG. 3C) The light irradiated from the mold 51 side is a photo-curable insulating resist layer positioned immediately below the light shielding layer 56. It is preferable to use parallel light in order to prevent light wraparound that causes 3 'curing.
Next, the mold 51 is separated from the insulating material layer 3 ″ and the remaining photocurable insulating resist layer 3 ′ (FIG. 4A). In this step, at least a part of the remaining photocurable insulating resist layer 3 ′ is molded. It may adhere to 51 and be removed together with the mold 51.

Subsequently, the insulating material layer 3 ″ is developed to remove the remaining photo-curable insulating resist layer 3 ′ and subjected to a post-bake treatment. Thereby, the recess 4 for forming the wiring, the recess 5 for forming the pad portion, and the like. Then, the insulating layer 3 having the through hole 6 for forming the interlayer connection via located in the recess 5 is obtained (FIG. 4B).
Next, in the conductor barrier layer forming step, the surface 3a of the insulating layer 3 including the inner wall surface of the recess 4 for forming the wiring, the recess 5 for forming the pad portion and the inner wall surface of the through hole 6 for forming the interlayer connection via is formed. A conductor barrier layer 18 is formed (FIG. 4C). The conductor barrier layer 18 can be formed by a known vacuum film formation method such as a sputtering method. The conductor barrier layer 18 is also formed on the substrate 2 exposed in the through hole 6 for forming the interlayer connection via. In the illustrated example, the conductor barrier layer 18 is indicated by a bold line.

The conductor barrier layer 18 suppresses the diffusion of the components of the conductor layer formed in the subsequent process into the insulating layer 3. Further, in the subsequent step of polishing the conductor layer, the conductor barrier layer 18 has a hardness higher than that of the conductor so that the conductor barrier layer 18 acts as a stopper. Such a conductor barrier layer 18 can be, for example, a composite layer in which Cr / Ti is laminated from the insulating layer 3 side when the conductor to be formed in the subsequent process is copper (Vickers hardness: 0.8 GPa). In addition, it shall consist of any one of molybdenum alloy, titanium compound such as TiN, tungsten alloy, silicon compound such as SiN, nickel compound such as NiP, cobalt alloy such as CoWP, tantalum compound such as TaN, etc. Can do. Among these, wet etching using a desired etching solution, oxidation resistance to dilute sulfuric acid and hydrochloric acid, copper thermal diffusion prevention, moisture resistance, surface resistance is several tens of Ω / □ or less, and cracks In particular, a Cr / Ti composite layer or a molybdenum alloy is particularly suitable as a material that does not easily cause the occurrence of the problem and has excellent adhesion to the insulating layer 3.

When a composite layer of Cr / Ti is used as the conductor barrier layer 18, the Cr layer (Vickers hardness: 1.06 GPa) ensures adhesion between the insulating layer 3 and the Ti layer, and the Ti layer (Vickers hardness: 1 .3 GPa) suppresses the diffusion of the conductor into the insulating layer 3 and acts as a stopper in the polishing process. The thickness of the Cr layer of such a Cr / Ti composite layer can be in the range of 10 to 20 nm, for example, and the thickness of the Ti layer can be in the range of 50 to 100 nm, for example. When the thickness of the Cr layer is less than 10 nm, the adhesion with the insulating layer 3 becomes insufficient, and when it exceeds 20 nm, the front and back conductivity of the conductor barrier layer 18 is not preferable. Further, if the thickness of the Ti layer is less than 50 nm, the effect of suppressing the diffusion of the conductor becomes insufficient, and if it exceeds 100 nm, the internal stress increases and the adhesion with the Cr layer is lowered, which is not preferable.

Moreover, as a molybdenum alloy used as the conductor barrier layer 18, the following molybdenum alloys can be mentioned, for example.
MoNiTi: 24 to 27.7% Ni / 6 to 12% Ti
MoTiZrC: 0.5% Ti / 0.08% Zr / 0.01 to 0.04% C
MoLa: 0.03 to 0.7% La ₂ O ₃
MoY: 0.47% Y ₂ O ₃ /0.08% Ce ₂ O ₃
MoRe: 5.0% Re; 41% Re
MoW: 20% W; 30% W; 50% W
MoCu: 15.0% Cu; 30% Cu
MoNb: 9.71% Nb
MoTa: 10.75% Ta

Among these molybdenum alloys, for example, a MoNiTi alloy (Vickers hardness: 1.53 GPa) can be easily formed by a known vacuum film forming method and has good adhesion to the insulating layer 3, and The effect of suppressing the diffusion of the conductor and the stopper function in the polishing process are good. When such a MoNiTi alloy is used, the thickness of the conductor barrier layer 18 can be set in the range of 50 to 100 nm, for example. When the thickness of the conductor barrier layer 18 when using the MoNiTi alloy is less than 50 nm, the effect of suppressing the diffusion of the conductor becomes insufficient, and when it exceeds 100 nm, the internal stress increases and the adhesion to the insulating layer 3 decreases, In addition, the front and back conductivity of the conductor barrier layer 18 is undesirably lowered.

Next, in a conductor forming step, a seed electrode layer is formed on the conductor barrier layer 18, and a conductor is deposited on the seed electrode layer by electroplating to form a recess 4 for forming a wiring, a recess for forming a pad portion. 5. The conductor layer 10 is formed so as to fill the through hole 6 for forming the interlayer connection via located in the recess 5 for forming the pad portion (FIG. 5A). FIG. 6 is an enlarged view of a portion surrounded by a chain line in FIG. 5A.
The seed electrode layer is preferably made of a material having a surface resistance of 1 Ω / □ or less, such as copper, nickel, nickel-chromium alloy, etc., and may be formed in a thickness range of 10 to 500 nm by a known vacuum film formation method such as sputtering. it can. Since this sheet electrode layer is integrated with the conductor layer 10, the seed electrode layer is omitted in the illustrated example. The conductor layer 10 forms a wiring, a pad portion, and an interlayer connection via constituting the wiring structure. For example, a material having a surface resistance of 1Ω / □ or less such as copper, nickel, nickel chrome alloy or the like is preferable. . Such a conductor layer 10 can be formed to be thicker than the insulating layer 3 by about several μm.

Next, the conductor layer 10 is polished in a polishing step (FIG. 5B). FIG. 7 is an enlarged view of a portion surrounded by a chain line in FIG. 5B. The conductor layer 10 can be polished by CMP (Chemical Mechanical Polishing). In the chemical mechanical polishing of the conductor layer 10, the hardness of the conductor barrier layer 18 is larger than the hardness of the conductor layer 10, so that the conductor barrier layer 18 acts as a polishing stopper. The chemical mechanical polishing of the conductor layer 10 can be stopped when the conductor barrier layer 18 located on the surface 3a of the insulating layer 3 is reached. However, it is not limited to this, The polishing process of the conductor layer 10 may be chemical polishing including etching, electrolytic polishing, and the like. In the chemical polishing of the conductor layer 10, a method in which the selectivity of the conductor layer 10 is higher than that of the conductor barrier layer 18 can be used. As a result, the conductor layer 10 can be selectively polished, and the conductor barrier layer 18 acts as a polishing stopper. The chemical polishing of the conductor layer 10 can be stopped when the conductor barrier layer 18 located on the surface 3a of the insulating layer 3 is reached. Further, the polishing process of the conductor layer 10 may be a combination of chemical polishing and chemical mechanical polishing. For example, after most of the conductor layer 10 is chemically polished, the residue may be removed by chemical mechanical polishing. Thus, without polishing the insulating layer 3, the wiring 14 is located in the wiring forming recess 4, the pad 15 is located in the pad forming recess 5, and the interlayer connection via forming through hole 6 is located. The wiring layer 11 including the interlayer connection via 16 can be formed, and a wiring structure having excellent insulation reliability can be easily manufactured.
Next, in the removing step, the exposed conductor barrier layer 18 located on the surface 3a of the insulating layer 3 is removed (FIG. 5C). FIG. 8 is an enlarged view of a portion surrounded by a chain line in FIG. 5C. The conductor barrier layer 18 can be removed by performing flash etching. For example, when the conductor barrier layer 18 is a composite layer of Cr / Ti, first, the Ti layer is removed by flash etching using a mixed solution of potassium hydroxide and hydrogen peroxide, and then an aqueous potassium ferricyanide solution, or The Cr layer can be removed by flash etching using an aqueous cerium ammonium nitrate solution. Further, when the conductor barrier layer 18 is formed of a molybdenum alloy, for example, a mixed solution of potassium hydroxide and hydrogen peroxide can be removed using a flash etching solution.

Thereby, the wiring structure 1 is obtained. The wiring structure 1 includes a wiring layer 11 including a wiring 14 located in the concave portion 4 of the insulating layer 3, a pad portion 15 located in the concave portion 5, and an interlayer connection via 16 located integrally with the pad portion 15 and located in the through hole 6. It has. The surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the surface 3 a of the insulating layer 3. The end 18 a of the conductor barrier layer 18 is at the same height as the surface 3 a of the insulating layer 3. That is, the surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the end portion 18 a of the conductor barrier layer 18.
In the case where the conductor barrier layer 18 remains at the bottom of the through hole 6 for forming the interlayer connection via and the base material 2 has wiring and pad portions, between these and the interlayer connection via 16 in the through hole 6. The conductor barrier layer 18 is interposed between the two. However, the conductor barrier layer 18 has a thickness of 100 nm or less as described above. Therefore, even if the surface resistance is several tens Ω / □ or more, the conduction function of the interlayer connection via is not hindered.
In the present invention, the wiring structure layer can be formed in multiple layers by repeating the above series of steps a desired number of times. For example, by repeating the above series of steps three times, a wiring structure _1ML having a three-layer structure as shown in FIG. 2 can be manufactured. As shown in FIG. 2, the wiring structure 1 _ML of a three-layer structure, the wiring layer 11A on which the wiring structure 1A is provided is therefore protrudes from the insulating layer 3A, a wiring structure located on the interconnection structure 1A The insulating layer 3B of 1B and the wiring layer 11A can be manufactured in an engaged state. Similarly, since the wiring layer 11B provided in the wiring structure 1B protrudes from the insulating layer 3B, the insulating layer 3C of the wiring structure 1C located on the wiring structure 1B and the wiring layer 11B are engaged with each other. Can be manufactured. Therefore, the wiring structure 1 _ML is provided that has high adhesion strength of the insulating layer 3B to the wiring layer 11A, high adhesion strength of the insulating layer 3C to the wiring layer 11B, excellent insulation reliability, and excellent adhesion between the wiring structures. can do. In addition, it is possible to provide a wiring structure 1 _ML having excellent high frequency characteristics as compared with a conventional wiring structure in which the surface of the wiring and the surface of the pad portion are roughened in order to improve the adhesion between the wiring structures. it can.
In the above description, the wiring structure having a three-layer structure is taken as an example, but the number of constituent layers of the wiring structure having a multilayer structure is not particularly limited. Further, the configuration of the wiring layer included in the wiring structure is not particularly limited.

Here, the mold 51 will be described in more detail. When the molding resin material used for imprinting is photocurable, the material of the mold base 52 constituting the mold 51 is a material that can transmit irradiation light for curing them. For example, glass such as quartz glass, silicate glass, calcium fluoride, magnesium fluoride, and acrylic glass, sapphire and gallium nitride, and resins such as polycarbonate, polystyrene, acrylic, and polypropylene, or these Any laminate material can be used. In addition, when the molding resin material to be used is not photocurable, the mold 51 does not have to be light transmissive, and other than the above materials, for example, metal such as silicon, nickel, titanium, and aluminum And these alloys, oxides, nitrides, or these arbitrary laminated materials can be used.

The thickness of the mold base 52 can be set in consideration of the strength of the material, suitability for handling, and the like, and can be set as appropriate within a range of about 300 μm to 10 mm, for example. In addition, the main surface 52a side of the mold base 52 may have a convex structure having two or more steps, or a mesa structure. In this case, the uppermost step is the main surface 52a, and the uneven structure 53 is formed on the main surface 52a. To position.
The convex part 54 provided in the mold 51 is a convex part for forming the concave part for forming the wiring in the insulating layer as described above. For example, the width is 0.5 to 10 μm, and the height from the main surface 52a is The thickness can be appropriately set in the range of 0.5 to 10 μm.
Moreover, the convex-shaped part 55 is a convex part for forming the recessed part for pad part formation in an insulating layer as mentioned above. In the case where the convex shape portion 55 has a circular shape in plan view, for example, the diameter of the convex shape portion 55 may be appropriately set within the range of 5 to 30 μm and the height from the main surface 52a within the range of 0.5 to 10 μm. it can.

Further, the light shielding layer 56 located at the center of the top flat surface 55a of the convex portion 55 is irradiated from the other surface 52b side of the mold base 52 in imprinting using a photocurable resin material to be molded. It is a layer that can be shielded to the extent that light curing of the resin material to be molded by light does not occur. Such a light shielding layer 56 can be, for example, a layer having an optical density (OD) of 2 or more, preferably 3 or more, and the material thereof is, for example, chromium, molybdenum, titanium, aluminum, silver, nickel or the like. Can be mentioned. The thickness of the light shielding layer 56 can be appropriately set so that the optical density is 2 or more. For example, when the material of the light shielding layer 56 is chromium, the thickness is preferably about 50 to 150 nm. When the thickness of the chromium light-shielding layer 56 is less than 50 nm, the optical density is less than 2 and the light-shielding property is insufficient. In particular, when using a light source with high illuminance, The thickness of the light shielding layer 56 is preferably 100 nm or more. On the other hand, if the thickness of the chromium light-shielding layer 56 exceeds 150 nm, the internal stress of the light-shielding layer 56 is increased, peeling is likely to occur, and the durability is lowered.
In addition, the mold to be used may not include the light shielding layer 56, and a further convex shape portion may be positioned at a substantially central portion of the top flat surface 55 a of the convex shape portion 55 instead. In this case, the further convex portion is a convex portion for forming a through hole for forming an interlayer connection via in the insulating layer. When the shape of the convex portion is a circular shape, for example, the convex portion is a columnar shape, a truncated cone shape, etc., and the diameter can be appropriately set in the range of 2 to 12 μm, and the thickness is This corresponds to the thickness t of the insulating layer 3 described above. Such a mold can penetrate the insulating layer 3 because the thickness of the convex portion 55 and the further convex portion corresponds to the thickness of the insulating layer 3.
The above-described embodiment of the method for manufacturing a wiring structure is an example, and the present invention is not limited to this embodiment. For example, in the above-described embodiment, the insulating layer 3 is formed by the imprint method, but the insulating layer 3 may be formed by a photolithography method.

FIG. 9 is a process diagram for explaining an embodiment of the method for manufacturing a wiring structure according to the present invention. In the insulating layer forming step, a recessed part for forming a pad part on the insulating layer and a position in the recessed part are shown. In this modification, an insulating layer having a through hole for forming an interlayer connection via and a recess for forming a wiring is formed by a photolithography method. 9, the same elements as those shown in FIGS. 3 and 4 are denoted by the same reference numerals.
Here, an insulating layer having a recess for forming a pad portion, a through hole for forming an interlayer connection via located in the recess, and a recess for forming a wiring is formed on the insulating layer by a photolithography method. A mask 91 is prepared (FIG. 9A). The mask 91 includes a light-transmitting region 93 that transmits exposure light,

semi-transparent regions

94 and 95 that transmit part of the exposure light, and a light-blocking region 96 that blocks exposure light. In the region where the concave portion is formed on the insulating layer, there are a semi-transparent region 94 having a linear shape in plan view and a semi-transparent region 95 having a circular shape in plan view. The semi-transparent region 94 having a linear shape in plan view is a region for forming a recess for forming a wiring in the insulating layer. On the other hand, the semi-transparent region 95 having a circular shape in plan view is a region for forming a recess for forming the pad portion in the insulating layer, and a light-shielding region 96 is provided at a substantially central portion of the semi-transparent region 95. positioned. Note that a linear semi-transparent region 94 is drawn out from the desired semi-transparent region 95. However, some of the plurality of semi-transparent regions 95 may be separated from the linear semi-transparent region 94. Since such a multi-tone photomask has a different amount of transmission of exposure light depending on each region, a pattern having at least three thicknesses is formed by performing exposure and development using this multi-tone photomask. be able to. However, the present invention is not limited to this. For example, two-step exposure may be performed using a photomask having a light transmitting region and a light shielding region. In this case, a multi-tone exposure is performed by using a mask that shields the

semi-transparent regions

94 and 95 in one exposure and using a mask that transmits the

semi-transparent regions

94 and 95 in the other exposure. It can be carried out.

Next, a photocurable insulating resist is supplied onto the substrate 2 to form a photocurable insulating resist layer 3 ′ on the substrate 2 (FIG. 9B). In the illustrated example, the base material 2 is described in a substrate shape for convenience, but may have a desired wiring and pad portion. Examples of the photo-curable insulating resist used include epoxy-based, benzocyclobutene-based, polybenzoxazole-based, polyimide-based, fluorine-based, and maleimide-based resists.
Next, the mask 91 is brought into contact, and light irradiation is performed from the back surface 92b side of the mask 91 to cure the photocurable insulating resist layer 3 ′ to form an insulating material layer 3 ″. The photocurable insulating resist layer 3 ′ located between the

light regions

94 and 95 and the base material 2 is left in the whole or part thereof uncured (FIG. 9C). It is preferable to use parallel light in order to prevent light from wrapping around such that the photo-curable insulating resist layer 3 ′ located directly below 96 is cured.
Next, the insulating material layer 3 ″ and the remaining photocurable insulating resist layer 3 ′ are separated from the mask 91. In this step, at least a part of the remaining photocurable insulating resist layer 3 ′ adheres to the mask 91. Then, it may be removed together with the mask 91.

Next, as in the above step, the insulating material layer 3 ″ is developed to remove the remaining photocurable insulating resist layer 3 ′ and subjected to a post-bake treatment. An insulating layer 3 having a recess 5 for forming a portion and a through hole 6 for forming an interlayer connection via located in the recess 5 can be obtained (FIG. 4B).

[Electronic device]
FIG. 10 is a schematic partial cross-sectional view showing an embodiment of the electronic device of the present invention, and FIG. 11 is a partially enlarged cross-sectional view of a portion surrounded by a circle in FIG. 10 and 11, the electronic device 100 is obtained by forming a multilayer wiring structure 1 _ML on a core substrate 31 and mounting a semiconductor element 101 via connection pads 81. In this embodiment, the multilayer wiring structure 1 _ML is the above-described wiring structure of the present invention, and such a multilayer wiring structure 1 _ML can be manufactured by the manufacturing method of the present invention. The description in is omitted.
In FIG. 10, in order to avoid drawing from being complicated, the insulating layer 3A is an interlayer insulating layer constituting the multilayer wiring structure 1 _ML, 3B, 3C, and the solder resist 71, the underfill resin 72 Is not shaded. The semiconductor element 101 can be, for example, a memory element, a logic element, or the like. In the illustrated example, the semiconductor element 101 is uniformly shaded regardless of its structure.
The core substrate 31 has a multilayer structure in which a core base material 32 and a plurality of conductor layers 35 are laminated on both surfaces of the core base material 32 with an insulating layer 34 interposed therebetween.

The core base material 32 includes a plurality of front and back conductive via portions 33 penetrating the core base material 32, and the surface of the core base material 32 (in the illustrated example, the surface side on which the multilayer wiring structure _1ML is disposed). , A conductor layer 33a connected to a predetermined front / back conduction via portion 33, and a conductor layer 33a ′ connected to a predetermined front / back conduction via portion 33 on the back surface of the core substrate 32. Such a core base material 32 may be an electrically insulating material such as glass, glass cloth-containing epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, or the like.

Conductive layers

35A and 35B are laminated on the surface side of the core base material 32 via insulating

layers

34A and 34B. The conductor layer 33a and the conductor layer 35A positioned above and below via the insulating layer 34A are connected by the interlayer connector 36A, and the conductor layer 35A and the conductor layer 35B positioned above and below via the insulating layer 34B are connected by the interlayer connector 36B. Connected with.
Conductive layers 35A ′ and 35B ′ are laminated on the back surface side of the core base material 32 via insulating layers 34A ′ and 34B ′. Then, the conductor layer 33a 'positioned above and below the conductor layer 35A' via the insulating layer 34A 'is connected by the interlayer connector 36A', and the conductor layer 35A 'positioned above and below the conductor layer via the insulating layer 34B'. 35B 'is connected by an interlayer connector 36B'. Further, a solder resist 38 is disposed so as to expose a desired portion of the conductor layer 35B ', and the exposed conductor layer 35B' includes a solder ball 41.

The conductor layer 35B located on the surface side of the core substrate 31 is a pad portion, and a multilayer wiring structure _1ML is disposed so as to be connected to the pad portion. The multilayer wiring structure _1ML has a wiring layer 11 composed of three

wiring layers

11A, 11B, and 11C. A semiconductor element 101 is mounted on a pad portion of the wiring layer 11C via a connection pad 81. Has been. In the illustrated example, the nickel layer 61 on the pad portion of the multilayer wiring structure 1 _ML wiring layer 11C, with the gold layer 62 is provided, a solder resist as the nickel layer 61, a gold layer 62 is exposed 71 is disposed. The connection pad 81 is thermocompression bonded to connect the gold layer 62 and the terminal 101 a of the semiconductor element 101. Further, the gap between the semiconductor element 101 and the multilayer wiring structure 1 _ML underfill resin 72 was heated and cured to fill the thermosetting resin is filled. The plurality of semiconductor elements 101 mounted in this manner may be different kinds of semiconductor elements.

The above-described electronic device is an example, and the electronic device that can be manufactured using the method for manufacturing a wiring structure according to the present invention is not limited to the above example. For example, the electronic device may include a multilayer wiring structure 1 ′ _ML as shown in FIG. FIG. 12 is a partial enlarged cross-sectional view of the electronic device corresponding to FIG. The multilayer wiring structure 1 ′ _ML in the electronic device 100 ′ shown in FIG. 12 has a through hole 7 for bump formation on the uppermost wiring structure 1C constituting the multilayer wiring structure _1ML. An insulating layer 3D provided and a bump 17 located in the through hole 7 are provided. The surface 17 a of the bump 17 is in a state protruding from the surface of the insulating layer 3 D, and the terminal 101 a of the semiconductor element 101 is connected to the bump 17 via the connection pad 81. The gap between the semiconductor element 101 and the wiring structure 1 is filled with an underfill resin 72 that is filled with a thermosetting resin and heat-cured. Such an electronic device 100 ′ does not require the formation of the nickel layer 61 and the gold layer 62 described above, and the configuration of the mounting portion of the semiconductor element 101 via the connection pad 81 is simpler than that of the electronic device 100. As a result, the number of steps is reduced, and the material cost can be reduced.

<Embodiment 2>
[Wiring structure]
FIG. 13 is a partial plan view showing an embodiment of a wiring structure according to the present invention. 14 is an enlarged partial sectional view taken along line II of the wiring structure shown in FIG. 13, and FIG. 15 is a partial enlarged view of the wiring structure shown in FIG. FIG. 16 is a partial perspective view showing an insulating layer constituting the wiring structure. In addition, this embodiment is essentially the same as Embodiment 1 of this invention except the structure of an alloy anchor layer and a silane coupling agent layer, and the repeated description is abbreviate | omitted.
13 to 16, the wiring structure 10 includes an insulating layer 3 positioned on the base material 2 and a wiring forming recess 4 positioned on the surface 3a side of the insulating layer 3 opposite to the base material 2. And the recessed portion 5 for forming the pad portion, the through hole 6 for forming the interlayer connection via located in the recessed portion 5, the wiring 14 located in the recessed portion 4 of the insulating layer 3, and the pad portion located in the recessed portion 5. 15, a wiring layer 21 including an interlayer connection via 16 integrated with the pad portion 15 and positioned in the through hole 6 is provided. The surface 14 a of the wiring 14 opposite to the substrate 2 and the surface 15 a of the pad portion 15 opposite to the substrate 2 are in a state protruding from the surface 3 a of the insulating layer 3. A conductor barrier layer 18 is interposed between the wiring 14, the pad portion 15, the interlayer connection via 16, and the insulating layer 3. That is, the conductor barrier layer 18 is disposed on the inner surface of the recess 4 for forming the wiring, the recess 5 for forming the pad portion, and the through hole 6 for forming the interlayer connection via located in the insulating layer 3. The wiring 14, the pad portion 15, and the interlayer connection via 16 are in contact with the conductor barrier layer 18. An end 18 a opposite to the substrate 2 in the stacking direction of the conductor barrier layer 18 is exposed on the surface 3 a side of the insulating layer 3. The end 18a of the conductor barrier layer 18 is at the same height as the surface 3a of the insulating layer 3 or is in a depressed state. That is, the surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the end portion 18 a of the conductor barrier layer 18. An alloy anchor layer 27 is located at a portion where the wiring 14 and the pad portion 15 are exposed on the surface 3 a side of the insulating layer 3, and a silane coupling agent layer 28 is formed on the alloy anchor layer 27. positioned. In FIG. 14, the silane coupling agent layer 28 is indicated by a bold line.
The base material 2 may have desired wiring and pad portions. However, in the illustrated example, the base material 2 is described as a substrate shape for convenience.

The alloy anchor layer 27 is a layer for ensuring adhesion and barrier properties between the wiring 14, the pad portion 15 and the silane coupling agent layer 28. The alloy anchor layer 27 contains the same metal as the conductor constituting the underlying wiring 14 and pad portion 15 and a metal that improves adhesion of the silane coupling agent by adding a hydroxyl group. When the conductor is copper, the same metal as the lower conductor is the same copper, and thus the alloy anchor layer 27 can exhibit good adhesion to the lower wiring 14 and the pad portion 15. Moreover, tin, iron, aluminum, copper, chromium etc. can be mentioned as a metal which provides a hydroxyl group. Therefore, the alloy anchor layer 27 can be an alloy of such a metal imparting a hydroxyl group and a conductor constituting the wiring 14 and the pad portion 15. When the conductor is copper, the alloy anchor layer 27 is A copper tin alloy layer, a copper iron alloy layer, a copper aluminum alloy layer, a chromium copper alloy layer, or the like can be used. For example, when the alloy anchor layer 27 is a copper-tin alloy layer, tin has a function of imparting a hydroxyl group to the surface of the alloy anchor layer 27, that is, the interface side with the silane coupling agent layer 28. By reacting with the coupling agent, the silane coupling agent layer 28 can be present on the wiring 14 and the pad portion 15 through the alloy anchor layer 27 with good adhesion. Moreover, since tin has a lower diffusibility to the insulating layer 3 than copper, the alloy anchor layer 27 made of a copper-tin alloy layer also has a function as a conductor barrier layer. As a result, the conductor 14 and the pad portion 15 are prevented from diffusing the conductor even in the portion exposed to the surface 3a side of the insulating layer 3.

Moreover, the alloy anchor layer 27 can further contain one or more of nickel, titanium, chromium, etc. as other metals. For example, when the alloy anchor layer 27 is a copper tin nickel alloy layer, nickel can stably form the alloy anchor layer in the alloy anchor layer forming step in the wiring structure manufacturing method described later. To do.
In such an alloy anchor layer 27, the composition weight ratio of the same metal as the underlying conductor / the metal exhibiting the function of imparting a hydroxyl group / other metal is in the range of 60 to 95/5 to 40/0 to 5. can do. When the composition weight ratio in the alloy anchor layer 27 is out of the above range, the alloy anchor layer 27 performs the above-described action, that is, the action of fixing the silane coupling agent layer 28 on the wiring 14 and the pad portion 15 with a good adhesion. In addition, the effect of suppressing the diffusion of the conductor from the wiring 14 and the pad portion 15 may be insufficient. The thickness of the alloy anchor layer 27 can be set in the range of 50 to 100 nm, preferably 60 to 80 nm. When the thickness of the alloy anchor layer 27 is less than 50 nm, the action of the alloy anchor layer 27 may be insufficiently expressed. On the other hand, if it exceeds 100 nm, further improvement of the above-described action of the alloy anchor layer 27 cannot be obtained, cracks are likely to occur due to film stress, and the time required for forming the alloy anchor layer is undesirably increased.

When the wiring structure is further laminated on the wiring structure 10, the silane coupling agent layer 28 provides adhesion between the wiring 14 and the pad portion 15 of the wiring structure 10 and the insulating layer of the upper wiring structure. It is to improve. In such a silane coupling agent layer 28, silicon atoms of the silane coupling agent constituting the silicon atom are bonded to the alloy anchor layer 27 through oxygen atoms, and reactive functional groups are bonded to the silicon atoms. This reactive functional group is a group that reacts with the organic component of the upper insulating layer. For example, amino group, epoxy group, mercapto group, sulfide group, acyl group, acetyl group, methacryl group, vinyl group, unsaturated group It may be a group selected from the group consisting of hydrocarbon groups. Such a reactive functional group is bonded to a silicon atom via a bond — (CH ₂ ) _n —. N in this bond is an integer of 1 to 10, but since the thickness of the silane coupling agent layer 28 is preferably uniform, n is preferably in the range of 1 to 3. Such a silane coupling agent layer 28 has a thickness of 5 nm or less, preferably a monomolecular layer of a silane coupling agent. The silane coupling agent layer 28 usually has a surface resistance of 1000 Ω / □ or more, but if the thickness is 5 nm or less, an interlayer connection via in the wiring structure laminated on the pad portion 15 and the wiring structure 10. It will not interfere with the conduction function.

By adopting such a configuration, when the wiring structure 10 is laminated to form a multilayer structure, electrical insulation of the upper and lower wirings by the insulating layer 3 can be reliably obtained, and the upper and lower wiring structures can be obtained. The adhesion strength is high. Further, due to the presence of the silane coupling agent layer 28, the adhesion between the wiring 14 and the pad portion 15 of the lower wiring structure 10 and the insulating layer 3 of the upper wiring structure 10 becomes sufficiently high. Accordingly, it is not necessary to roughen the surfaces of the wiring 14 and the pad portion 15, there is no rough surface along the longitudinal direction of the wiring, and the high-frequency characteristics of the wiring are excellent. A stable connection between the pad portion and the upper interlayer connection via can be obtained. Furthermore, by such cooperation of the high adhesion and the conductor barrier function by the conductor barrier layer 18 and the alloy anchor layer 27, the insulation reliability between the wires or between the wires and the pads is excellent, and the high pitch is achieved by the narrow pitch. Densification is possible.

FIG. 17 is a schematic partial cross-sectional view showing an example of a three-layer wiring structure including a wiring structure 10A including a wiring layer 21A, a wiring structure 10B including a wiring layer 21B, and a wiring structure 10C including a wiring layer 21C. It is. As shown in FIG. 17, in the wiring structure _10ML having a three-layer structure, the wiring layer 21A included in the wiring structure 10A protrudes from the insulating layer 3A, so that the wiring structure positioned on the wiring structure 10A. 10B insulating layer 3B and wiring layer 21A are engaged. Further, in the wiring layer 21A provided in the wiring structure 10A, the silane coupling agent layer 28 is located on the wiring 14 and the pad portion 15 exposed on the surface side of the insulating layer 3A via the alloy anchor layer 27. Adhesiveness between the insulating layer 3B and the wiring layer 21A of the wiring structure 10B located on the wiring structure 10A is sufficiently high. Similarly, since the wiring layer 21B included in the wiring structure 10B protrudes from the insulating layer 3B, the insulating layer 3C of the wiring structure 10C located on the wiring structure 10B is engaged with the wiring layer 21B. It has become. Further, in the wiring layer 21B provided in the wiring structure 10B, the silane coupling agent layer 28 is located on the wiring 14 and the pad portion 15 exposed on the surface side of the insulating layer 3B via the alloy anchor layer 27. The adhesion between the insulating layer 3C and the wiring layer 21B of the wiring structure 10C located on the wiring structure 10B is sufficiently high. Therefore, wiring structure 10 _ML of three-layer structure, the adhesion strength of the insulating layer 3B for the wiring layer 21A, are those high adhesion strength of the insulating layer 3C for the wiring layer 21B, which is excellent in insulation reliability, the wiring structure Excellent mutual adhesion. Unlike the conventional wiring structure in which the surface of the wiring and the surface of the pad portion are roughened in order to improve the adhesion between the wiring structures, the high frequency characteristics of the wiring are excellent.
In the above description, the wiring structure having a three-layer structure is taken as an example, but the number of constituent layers of the wiring structure having a multilayer structure is not particularly limited.

The above-described embodiment of the wiring structure is an example, and the present invention is not limited to this embodiment. For example, the silane coupling agent layer 28 on the alloy anchor layer 27 located in the pad portion 15 has an annular shape in plan view, exists at a predetermined width from the periphery of the alloy anchor layer 27, and is centered on the alloy anchor layer 27. It may not exist in the part. FIG. 18 shows an example having such a silane coupling agent layer as the above-described three-layer wiring structure 10 _ML , and FIG. 19 shows a single layer constituting the wiring structure 10 _ML . It is a fragmentary perspective view which shows a wiring structure (in the example of illustration, wiring structure 11A). As shown in FIGS. 18 and 19, the silane coupling agent layer 28 located on the pad portion 15 has a predetermined width W from the periphery to the center of the alloy anchor layer 27 having a circular shape in plan view. The existing planar view shape is annular. The width W of the silane coupling agent layer 28 is, for example, the interlayer connection of the upper wiring structure 10B at a portion where the silane coupling agent layer 28 does not exist and the alloy anchor layer 27 is exposed in the lower wiring structure 10A. The via 16 can be set to be connectable via the conductor barrier layer 18. In this way, the lower layer alloy anchor layer 27 and the upper interlayer connection via 16 (conductor barrier layer 18) are directly connected, so that the connection resistance in the interlayer connection can be further reduced. In this case, the thickness of the cyclic silane coupling agent layer 28 located on the pad portion 15 via the alloy anchor layer 27 and the thickness of the silane coupling agent located on the wiring 14 via the alloy anchor layer 27 exceeds 5 nm. It may be a thing. However, the width W of the silane coupling agent layer 28 is slightly large, and a part of the silane coupling agent layer 28 exists between the lower alloy anchor layer 27 and the upper interlayer connection via 16 (conductor barrier layer 18). It may be.

Moreover, in the above-described embodiment, the wiring structure includes one type of wiring in the cross-sectional shape, but may include two or more types of cross-sectional wiring.
Further, among the plurality of pad portions 15, there may be one connected to the wiring 14 and one separated from the wiring 14. The pad portion 15 that is separated from the wiring 14 becomes a dummy pad portion, but in order to ensure the strength uniformity in the plane of the wiring structure, the presence of the dummy pad portion that is separated from the wiring 14 exists. Is advantageous.

[Method for manufacturing wiring structure]
FIG. 20 is a process diagram for explaining an embodiment of a method for manufacturing a wiring structure according to the present invention, and shows an example of manufacturing the wiring structure 10 described above. In the method for manufacturing a wiring structure according to the present embodiment, the insulating layer forming step, the conductor barrier layer forming step, the conductor layer forming step, the polishing step, and the removing step are the same as those in the first embodiment. Is omitted. The structure shown in FIG. 20A is obtained using the same manufacturing method as in the first embodiment. The structure includes a wiring layer 21 including a wiring 14 positioned in the recess 4 of the insulating layer 3, a pad portion 15 positioned in the recess 5, and an interlayer connection via 16 positioned integrally with the pad portion 15 and positioned in the through hole 6. ing. The surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the surface 3 a of the insulating layer 3. The end 18 a of the conductor barrier layer 18 is at the same height as the surface 3 a of the insulating layer 3. That is, the surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the end portion 18 a of the conductor barrier layer 18.

Next, in an alloy anchor layer forming step, an alloy anchor layer 27 is formed on the surface of the wiring 14 exposed on the surface 3a side of the insulating layer 3 and the surface of the pad portion 15 (FIG. 20B). Formation of the alloy anchor layer 27 can be performed by immersing it in a displacement plating solution. For example, when a copper tin alloy layer is formed as the alloy anchor layer 27, copper is eluted and tin is deposited on the surface of the wiring 14 and the surface of the pad portion 15 by dipping in a substitution tin plating solution. A copper-tin alloy layer can be formed. In this case, since tin has a lower potential than copper, a substituted tin plating solution containing a chemical that lowers the potential of copper is used. As such a substitution tin plating solution, for example, Mec Co., Ltd. flat bond GT etc. can be mentioned.

In the alloy anchor layer 27 (copper tin alloy layer) formed in this way, tin is alloyed with copper and unevenly distributed on the surface side in the thickness direction. Thereby, a copper tin alloy layer expresses favorable adhesive strength with respect to the wiring 14 and the pad part 15 which consist of copper. On the other hand, a hydroxyl group is imparted to the surface of the alloy anchor layer 27 by tin unevenly distributed on the surface of the copper-tin alloy layer. Therefore, in the formation of the silane coupling agent layer 28 to be described later, it becomes easy for the silicon atoms of the silane coupling agent to be bonded to the alloy anchor layer 27 via the oxygen atoms, and the silane coupling agent layer 28 is bonded to the alloy anchor layer. 27 can be fixed to the wiring 14 and the pad portion 15 with good adhesion. Further, since tin has a lower diffusibility to the insulating layer 3 than copper, the surface side of the copper tin alloy layer also has a function as a conductor barrier layer for copper as a conductor.

In forming the alloy anchor layer 27 using the displacement plating solution, the alloy anchor layer 27 can be formed to have a thickness in the range of 50 to 100 nm, preferably in the range of 60 to 80 nm. When the thickness of the alloy anchor layer 27 to be formed is less than 50 nm, the action of the alloy anchor layer 27, that is, the action of fixing the silane coupling agent layer 28 on the wiring 14 and the pad portion 15 with a good adhesion force, the wiring 14 In some cases, the effect of suppressing the diffusion of the conductor from the pad portion 15 may be insufficient. On the other hand, if it exceeds 100 nm, further improvement of the above-described action of the alloy anchor layer 27 cannot be obtained, cracks are likely to occur due to film stress, and the time required for forming the alloy anchor layer is undesirably increased.
Moreover, when forming the alloy anchor layer 27 using a displacement plating solution, the alloy anchor layer 27 can be formed stably by including at least one kind of nickel or the like in the displacement tin plating solution. For example, since nickel suppresses substitution of tin and copper by forming a tin-nickel alloy, it is easy to control the alloy anchor layer to be formed to have a desired thickness.
Next, in the silane coupling agent layer forming step, a silane coupling agent layer 28 is formed on the alloy anchor layer 27 (FIG. 20C). In the illustrated example, the silane coupling agent layer 28 is indicated by a thick line.

The silane coupling agent layer 28 can be formed by bringing a silane coupling agent into contact with the insulating layer 3 including the alloy anchor layer 27 and then washing. In the silane coupling agent in contact with the alloy anchor layer 27, the silicon atoms move to the surface of the alloy anchor layer 27 through hydrogen bonds with the hydroxyl group imparted to the surface of the alloy anchor layer 27 as described above. Through the dehydration condensation reaction, a strong covalent bond is generated with the surface of the alloy anchor layer 27, and the silane coupling agent layer 28 is formed. And since the reactive functional group which reacts with an organic component has couple | bonded with the silicon atom of the silane coupling agent layer 28 formed in this way, wiring 14 of this wiring structure, pad part 15 and The adhesion of the upper wiring structure 10 to the insulating layer 3 is sufficiently high.

The silane coupling agent to be used can be appropriately selected. The reactive functional group of the silane coupling agent is, for example, from the group consisting of an amino group, an epoxy group, a mercapto group, a sulfide group, an acyl group, an acetyl group, a methacryl group, a vinyl group, a carboxylic acid, and an unsaturated hydrocarbon group. There may be mentioned selected groups, which are bonded to the silicon atom via a bond-(CH ₂ ) _n- . N in the bond is an integer of 1 to 10, but the molecular weight is preferably low in order to make it more uniform than the thickness of the silane coupling agent layer 28. Therefore, n is preferably in the range of 1 to 3. The thickness of the silane coupling agent layer 28 to be formed is 5 nm or less, preferably a monomolecular layer of the silane coupling agent. If the thickness of the silane coupling agent layer 28 to be formed exceeds 5 nm, the electrical resistance between the pad portion 15 and the interlayer connection via in the wiring structure laminated on the wiring structure 10 is not preferable.

Thereby, the wiring structure 10 is obtained. This wiring structure 10 includes a wiring layer 21 including a wiring 14 located in the concave portion 4 of the insulating layer 3, a pad portion 15 located in the concave portion 5, and an interlayer connection via 16 located integrally with the pad portion 15 and located in the through hole 6. It has. The surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the surface 3 a of the insulating layer 3. The end 18 a of the conductor barrier layer 18 is at the same height as the surface 3 a of the insulating layer 3. That is, the surface 14 a of the wiring 14 and the surface 15 a of the pad portion 15 are in a state of protruding from the end portion 18 a of the conductor barrier layer 18. Further, in this wiring structure 10, a silane coupling agent layer 28 is located at a portion exposed from the insulating layer 3 of the wiring 14 and the pad portion 15 via an alloy anchor layer 27. Accordingly, when the wiring structure 10 is laminated to form a multilayer structure, the wiring 14 and the pad portion 15 of the lower wiring structure 10 and the upper wiring structure 10 are formed due to the presence of the silane coupling agent layer 28. Adhesiveness with the insulating layer 3 is sufficiently high. As a result, it is not necessary to roughen the surfaces of the wiring 14 and the pad portion 15, the rough surface does not exist along the longitudinal direction of the wiring, and the high-frequency characteristics of the wiring are excellent. The connection between the pad portion and the upper interlayer connection via becomes stable. Furthermore, by such cooperation of the high adhesion and the conductor barrier function by the conductor barrier layer 18 and the alloy anchor layer 27, the insulation reliability between the wires or between the wires and the pads is excellent, and the high pitch is achieved by the narrow pitch. Densification is possible.
In the case where the conductor barrier layer 18 remains at the bottom of the through hole 6 for forming the interlayer connection via and the base material 2 has wiring and pad portions, between these and the interlayer connection via 16 in the through hole 6. The conductor barrier layer 18 is interposed between the two. However, since the thickness of the conductor barrier layer 18 is in the range of 50 to 100 nm as described above, even if the surface resistance is several tens of Ω / □ or more, the conductive function of the interlayer connection via is not affected. Absent.

In the present invention, the wiring structure can be formed in multiple layers by repeating the above-described series of steps a desired number of times. For example, by repeating the above series of steps three times, a wiring structure _10ML having a three-layer structure as shown in FIG. 17 can be manufactured. In this case, the silane coupling agent layer 28 exists between the pad portion 15 of the lower wiring structure and the interlayer connection via 16 of the upper wiring structure, but as described above, the silane coupling agent layer 28. Therefore, even if the surface resistance is 1000Ω / □ or more, the conduction function of the interlayer connection via is not hindered.

Further, in the case where the wiring structure is laminated in multiple layers, as shown in FIG. 18 and FIG. 19, the silane coupling agent layer 28 on the alloy anchor layer 27 located in the pad portion 15 has an annular shape. A structure that has an annular shape in plan view and exists at a predetermined width from the periphery of the alloy anchor layer 27 and does not exist at the center of the alloy anchor layer 27 can be formed as follows. For example, a case where the upper wiring structure 10B is formed on the wiring structure 10A will be described. In the step of forming the insulating layer of the wiring structure 10B, the silane coupling agent layer 28 of the lower wiring structure 10A is exposed in the through hole 6 when the through hole 6 for forming the interlayer connection via is formed. By removing the exposed silane coupling agent layer 28 by dry etching, the silane coupling agent layer 28 included in the wiring structure 10A is electrically connected to the interlayer connection via of the upper wiring structure 10B. The silane coupling agent layer 28 may have an annular shape in plan view and may be present at a predetermined width from the periphery of the alloy anchor layer 27 and may not be present at the center of the alloy anchor layer 27.

A silane cup that forms an etching resist pattern on the wiring structure 10A and is electrically connected to the interlayer connection via of the upper wiring structure 10B in the silane coupling agent layer 28 included in the wiring structure 10A. With regard to the ring agent layer 28, a desired portion at the center is exposed, and the exposed silane coupling agent layer 28 is removed by dry etching to form a silane coupling agent layer 28 having a circular shape in plan view. Thereafter, an upper wiring structure 10B may be formed. The silane coupling agent layer 28 in the uppermost wiring structure 10C of the three-layer wiring structure _10ML shown in FIG. 18 can be formed by such a method.

[Electronic device]
21 is a schematic partial cross-sectional view showing an embodiment of the electronic device of the present invention, and FIG. 22 is a partially enlarged cross-sectional view of a portion surrounded by a circle in FIG. 21 and 22, an electronic device 200 is obtained by forming a multilayer wiring structure 10 _ML on a core substrate 131 and mounting

semiconductor elements

111 and 112 via connection pads 171. In this embodiment, the multilayer wiring structure 10 _ML is the above-described wiring structure of the present invention, and such a multilayer wiring structure 10 _ML can be manufactured by the manufacturing method of the present invention. The description in is omitted.
In FIG. 21, in order to avoid drawing from being complicated, the insulating layer 3A is an interlayer insulating layer constituting the multilayer wiring structure _{10 ML, 13B, 13C, 13D} , and a solder resist 161, a sealing The resin 162 is not shaded. The

semiconductor elements

111 and 112 can be, for example, memory elements, logic elements, etc., but in the illustrated example, they are uniformly shaded regardless of their structures.
The core substrate 131 has a multilayer structure in which a core base material 132 and a plurality of conductor layers 135 are laminated on both surfaces of the core base material 132 with an insulating layer 34 interposed therebetween.

The core base material 132 includes a plurality of front and back conductive via portions 133 penetrating the core base material 132 and the surface of the core base material 132 (in the illustrated example, the surface side on which the multilayer wiring structure _10ML is disposed). , A conductor layer 133a connected to a predetermined front / back conduction via portion 133, and a conductor layer 133a ′ connected to a predetermined front / back conduction via portion 133 on the back surface of the core base material 132. Such a core substrate 132 may be, for example, glass, glass cloth-containing epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, silicon, or the like.

Conductive layers

135A and 135B are laminated on the surface side of the core base material 132 via insulating

layers

34A and 134B. The conductor layer 133a positioned above and below the conductor layer 135A is connected by an interlayer connector 136A via the insulating layer 34A, and the conductor layer 135A and conductor layer 135B positioned vertically via the insulating layer 34B are connected by the interlayer connector 136B. Connected with.

Further, conductor layers 135A ′, 135B ′, and 135C ′ are laminated on the back surface side of the core base material 132 through insulating layers 34A ′, 134B ′, and 134C ′. The conductor layer 133a 'positioned above and below the conductor layer 135A' via the insulating layer 34A 'is connected by the interlayer connector 136A', and the conductor layer 135A 'positioned above and below the conductor layer via the insulating layer 34B'. 135B 'is connected by an interlayer connector 136B', and the conductor layer 135B 'positioned above and below the conductor layer 135C' is connected by an interlayer connector 136C 'via an insulating layer 34C'. Further, a solder resist 138 is disposed so as to expose a desired portion of the conductor layer 135C ′, and a solder ball 151 is located on the exposed conductor layer 135C ′ via a nickel layer 141 and a gold layer 142.

The conductor layer 135B located on the surface side of the core substrate 131 is a pad portion, and the surface of the conductor layer 135B is exposed on the surface flattened by the flattening resin 137. A multilayer wiring structure _10ML is disposed so as to be connected to the conductor layer 135B (pad portion). Wiring structure 10 _ML of this multilayer wiring layers 21A, 21B, 21C, has a wiring layer 21 made of four layers of 21D, the semiconductor device via the connection pads 171 on the pad portion of the

wiring layer 21C

111 , 112 are implemented. In the illustrated example, the nickel layer 146 on the pad portion of the wiring layer 21C of the multilayer wiring structure 10 _ML, with the gold layer 147 is provided, a solder resist as the nickel layer 146, a gold layer 147 is exposed 161 is disposed. The connection pad 171 connects the gold layer 147 and the

terminals

111a and 112a of the

semiconductor elements

111 and 112 by thermocompression bonding. Further, the gap between the

semiconductor elements

111 and 112 and the multilayer wiring structure 10 _ML is a sealing resin 162 which is heated and cured to fill the thermosetting resin is filled.

In addition, the electronic device of the present invention may include a multilayer wiring structure 10 ′ _ML as shown in FIG. FIG. 23 is a partial enlarged cross-sectional view of an electronic device corresponding to FIG. The multilayer wiring structure 10 ′ _ML in the electronic device 200 ′ shown in FIG. 23 has a three-layer structure having

wiring layers

21A, 21B, and 21C, and bumps are formed on the uppermost wiring layer 21C and insulating layer 3C. 19A, an insulating layer 3D having a through hole 19B for an interlayer connection via located in the recess 19A, a bump 29A located in the recess 19A, and an interlayer connection via 29B located in the through hole 19B It is. The surface of the bump 29A protrudes from the surface of the insulating layer 3D, and the

terminals

111a and 112a of the

semiconductor elements

111 and 112 are connected to the bump 29A via the connection pads 171. . A gap between the

semiconductor elements

111 and 112 and the wiring structure 10 ′ _ML is filled with a sealing resin 162 that is filled with a thermosetting resin and heat-cured. Such an electronic device 200 ′ does not require the formation of the nickel layer 146 and the gold layer 147, and the configuration of the mounting portion of the

semiconductor elements

111 and 112 via the connection pads 171 is simpler than that of the electronic device 200. Thus, the number of processes is reduced, and the material cost can be reduced.

FIG. 24 is a schematic partial cross-sectional view showing another embodiment of the electronic device of the present invention. 24, the electronic device 201 includes a multilayer wiring structure 10 on a resin-encapsulated semiconductor element 211 in which

semiconductor elements

221 and 222 are encapsulated with an encapsulating resin 231 so that

terminals

221a and 222a are exposed. _ML is formed and solder balls 261 are disposed. In this embodiment, the multilayer wiring structure 10 _ML is the above-described wiring structure of the present invention, and such a multilayer wiring structure 10 _ML can be manufactured by the manufacturing method of the present invention. The description in is omitted.

The

semiconductor elements

221, 222 can be, for example, memory elements, logic elements, etc., but in the illustrated example, they are uniformly hatched regardless of their structures.
The multilayer wiring structure _10ML has a wiring layer 21 including three

wiring layers

21A, 21B, and 21C, and includes a through hole 241A for an interlayer connection via on the wiring layer 21C and the insulating layer 3C. An insulating layer 231, an interlayer connection via 241 located in the through hole 241 A, and a bump 245 located on the insulating layer 231 connected to the interlayer connection via 241 are provided. Solder balls 261 are located on the bumps 245 with the nickel layer 251 and the gold layer 252 interposed therebetween.
In addition, as shown in FIG. 25, the electronic device of the present invention may be an electronic device 201 ′ in which a solder resist 271 is disposed so that the solder balls 261 are exposed.

FIG. 26 is a schematic partial cross-sectional view showing another embodiment of the electronic device of the present invention. In FIG. 26, the electronic device 301 forms the single-layer wiring structure 10 on the resin-encapsulated semiconductor element 311 in which the semiconductor element 321 is encapsulated with an encapsulating resin 331 so that the terminal 321a is exposed. The solder balls 361 are disposed. In this embodiment, the single-layer wiring structure 10 is the above-described wiring structure of the present invention, and such a wiring structure 10 can be manufactured by the manufacturing method of the present invention. Is omitted.
The single-layer wiring structure 10 has a wiring layer 21 including wirings 14, pad portions 15, and interlayer connection vias 16, and solder balls 361 are located on the desired pad portions 15.
In the electronic device 301 in which the wiring layer 21 is a single layer, a silane coupling agent layer (not shown) is formed on the wiring 14 and the pad portion 15 of the wiring structure 10 via an alloy anchor layer (not shown). However, such a silane coupling agent layer has an effect of improving the adhesion with an epoxy-based mold sealing resin when mounting a semiconductor chip.

Such an electronic device of the present invention has excellent high-frequency characteristics of wiring, enables high-density wiring, and is excellent in adhesion between the wiring structures constituting the circuit, and has high reliability.
The above-described embodiment of the electronic device is an exemplification, and the present invention is not limited to the embodiment. For example, the multilayer wiring structure 10 _ML and the silane coupling agent layer 28 constituting the single-layer wiring structure 10 have an annular shape in plan view, and exist with a predetermined width from the periphery of the alloy anchor layer 27. A structure that does not exist in the central portion of the alloy anchor layer 27 may be used.

Next, the present invention will be described in more detail with reference to examples.
[Example 1]
First, as an imprint mold, a concavo-convex structure having a convex portion with a height of 2 μm from the main surface was provided on one surface of a mold substrate made of 675 μm thick quartz glass (65 mm square). A mold was prepared. The concavo-convex structure provided in this mold is composed of two types of convex portions, ie, a convex portion having a linear shape in plan view and a convex portion having a circular shape in plan view. The linear convex portion was a line / space (5 μm / 5 μm) shape. The circular convex portion had a diameter of 30 μm and existed at a density of 225 pieces / mm ² (65 μm pitch). Further, a light shielding layer made of a chromium thin film having a diameter of 20 μm is located at a substantially central portion of the top plane of the convex portion having a circular shape in plan view.

Next, an insulating layer was formed using the above-mentioned imprint mold (insulating layer forming step). That is, a silicon substrate was prepared as a transfer substrate, and a chromium titanium thin film and a copper thin film were laminated on the surface of the transfer substrate by sputtering. Next, an epoxy-based UV-curable insulating resist solution (SU-8 3000 series manufactured by Nippon Kayaku Co., Ltd.) is supplied onto the copper thin film on the surface of the transfer substrate so that the film thickness after post-baking is about 6 μm. After coating, the resist film was obtained by drying by soft baking using a hot plate. Next, the mold is pressed against the resist film, and in this state, an ultraviolet ray of a parallel light component including a wavelength component of 350 to 405 nm is irradiated from the back side of the mold to generate acid at a selected portion of the resist film, and then PEB (Post The resist film was first-cured by heat treatment using exposure (bake). Thereafter, the mold is pulled off, and development processing is performed with PM thinner (propylene glycol monomethyl ether acetate) to form a pattern structure on the transfer substrate, followed by post-baking (nitrogen atmosphere 180 ° C., 60 minutes) for secondary curing. went. Thereby, an insulating layer was formed on the silicon substrate (see FIG. 4B). This insulating layer has a recess for forming a wiring in the shape of a line / space (5 μm / 5 μm), a recess for forming a pad portion having a diameter of 30 μm, and a through-hole having a diameter of 20 μm located at a substantially central portion of the recess. The copper thin film was exposed in the through hole.

Next, in the conductor barrier layer forming step, the inner wall surface of the wiring forming recess, the surface of the insulating layer including the recess for forming the pad portion and the inner wall surface of the through hole for forming the interlayer connection via, and the through hole are exposed. On the copper thin film, a chromium layer (thickness 15 nm) and a titanium layer (thickness 50 nm) were laminated in this order by a sputtering method to form a conductor barrier layer (Cr / Ti composite layer) (see FIG. 4C). The chromium layer had a Vickers hardness of 1.06 GPa, and the titanium layer had a Vickers hardness of 1.3 GPa.
Next, in the conductor formation step, a copper thin film (thickness 200 nm) is formed on the conductor barrier layer by sputtering to form a seed electrode layer, and copper is deposited by electroplating using this seed electrode layer as a plating electrode. A conductor made of copper (Vickers hardness: 0.8 GPa) so as to fill a recess for forming a wiring, a recess for forming a pad, and a through hole for forming an interlayer connection via located in the recess for forming the pad A layer was formed (see FIG. 5A). This conductor layer was formed to be about 3 μm thicker than the insulating layer.
Next, the conductor layer was polished by CMP (polishing step). In this polishing, the conductor barrier layer acted as a polishing stopper (see FIG. 7).

Next, in the removing step, the exposed conductor barrier layer located on the surface of the insulating layer was removed (see FIG. 5C). That is, first, the titanium layer was removed by flash etching using a mixed solution of potassium hydroxide and hydrogen peroxide, and then the chromium layer was removed by flash etching using an aqueous potassium ferricyanide solution.
Thereby, a wiring structure was manufactured on the silicon substrate. In this wiring structure, the surface of the wiring and the surface of the pad portion protruded 65 nm from the insulating layer. The edge part of the conductor barrier layer was the same height as the surface of the insulating layer. Moreover, the thickness of the insulating layer was 6 μm, and it was confirmed that it had the expected thickness.

On this wiring structure, the above-mentioned ultraviolet curable insulating resist solution is supplied and coated so that the film thickness after post-baking is about 6 μm, and then dried by soft baking using a hot plate. A membrane was obtained. Next, the resist film was irradiated with ultraviolet rays having a parallel light component including a wavelength component of 350 to 405 nm, and the same primary curing and secondary curing as described above were performed to form an insulating layer. Thereafter, the peel strength of this insulating layer was measured under the following conditions. As a result, it was 0.38 kN / m, and when the wiring structures were laminated, it was confirmed that good adhesion between the wiring structures was obtained. .
(Measurement of peel strength)
In accordance with JIS C 6481-1996, a 10 mm wide test piece is provided with a peeling margin at the end, and the portion is gripped and pulled in the direction of 90 degrees at a speed of 20 mm / sec. It was measured.

[Example 2]
In the conductor barrier layer forming step, a molybdenum alloy layer (thickness 50 nm) is formed by a sputtering method using a MoNiTi alloy (MTD-54 manufactured by Hitachi Metals, Vickers hardness: 1.53 GPa) as a target. A wiring structure was manufactured in the same manner as in Example 1 except that the molybdenum alloy layer was removed by flash etching using a mixed solution of potassium hydroxide and hydrogen peroxide. In this wiring structure, the surface of the wiring and the surface of the pad portion protruded from the insulating layer by 50 nm. The edge part of the conductor barrier layer was the same height as the surface of the insulating layer. Moreover, the thickness of the insulating layer was 6 μm, and it was confirmed that it had the expected thickness.
On this wiring structure, an insulating layer was formed in the same manner as in Example 1, and then the peel strength of this insulating layer was measured. As a result, it was 0.38 kN / m. It was confirmed that good adhesion between structures was obtained.

[Comparative Example 1]
In the conductor barrier layer forming step, an aluminum layer (thickness: 100 nm, Vickers hardness: 0.17 GPa) is formed by a sputtering method instead of the chromium layer / titanium layer in Example 1 to form a conductor barrier layer. Thereafter, the conductor forming step was performed in the same manner as in Example 1.
Next, in the same manner as in Example 1, the conductor layer was polished by CMP. In this polishing, the conductor barrier layer does not act as a polishing stopper, and the polishing cannot be stopped when the conductor layer on the insulating layer is polished. The polishing proceeds to the insulating layer, and the thickness of the insulating layer is 4 As a result, the insulating layer was thinner than those in Examples 1 and 2.
Through the above polishing process, a wiring structure was obtained in which the surface of the wiring and the surface of the pad portion were flush with the surface of the insulating layer. The edge part of the conductor barrier layer was the same height as the surface of the insulating layer.
On this wiring structure, an insulating layer was formed in the same manner as in Example 1, and then the peel strength of this insulating layer was measured. As a result, it was 0.15 kN / m. It was confirmed that the adhesion between the structures was inferior to the wiring structures of Examples 1 and 2.

[Comparative Example 2]
A wiring structure was manufactured in the same manner as in Comparative Example 1. Next, a roughening process using a hydrogen peroxide-sulfuric acid based chemical solution was performed to roughen the surface of the wiring and the surface of the pad portion, thereby obtaining a wiring structure. As a result of measuring the average roughness of the surface of the wiring and the surface of the pad portion before and after the roughening treatment using a surface roughness meter, it was confirmed that the average roughness increased from 21 nm to 110 nm.
On this wiring structure, an insulating layer was formed in the same manner as in Example 1, and then the peel strength of this insulating layer was measured. As a result, it was 0.32 kN / m. From this result, when the wiring structures are stacked, the wiring structures of Examples 1 and 2 can have the same or better adhesion than the conventional wiring structures in which the surface of the wiring and the surface of the pad portion are roughened. Was confirmed.

[Comparative Example 3]
In the conductor barrier layer forming step, the chromium layer (thickness 15 nm, Vickers hardness: 1.06 GPa) and nickel layer (thickness 50 nm, Vickers hardness: 0) are formed by sputtering instead of the chromium layer / titanium layer of Example 1. .9 GPa) to form a conductor barrier layer.
However, the film stress of the nickel layer is large, the adhesion between the conductor barrier layer and the epoxy insulating layer cannot be obtained, the conductor barrier layer is peeled off, and the process cannot proceed.

Applicable for manufacturing various wiring structures and electronic devices.

_{_{1,1 ML, 1 ML ', 1A}} , 1B, 1C, 10,10 ML, 10 ML', 10A, 10B, 10C ... wiring structure 2 ...

substrate

3, 3A, 3B, 3C ... insulating layer 4 ... wire Recesses for forming 5 ... Recesses for forming pad parts 6 ... Through holes for forming interlayer connection vias 11, 11A, 11B, 11C ... Wiring layer 14 ... Wiring 14a ... Surface of wiring 15 ... Pad part 15a ... Surface of pad part DESCRIPTION OF SYMBOLS 16 ... Interlayer connection via 18 ... Conductor barrier layer 100,100 ', 200,200' ... Electronic device 31 ... Core substrate 51 ... Imprint mold 91 ... Photolithographic mask 101,111,112 ... Semiconductor element

Claims

A first insulating layer having a recess in the first surface;
A first conductor layer located in the recess and protruding from the first surface;
A wiring structure having a conductor barrier layer interposed between the first conductor layer and the first insulating layer.
A first insulating layer having a recess in the first surface;
A first conductor layer located in the recess and protruding from the first surface;
A conductor barrier layer interposed between the first conductor layer and the first insulating layer;
And an alloy anchor layer located on the first conductor layer exposed on the first surface.
The wiring structure according to claim 1 or 2, further comprising a base material positioned on a second surface opposite to the first surface.
The wiring structure according to claim 3, further comprising a second insulating layer located on the first surface.
The wiring structure according to claim 4, wherein, in the first surface, the height of the first conductor layer in the stacking direction is higher than the height of the conductor barrier layer.
5. The wiring structure according to claim 4, wherein the first conductor layer is copper, and the conductor barrier layer is a chromium / titanium composite layer or a molybdenum alloy layer.
The wiring structure according to claim 4, wherein the conductor barrier layer has a thickness in the range of 50 to 100 nm.
The wiring structure according to claim 2, further comprising a silane coupling agent layer located on the alloy anchor layer.
The wiring structure according to claim 2, wherein the alloy anchor layer is a copper tin alloy layer or a copper tin nickel alloy layer.
The wiring structure according to claim 2, wherein the alloy anchor layer has a thickness in a range of 50 to 100 nm.
A first through-hole penetrating the first insulating layer and connected to the recess;
A second through hole penetrating the second insulating layer and connected to the recess;
A second conductor layer located in the second through hole and electrically connected to the first conductor layer;
The said 1st conductor layer is located in the said recessed part and the said 1st through-hole, and the said conductor barrier layer is interposed between the said 1st conductor layer and the said 1st insulating layer. Wiring structure.
The wiring structure according to claim 11,
A core substrate electrically connected to the first conductor layer;
An electronic device comprising: a semiconductor element electrically connected to the second conductor layer.
An insulating layer forming step of forming an insulating layer having a recess on the first surface on the substrate;
A conductor barrier layer forming step of forming a conductor barrier layer on the first surface including the inner wall surface of the recess;
Forming a seed electrode layer so as to cover at least the conductor barrier layer, and forming a conductor layer on the seed electrode layer by electroplating; and
A polishing step of polishing the conductor layer using the conductor barrier layer on the first surface as a stopper;
And a removing step of removing the conductor barrier layer on the first surface.
The wiring structure according to claim 13, further comprising an alloy anchor layer forming step of forming an alloy anchor layer on the conductor layer by immersing the first surface in a displacement plating solution after the removing step. Manufacturing method.
The method for manufacturing a wiring structure according to claim 14, wherein in the alloy anchor layer forming step, the alloy anchor layer is a copper tin alloy layer or a copper tin nickel alloy layer.
After the alloy anchor layer forming step, a silane coupling agent layer is formed on the alloy anchor layer by bringing a silane coupling agent into contact with the first surface and then washing. The method for manufacturing a wiring structure according to claim 15, further comprising a step.
The method for manufacturing a wiring structure according to claim 13 or 14, wherein, in the insulating layer forming step, the recess is formed by using an imprint method.
The method for manufacturing a wiring structure according to claim 13 or 14, wherein, in the insulating layer forming step, the concave portion is formed using a photolithography method.
The method for manufacturing a wiring structure according to claim 13 or 14, wherein the conductor layer is chemically polished in the polishing step.
20. The method for manufacturing a wiring structure according to claim 19, wherein, in the polishing step, the conductor layer is chemically polished and then further subjected to chemical mechanical polishing.
21. The method of manufacturing a wiring structure according to claim 20, wherein in the polishing step, chemical polishing is performed such that the selectivity of the conductor layer is higher than that of the conductor barrier layer.
15. The method for manufacturing a wiring structure according to claim 13, wherein the conductor layer is subjected to chemical mechanical polishing in the polishing step.
The method for manufacturing a wiring structure according to claim 22, wherein the conductor barrier layer has a hardness larger than a hardness of the conductor layer.
In the conductor barrier layer forming step, the conductor barrier layer is either a chromium / titanium composite layer or a molybdenum alloy layer,
The method for manufacturing a wiring structure according to claim 13 or 14, wherein, in the conductor layer forming step, the conductor layer is copper.