TWI450371B - Semiconductor device and manufacture method thereof - Google Patents

Description

Semiconductor device and method of manufacturing same

This invention relates to semiconductor technology, and more particularly to an image sensor device.

In the wafer level packaging process of a semiconductor, a post passivation interconnection (PPI) is formed to re-stamp the solder joint on the wafer, and the chip package is reduced by the effective use of the surface area of the wafer. volume. The inner protective layer structure of the rear protective layer usually comprises a redistributed circuit layer and a protective layer thereof, and one end of the redistributed wiring layer is not covered by the protective layer. In this case, the interconnect structure of the protective layer tends to be poor in adhesion between the redistributed circuit layer and the protective layer, and the connection structure of the outer connecting end of the redistributed circuit layer is not well connected to the end point. This causes a problem of poor reliability of the packaged semiconductor device.

On the other hand, as the circuit density increases and the size is reduced in the semiconductor wafer, the number of layers of the metal wiring pattern must also be increased, and the pitch must be reduced to effectively connect the separate components in the semiconductor wafer. The plurality of layers are referred to as an interlayer insulating (ILD) insulating film or insulating material for separating metal interconnects of different layers. Cerium oxide is often used as an ILD layer with a dielectric constant of 4.0 to 4.5 (vacuum is 1). However, as the pitch of the metal wires is reduced, since the capacitance value is inversely proportional to the wire pitch, the capacitance value within the layer or between the layers is also increased, and the RC delay time is increased. Since the RC delay time will be transmitted to the signal in the circuit Time has an adverse effect. Therefore, it is necessary to reduce the dielectric constant of the insulating material between the metal wires to reduce the RC delay time and to improve the performance of the circuit such as the clock.

When an insulating material having a dielectric constant of less than 3, commonly referred to as a low dielectric constant material, is used as an interlayer dielectric layer between metal wires, the adhesion strength between the metal and the metal is lower than that between the cerium oxide and the metal. Adhesion strength. Therefore, in the process of semiconductor package or in the subsequent application of the packaged semiconductor device, the interlayer dielectric layer of the low dielectric constant material is often peeled off due to external mechanical stress, thereby damaging the device. The effectiveness of the device even invalidates the device.

In view of the above, a preferred embodiment of the present invention provides a semiconductor device and a method of fabricating the same, which can improve the semiconductor by improving the adhesion between the rewiring circuit layer and the protective layer and improving the structure of the protective layer. The reliability of the device.

Another preferred embodiment of the present invention provides a semiconductor device and a method of fabricating the same that can avoid or reduce the problem of peeling of an interlayer dielectric layer of a low dielectric constant material by buffering external mechanical stress.

A preferred embodiment of the present invention provides a semiconductor device comprising: a semiconductor wafer having a first surface; a conductive electrode exposed to the first surface; and a protective layer covering the semiconductor wafer, The protective layer has a protective layer penetrating through the conductive electrode; a redistributed circuit layer is disposed on the protective layer, and the redistributed circuit layer passes through the The protective layer opening is electrically connected to the conductive electrode, the redistributed wiring layer has an aluminum layer; a nickel/gold layer is on the upper surface of the aluminum layer of the redistribution wiring layer; and a solder resist layer is disposed on the protective layer On the redistribution circuit layer, an end of the redistribution circuit layer and the nickel/gold layer above it are exposed.

Another embodiment of the present invention further provides a semiconductor device comprising: a semiconductor wafer having a first surface; a first conductive electrode and a second conductive electrode exposed to the first surface; a protective layer On the first surface of the semiconductor wafer, the protective layer has a first protective layer opening and a second protective layer opening therethrough, and is respectively located on the first conductive electrode and the second conductive electrode; a metal layer is embedded in the protective layer, the metal layer is electrically connected to the second conductive electrode, but is electrically isolated from the first conductive electrode by the protective layer; a first redistributed circuit layer is disposed on the protective layer The first redistribution circuit layer is electrically connected to the first conductive electrode via the first protective layer opening, the first redistribution circuit layer has a first aluminum layer; and a nickel/gold layer is disposed on the first redistribution line An upper surface of the layer; a second redistribution circuit layer is electrically connected to the second conductive electrode via the second protective layer opening, and the second redistribution circuit layer has a a second aluminum layer; a nickel/gold layer in the An upper surface of the first aluminum layer of the wiring layer and an upper surface of the second aluminum layer of the second redistribution layer; and a solder resist layer on the protective layer, the first redistribution layer, and Exposing a first end point of the first redistribution circuit layer and the nickel/gold layer above the first redistribution circuit layer, and a second end point of the second redistribution circuit layer The nickel/gold layer above.

Another preferred embodiment of the present invention further provides a method of fabricating a semiconductor device, comprising: providing a semiconductor wafer having at least one semiconductor wafer having a conductive electrode exposed to the semiconductor wafer Forming a protective layer on the first surface of the semiconductor wafer, the protective layer having a protective layer penetrating through the conductive electrode; forming a redistributed wiring layer on the protective layer, the redistributing circuit layer Electrically connecting the conductive electrode via the protective layer opening, the redistributed wiring layer has an aluminum layer and a TiW layer on the lower surface of the aluminum layer; and plating an upper surface of the aluminum layer on the redistribution wiring layer a nickel/gold layer; and forming a solder resist layer on the protective layer and the redistribution wiring layer, exposing an end point of the redistribution wiring layer and the nickel/gold layer thereon; wherein the protective layer is formed The method further includes: forming a first protective film on the semiconductor wafer, the first protective film having a first opening penetrating the conductive electrode; forming a metal layer on the first protective film; open Filling a sacrificial layer; providing a solution having an electrically coated insulating material; immersing the semiconductor wafer in the solution to adhere the electrocoated insulating material to the metal other than the sacrificial layer Forming a second protective film on the second surface opposite to the first surface of the semiconductor wafer; and removing the sacrificial layer to have the second protective film have a second through Opening to the conductive electrode, the second opening serves as the protective layer opening.

Another preferred embodiment of the present invention further provides a method of fabricating a semiconductor device, comprising: providing a semiconductor wafer having at least one semiconductor wafer, the semiconductor wafer having a first conductive electrode and a first The second conductive electrode is exposed on a first surface of the semiconductor wafer; a first protective film is formed on the semiconductor wafer, the first protective film has a first opening exposing the first conductive electrode, and a second opening Exposing the second conductive electrode; forming a resist material covering the first conductive electrode exposed to the first opening, and the second conductive electrode is still exposed to the second opening; on the first protective film, the resistor Depositing a metal layer on the sidewall of the second opening and the exposed second conductive electrode; removing the resist material and simultaneously removing the metal layer formed on the resist material; a discontinuous metal layer is disposed on the first protective film outside the first opening and extends into the second opening; a sacrificial layer is filled in each of the first opening and the second opening; Providing a solution having an electrically coated insulating material; dipping the semiconductor wafer into the solution to adhere the electrically coated insulating material to the discontinuous metal layer other than the sacrificial layers, and The semiconductor wafer and the first Forming a second protective film on a second surface opposite to the surface; removing the sacrificial layers, and causing the second protective film to have a third opening to expose the first conductive electrode and a fourth opening to expose The discontinuous metal layer on the second conductive electrode; forming a first redistribution circuit layer and a second redistribution circuit layer on the second protective film, the first redistribution circuit layer is electrically connected via the third opening Connecting the first conductive electrode, the second redistribution circuit layer is electrically connected to the second conductive electrode via the fourth opening, the first redistribution circuit layer has a first aluminum layer And a first TiW layer on the lower surface of the first aluminum layer, the second redistribution wiring layer has a second aluminum layer and a second TiW layer on the lower surface of the second aluminum layer; Depositing a nickel/gold layer on the upper surface of the first aluminum layer of the first redistribution circuit layer and the second aluminum layer of the second redistribution circuit layer; forming a solder resist layer Exposing a first end point of the first redistribution layer and the nickel/gold layer on the first redistribution layer and the second redistribution layer A second end of the wiring layer and the nickel/gold layer above it.

The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A semiconductor wafer 100 is shown. The semiconductor wafer 100 is a wafer that has completed an integrated circuit process and has a plurality of semiconductor wafers 101. The semiconductor device of the preferred embodiment of the present invention is a wafer-level package as an example, and its structure and characteristics are described, that is, products obtained by directly packaging the entire semiconductor wafer 100 after completing the integrated circuit process. In this embodiment, the semiconductor wafer 100 is a germanium wafer; in other embodiments, the semiconductor wafer 100 may also be other elemental or compound semiconductor wafers, such as germanium, germanium, gallium arsenide, or other semiconductors. Wafer.

In the embodiment of the package of the present invention, it can be applied to various electronic components including integrated circuits such as active or passive elements, digital circuits or analog circuits, for example, About optoelectronic Devices), Micro Electro Mechanical Systems (MEMS), micro fluidic systems, or physical sensors that measure physical quantities such as heat, light, and pressure. In particular, wafer-level packaging processes can be used for image sensors, light-emitting diodes, solar cells, RF circuits, accelerators, gyroscopes, and micro actuators. Semiconductor wafers such as surface acoustic wave elements, pressure sensors, or ink printer heads are packaged. The wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed on a carrier wafer. The encapsulation process is also referred to as a wafer level packaging process. The above wafer level packaging process is also suitable for stacking a plurality of wafers having integrated circuits by stacking to form a package of multi-layer integrated circuit devices.

Next, please refer to FIG. 2A, which is a cross-sectional view of a semiconductor wafer 101 in the semiconductor wafer 100 shown in FIG. 1, showing a semiconductor device according to a first embodiment of the present invention, which has one of the semiconductor wafers 100. The semiconductor wafer 101, a first protective film 111, a redistribution wiring layer 130, a nickel/gold layer 150, and a solder resist layer 160.

The semiconductor wafer 100 has a wafer front surface 100a including an active surface and a wafer back surface 100b. Therefore, the semiconductor wafer 101 also has a wafer front surface 100a and a crystal back surface 100b. The semiconductor wafer 101 also has a conductive electrode, such as a conductive contact pad or a red cloth. A circuit layer (RDL), here exemplified by a top metal 102, is electrically connected to circuit components inside the wafer. In the present embodiment, the top layer metal 102 is embedded in a dielectric layer 104 that is exposed over the wafer front side 100a of the semiconductor wafer 101; in other embodiments, the dielectric layer 104 shown in FIG. 2A is not formed. The semiconductor wafer 101 further has one or more metal interconnect layers and a corresponding interlayer dielectric layer under the top metal 102. However, this has little to do with the features of the present invention. Therefore, the present invention will be omitted for brevity.

On the front surface 100a of the semiconductor wafer 101, a first protective film 111 is provided as a protective layer of the semiconductor wafer 101. The first protective film 111 has a through opening 111a as a protective layer opening, and the opening 111a is located on the top metal 102. And expose it. The first protective film 111 may be substantially the same as the solder resist layer 160 to be described later, or may be a polyimide.

Formed on the first protective film 111 is a redistributed wiring layer 130, and the redistributed wiring layer 130 is electrically connected to the top metal 102 via the opening 111a. The redistribution wiring layer 130 has an aluminum layer 132 and a TiW layer 131 on the lower surface of the aluminum layer 132 in one embodiment. Here, the TiW layer 131 is selected as an interface layer between the redistribution wiring layer 130 and the first protective film 111 / the top metal 102, so that the redistribution wiring layer 130 is closely adhered to the first protective film 111 / the top metal 102 .

A nickel/gold layer 150 is formed on the upper surface of the aluminum layer 132 of the redistribution wiring layer 130. The nickel/gold layer 150 is formed by coating a nickel film with a gold film, in addition to preventing the aluminum layer 132 from being oxidized. Can also be used as a weight The adhesive layer between the wiring layer 130 and the solder resist layer 160 thereon increases the adhesion therebetween, thereby improving the reliability of the semiconductor device of the first embodiment of the present invention.

In addition, the redistribution wiring layer 130 has the aluminum layer 132 as its main body, and the TiW layer 131 serves as an adhesion layer between the aluminum layer 132 and the structure below it, in addition to improving the reliability of the semiconductor device of the first embodiment of the present invention. In addition to the contribution, the use of the aluminum layer 132 can also simplify the process of redistributing the wiring layer 130 and reduce the cost of the process.

A solder mask layer 160 is disposed on the first protective film 111 and the redistribution wiring layer 130, and has an opening 161 to expose an end point 133 of the redistribution wiring layer 130 and a nickel/gold layer 150 above it. The solder resist layer 160, or "green paint" because of its color, can prevent the redistribution circuit layer 130 from bridging with other adjacent redistribution circuit layers (not shown) due to contact with the solder material in the subsequent process. It is also possible to prevent contamination of a semiconductor device according to the first embodiment of the present invention by a pollutant such as moisture, and an example of the composition is: (hereinafter "CAS No." is a CAS number) (1) bisphenol A type epoxy Resin (EPOXY RESIN, CAS No.: 25068-38-6), concentration 40.0% ~ less than 60.0%; (2) 1-methoxy-2-propyl acetate, CAS No .:108-65-6), concentration 25.0%~ less than 40.0%; (3) Bisphenol-F epoxy resin or epoxy phenol novolac, CAS No.: 28064-14-4, concentration 20.0%~ less than 25.0%; and (4) 2-methoxypropyl acetate, CAS No.: 70657-70-4), the concentration is 0.1 to less than 0.2%.

In one embodiment, the dielectric layer 104 and the interlayer dielectric layer underneath the dielectric layer 104 are low-k dielectric layers, so it may be added between the end point 133 of the redistribution circuit layer 130 and the first protective film 111 as needed. A stress buffering insulator 115, when the semiconductor device shown in FIG. 2A is subjected to external mechanical stress due to subsequent processes and working environments, can function as a buffer to avoid or slow down the dielectric layer 104 having a lower mechanical strength. The impact of the stress on the underlying dielectric layer and the underlying dielectric layer avoids or reduces the possibility of peeling off or reduces the extent of peeling.

Referring to FIG. 2B, the nickel/gold exposed to the end point 133 of the opening 161 and above may be exposed by stencil printing, ball bonding, soldering or the like of a paste of electroconductive particles. On the layer 150, a bump 171 is formed as a connecting member between the semiconductor device of the first embodiment of the present invention and an external device such as a package substrate or a printed circuit board as shown in FIG. 2A. The material of the bump 171 may be, for example, a solder, gold, copper, gold or copper plated with soft solder, or a polymer having conductivity, or the like. As shown in FIG. 2B, when the bump 171 is a soft solder, the corresponding position of the nickel/gold layer 150 is dissolved in the bump 171, and the subsequent interface between the bump 171 and the aluminum layer 132 and the portion of the bump 171. A part of the composition such as tin forms a metal intermetallic compound, and an adhesion force between the bump 171 and the aluminum layer 132 is increased.

In FIG. 2B, since the thickness of the solder resist layer 160 is higher than the redistribution wiring layer 130 and the nickel gold layer 150 thereon, the deeper opening 161 of the bump 171 can provide a deeper and firmer Foundation The adhesion of the bump 171 further enhances the reliability of the semiconductor device of the first embodiment of the present invention.

Next, the semiconductor device of the second embodiment of the present invention shown in FIGS. 3A and 3B is provided with a composite protective layer structure to provide further stress buffering capability, and to strengthen the dielectric layer 104 and the underlying portion thereof. Protection of the interlayer dielectric layer.

The semiconductor wafer 100 and its semiconductor wafer 101 and the wafer front surface 100a and the crystal back surface 100b, the conductive electrode 102, the dielectric layer 104, the first protective film 111, the redistribution wiring layer 130, and the TiW layer thereof in FIGS. 3A and 3B The 131 and the aluminum layer 132, the nickel/gold layer 150, the solder resist layer 160, and the opening 161 thereof are the same as or equivalent to those described above with reference to FIGS. 2A and 2B, and thus detailed description thereof will be omitted.

Compared with the one shown in FIG. 2A, the protective layer 110 of the semiconductor device of the second embodiment of the present invention shown in FIG. 3A is a multi-layered composite structure in which the metal layer 120 is embedded, and because of the embedded metal. For the layer 120, the protective layer 110 can be divided into a first protective film 111 under the metal layer 120 and a second protective film 112 above the first protective film 111. The second protective film 112 also has an opening 112a. The top metal 102 is exposed, where the opening 112a becomes the protective layer opening throughout the protective layer 110. The redistribution circuit layer 130 is formed on the second protective film 112 of the protective layer 110 and electrically connected to the top metal 102 via the opening 112a.

In this embodiment, the dielectric layer 104 and the interlayer dielectric layer under the foregoing are low-k dielectric layers, and the semiconductor device shown in FIG. 3A When the external mechanical stress acts on the subsequent process and the working environment, the sandwich structure of the second protective film 112 - the metal layer 120 - the first protective film 111 formed by the protective layer 110 and the embedded metal layer 120 can exert stress The function of the buffer to reduce or even avoid external mechanical stress causes the dielectric layer 104 and the interlayer dielectric layer underneath it to be peeled off. In addition, a stress buffer insulator 115 may be added between the end point 133 of the redistribution circuit layer 130 and the protective layer 110, and a buffer layer may be added to strengthen the dielectric layer 104 and the interlayer dielectric layer below the dielectric layer 104. protection of.

In addition, when the material of the second protective film 112 is selected as an electro-deposition coating material containing an epoxy resin or a polyimide component, in addition to the second coating film The protective film 112 is formed on the metal layer 120, and the second protective film 112 is also formed on the crystal back surface 100b of the semiconductor wafer 100 (or the semiconductor wafer 101). The second protective film 112 on the crystal back surface 100b can serve not only as a stress buffer layer of the semiconductor wafer 100 (or the semiconductor wafer 101), but also avoids the process of transporting the fragile semiconductor wafer 100 (or the semiconductor wafer 101) or In a subsequent process (for example, a wafer dicing process), chipping or edge chipping occurs due to external stress; and the second protective film 112 on the crystal back surface 100b may be marked by a laser or the like to mark The identity, status, and/or other necessary information of each semiconductor wafer 101. In other embodiments, the second protective film 112 having the same material as the first protective film 111 or other known dielectric materials may be selected. In this case, the second protective film 112 is not necessarily formed on the back surface of the crystal. On 100b.

In the embodiment shown in FIG. 3A, the top metal 102 is an I/O (input/output) terminal of the semiconductor wafer 101, so that the top metal 102 and the metal layer 120 of the semiconductor wafer 101 are electrically connected by the protective layer 110. In isolation, the metal layer 120 of the present embodiment does not electrically contact the top metal 102. The metal layer 120 shown in FIG. 3A can be used as a shield layer in addition to the stress buffer layer, and the circuit of the interconnect of the semiconductor wafer 101 underneath is prevented or slowed from external electromagnetic interference.

Referring to FIG. 3B, the semiconductor wafer 101 may further have a top metal 106 exposed on the front surface 100a of the wafer. The top metal 106 is used as a ground contact for the semiconductor wafer 101, or is arranged to make the contacts uniform or symmetrical. The metal layer 120 can electrically contact the top metal 106 by the dummy contacts provided. The metal layer 120 at this time can serve as a ground layer in addition to the stress buffer layer and the shield layer.

In FIG. 3B, the metal layer 120 is electrically connected to the top metal 106 exposed to the opening 111b via the opening 111b of the first protective film 111. After the second protective film 112 is formed, the opening 112b becomes a protective layer opening through the entire protective layer 110, and the opening 112b exposes the top metal 106 and the metal layer 120 thereabove.

A repeating wiring layer 140 is formed on the second protective film 112 of the protective layer 110, and is electrically connected to the metal layer 120 via the opening 112b to electrically connect the top metal 106. The redistribution wiring layer 140 has an aluminum layer 142 and a TiW layer 141 on the lower surface of the aluminum layer 142. Here, the TiW layer 141 serves as an interface layer between the redistribution wiring layer 140 and the second protective film 112/top metal 106, so that the redistribution wiring layer 140 and the second protective film 112/ The top metal 106 is tightly bonded. The nickel/gold layer 150 is also formed on the upper surface of the aluminum layer 142 of the redistribution wiring layer 140.

Similarly, the redistribution wiring layer 140 has an aluminum layer 142 as its main body, and the TiW layer 141 serves as an adhesion layer between the aluminum layer 142 and its underlying structure, in addition to improving the reliability of the semiconductor device of the second embodiment of the present invention. In addition to the contribution, the use of the aluminum layer 142 can also simplify the process of redistributing the wiring layer 140 and reduce the cost of the process.

A solder resist layer 160 is disposed on the second protective film 112 and the redistribution circuit layer 130 of the protective layer 110, and has an opening 162 to expose an end point 143 of the redistribution wiring layer 140 and a nickel/gold layer thereon. 150.

The stress protection effect of the protective layer 110 and the embedded metal layer 120 on the semiconductor device shown in FIG. 3B is the same as that described above in FIG. 3A. In addition, a stress buffering insulator 116 may be added between the end point 143 of the redistribution circuit layer 140 and the protective layer 110, and a layer of buffer may be added to strengthen the interlayer dielectric between the dielectric layer 104 and the underlying layer. Layer protection.

In addition, the bump structure (not shown) which is the same as or equivalent to that shown in FIG. 2B can also be formed in the 3A, 3B diagrams, respectively, the end points 133, 143 exposed by the openings 161, 162 and above. Nickel/gold layer 150.

Next, in the drawings 4A to 4H and 5A to 5F, a method of manufacturing the semiconductor device of the present invention will be described in a series of cross-sectional views. The products obtained by the steps shown in FIGS. 4A to 4H and 5A to 5F are the semiconductor devices shown in FIGS. 3A and 3B, but the steps can also be applied to the semiconductor devices shown in FIGS. 2A and 2B. The manufacture is detailed as described later.

In addition, in each of the cross-sectional views shown in FIGS. 4A to 4H and 5A to 5F, the region 1 and the region 2 are divided, and the region 1 is used to display the method of manufacturing the semiconductor device shown in FIG. 3A. In the region 2, a method of manufacturing the semiconductor device shown in FIG. 3B is presented.

Referring first to FIG. 4A, a semiconductor wafer 100 is provided in this step having at least one semiconductor wafer 101 having conductive electrodes, such as top layers of metal 102 and 106 exposed on surface 100a of semiconductor wafer 100. An example of a schematic view of the semiconductor wafer 100 is shown in FIG. The top metals 102 and 106 are respectively I/O terminals of the semiconductor wafer 101, ground contacts, or dummy contacts provided for uniform or symmetrical arrangement of the contacts, respectively. Between the dielectric layer 104 is isolated.

Next, referring to FIG. 4B, a first protective film 111 is formed on the semiconductor wafer 100. The first protective film 111 has openings 111a and 111b to expose the top metals 102 and 104, respectively. For example, after the first protective film 111 is formed on the active surface 100a of the semiconductor wafer 100 in a comprehensive manner, the first protective film 111 is patterned using a technique such as photolithography to form a top exposed metal, respectively. Openings 111a and 111b of 102 and 104.

Referring then to FIG. 4C, a resist material 181 is formed to cover the top metal 102 exposed to the opening 111a while the top metal 106 is still exposed to the opening 111b without being covered by the resist material 181. For example, a resist layer (not shown) may be formed on the semiconductor wafer 100 of the structure shown in FIG. 4B by a spin coating method, for example, and then passed through a photomask (not shown). After the line exposure, the other unnecessary resist materials are removed through the development step, and the resist material 181 shown in FIG. 4C is completed. The completed resist material 181 may extend beyond the range of the opening 111a to a small extent and extend to the first protective film 111 around the opening 111a.

Then, referring to FIG. 4D, a metal layer 120 is deposited on the first protective film 111, on the resist material 181, on the sidewall of the opening 111b, and on the exposed top metal 106. The metal layer 120 can be deposited comprehensively on the semiconductor wafer 100 of the structure shown in FIG. 4C by, for example, evaporation, sputtering, or other physical or chemical vapor deposition.

Then, referring to FIG. 4E, the resist material 181 shown in FIG. 4D is removed using lift-off, and the metal layer 120 formed on the resist material is simultaneously removed, leaving The next discontinuous metal layer is located on the first protective film 111 outside the opening 111a and extends into the opening 111b. In addition, when the resist material 181 shown in FIG. 4D is removed, it is also possible to slightly enlarge the removal range of the metal layer 120 around the opening 111a.

Further, when only the semiconductor device shown in FIG. 3B is formed, the steps shown in FIGS. 4C and 4E need not be performed, and the steps shown in FIG. 4D may be performed.

Then, referring to FIG. 4F, a sacrificial layer 182 is filled in each of the openings 111a and 111b. The material and formation method of the sacrificial layer 182 may be the same as the resist material 181. Similarly, the completed sacrificial layer 182 may extend beyond the extent of the openings 111a, 111b to a small extent and extend to the first protective film 111 around the openings 111a, 111b, respectively.

Then, referring to FIG. 4G, in this step, a solution 210 containing an epoxy-based or polyimide-based electrode coating material (Electro-deposition coating material) is provided, and the solution 210 is contained in In a container 200, the container 200 is sized to permit immersion of the semiconductor wafer 100 shown in FIG. 4F and the structure thereon in solution 210. Next, the semiconductor wafer 100 shown in FIG. 4F is immersed in the solution 210, so that the insulating material adheres only to the exposed metal layer 120 and the crystal back surface 100b of the semiconductor wafer 100 due to its properties after being energized. The second protective film 112 is formed, and the completed structure is as shown in FIG. 4H. Therefore, with the present invention, the step of separately forming a protective layer on the crystal back surface 100b can be eliminated, and the process cost of the semiconductor device of the preferred embodiment of the present invention can be reduced.

Then, referring to FIG. 5A, the sacrificial layer 182 shown in FIG. 4H is removed, and the second protective film 112 has an opening 112a to expose the top metal 102 and an opening 112b to expose the metal layer 120 on the top metal 106. In some cases, after the sacrificial layer 182 is removed, a reflow step is performed. In the reflow process, the material of the second protective film 112 originally located in the peripheral region other than the openings 111a, 111b is shown in FIG. It is possible to flow into the edge portions of the openings 111a, 111b, and generally cover the side walls of the openings 111a, 111b as shown in Fig. 5A. At this time, the openings 112a and 112b become the protective film openings penetrating the protective film 110 including the first protective film 111 and the second protective film 112.

The steps shown in Fig. 5B are not necessary steps of the present invention, but the steps of whether or not to perform are selected as needed. As shown in Figure 5B In this step, the stress buffering insulators 115 and 116 are respectively formed on the predetermined position of the end point 133 of the redistribution wiring layer 130 of the second protective film 112, and the end of the wiring layer 140 is overlapped with the second protective film 112. Point 143 is at a predetermined location. For example, a material layer (not shown) of the stress buffering insulator can be formed on the structure above the active surface 100a of the semiconductor wafer 100 shown in FIG. 5A, and the stress buffer can be buffered by, for example, photolithography etching. The material layer of the insulator is patterned to form the stress buffering insulators 115, 116 shown in Fig. 5B.

Then, referring to FIG. 5C, the redistribution circuit layers 130 and 140 are formed on the second protective film 112. The redistribution circuit layer 130 is electrically connected to the top metal 102 via the opening 112a, and the redistribution circuit layer 140 is connected to the metal via the opening 112b. The layer 120 is electrically connected to the top metal 106, the redistribution wiring layer 130 has an aluminum layer 132 and a TiW layer 131 on the lower surface of the aluminum layer 132, and the redistribution wiring layer 140 has an aluminum layer 142 and a TiW layer 141 on the aluminum layer 142. lower surface. For example, a material layer of TiW may be sequentially formed on the structure above the active surface 100a of the semiconductor wafer 100 shown in FIG. 5A or 5B by evaporation, sputtering, or other physical or chemical vapor deposition method (not drawn) After the aluminum material layer (not shown) is formed, the material layer of the TiW and the aluminum material layer are patterned by, for example, photolithography etching to form the redistribution wiring layer 130 shown in FIG. 140. In the case where the stress buffering insulators 115, 116 shown in FIG. 5B are selectively formed, the end points 133 of the redistribution wiring layer 130 and the end points 144 of the redistribution wiring layer 140 are formed in the stress buffering insulators 115 and 116, respectively. on.

Then, referring to FIG. 5D, the aluminum layer 132 of the wiring layer 130 is redistributed. On the upper surface, on the upper surface of the aluminum layer 142 of the redistribution wiring layer 140, a nickel/gold layer 150 is plated. For example, electroplating, electroless plating, or a combination thereof may be used to sequentially plate a nickel metal film (not shown) and a gold on the upper surfaces of the aluminum layers 132 and 142. The metal film (not shown) completes the nickel/gold layer 150 shown in FIG. 5D.

Then, referring to FIG. 5E, a solder resist layer 160 is formed on the protective layer 110, the redistribution wiring layer 130, and the redistribution wiring layer 140, exposing the end point 133 of the redistribution wiring layer 130 and the nickel/gold layer above it. 150, and the end point 143 of the redistribution circuit layer 140 and the nickel/gold layer 150 above it. For example, a green lacquer layer (not shown) may be applied on the upper structure of the semiconductor wafer 100 shown in FIG. 5D, and the exposed end 133 and the nickel above it may be formed by, for example, lithography, etching, or the like. The gold layer 150, and the openings 161 and 162 of the end point 143 and the nickel/gold layer 150 above it, and depending on the nature of the material, determine whether to perform a hardening step such as illumination or heating, and complete the solder resist shown in FIG. 5E. Layer 160. As shown in Fig. 5E, the structure shown in the region 1 in the figure is the semiconductor device shown in Fig. 3A, and the structure shown in the region 2 in the figure is the semiconductor device shown in Fig. 3B.

Then, referring to FIG. 5F, in the structure exposed to the openings 161 and 162 in FIG. 5E, a bump 171 and a bump 172 are respectively formed, and the materials of the two are preferably substantially the same, and the same is conductive. Sexual material. When the bumps 171 and 172 are soft solder, as described above, the nickel/gold layers 150 in the openings 161, 162 are respectively dissolved in the bumps 171, 172, and become the aluminum layers 132, 142 and the lower portions thereof. The intermetallic compound in the interface between.

Further, regarding the method of forming the semiconductor device shown in FIGS. 2A and 2B, reference may be made to the configuration of any of the regions 1 or 2 in the steps shown in FIGS. 4A to 4H and 5A to 5F. To form the semiconductor device shown in FIGS. 2A and 2B, the steps described in the above FIGS. 4A and 4B can be performed first, and after the structure shown in FIG. 4B is completed, the first protective film 111 is used as the completed. The protective layer, the openings 111a and/or 112a as the protective layer openings penetrating the protective layer, directly perform the respective equivalent steps shown in FIG. 5B or 5C. Similarly, the equivalent step shown in Fig. 5B is not a necessary step of the present invention, but a step of selecting whether or not to perform it can be selected as needed. In the step shown in FIG. 5C, it is changed to form the redistribution circuit layer 130 and/or 140 on the first protective film 111, and the redistribution circuit layer 130 is electrically connected to the top metal 102 via the opening 111a. The wiring layer 140 is electrically connected to the top layer metal 106 via the opening 111b and the metal layer 120. The redistribution wiring layer 130 has an aluminum layer 132 and a TiW layer 131 on the lower surface of the aluminum layer 132, and the redistribution wiring layer 140 has an aluminum layer. 142 and TiW layer 141 are on the lower surface of aluminum layer 142. Then, after completing the equivalent steps shown in FIGS. 5D and 5E, the semiconductor device shown in FIG. 2A is completed, and then the semiconductor shown in FIG. 2B is completed after the equivalent step shown in FIG. 5F is completed. Device.

Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and it is possible to make a few changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

1, 2‧‧‧ area

100‧‧‧Semiconductor wafer

100a‧‧‧ wafer front

100b‧‧‧ crystal back

101‧‧‧Semiconductor wafer

102, 106‧‧‧ conductive electrode

104‧‧‧ dielectric layer

110‧‧‧Protective layer

111‧‧‧First protective film

112‧‧‧Second protective film

111a, 111b, 112a, 112b, 161, 162‧‧

115, 116‧‧‧ stress buffer insulation

120‧‧‧metal layer

130, 140‧‧‧Re-distribution layer

131, 141‧‧‧TiW layer

132, 142‧‧‧ aluminum layer

133, 143‧‧‧ endpoint

150‧‧‧ Nickel/gold layer

160‧‧‧ solder mask

171, 172‧‧ ‧ bumps

181‧‧‧Resistant materials

182‧‧‧ sacrificial layer

200‧‧‧ container

210‧‧‧solution

Figure 1 is a top plan view showing a semiconductor wafer.

2A and 2B are a series of sectional views showing a semiconductor device according to a first embodiment of the present invention.

3A and 3B are a series of sectional views showing a semiconductor device according to a second embodiment of the present invention.

4A to 4H and 5A to 5F are a series of sectional views showing a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention shown in Figs. 3A and 3B.

100‧‧‧Semiconductor wafer

100a‧‧‧ wafer front

100b‧‧‧ crystal back

101‧‧‧Semiconductor wafer

102‧‧‧Conductive electrode

104‧‧‧ dielectric layer

111‧‧‧First protective film

111a‧‧‧ openings

115‧‧‧stress buffer insulation

130‧‧‧Re-distribution layer

131‧‧‧TiW layer

132‧‧‧Aluminum layer

133‧‧‧Endpoint

150‧‧‧ Nickel/gold layer

160‧‧‧ solder mask

161‧‧‧ openings

Claims (14)

A semiconductor device comprising: a semiconductor wafer having a first surface; a conductive electrode exposed to the first surface; a protective layer covering the semiconductor wafer, the protective layer having a protective layer penetrating through the conductive electrode And a redistributed circuit layer on the protective layer, the redistributed circuit layer is electrically connected to the conductive electrode via the protective layer opening, the redistributed circuit layer has an aluminum layer; and a nickel/gold layer is disposed on the redistributed circuit layer An upper surface of the aluminum layer; and a solder resist layer on the protective layer and the redistribution wiring layer, exposing an end of the redistribution wiring layer and the nickel/gold layer above it. The semiconductor device of claim 1, further comprising a metal layer embedded in the protective layer. The semiconductor device of claim 2, wherein the protective layer further comprises a first protective film and a second protective film sandwiched between the metal layers. The semiconductor device of claim 3, wherein: the metal layer is on the first protective film; and the second protective film is located not only on the first protective film and the metal layer but also on the semiconductor a second surface of the wafer opposite the first surface. The semiconductor device according to claim 3, wherein the material of the first protective film is substantially the same as the solder resist layer, or is a poly A polyimide, and the redistribution wiring layer further includes a TiW layer on the lower surface of the aluminum layer. The semiconductor device according to claim 3, wherein the second protective film is an electrically coated insulating film. The semiconductor device of claim 1, further comprising a stress buffering insulator between the end of the redistribution wiring layer and the protective layer. The semiconductor device of claim 2, wherein the conductive electrode is an output/input contact of the semiconductor wafer, and the metal layer is electrically isolated from the conductive electrode by the protective layer, and serves as a Electromagnetic screen layer. The semiconductor device of claim 8, wherein the conductive electrode is a ground contact or a dummy contact of the semiconductor wafer, and the metal layer is electrically connected to the conductive electrode. A semiconductor device comprising: a semiconductor wafer having a first surface; a first conductive electrode and a second conductive electrode exposed on the first surface; a protective layer on the first surface of the semiconductor wafer, the The protective layer has a first protective layer opening and a second protective layer opening therethrough, and is respectively located on the first conductive electrode and the second conductive electrode; a metal layer is embedded in the protective layer, the metal The layer is electrically connected to the second conductive electrode, but is electrically separated from the first conductive electrode by the protective layer a first redistribution circuit layer is electrically connected to the first conductive electrode via the first protective layer opening, and the first redistribution circuit layer has a first aluminum a second redistribution circuit layer is electrically connected to the second conductive electrode via the second protective layer opening, and the second redistributed circuit layer has a second aluminum a layer; a nickel/gold layer on an upper surface of the first aluminum layer of the first redistribution wiring layer and an upper surface of the second aluminum layer of the second redistribution wiring layer; and a solder resist layer for the protection Exposing a first end point of the first redistribution circuit layer and the nickel/gold layer above the layer, the first redistribution circuit layer, and the second redistribution circuit layer, and the second weight A second end of the wiring layer and the nickel/gold layer above it. The semiconductor device of claim 10, wherein the protective layer further comprises a first protective film and a second protective film sandwiched between the metal layers; the first redistribution circuit layer further comprises a a first TiW layer on the lower surface of the first aluminum layer; and the second redistribution circuit layer further includes a second TiW layer on the lower surface of the second aluminum layer, wherein: the metal layer is located at the first a protective film; and the second protective film is located not only on the first protective film and the metal layer but also on a second surface of the semiconductor wafer opposite to the first surface. The semiconductor device of claim 11, wherein the second protective film is an electrically coated insulating film; the first conductive electrode is An output/input contact of the semiconductor wafer; and the second conductive electrode is a ground contact or a dummy contact of the semiconductor wafer. A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer having at least one semiconductor wafer having a conductive electrode exposed on a first surface of the semiconductor wafer; forming a protective layer on the semiconductor wafer On the first surface, the protective layer has a protective layer penetrating the conductive electrode; a redistributed circuit layer is formed on the protective layer, and the redistributed circuit layer is electrically connected to the conductive electrode via the protective layer opening. The redistribution circuit layer has an aluminum layer and a TiW layer on the lower surface of the aluminum layer; a nickel/gold layer is plated on the upper surface of the aluminum layer of the redistribution circuit layer; and a solder resist layer is formed on Exposing the protective layer and the redistribution layer to an end of the redistribution layer and the nickel/gold layer thereon; wherein the step of forming the protective layer further comprises: forming a first protective film on the semiconductor On the wafer, the first protective film has a first opening penetrating the conductive electrode; forming a metal layer on the first protective film; filling a first sacrificial layer in the first opening; providing a solution, An electrically insulating material is coated; the semiconductor wafer is immersed in the solution, and the electrically coated insulating material is adhered to the metal layer other than the sacrificial layer, and the semiconductor wafer is a surface opposite to a second surface to form a first a second protective film; and removing the sacrificial layer such that the second protective film has a second opening penetrating the conductive electrode, and the second opening serves as the protective layer opening. A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer having at least one semiconductor wafer, the semiconductor wafer having a first conductive electrode and a second conductive electrode exposed on a first surface of the semiconductor wafer; forming a first protective film on the semiconductor wafer, the first protective film has a first opening exposing the first conductive electrode, and a second opening exposing the second conductive electrode; forming a resist material covering the exposed The first conductive electrode of the first opening, wherein the second conductive electrode is still exposed to the second opening; on the first protective film, the resist material, the sidewall of the second opening, and the exposed Depositing a metal layer on the second conductive electrode; removing the resist material and simultaneously removing the metal layer formed on the resist material leaving a discontinuous metal layer outside the first opening The first protective film extends into the second opening; each of the first opening and the second opening is filled with a sacrificial layer; and a solution is provided, which has an electrically coated insulating material; The The conductive wafer is immersed in the solution, and the electrically coated insulating material is adhered to the discontinuous metal layer other than the sacrificial layer and a second surface of the semiconductor wafer opposite to the first surface Forming a second protective film; Removing the sacrificial layer, the second protective film having a third opening to expose the first conductive electrode and a fourth opening to expose the discontinuous metal layer on the second conductive electrode; forming a first The redistribution circuit layer and the second redistribution circuit layer are electrically connected to the second conductive film, and the first redistribution circuit layer is electrically connected to the first conductive electrode via the third opening, and the second redistribution circuit layer is The fourth opening is electrically connected to the second conductive electrode, and the first redistribution circuit layer has a first aluminum layer and a first TiW layer on a lower surface of the first aluminum layer. The second redistribution circuit layer has a second aluminum layer and a second TiW layer on the lower surface of the second aluminum layer; on the upper surface of the first aluminum layer of the first redistribution circuit layer, and the first Depositing a nickel/gold layer on the upper surface of the second aluminum layer of the double wiring layer; and forming a solder resist layer on the protective layer, the first redistribution wiring layer, and the second redistribution wiring layer Exposing a first end point of the first redistribution circuit layer and the nickel/gold layer above the first redistribution circuit layer, and the second redistribution line And a second terminal of the nickel / gold layer above.