WO2017107292A1 - 触控驱动电路 - Google Patents

触控驱动电路 Download PDF

Info

Publication number
WO2017107292A1
WO2017107292A1 PCT/CN2016/072847 CN2016072847W WO2017107292A1 WO 2017107292 A1 WO2017107292 A1 WO 2017107292A1 CN 2016072847 W CN2016072847 W CN 2016072847W WO 2017107292 A1 WO2017107292 A1 WO 2017107292A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
electrically connected
output end
touch driving
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/072847
Other languages
English (en)
French (fr)
Inventor
龚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US14/913,997 priority Critical patent/US9880650B1/en
Publication of WO2017107292A1 publication Critical patent/WO2017107292A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display

Definitions

  • the present invention relates to the field of touch display technologies, and in particular, to a touch drive circuit.
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the touch panel provides a new human-computer interaction interface that is more direct and user-friendly.
  • the touch panel is integrated with the display panel of the flat display device to form a touch display panel, which enables the flat display device to have a touch function, and can be input through a finger, a stylus, etc., and the operation is more intuitive and simple.
  • the touch display panel is generally divided into a separate touch display panel and an embedded touch display panel.
  • the embedded touch display panel combines the touch panel and the display panel, and embeds the touch panel function into the display. Inside the panel, the display panel has both the function of displaying and sensing touch input. Compared with the separate touch display panel, the embedded touch display panel has the advantages of being lighter and thinner, having better transmittance and contrast, and lower cost.
  • a Hyrid In Cell touch display panel is further formed, that is, a touch driving electrode is formed by using a common electrode on one side of the array substrate, and oxidation by back plating is performed on the color film substrate side.
  • Indium Tin Oxide (ITO) forms a touch sensing electrode.
  • the hybrid in-cell touch display panel currently used has a driving circuit similar to the GOA circuit on the side of the array substrate so that the touch driving electrodes are scanned line by line.
  • 1 is a touch driving circuit of a hybrid in-cell touch display panel, comprising: a cascaded multi-level touch driving unit, each of the touch driving units includes: a level transmitting unit 100 The selection unit 200 and the output unit 300; wherein N is a positive integer, in addition to the first-level touch driving unit, in the N-th touch driving unit:
  • the level transfer unit 100 includes: a first NOT gate F1, the input end of the first NOT gate F1 is connected to the Mth clock signal CK(M), and the output end is electrically connected to the first tri-state NOT gate SF1.
  • the drive unit's level transmission signal ST(N-1) the output end is electrically connected to the output end of the second three-state NOT gate SF2, and the high potential control termination
  • the low potential control terminal is electrically connected to the output end of the first NOT gate F1; the second tristate NOT gate SF2, the input power of the second tristate NOT gate SF2 Connected to the output end of the second NOT gate F2, the output end is electrically connected to the output end of the first tri-state NOT gate SF1, and the high
  • the selection unit 200 includes: a third NOT gate F3, the input end of the third NOT gate F3 is electrically connected to the output end of the NAND gate YF1, and the output selection signal Select is connected, and the output end is electrically connected to the fourth non-gate.
  • An input terminal of the gate F4, a fourth NOT gate F4, an output end of the fourth NOT gate F4 is electrically connected to a gate of the second N-type thin film transistor T2, and a second N-type thin film transistor T2, the second N
  • the source of the thin film transistor T2 is electrically connected to the constant voltage low potential VGL, and the drain is electrically connected to the input end of the fifth invertor F5;
  • the first transfer gate TG1, the high potential control end of the first transfer gate TG1 Electrically connected to the output end of the third NOT gate F3, the low potential control end is electrically connected to the output end of the fourth NOT gate F4, the input end is connected to the first control signal TXSW, and the output end is electrically connected to the fifth NOT gate.
  • the output end is electrically connected to the first control signal TXSW, and the output end is electrically connected to the input end of the ninth non-gate F9
  • a third transmission gate TG3 the high potential control end of the third transmission gate TG3 is electrically connected to the output end of the fourth inversion gate F4, and the low potential control end is electrically connected to the output end of the third inversion gate F3, the input
  • the terminal is electrically connected to the second control signal HRSW, and the output end is electrically connected to the input end of the ninth NOT gate F9;
  • the output unit 300 includes: a fifth NOT gate F5, an output end of the fifth NOT gate F5 is electrically connected to an input end of the sixth NOT gate F6; a sixth NOT gate F6, and the sixth NOT gate F6
  • the output end is electrically connected to the input end of the seventh NOT gate F7; the seventh NOT gate F7, the output end of the seventh NOT gate F7 is electrically connected to the low potential control end of the fourth transmission gate TG4; F8, the input end of the eighth NOT gate F8 is electrically connected to the output end of the fifth NOT gate F5, the output end is electrically connected to the high potential control end of the fourth transmission gate TG4; the fourth transmission gate TG4, the The input end of the fourth transmission gate TG4 is connected to the effective pulse touch drive signal TXH, and the output end is electrically connected to the drive output terminal OUT(N); a ninth non-gate F9, the output end of the ninth non-gate F9 is electrically connected to the input end of the tenth non-gate F10; the tenth non-
  • the selection signal Select outputted from the output of the NAND gate YF1 is controlled by the first control signal TXSW and the second control signal HRSW.
  • the touch driving circuit operates in different modes: when the selection signal Select is low, and the first control signal TXSW is high, the step-by-step output effective pulse touch driving signal TXH is realized; when the selection signal Select is high, the second When the control signal HRSW is low, the constant voltage low potential signal TXL is output; when the selection signal Select is high, and the second control signal HRSW is also high, the touch driving circuit is in the high impedance mode.
  • the touch driving circuit of the above-mentioned existing hybrid in-cell touch display panel can effectively reduce the number of output ports of the integrated circuit, the number of signals and devices used therein is too large, resulting in a layout space occupied by the touch driving circuit. More, it is not conducive to the narrow frame design of the touch display panel.
  • An object of the present invention is to provide a touch driving circuit, which can simplify the circuit structure, reduce the number of components and the number of signals, and reduce the layout space occupied by the touch driving circuit, thereby reducing the touch display panel.
  • the width of the border enables the narrow border design of the touch display panel.
  • the present invention provides a touch driving circuit, including a cascaded multi-level touch driving unit, each of the touch driving units includes: a level transfer selecting unit, and an output unit;
  • N be a positive integer.
  • the level selection unit includes:
  • a first NOT gate wherein the input end of the first NOT gate is connected to the Mth clock signal, and the output end is electrically connected to the low potential control end of the first tri-state NOT gate and the high potential control of the second tri-state NOT gate end;
  • a first three-state non-gate wherein the input end of the first three-state non-gate is connected to the level-transmitting signal of the first-stage N-1-level touch driving unit, and the output end is electrically connected to the second three-state non-gate
  • the output end, the high potential control end is connected to the Mth clock signal, and the low potential control end is electrically connected to the output end of the first non-gate;
  • the input end of the second tri-state NOT gate is electrically connected to the output end of the second NOT gate, and the output end is electrically connected to the output end of the first tri-state NOT gate, and the high-potential control terminal Electrically connected to the output end of the first NOT gate, and the low potential control end is connected to the Mth clock signal;
  • a second NOT gate wherein the input end of the second NOT gate is electrically connected to the output end of the first tri-state NOT gate and the output end of the second tri-state NOT gate, and the output end is electrically connected to the second tri-state NOT gate Input and output the signal of the level;
  • a gate of the first P-type thin film transistor is electrically connected to a reset signal, a source is connected to a constant voltage high potential, and a drain is electrically connected to an input end of the second non-gate;
  • the first input end of the NAND gate is electrically connected to the output end of the second NOT gate, the second input end is connected to the M+1th clock signal, and the output end outputs the selection signal;
  • the output unit includes:
  • the input end of the third non-gate is electrically connected to the output end of the NAND gate, and the selection signal is connected, and the output end is electrically connected to the input end of the fourth non-gate;
  • the output end of the fourth non-gate is electrically connected to the input end of the fifth non-gate;
  • the output end of the fifth non-gate is electrically connected to the input end of the sixth non-gate;
  • the output end of the sixth non-gate is electrically connected to the low potential control end of the first transmission gate and the high potential control end of the second transmission gate;
  • the input end of the seventh non-gate is electrically connected to the output end of the fourth non-gate, and the output end is electrically connected to the high potential control end of the first transmission gate and the low potential control of the second transmission gate end;
  • a first transmission gate an input end of the first transmission gate is connected to an effective pulse touch driving signal, and an output end is electrically connected to an output end of the touch driving circuit;
  • a second transmission gate the input end of the second transmission gate is electrically connected to the constant voltage low potential signal, and the output end is electrically connected to the output end of the touch driving circuit.
  • the output of the touch driving circuit When the selection signal of the NAND gate output is high, the output of the touch driving circuit outputs an effective pulse touch driving signal.
  • the output of the touch driving circuit When the selection signal of the NAND gate output is low, the output of the touch driving circuit outputs a constant voltage low potential signal.
  • the first three-state non-gate and the second non-gate operate, and the level-transmitted signal of the upper-stage N-1th touch driving unit is transmitted to the touch driving circuit of the first stage.
  • the second three-state NOT gate and the second NOT gate work to latch the level-transmitting signal of the first-stage N-1th touch driving unit.
  • the pulse period of the effective pulse touch driving signal is smaller than the pulse period of the clock signal.
  • the touch driving circuit of the hybrid in-cell touch display panel includes two clock signals: a first clock signal and a second clock signal.
  • the M+1th clock signal is the second clock signal; when the Mth clock signal is the second clock signal, First The M+1 clock signal is the first clock signal.
  • the input end of the first tri-state non-gate is connected to the circuit start signal, and the input end of the first non-gate is connected to the first clock signal, and the NAND gate is The second input terminal is connected to the second clock signal.
  • the present invention further provides a touch driving circuit comprising a cascaded multi-level touch driving unit, each of the touch driving units comprising: a level transfer selecting unit and an output unit;
  • N be a positive integer.
  • the level selection unit includes:
  • a first NOT gate wherein the input end of the first NOT gate is connected to the Mth clock signal, and the output end is electrically connected to the low potential control end of the first tri-state NOT gate and the high potential control of the second tri-state NOT gate end;
  • a first three-state non-gate wherein the input end of the first three-state non-gate is connected to the level-transmitting signal of the first-stage N-1-level touch driving unit, and the output end is electrically connected to the second three-state non-gate
  • the output end, the high potential control end is connected to the Mth clock signal, and the low potential control end is electrically connected to the output end of the first non-gate;
  • the input end of the second tri-state NOT gate is electrically connected to the output end of the second NOT gate, and the output end is electrically connected to the output end of the first tri-state NOT gate, and the high-potential control terminal Electrically connected to the output end of the first NOT gate, and the low potential control end is connected to the Mth clock signal;
  • a second NOT gate wherein the input end of the second NOT gate is electrically connected to the output end of the first tri-state NOT gate and the output end of the second tri-state NOT gate, and the output end is electrically connected to the second tri-state NOT gate Input and output the signal of the level;
  • a gate of the first P-type thin film transistor is electrically connected to a reset signal, a source is connected to a constant voltage high potential, and a drain is electrically connected to an input end of the second non-gate;
  • the first input end of the NAND gate is electrically connected to the output end of the second NOT gate, the second input end is connected to the M+1th clock signal, and the output end outputs the selection signal;
  • the output unit includes:
  • the input end of the third non-gate is electrically connected to the output end of the NAND gate, and the selection signal is connected, and the output end is electrically connected to the input end of the fourth non-gate;
  • the output end of the fourth non-gate is electrically connected to the input end of the fifth non-gate;
  • the output end of the fifth non-gate is electrically connected to the input end of the sixth non-gate;
  • the output end of the sixth non-gate is electrically connected to the low potential control end of the first transmission gate and the high potential control end of the second transmission gate;
  • the input end of the seventh non-gate is electrically connected to the output end of the fourth non-gate, and the output end is electrically connected to the high potential control end of the first transmission gate and the low potential control of the second transmission gate end;
  • a first transmission gate wherein an input end of the first transmission gate is connected to an effective pulse touch driving signal, The output end is electrically connected to the output end of the touch driving circuit;
  • the first three-state non-gate and the second non-gate operate, and the level-transmitted signal of the upper-level N-1th-level touch driving unit is transmitted to the local touch.
  • a driving circuit when the Mth clock signal is low, the second three-state NOT gate and the second NOT gate operate to latch the level-transmitting signal of the N-1th touch driving unit of the previous stage;
  • the pulse period of the effective pulse touch driving signal is smaller than the pulse period of the clock signal
  • clock signals There are two clock signals: a first clock signal and a second clock signal.
  • the invention has the beneficial effects that the touch driving circuit provided by the invention only controls the operation of the transmission gate by selecting signals, and realizes the output of the effective pulse touch driving signal and the constant voltage low potential signal, which is simplified compared with the prior art.
  • the circuit structure reduces the number of components and two control signals, thereby reducing the layout space occupied by the touch driving circuit, reducing the border width of the touch display panel, and contributing to the narrow border of the touch display panel. design.
  • 1 is a circuit diagram of a touch driving circuit of a hybrid in-cell touch display panel
  • FIG. 2 is a timing diagram of the touch driving circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a touch driving circuit of the present invention.
  • FIG. 4 is a timing diagram of the touch driving circuit shown in FIG. 3;
  • FIG. 5 is a circuit diagram of a first-level touch driving unit in the touch driving circuit of the present invention.
  • the present invention provides a touch driving circuit, including a cascaded multi-level touch driving unit, each of which includes: a level transfer selecting unit 10 and an output unit 20 .
  • N be a positive integer.
  • the level selection unit 10 includes:
  • the first NOT gate F1 the input end of the first NOT gate F1 is connected to the Mth clock signal CK(M), and the output end is electrically connected to the low potential control end of the first tri-state NOT gate SF1 and the second three a high potential control terminal of the NAND gate SF2;
  • the first tri-state NOT gate SF1 the input end of the first tri-state NOT gate SF1 is connected to the grade transmission signal ST(N-1) of the first-stage N-1-th touch driving unit, and the output end is electrically connected.
  • the high-potential control terminal is connected to the M-th clock signal CK(M), and the low-potential control terminal is electrically connected to the output end of the first NOT gate F1;
  • the second tri-state NOT gate SF2 the input end of the second tri-state NOT gate SF2 is electrically connected to the output end of the second NOT gate F2, and the output end is electrically connected to the output end of the first tri-state NOT gate SF1.
  • the high potential control terminal is electrically connected to the output end of the first NOT gate F1, and the low potential control terminal is connected to the Mth clock signal CK(M);
  • the second non-gate F2 the input end of the second non-gate F2 is electrically connected to the output end of the first tri-state NOT gate SF1 and the output end of the second tri-state NOT gate SF2, and the output end is electrically connected to the second end
  • the first P-type thin film transistor T1 has a gate electrically connected to the reset signal Reset, a source connected to the constant voltage high potential VGH, and a drain electrically connected to the second non-gate F2. Input
  • the NAND gate YF1 the first input end of the NAND gate YF1 is electrically connected to the output end of the second NOT gate F2, and the second input end is connected to the M+1th clock signal CK(M+1), Output output selection signal Select;
  • the output unit 20 includes:
  • a third NOT gate F3 the input end of the third NOT gate F3 is electrically connected to the output end of the NAND gate YF1, and the selection signal is selected, and the output end is electrically connected to the input end of the fourth NOT gate F4;
  • a fourth NOT gate F4 the output end of the fourth NOT gate F4 is electrically connected to the input end of the fifth NOT gate F5;
  • the output end of the fifth non-gate F5 is electrically connected to the input end of the sixth NOT gate F6;
  • a sixth inverting gate F6 the output end of the sixth inverting gate F6 is electrically connected to the low potential control end of the first transmission gate TG1 and the high potential control end of the second transmission gate TG2;
  • the seventh non-gate F7 the input end of the seventh non-gate F7 is electrically connected to the output end of the fourth non-gate F4, and the output end is electrically connected to the high-potential control end and the second transmission gate of the first transmission gate TG1 Low potential control terminal of TG2;
  • the first transmission gate TG1 the input end of the first transmission gate TG1 is connected to the effective pulse touch driving signal TXH, and the output end is electrically connected to the output end OUT(N) of the touch driving circuit;
  • the input end of the second transmission gate TG2 is connected to the constant voltage low potential signal TXL, and the output end is electrically connected to the output end OUT(N) of the touch driving circuit.
  • the Mth clock signal CK(M) when the Mth clock signal CK(M) is high, the first three-state NOT gate SF1 and the second NOT gate F2 work, and the level of the N-1th touch driving unit of the previous stage is transmitted.
  • the signal ST(N-1) is transmitted to the touch driving circuit of the current level; when the Mth clock signal CK(M) is low, the second three-state NOT gate SF2 and the second non-gate F2 operate, latching The graded signal ST(N-1) of the upper N-1th touch driving unit.
  • the touch drive circuit output terminal OUT(N) When the selection signal Select of the output of the NAND gate YF1 is high, the touch drive circuit output terminal OUT(N) outputs the effective pulse touch drive signal TXH; when the NAND gate YF1 outputs the select signal Select is low At the potential, the output terminal OUT(N) of the touch driving circuit outputs a constant voltage low potential signal TXL.
  • the pulse period of the effective pulse touch driving signal TXH is smaller than the pulse period of the clock signal.
  • Each level of the driver circuit is connected to two clock signals: a first clock signal CK (1), and a second clock signal CK (2).
  • a first clock signal CK (1) When the Mth clock signal CK(M) is the first clock signal CK(1), the M+1th clock signal CK(M+1) is the second clock signal CK(2);
  • the M+1th clock signal CK(M+1) is the first clock signal CK(1).
  • the first clock signal CK(1) and the second clock signal CK(2) alternately alternately input the input end of the first NOT gate F1 and the second input end of the NAND gate YF1 of the touch driving units of each stage.
  • the input end of the first NOT gate F1 is connected to the first clock signal CK(1), and the second input end of the NAND gate YF1 is connected to the second clock signal CK.
  • the input end of the first NOT gate F1 is connected to the second clock signal CK(2), and the second input end of the NAND gate YF1 is connected to the first clock signal CK.
  • the input end of the first NOT gate F1 is connected to the first clock signal CK(1), and the second input end of the NOT gate YF1 is connected to the second clock signal. CK (2), and so on to the last level of the touch drive unit.
  • the transmission gate is composed of an N-type thin film transistor and a P-type thin film transistor group, wherein a gate of the N-type thin film transistor is used as a high potential control terminal of the transmission gate, and a gate of the P-type thin film transistor is used as a transmission gate.
  • Potential control terminal, source of N-type thin film transistor and P-type thin film transistor A source is electrically connected as an input end of the transmission gate, and a drain of the N-type thin film transistor is electrically connected to a drain of the P-type thin film transistor as an output end of the transmission gate.
  • the first three-state NOT gate SF1 and the second three-state NOT gate SF2 are control switches when the high potential control terminal is connected to a high level (logic 1) and the low potential control terminal is connected to a low level (logic 0).
  • the tri-state non-gate exhibits a normal non-gate output (the input terminal is 0, then the output terminal is 1; the input terminal is 1, the output terminal is 0); and when the high-potential control terminal is connected to the low level (logic 0)
  • the tri-state gate is equivalent to a resistor with a very high resistance value, and is regarded as a state in which no current flows through the digital circuit, that is, an open circuit.
  • the input end of the first tri-state transmission gate SF1 is electrically connected to the circuit start signal STV.
  • the working process of the touch driving circuit of the hybrid in-cell touch display panel of the present invention is as follows:
  • the Mth clock signal CK(M) and the level-transmitted signal ST(N-1) of the upper-level touch driving unit are both provided high.
  • the M+1th clock signal CK(M+1) provides a low potential
  • the high potential of the Mth clock signal CK(M) is directly supplied to the high potential control terminal of the first tristate NOT gate SF1 and the second three
  • the low potential control terminal of the NOT gate SF2 is supplied to the low potential control terminal of the first tri-state NOT gate SF1 and the high potential control terminal of the second tri-state NOT gate SF2 via the first NOT gate F1.
  • the second tri-state NOT gate SF2 When the first three-state NOT gate SF1 is working, the second tri-state NOT gate SF2 is open, and the level-transmitting signal ST(N-1) of the N-1th-level touch driving unit is via the first tri-state NOT gate SF1 and the
  • the second NOT gate F2 provides a high potential to the first input terminal of the NAND gate YF1 after two inversions, the M+1th clock signal CK(M+1) is low, and the selection signal outputted by the NAND gate YF1 output terminal Select is high, and the selection signal Select provides a high potential to the low potential control end and the second transmission of the first transmission gate TG1 via the third, fourth, fifth, and sixth NOT gates F3, F4, F5, and F6.
  • Door TG2 a potential control terminal, wherein the selection signal Select provides a low potential to the low potential control end of the first transmission gate TG1 and the second transmission gate TG2 via the third, fourth, and seventh NOT gates F3, F4, and F7
  • the potential control terminal, the first transmission gate TG1 is closed, the second transmission gate TG2 is operated, and the output terminal OUT(N) of the touch driving circuit outputs a constant voltage low potential signal TXL;
  • the Mth clock signal CK(M) becomes a low potential
  • the M+1th clock signal CK(M+1) becomes a high potential
  • the second three-state NOT gate SF2 operates, and the first three-state NOT gate SF1
  • the second three-state NOT gate SF2 and the second NOT gate F2 cooperate to latch the high potential of the level transmission signal ST(N-1) of the upper N-1th touch driving unit, and maintain the NAND gate YF1.
  • the potential of the first input terminal is high, the selection signal select becomes low, and the selection signal Select provides a low potential after the third, fourth, fifth, and sixth non-gates F3, F4, F5, and F6.
  • the Mth clock signal CK(M) goes high again, the M+1th clock signal CK(M+1) goes low, the second tri-state NOT gate SF2 turns off, the first tri-state NOT gate
  • the SF1 works, the level transmission signal ST(N-1) of the upper touch driving unit is turned to a low potential, and the level transmission signal ST(N-1) of the first N-1 stage touch driving unit passes through the first three
  • the non-gate SF1 and the second NOT gate F2 are input to the first input terminal of the NAND gate YF1
  • the selection signal outputted by the output terminal of the NAND gate YF1 Select is always high, the first transmission gate TG1 is turned off, the second transmission gate TG2 is operated, and the output terminal OUT(N) of the touch driving circuit continuously outputs the constant voltage low potential signal TXL.
  • the touch driving circuit of the present invention can ensure the normal operation of the touch driving circuit. Compared with the touch driving circuit of the existing hybrid in-cell touch display panel shown in FIG. 1 , the selection unit 200 and the first control are reduced.
  • the setting of the signal TXSW and the second control signal HRSW, and the circuit structure of the output unit 20 in the present invention is simpler, the simplified circuit structure is achieved, the number of components and control signals is reduced, and the layout space occupied by the touch driving circuit is reduced.
  • the touch driving circuit of the present invention controls the operation of the transmission gate only by selecting a signal, and realizes the output of the effective pulse touch driving signal and the constant voltage low potential signal, which simplifies the circuit structure compared with the prior art.
  • the plurality of components and two control signals are reduced, thereby reducing the layout space occupied by the touch driving circuit, reducing the width of the border of the touch display panel, and contributing to the narrow bezel design of the touch display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Position Input By Displaying (AREA)

Abstract

一种触控驱动电路，仅通过选择信号(Select)控制传输门(TG1或TG2)工作，实现了有效脉冲触控驱动信号(TXH)和恒压低电位信号(TXL)的输出，相比于现有技术简化了电路结构，减少了多个元器件和两条控制信号，从而减少了触控驱动电路占用的布局空间，减小了触控显示面板的边框宽度，有助于实现触控显示面板的窄边框设计。

Description

触控驱动电路 技术领域
本发明涉及触控显示技术领域，尤其涉及一种触控驱动电路。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
触控面板(Touch panel)提供了一种新的人机互动界面，其在使用上更直接、更人性化。将触控面板与平面显示装置的显示面板整合在一起，形成触控显示面板，能够使平面显示装置具有触控功能，可通过手指、触控笔等执行输入，操作更加直观、简便。触控显示面板通常分为分离式触控显示面板和嵌入式触控显示面板，其中，嵌入式触控显示面板是将触控面板和显示面板结合为一体，并将触控面板功能嵌入到显示面板内，使得显示面板同时具备显示和感知触控输入的功能。嵌入式触控显示面板相比于分离式触控显示面板具有更轻薄、透过率和对比度更佳、及成本较低的优点。在嵌入式触控显示面板中又包括混合内嵌型(Hyrid In Cell)触控显示面板，即在阵列基板一侧利用公共电极形成触控驱动电极，在彩膜基板一侧利用背镀的氧化铟锡(Indium Tin Oxide，ITO)形成触控感应电极。
目前使用的混合内嵌型触控显示面板在阵列基板一侧制作有类似于GOA电路的驱动电路使得触控驱动电极逐行扫描。图1所示为现有的一种混合内嵌式触控显示面板的触控驱动电路，包括：级联的多级触控驱动单元，每一级触控驱动单元均包括：级传单元100、选择单元200、及输出单元300；设N为正整数，除第一级触控驱动单元外，在第N级触控驱动单元中：
所述级传单元100包括：第一非门F1，所述第一非门F1的输入端接入第M条时钟信号CK(M)，输出端电性连接于第一三态非门SF1的低电位控制端和第二三态非门SF2的高电位控制端；第一三态非门SF1，所述第一三态非门SF1的输入端接入上一级第N-1级触控驱动单元的级传信号ST(N-1)，输出端电性连接于第二三态非门SF2的输出端，高电位控制端接 入第M条时钟信号CK(M)，低电位控制端电性连接于第一非门F1的输出端；第二三态非门SF2，所述第二三态非门SF2的输入端电性连接于第二非门F2的输出端，输出端电性连接于第一三态非门SF1的输出端，高电位控制端电性连接于第一非门F1的输出端，低电位控制端接入第M条时钟信号CK(M)；第二非门F2，所述第二非门F2的输入端电性连接于第一三态非门SF1的输出端与第二三态非门SF2的输出端，输出端电性连接于第二三态非门SF2的输入端并输出本级级传信号ST(N)；第一P型薄膜晶体管T1，所述第一P型薄膜晶体管T1的栅极电性连接于复位信号Reset，源极电性连接于恒压高电位VGH，漏极电性连接于第二非门F2的输入端；以及与非门YF1，所述与非门YF1的第一输入端电性连接于第二非门F2的输出端，第二输入端接入第M+1条时钟信号CK(M+1)，输出端输出选择信号Select；
所述选择单元200包括：第三非门F3，所述第三非门F3的输入端电性连接于与非门YF1的输出端，接入输出选择信号Select，输出端电性于第四非门F4的输入端；第四非门F4，所述第四非门F4的输出端电性连接于第二N型薄膜晶体管T2的栅极；第二N型薄膜晶体管T2，所述第二N型薄膜晶体管T2的源极电性连接于恒压低电位VGL，漏极电性连接于第五非门F5的输入端；第一传输门TG1，所述第一传输门TG1的高电位控制端电性连接于第三非门F3的输出端，低电位控制端电性连接于第四非门F4的输出端，输入端接入第一控制信号TXSW，输出端电性连接于第五非门F5的输入端；第二传输门TG2，所述第二传输门TG2的高电位控制端电性连接于第三非门F3的输出端，低电位控制端电性连接于第四非门F4的输出端，输入端电性连接于第一控制信号TXSW，输出端电性连接于第九非门F9的输入端；以及第三传输门TG3，所述第三传输门TG3的高电位控制端电性连接于第四非门F4的输出端，低电位控制端电性连接于第三非门F3的输出端，输入端电性连接于第二控制信号HRSW，输出端电性连接于第九非门F9的输入端；
所述输出单元300包括：第五非门F5，所述第五非门F5的输出端电性连接于第六非门F6的输入端；第六非门F6，所述第六非门F6的输出端电性连接于第七非门F7的输入端；第七非门F7，所述第七非门F7的输出端电性连接于第四传输门TG4的低电位控制端；第八非门F8，所述第八非门F8的输入端电性连接于第五非门F5的输出端，输出端电性连接于第四传输门TG4的高电位控制端；第四传输门TG4，所述第四传输门TG4的输入端接入有效脉冲触控驱动信号TXH，输出端电性连接于驱动输出端OUT(N)； 第九非门F9，所述第九非门F9的输出端电性连接于第十非门F10的输入端；第十非门F10，所述第十非门F10的输出端电性连接于第十一非门F11的输入端；第十一非门F11，所述第十一非门F11的输出端电性连接于第五传输门TG5的高电位控制端；第十二非门F12，所述第十二非门F12的输入端电性连接于第九非门F9的输出端，输出端电性连接于第五传输门TG5的低电位控制端；以及第五传输门TG5，所述第五传输门TG5的输入端接入恒压低电位信号TXL，输出端电性连接于触控驱动电路输出端OUT(N)。
在图1所示的现有的混合内嵌式触控显示面板的触控驱动电路中，与非门YF1的输出端输出的选择信号Select配合第一控制信号TXSW和第二控制信号HRSW来控制触控驱动电路工作在不同的模式：当选择信号Select为低电位，第一控制信号TXSW为高电位时，实现逐级输出有效脉冲触控驱动信号TXH；当选择信号Select为高电位，第二控制信号HRSW为低电位时，输出恒压低电位信号TXL；当选择信号Select为高电位，第二控制信号HRSW也为高电位时，该触控驱动电路处于高阻态工作模式。
上述现有的混合内嵌式触控显示面板的触控驱动电路虽然能够有效降低集成电路的输出端口的数量，但是其采用的信号和器件过多，导致该触控驱动电路占用的布局空间过多，不利于触控显示面板的窄边框设计。
发明内容
本发明的目的在于提供一种触控驱动电路，相比于现有技术能够简化电路结构，减少元器件数量和信号数量，减少触控驱动电路占用的布局空间，从而减小触控显示面板的边框宽度，实现触控显示面板的窄边框设计。
为实现上述目的，本发明提供了一种触控驱动电路，包括级联的多级触控驱动单元，每一级触控驱动单元均包括：级传选择单元、及输出单元；
设N为正整数，除第一级触控驱动单元外，在第N级触控驱动单元中：
所述级传选择单元包括：
第一非门，所述第一非门的输入端接入第M条时钟信号，输出端电性连接于第一三态非门的低电位控制端和第二三态非门的高电位控制端；
第一三态非门，所述第一三态非门的输入端接入上一级第N-1级触控驱动单元的级传信号，输出端电性连接于第二三态非门的输出端，高电位控制端接入第M条时钟信号，低电位控制端电性连接于第一非门的输出端；
第二三态非门，所述第二三态非门的输入端电性连接于第二非门的输出端，输出端电性连接于第一三态非门的输出端，高电位控制端电性连接于第一非门的输出端，低电位控制端接入第M条时钟信号；
第二非门，所述第二非门的输入端电性连接于第一三态非门的输出端与第二三态非门的输出端，输出端电性连接于第二三态非门的输入端并输出本级级传信号；
第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于复位信号，源极接入恒压高电位，漏极电性连接于第二非门的输入端；
以及与非门，所述与非门的第一输入端电性连接于第二非门的输出端，第二输入端接入第M+1条时钟信号，输出端输出选择信号；
所述输出单元包括：
第三非门，所述第三非门的输入端电性连接于与非门的输出端，接入选择信号，输出端电性连接于第四非门的输入端；
第四非门，所述第四非门的输出端电性连接于第五非门的输入端；
第五非门，所述第五非门的输出端电性连接于第六非门的输入端；
第六非门，所述第六非门的输出端电性连接于第一传输门的低电位控制端及第二传输门的高电位控制端；
第七非门，所述第七非门的输入端电性连接于第四非门的输出端，输出端电性连接于第一传输门的高电位控制端及第二传输门的低电位控制端；
第一传输门，所述第一传输门的输入端接入有效脉冲触控驱动信号，输出端电性连接于触控驱动电路输出端；
以及第二传输门，所述第二传输门的输入端电性连接于恒压低电位信号，输出端电性连接于触控驱动电路输出端。
当所述与非门输出的选择信号为高电位时，触控驱动电路输出端输出有效脉冲触控驱动信号。
当所述与非门输出的选择信号为低电位时，触控驱动电路输出端输出恒压低电位信号。
当所述第M条时钟信号为高电位时，第一三态非门与第二非门工作，上一级第N-1级触控驱动单元的级传信号传入本级触控驱动电路；当所述第M条时钟信号为低电位时，第二三态非门与第二非门工作，锁存上一级第N-1级触控驱动单元的级传信号。
所述有效脉冲触控驱动信号的脉冲周期小于时钟信号的脉冲周期。
所述混合内嵌式触控显示面板的触控驱动电路包括两条时钟信号：第一条时钟信号、和第二条时钟信号。
当所述第M条时钟信号为第一条时钟信号时，所述第M+1条时钟信号为第二条时钟信号；当所述第M条时钟信号为第二条时钟信号时，所述第 M+1条时钟信号为第一条时钟信号。
在第一级触控驱动单元中，第一三态非门的输入端接入电路起始信号，所述第一非门的输入端接入第一条时钟信号，所述与非门的第二输入端接入第二条时钟信号。
本发明还提供一种触控驱动电路，包括级联的多级触控驱动单元，每一级触控驱动单元均包括：级传选择单元、及输出单元；
设N为正整数，除第一级触控驱动单元外，在第N级触控驱动单元中：
所述级传选择单元包括：
第一非门，所述第一非门的输入端接入第M条时钟信号，输出端电性连接于第一三态非门的低电位控制端和第二三态非门的高电位控制端；
第一三态非门，所述第一三态非门的输入端接入上一级第N-1级触控驱动单元的级传信号，输出端电性连接于第二三态非门的输出端，高电位控制端接入第M条时钟信号，低电位控制端电性连接于第一非门的输出端；
第二三态非门，所述第二三态非门的输入端电性连接于第二非门的输出端，输出端电性连接于第一三态非门的输出端，高电位控制端电性连接于第一非门的输出端，低电位控制端接入第M条时钟信号；
第二非门，所述第二非门的输入端电性连接于第一三态非门的输出端与第二三态非门的输出端，输出端电性连接于第二三态非门的输入端并输出本级级传信号；
第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于复位信号，源极接入恒压高电位，漏极电性连接于第二非门的输入端；
以及与非门，所述与非门的第一输入端电性连接于第二非门的输出端，第二输入端接入第M+1条时钟信号，输出端输出选择信号；
所述输出单元包括：
第三非门，所述第三非门的输入端电性连接于与非门的输出端，接入选择信号，输出端电性连接于第四非门的输入端；
第四非门，所述第四非门的输出端电性连接于第五非门的输入端；
第五非门，所述第五非门的输出端电性连接于第六非门的输入端；
第六非门，所述第六非门的输出端电性连接于第一传输门的低电位控制端及第二传输门的高电位控制端；
第七非门，所述第七非门的输入端电性连接于第四非门的输出端，输出端电性连接于第一传输门的高电位控制端及第二传输门的低电位控制端；
第一传输门，所述第一传输门的输入端接入有效脉冲触控驱动信号， 输出端电性连接于触控驱动电路输出端；
以及第二传输门，所述第二传输门的输入端接入恒压低电位信号，输出端电性连接于触控驱动电路输出端；
其中，当所述与非门输出的选择信号为高电位时，触控驱动电路输出端输出有效脉冲触控驱动信号；
其中，当所述与非门输出的选择信号为低电位时，触控驱动电路输出端输出恒压低电位信号；
其中，当所述第M条时钟信号为高电位时，第一三态非门与第二非门工作，上一级第N-1级触控驱动单元的级传信号传入本级触控驱动电路；当所述第M条时钟信号为低电位时，第二三态非门与第二非门工作，锁存上一级第N-1级触控驱动单元的级传信号；
其中，所述有效脉冲触控驱动信号的脉冲周期小于时钟信号的脉冲周期；
其中，包括两条时钟信号：第一条时钟信号、和第二条时钟信号。
本发明的有益效果：本发明提供的一种触控驱动电路，仅通过选择信号控制传输门工作，实现了有效脉冲触控驱动信号和恒压低电位信号的输出，相比于现有技术简化了电路结构，减少了多个元器件和两条控制信号，从而减少了触控驱动电路占用的布局空间，减小了触控显示面板的边框宽度，有助于实现触控显示面板的窄边框设计。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种混合内嵌式触控显示面板的触控驱动电路的电路图；
图2为图1所示触控驱动电路的时序图；
图3为本发明的触控驱动电路的电路图；
图4为图3所示触控驱动电路的时序图；
图5为本发明的触控驱动电路中第一级触控驱动单元的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图3与图4，本发明提供一种触控驱动电路，包括级联的多级触控驱动单元，每一级触控驱动单元均包括：级传选择单元10、及输出单元20。
设N为正整数，除第一级触控驱动单元外，在第N级触控驱动单元中：
所述级传选择单元10包括：
第一非门F1，所述第一非门F1的输入端接入第M条时钟信号CK(M)，输出端电性连接于第一三态非门SF1的低电位控制端和第二三态非门SF2的高电位控制端；
第一三态非门SF1，所述第一三态非门SF1的输入端接入上一级第N-1级触控驱动单元的级传信号ST(N-1)，输出端电性连接于第二三态非门SF2的输出端，高电位控制端接入第M条时钟信号CK(M)，低电位控制端电性连接于第一非门F1的输出端；
第二三态非门SF2，所述第二三态非门SF2的输入端电性连接于第二非门F2的输出端，输出端电性连接于第一三态非门SF1的输出端，高电位控制端电性连接于第一非门F1的输出端，低电位控制端接入第M条时钟信号CK(M)；
第二非门F2，所述第二非门F2的输入端电性连接于第一三态非门SF1的输出端与第二三态非门SF2的输出端，输出端电性连接于第二三态非门SF2的输入端并输出本级级传信号ST(N)；
第一P型薄膜晶体管T1，所述第一P型薄膜晶体管T1的栅极电性连接于复位信号Reset，源极接入恒压高电位VGH，漏极电性连接于第二非门F2的输入端；
以及与非门YF1，所述与非门YF1的第一输入端电性连接于第二非门F2的输出端，第二输入端接入第M+1条时钟信号CK(M+1)，输出端输出选择信号Select；
所述输出单元20包括：
第三非门F3，所述第三非门F3的输入端电性连接于与非门YF1的输出端，接入选择信号Select，输出端电性连接于第四非门F4的输入端；
第四非门F4，所述第四非门F4的输出端电性连接于第五非门F5的输入端；
第五非门F5，所述第五非门F5的输出端电性连接于第六非门F6的输入端；
第六非门F6，所述第六非门F6的输出端电性连接于第一传输门TG1的低电位控制端及第二传输门TG2的高电位控制端；
第七非门F7，所述第七非门F7的输入端电性连接于第四非门F4的输出端，输出端电性连接于第一传输门TG1的高电位控制端及第二传输门TG2的低电位控制端；
第一传输门TG1，所述第一传输门TG1的输入端接入有效脉冲触控驱动信号TXH，输出端电性连接于触控驱动电路输出端OUT(N)；
以及第二传输门TG2，所述第二传输门TG2的输入端接入恒压低电位信号TXL，输出端电性连接于触控驱动电路输出端OUT(N)。
具体地，当所述第M条时钟信号CK(M)为高电位时，第一三态非门SF1与第二非门F2工作，上一级第N-1级触控驱动单元的级传信号ST(N-1)传入本级触控驱动电路；当所述第M条时钟信号CK(M)为低电位时，第二三态非门SF2与第二非门F2工作，锁存上一级第N-1级触控驱动单元的级传信号ST(N-1)。
所述与非门YF1的输出的选择信号Select为高电位时，触控驱动电路输出端OUT(N)输出有效脉冲触控驱动信号TXH；当所述与非门YF1输出的选择信号Select为低电位时，触控驱动电路输出端OUT(N)输出恒压低电位信号TXL。
进一步地，所述有效脉冲触控驱动信号TXH的脉冲周期小于时钟信号的脉冲周期。
每一级驱动电路均接入两条时钟信号：第一条时钟信号CK(1)、和第二条时钟信号CK(2)。当所述第M条时钟信号CK(M)为第一条时钟信号CK(1)时，所述第M+1条时钟信号CK(M+1)为第二条时钟信号CK(2)；当所述第M条时钟信号CK(M)为第二条时钟信号CK(2)时，所述第M+1条时钟信号CK(M+1)为第一条时钟信号CK(1)。所述第一条时钟信号CK(1)、第二条时钟信号CK(2)交替轮流接入各级触控驱动单元的第一非门F1的输入端和与非门YF1的第二输入端，例如：在第一级触控驱动单元中，第一非门F1的输入端接入第一条时钟信号CK(1)，与非门YF1的第二输入端接入第二条时钟信号CK(2)；在第二级触控驱动单元中，第一非门F1的输入端接入第二时钟信号CK(2)，与非门YF1的第二输入端接入第一条时钟信号CK(1)；在第三级触控驱动单元中，第一非门F1的输入端接入第一条时钟信号CK(1)，与非门YF1的第二输入端接入第二条时钟信号CK(2)，依次类推至最后一级触控驱动单元。
所述传输门由一N型薄膜晶体管和一P型薄膜晶体管组和构成，其中，N型薄膜晶体管的栅极作为传输门的高电位控制端，P型薄膜晶体管的栅极作为传输门的低电位控制端，N型薄膜晶体管的源极与P型薄膜晶体管的 源极电性连接作为所述传输门的输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为所述传输门的输出端。
第一三态非门SF1和第二三态非门SF2是一种控制开关，当高电位控制端接入高电平(逻辑1)且低电位控制端接入低电平(逻辑0)时，三态非门呈现正常的非门输出(输入端为0，则输出端为1；输入端为1，则输出端为0)；而当高电位控制端接入低电平(逻辑0)且低电位控制端接入高电平(逻辑1)时，三态门相当于一个电阻值极高的电阻，在数字电路中视为没有电流通过的状态，即为断路。
特别地，请参阅图5，在第一级触控驱动单元中，所述第一三态传输门SF1的输入端电性连接于电路起始信号STV。
请参阅图3、图5、并结合图4，本发明的混合内嵌式触控显示面板的触控驱动电路的工作过程如下：
首先，第M条时钟信号CK(M)和上一级触控驱动单元的级传信号ST(N-1)(在第一级触控驱动单元中即为电路起始信号STV)均提供高电位，第M+1条时钟信号CK(M+1)提供低电位，第M条时钟信号CK(M)的高电位直接提供给第一三态非门SF1的高电位控制端和第二三态非门SF2的低电位控制端，并经由第一非门F1变为低电位提供给第一三态非门SF1的低电位控制端和第二三态非门SF2的高电位控制端，此时第一三态非门SF1工作，第二三态非门SF2断路，所述第N-1级触控驱动单元的级传信号ST(N-1)经由第一三态非门SF1和第二非门F2两次反相后提供高电位至与非门YF1的第一输入端，第M+1条时钟信号CK(M+1)为低电位，与非门YF1输出端输出的选择信号Select为高电位，该选择信号Select经由第三、第四、第五、及第六非门F3、F4、F5、F6后提供高电位至第一传输门TG1的低电位控制端和第二传输门TG2的高电位控制端，同时所述选择信号Select经由第三、第四、及第七非门F3、F4、F7后提供低电位至第一传输门TG1的高电位控制端和第二传输门TG2的低电位控制端，第一传输门TG1关闭，第二传输门TG2工作，触控驱动电路的输出端OUT(N)输出恒压低电位信号TXL；
随后，第M条时钟信号CK(M)变为低电位，第M+1条时钟信号CK(M+1)变为高电位，第二三态非门SF2工作，第一三态非门SF1关闭，第二三态非门SF2与第二非门F2共同作用锁存上一级第N-1级触控驱动单元的级传信号ST(N-1)的高电位，保持与非门YF1第一输入端的电位为高电位，选择信号select变为低电位，所述选择信号Select经由第三、第四、第五、及第六非门F3、F4、F5、F6后提供低电位至第一传输门TG1的低电位控制 端和第二传输门TG2的高电位控制端，同时该选择信号Select经由第三、第四、及第七非门F3、F4、F7后提供高电位至第一传输门TG1的高电位控制端和第二传输门TG2的低电位控制端，第一传输门TG1工作，第二传输门TG2关闭，触控驱动电路的输出端OUT(N)输出有效脉冲触控驱动信号TXH。
最后，第M条时钟信号CK(M)再次变为高电位，第M+1条时钟信号CK(M+1)变为低电位，第二三态非门SF2关闭，第一三态非门SF1工作，上一级触控驱动单元的级传信号ST(N-1)转变为低电位，所述第N-1级触控驱动单元的级传信号ST(N-1)经由第一三态非门SF1和第二非门F2后传入与非门YF1的第一输入端，由于与非门YF1的第一输入端恒为低电位，则与非门YF1的输出端输出的选择信号Select恒为高电位，第一传输门TG1关闭，第二传输门TG2工作，触控驱动电路的输出端OUT(N)持续输出恒压低电位信号TXL。
本发明的触控驱动电路能够保证触控驱动电路正常工作，相比于图1所示的现有的混合内嵌式触控显示面板的触控驱动电路，减少了选择单元200、第一控制信号TXSW、第二控制信号HRSW的设置，且本发明中输出单元20的电路结构更加简单，达到了简化电路结构，减少元器件和控制信号数量，从而减少触控驱动电路占用的布局空间，减小触控显示面板的边框宽度的目的。
综上所述，本发明的触控驱动电路，仅通过选择信号控制传输门工作，实现了有效脉冲触控驱动信号和恒压低电位信号的输出，相比于现有技术简化了电路结构，减少了多个元器件和两条控制信号，从而减少了触控驱动电路占用的布局空间，减小了触控显示面板的边框宽度，有助于实现触控显示面板的窄边框设计。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种触控驱动电路，包括级联的多级触控驱动单元，每一级触控驱动单元均包括：级传选择单元、及输出单元；
    设N为正整数，除第一级触控驱动单元外，在第N级触控驱动单元中：
    所述级传选择单元包括：
    第一非门，所述第一非门的输入端接入第M条时钟信号，输出端电性连接于第一三态非门的低电位控制端和第二三态非门的高电位控制端；
    第一三态非门，所述第一三态非门的输入端接入上一级第N-1级触控驱动单元的级传信号，输出端电性连接于第二三态非门的输出端，高电位控制端接入第M条时钟信号，低电位控制端电性连接于第一非门的输出端；
    第二三态非门，所述第二三态非门的输入端电性连接于第二非门的输出端，输出端电性连接于第一三态非门的输出端，高电位控制端电性连接于第一非门的输出端，低电位控制端接入第M条时钟信号；
    第二非门，所述第二非门的输入端电性连接于第一三态非门的输出端与第二三态非门的输出端，输出端电性连接于第二三态非门的输入端并输出本级级传信号；
    第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于复位信号，源极接入恒压高电位，漏极电性连接于第二非门的输入端；
    以及与非门，所述与非门的第一输入端电性连接于第二非门的输出端，第二输入端接入第M+1条时钟信号，输出端输出选择信号；
    所述输出单元包括：
    第三非门，所述第三非门的输入端电性连接于与非门的输出端，接入选择信号，输出端电性连接于第四非门的输入端；
    第四非门，所述第四非门的输出端电性连接于第五非门的输入端；
    第五非门，所述第五非门的输出端电性连接于第六非门的输入端；
    第六非门，所述第六非门的输出端电性连接于第一传输门的低电位控制端及第二传输门的高电位控制端；
    第七非门，所述第七非门的输入端电性连接于第四非门的输出端，输出端电性连接于第一传输门的高电位控制端及第二传输门的低电位控制端；
    第一传输门，所述第一传输门的输入端接入有效脉冲触控驱动信号，输出端电性连接于触控驱动电路输出端；
    以及第二传输门，所述第二传输门的输入端接入恒压低电位信号，输出端电性连接于触控驱动电路输出端。
  2. 如权利要求1所述的触控驱动电路，其中，当所述与非门输出的选择信号为高电位时，触控驱动电路输出端输出有效脉冲触控驱动信号。
  3. 如权利要求1所述的触控驱动电路，其中，当所述与非门输出的选择信号为低电位时，触控驱动电路输出端输出恒压低电位信号。
  4. 如权利要求1所述的触控驱动电路，其中，当所述第M条时钟信号为高电位时，第一三态非门与第二非门工作，上一级第N-1级触控驱动单元的级传信号传入本级触控驱动电路；当所述第M条时钟信号为低电位时，第二三态非门与第二非门工作，锁存上一级第N-1级触控驱动单元的级传信号。
  5. 如权利要求1所述的触控驱动电路，其中，所述有效脉冲触控驱动信号的脉冲周期小于时钟信号的脉冲周期。
  6. 如权利要求1所述的触控驱动电路，其中，包括两条时钟信号：第一条时钟信号、和第二条时钟信号。
  7. 如权利要求6所述的触控驱动电路，其中，当所述第M条时钟信号为第一条时钟信号时，所述第M+1条时钟信号为第二条时钟信号；当所述第M条时钟信号为第二条时钟信号时，所述第M+1条时钟信号为第一条时钟信号。
  8. 如权利要求7所述的触控驱动电路，其中，在第一级触控驱动单元中，第一三态非门的输入端接入电路起始信号，所述第一非门的输入端接入第一条时钟信号，所述与非门的第二输入端接入第二条时钟信号。
  9. 一种触控驱动电路，包括级联的多级触控驱动单元，每一级触控驱动单元均包括：级传选择单元、及输出单元；
    设N为正整数，除第一级触控驱动单元外，在第N级触控驱动单元中：
    所述级传选择单元包括：
    第一非门，所述第一非门的输入端接入第M条时钟信号，输出端电性连接于第一三态非门的低电位控制端和第二三态非门的高电位控制端；
    第一三态非门，所述第一三态非门的输入端接入上一级第N-1级触控驱动单元的级传信号，输出端电性连接于第二三态非门的输出端，高电位控制端接入第M条时钟信号，低电位控制端电性连接于第一非门的输出端；
    第二三态非门，所述第二三态非门的输入端电性连接于第二非门的输出端，输出端电性连接于第一三态非门的输出端，高电位控制端电性连接于第一非门的输出端，低电位控制端接入第M条时钟信号；
    第二非门，所述第二非门的输入端电性连接于第一三态非门的输出端与第二三态非门的输出端，输出端电性连接于第二三态非门的输入端并输出本级级传信号；
    第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于复位信号，源极接入恒压高电位，漏极电性连接于第二非门的输入端；
    以及与非门，所述与非门的第一输入端电性连接于第二非门的输出端，第二输入端接入第M+1条时钟信号，输出端输出选择信号；
    所述输出单元包括：
    第三非门，所述第三非门的输入端电性连接于与非门的输出端，接入选择信号，输出端电性连接于第四非门的输入端；
    第四非门，所述第四非门的输出端电性连接于第五非门的输入端；
    第五非门，所述第五非门的输出端电性连接于第六非门的输入端；
    第六非门，所述第六非门的输出端电性连接于第一传输门的低电位控制端及第二传输门的高电位控制端；
    第七非门，所述第七非门的输入端电性连接于第四非门的输出端，输出端电性连接于第一传输门的高电位控制端及第二传输门的低电位控制端；
    第一传输门，所述第一传输门的输入端接入有效脉冲触控驱动信号，输出端电性连接于触控驱动电路输出端；
    以及第二传输门，所述第二传输门的输入端接入恒压低电位信号，输出端电性连接于触控驱动电路输出端；
    其中，当所述与非门输出的选择信号为高电位时，触控驱动电路输出端输出有效脉冲触控驱动信号；
    其中，当所述与非门输出的选择信号为低电位时，触控驱动电路输出端输出恒压低电位信号；
    其中，当所述第M条时钟信号为高电位时，第一三态非门与第二非门工作，上一级第N-1级触控驱动单元的级传信号传入本级触控驱动电路；当所述第M条时钟信号为低电位时，第二三态非门与第二非门工作，锁存上一级第N-1级触控驱动单元的级传信号；
    其中，所述有效脉冲触控驱动信号的脉冲周期小于时钟信号的脉冲周期；
    其中，包括两条时钟信号：第一条时钟信号、和第二条时钟信号。
  10. 如权利要求9所述的触控驱动电路，其中，当所述第M条时钟信号为第一条时钟信号时，所述第M+1条时钟信号为第二条时钟信号；当所 述第M条时钟信号为第二条时钟信号时，所述第M+1条时钟信号为第一条时钟信号。
  11. 如权利要求10所述的触控驱动电路，其中，在第一级触控驱动单元中，第一三态非门的输入端接入电路起始信号，所述第一非门的输入端接入第一条时钟信号，所述与非门的第二输入端接入第二条时钟信号。
PCT/CN2016/072847 2015-12-23 2016-01-29 触控驱动电路 Ceased WO2017107292A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/913,997 US9880650B1 (en) 2015-12-23 2016-01-29 Driver circuit for touch panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510980039.9A CN105373260B (zh) 2015-12-23 2015-12-23 触控驱动电路
CN201510980039.9 2015-12-23

Publications (1)

Publication Number Publication Date
WO2017107292A1 true WO2017107292A1 (zh) 2017-06-29

Family

ID=55375521

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/072847 Ceased WO2017107292A1 (zh) 2015-12-23 2016-01-29 触控驱动电路

Country Status (3)

Country Link
US (1) US9880650B1 (zh)
CN (1) CN105373260B (zh)
WO (1) WO2017107292A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111965913A (zh) * 2020-09-14 2020-11-20 浙江富申科技有限公司 窄边框电子纸显示装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105654902B (zh) * 2016-03-31 2018-03-27 上海天马微电子有限公司 一种oled显示面板、触控电极驱动电路以及驱动方法
CN105810165B (zh) * 2016-05-20 2018-09-28 武汉华星光电技术有限公司 一种cmos goa电路结构及液晶显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100011571A (ko) * 2008-07-25 2010-02-03 엘지디스플레이 주식회사 터치센서 내장 표시장치와 그 구동방법
CN103996371A (zh) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 显示驱动电路、阵列基板及触摸显示装置
CN204166519U (zh) * 2014-11-12 2015-02-18 京东方科技集团股份有限公司 触控电极的驱动单元、驱动电路及触控面板
CN104793801A (zh) * 2015-05-08 2015-07-22 厦门天马微电子有限公司 一种内嵌式触摸显示装置和触摸显示屏
CN104932747A (zh) * 2015-06-24 2015-09-23 京东方科技集团股份有限公司 一种触控驱动单元、触控面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101056284B1 (ko) * 2009-10-22 2011-08-11 삼성모바일디스플레이주식회사 센서 스캔 드라이버 및 이를 구비한 터치 스크린 내장형 평판표시장치
CN104503612B (zh) * 2014-12-12 2017-11-10 上海天马微电子有限公司 一种触控显示面板和电子设备
CN104932134B (zh) * 2015-06-30 2018-01-30 厦门天马微电子有限公司 一种触控显示基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100011571A (ko) * 2008-07-25 2010-02-03 엘지디스플레이 주식회사 터치센서 내장 표시장치와 그 구동방법
CN103996371A (zh) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 显示驱动电路、阵列基板及触摸显示装置
CN204166519U (zh) * 2014-11-12 2015-02-18 京东方科技集团股份有限公司 触控电极的驱动单元、驱动电路及触控面板
CN104793801A (zh) * 2015-05-08 2015-07-22 厦门天马微电子有限公司 一种内嵌式触摸显示装置和触摸显示屏
CN104932747A (zh) * 2015-06-24 2015-09-23 京东方科技集团股份有限公司 一种触控驱动单元、触控面板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111965913A (zh) * 2020-09-14 2020-11-20 浙江富申科技有限公司 窄边框电子纸显示装置
CN111965913B (zh) * 2020-09-14 2024-06-07 浙江富申科技有限公司 窄边框电子纸显示装置

Also Published As

Publication number Publication date
CN105373260A (zh) 2016-03-02
US20180032183A1 (en) 2018-02-01
CN105373260B (zh) 2018-06-01
US9880650B1 (en) 2018-01-30

Similar Documents

Publication Publication Date Title
CN105185318B (zh) 栅线驱动电路、输出发射控制信号的电路及触控显示装置
US9864472B2 (en) Touch driving detection circuit, display panel and display device
TWI415052B (zh) 開關裝置與應用該開關裝置之移位暫存器電路
CN105321462B (zh) 显示设备
CN105702295B (zh) 移位寄存器单元、栅极驱动电路、显示面板及显示装置
CN102201194B (zh) 移位寄存器电路
TWI582739B (zh) 顯示器面板
KR102120070B1 (ko) 표시장치 및 그 구동방법
TWI427591B (zh) 閘極驅動電路
CN103996371B (zh) 显示驱动电路、阵列基板及触摸显示装置
CN104464595B (zh) 扫描驱动电路及显示装置
CN104167171B (zh) 一种像素电路和显示装置
WO2016090849A1 (zh) 移位寄存器及其驱动方法、移位扫描电路和显示装置
CN102855858B (zh) 一种双向扫描控制开关、栅极驱动电路及工作方法
US10540925B2 (en) Shift register unit circuit, method for driving the same, gate drive circuit and display device
US20210225249A1 (en) Scan shift circuit, touch shift circuit, driving method and related apparatus
CN106935206A (zh) 移位寄存器单元、移位寄存器电路及驱动方法、显示面板
CN100536030C (zh) 双向移位寄存器
CN102820007B (zh) 阵列基板行驱动电路、显示面板及显示装置
CN102968956B (zh) 有源有机电致发光显示器的扫描驱动器及其驱动方法
CN117032483A (zh) 显示装置
CN102708776B (zh) 移位寄存器、液晶显示器栅极驱动装置及液晶显示器
US11837172B2 (en) Gate driving circuit and display device
WO2017107292A1 (zh) 触控驱动电路
CN108389559A (zh) 移位寄存器模块及驱动方法、栅极驱动电路和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16877106

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16877106

Country of ref document: EP

Kind code of ref document: A1