WO2017106835A1

WO2017106835A1 - Scalable integrated data converter

Info

Publication number: WO2017106835A1
Application number: PCT/US2016/067529
Authority: WO
Inventors: Susan Marya SCHOBER; Robert C. Schober
Original assignee: Circuit Seed, Llc
Priority date: 2015-12-17
Filing date: 2016-12-19
Publication date: 2017-06-22
Also published as: JP2019504585A; JP6690015B2; EP3391544A1; JP2020115577A; CN108702155A; EP3391544A4

Abstract

The present invention relates to an integrated data converter, in particular analog to digital converters (ADC) and digital to analog converters (DAC), using a charge-based approach. Complimentary pairs of current field effect transistors are used to form amplifiers for forming scalable ADCs and DACs are disclosed, including successive approximation data converters (ADCs and DACs), and pipe-lined data converters (ADCs and DACs).

Description

SCALABLE INTEGRATED DATA CONVERTER CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to US Provisional Application No. 62/268,983, filed on December 17, 2015, and PCT International Application No. PCT/US2016/044770, filed on July 29, 2016, the contents of which are incorporated herein by reference in their entirety. BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to an integrated data converter, in particular analog to digital converters and digital to analog converters, using a charge-based approach. Description of Related Art

The new millennium brings with it a demand for connectivity that is expanding at an extremely rapid pace. By the end of year 2015, the number of global network connections exceeded two times the world population and it is estimated that in 2020 more than 30 billion devices will be wirelessly connected to the cloud forming the Internet of Things (or“IoT”). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last two decades. Following Moore’s Law, development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) devices allowed incorporation of digital and analog system elements, such as bulky Analog-to-Digital converters or transceivers, into a more cost effective single chip solution.

In the last few years, however, while digital circuits have largely followed the predicted path and benefited from the scaling of CMOS technology into ultra-deep submicron (sub-µm), analog circuits have not been enabled to follow the same trend, and may never be enabled without a paradigm shift in analog design. Analog and radio frequency (or“RF”) designers still struggle to discover how to make high-performance integrated circuits (or“ICs”) for ultra-deep sub-µm feature sizes without losing the benefits of shrinking size; including reduced power, compact footprint, and higher operational frequencies. Truly a paradigm shift is needed to break through the established science of analog design to meet the system on chip (SoC) demands of the new millennium. Prior Art:

The core building block of analog circuits is the amplifier. Discrete component amplifiers are free to use resistors, capacitors, inductors, transformers, and non-linear elements as well as various types of transistors. Unwanted parasitics between various components are normally negligible. However, in order to build amplifiers within an integrated circuit, the normal analog circuit components are not readily available, and often take special IC process extensions to obtain these circuit elements if at all. The parasitics on integrated circuit amplifiers are severe due to their close proximity and being coupled together through the silicon wafer they are integrated into. Moore’s law IC process advancements are focused on digital, microprocessor, and memory process development. It takes a generation (~18 months) or two to extend the IC process to incorporate analog components, thus analog functionality is generally not included on the latest process single chip systems. These“mixed-mode” IC processes are less available, vender dependent, and more expensive as well as being highly subject to parametric variation. It takes substantial engineering to include sparse analog functionality on any IC which becomes specific to its IC vender and process node. Because analog circuitry is carefully and specifically designed or arranged for each process node, such analog circuitry is highly non-portable. Reprobating this limitation, analog circuit design engineers are becoming scarce and are slowly retiring without adequate replacements.

Operational Amplifiers (or OpAmps) are the fundamental IC analog gain block necessary to process analog information. OpAmps make use of a very highly matched pair of transistors to form a differential pair of transistors at the voltage inputs. Matching is a parameter that is readily available on an integrated circuit, but to approach the required level of matching, many considerations are used: like centroid layout, multiple large devices, well isolation, and physical layout techniques among many other considerations. Large area matched sets of transistors are also used for current mirrors and load devices. OpAmps require current sources for biasing. OpAmps further require resistor and capacitor (or RC) compensation poles to prevent oscillation. Resistors are essential for the“R” and the value of the RC time constant is relatively precise. Too big value for a resistor would make the amplifier too slow and too small results in oscillation. Constant“bias” currents add to the power consumed. In general, these bias currents want to be larger than the peak currents required during full signal operation.

As IC processes are shrunk, the threshold voltages remain somewhat constant. This is because the metal-oxide-semiconductor (or MOS) threshold cutoff curve does not substantially change with shrinking of the IC processes and the total chip OFF leakage current must be kept small enough to not impact the full-chip power supply leakage. The threshold and saturation voltage tends to take up the entire power supply voltage, not leaving sufficient room for analog voltage swings. To accommodate this lack of signal swing voltage, OpAmps were given multiple sets of current mirrors, further complicating their design, while consuming more power and using additional physical layout area. This patent introduces amplifier designs that operate even better as power supply voltages are shrunk far below 1 volt.

The conventional MOS amplifier gain formation is an input voltage driving a trans- conductance (g_m) which converts the input voltage into an output current. This output current then drives an output load which is normally the output of a current source for the purpose of establishing a high load resistance. This high resistance load converts the output current back into an output voltage. The equivalent output load resistance is actually the parallel combination of the load current source transistor and the amplifier output transistors. In order to keep this equivalent load resistance high to provide the required voltage gain, these load transistors must be very long, but to drive enough current these transistors must be very wide also, thus very large transistors are necessary. It also might be noted that the load resistance the amplifier output drive is additional parallel resistance that reduces the voltage gain. It should also be noted that a load capacitance interacts with the amplifier’s output resistance, modifying the AC performance. What is actually needed is exactly the inverse operating principle, which the present invention is about.

Normally MOS amplifiers operate within a square-law relationship due to the strong inversion MOS transistor square-law characteristics; these are not very well defined or predictably stable to the degree that analog circuits would need. Exponential-law operation, like bipolar transistors operation is higher gain, stable, and well defined. At very weak operating conditions, MOS transistors convert to exponential operation, but they are too slow to be of very much use. Furthermore, the“moderate-inversion” transition between these two operating modes provide non-linarites that lower the quality of analog MOS circuits. At the threshold voltage, where MOS transistors operate around, is where 50% of the current is square-law and the other 50% is exponential. This is the definition of threshold voltage in the latest MOS simulation equations. Full exponential MOS operation at high speed would provide higher gain that is predictable, stable, and well defined. This patent is about amplifiers that operate in the exponential mode.

Now, building analog circuits on an IC has always been problematic. Engineering around poorly performing analog components has been the overriding objective for analog IC designers since analog circuits have been integrated. This drove the need for digital signal processing with algorithm development yielding digital magic.

Today the real-world of analog circuit design, signals still need to be converted on both the front and back end of signal processing systems. This need has become a road-block at deep sub-µm scale.

Another problem may be that solid-state amplifiers have been notoriously non-linear since their inception. To make them linear, increased open loop gain (with levels significantly higher than is ultimately needed) is traded for control over actual circuit gain and linearity through the use of a closed loop (feedback). A closed loop amplifier requires negative feedback. Most amplifier stages are inverting, providing the necessary negative feedback. A single stage inverter, with a closed loop, is stable (does not oscillate). Increased loop gain requires stages be added such that there are always an odd number of stages (sign is negative), to provide the necessary negative feedback. While a single stage amplifier is inherently stable, three stages and most definitely five stages are unstable (they always oscillate– because they are ring oscillators).

The problem then is how to properly compensate a multi-stage closed loop amplifier while maintaining a reasonable gain-bandwidth product. This is particularly difficult at deep- sub-micron scale where circuit stages must be simple in their design. The severely limited power supply voltages preclude the use of conventional analog design approaches. Additionally, it is desirable to avoid reliance upon analog extensions but rather to accomplish the necessary analog functions using all digital parts, to improve yields and decrease costs. Using all digital parts allows analog functions at process nodes that do not yet have analog extensions, and may never have them.

There is a long-felt need for low-cost / high-performance analog front end devices or components, such as integrated data converters including, but not limited to, analog to digital converters and digital to analog converters, integrated on a single chip for affordable high- volume devices such as the Internet of things, smart-sensors, and other ubiquitous devices. SUMMARY OF THE INVENTION

The present invention relates to an integrated data converter, in particular analog to digital converters and digital to analog converters, using a charge-based approach. The present invention further relates to circuits built out of a novel and inventive compound device structure, which enables a charge-based approach that takes advantage of exponential relationships of a super-saturated source channel field-effect transistor, which possesses sub-threshold-like operation when used for analog CMOS circuit designs. The present invention is an evolution of an ordinary CMOS inverter. It provides extremely high precision, speed, linearity, low noise, and a compact physical layout, using an all-digital nanoscale or deep sub-µm IC process. In addition to the expected digital inverter function, five classes of analog circuits are exemplified: a voltage input amplifier, a current input amplifier, a current inverter as opposed to a current mirror, an adjustable delay circuit, and a voltage or current reference source. Take special note that analog functionality is realized, in a digital IC process, using a single moderately optimized digital logic circuit cell.

According to one aspect of the present invention, it provides a scalable charge based successive approximation analog to digital converter.

According to another aspect of the present invention, it provides a scalable charge based differential successive approximation analog to digital converter.

According to yet another aspect of the present invention, it provides a scalable charge based successive approximation digital to analog converter.

According to yet further aspect of the present invention, it provides a scalable charge based differential successive approximation digital to analog converter.

According to yet further aspect of the present invention, it provides a charge based pipe- line digital to analog converter.

According to yet further aspect of the present invention, it provides a charge based pipe- line differential digital to analog converter.

According to yet further aspect of the present invention, it provides a charge based pipe- line analog to digital converter. According to yet further aspect of the present invention, it provides a charge based pipe- line differential analog to digital converter. BRIEF DESCRIPTION OF FIGURES:

Figure 1 illustrates a three (3) dimensional prospective view of a current field-effect transistor (or iFET) with a new mid-channel bi-directional current port (iPort) of the present invention;

Figure 2 illustrates a cross-sectional view of iFET of the present invention with visualized channel charge distributions;

Figure 3 shows schematic diagrams of various iFETs of the present invention;

Figure 4 illustrates a schematic diagram of complimentary pair of iFETs (or CiFET) of the present invention;

Figure 5 illustrates a physical layout abstraction of a complementary pair of iFETs (or CiFET) compound device of the present invention;

Figure 6 shows a three (3) dimensional perspective view of the CiFET compound device; Figure 7 illustrates cross-sectional view at Section AA of Figure 5 or 6;

Figure 8a illustrates a schematic diagram of a 3-Stage compensated CiFET amplifier (or CiAmp) transistor of the present invention;

Figure 8b illustrates a symbol for the CiAmp of the present invention;

Figures 9a and 9b show schematic diagrams of a bit-slice of a compact DAC (with ½ gain) including voltage addition capability using a sample and hold amplifier in accordance with the present invention;

Figures 10a and 10b illustrate schematic diagrams of a successive-approximation digital to analog converter (DAC) of the present invention;

Figures 11a and 11b illustrate schematic diagrams of a preferred embodiment of a bit- slice of a high precision full-differential digital to analog converter (DAC) of the present invention;

Figures 12a and 12b illustrate schematic diagrams of a successive-approximation differential DAC of the present invention;

Figures 13a and 13b illustrate schematic diagrams of a bit-slice of analog to digital converter (ADC) of the present invention; Figures 14a and 14b illustrate schematic diagrams of a successive-approximation analog to digital converter (ADC) of the present invention;

Figures 15a and 15b illustrate schematic diagrams of a bit-slice of differential ADC of the present invention;

Figures 16a and 16b illustrate schematic diagrams of a successive-approximation differential ADC of the present invention;

Figures 17a and 17b illustrate schematic diagrams of a pipe-line DAC of the present invention;

Figures 18a and 18b illustrate schematic diagrams of a pipe-line differential DAC of the present invention;

Figures 19a and 19b illustrate schematic diagrams of a pipe-line ADC of the present invention;

Figures 20a and 20b illustrate schematic diagrams of a pipe-line differential ADC of the present invention;

Figure 21 illustrates one example of timing diagram and output data of an ADC (one shown in Figures 14a and 14b);

Figure 22 illustrates one example of timing diagram and output voltage of a differential DAC (one shown in Figures 12a and 12b);

Figure 23 illustrates data converter operating voltages ranges of the present invention; and

Figure 24 illustrates a functional diagram of two-phase data converter of the present invention. DETAILED DESCRIPTION OF THE INVENTION A MOS structure referred to herein as an iFET, where the letter“i” refers to a current and “FET” refers to a Field Effect Transistor, is the enabling element of several high performance and novel designs of the present invention. The present invention is based on the addition of a direct connection to a mid-point in a Field Effect Transistor (or FET) channel and the realization that this is a low impedance port (current port, or herein referred to as“iPort”) providing a bidirectional current sink/source mid-channel with a very low input impedance at a low saturation voltage, and additionally connecting reciprocal iFETs pairs of opposite“conductivity type” (P-type & N-type) interconnected to take advantage of their complementary nature to operate as a team and symmetry to self-bias near the midpoint between power supplies. In addition, the relative strength of the first and second channels of the iFETs can be adjusted (threshold choice, relative sizing, and doping profiles) to tailor the gain, speed, quiescent current and input impedance of such a complementary iFET (or CiFET) compound device of the present invention.

The iFET, with its iPort provides an uncommon and unexpected solution to the compensation problem, and then continues to provide new or alternative solutions to other old problems, exceeding industry expectations. The advantages of operating circuits in“weak inversion” have long been known but, so also has problems. The CiFET enable circuits to exploit the high gain and wider dynamic range available in“weak inversion,” without sacrificing superior speed performance. The CiFET compound device provides a standard active IC gain device that is superior to ordinary analog MOSETs making digital ICs host analog functionality. It is not a tradeoff.

The following is a list of some of the unusual aspects of a CiFET based circuit, including, but not limited to:

x Operates at low power supply voltage;

x High gain;

x Extremely linear;

x Very high speed (wide band);

x Self-Biasing;

x Low noise;

x Quick recovery (DC);

x Uses all digital parts and processes;

x iPorts respond to charge (things in nature are charge based) rather than Voltage across a Resistance; and

x iPort has wide dynamic range with constant gain in an open loop.

Referring to Figures 1 and 2, according to a preferred embodiment of the present invention, it provides a current FET (or iFET) 200, which is comprised of substrate 26, source terminal 24. and drain terminal 29, defining therebetween two channels 23 and 25, on the substrate 26, typically the first (source channel 23) is connected to the power supply (not shown) while the second (drain channel 25) connects to the load (not shown). The substrate 26 is N- or P-type. The two channels, source and drain channels 23 and 25, respectively, are connected to each other as shown in Figures 1, and 2, at the iPort control terminal 21, and the channels 23 and 25 share a common gate control terminal 27. This configuration means that the iFET 200 has more than one control input terminal.

The gate control terminal 27 operates like a conventional MOSFET insulated gate, with its high input impedance and a characteristic Trans-conductance (g_m) transfer function. Typical values of (g_m) for a small-signal MOSFET transistor are 1 to 30 millisiemens (1 millisiemen = 1/1K-ohm) each, a measure of Trans-conductance.

The iPort control terminal 21 is low impedance with respect to the source terminal 24, and has a transfer function that looks more like beta (ȕ) of a bipolar transistor, but is actually Trans-resistance (or r_m), or more generally, especially at high frequencies, Trans-impedance, measured in K-ohms, where the output voltage is a consequence of an input current. Depending on the channel sizing ratio of the CiFET the typical resistance values (or values of r_m) for a small-signal iFET transistor 200 DUH^IURP^^.^^WR^^0^^^D^PHDVXUH^RI^7UDQV-resistance. Current input to voltage output (Trans-impedance) is the basis for the assertion that 1µA in will yield an output of 100mV (or a gain of 100,000:1) at a large signal level, or 1pA in will yield an output of 100 nanoV (or a gain of 100,000:1) in a low noise amplifier (or LNA) (both results from the same circuit and linear over this dynamic range).

These values have been shown to remain true for a single minimum sized iFET, with inputs from 1 pico-ampere to 10 micro-amperes, using the same circuit in simulation. In 180 nm CMOS construction the noise floor limits measurements below about 10 pico-amps. iFETS can be constructed with different length to width proportions with very predictably differing results.

High gain, uncharacteristic or surprising results differing from the state of the art designs, is the result of the“Weak inversion” characteristics of the source channel 23 of the iFET 200 operating in a highly ionized super-saturation mode of Figure 2.

Speed in this super-saturated source channel 23 is not limited by the transit time of carriers along the channel 23, but the high concentration of ionized charge carriers in the active channel only have to push the surrounding charge a little as charge is either added or removed from the channel 23 by means of the iPort control terminal 21, resulting in a diffusion current which is defined by exponential relationship as has been realized when a MOSFET is operated in weak-inversion. This is in contrast to an electric field causing the charge to transit the channel, which is a square-law function of the gate control voltage. In this configuration, speed is faster than logic built from the same fundamental transistors and unhampered by the“Weak inversion” stage that has higher gains like bipolar transistors. As opposed to bipolar transistors, control current can go either in or out of the iPort control terminal 21 as well as operate with no iPort current, which is useful for creating a self-bias operating point. Current summed into either or both iPorts linearly raises the output voltage by a trans-resistance (r_m). Since the input resistance is essentially constant, the input current has an equivalent input voltage effecting a voltage gain over an excessively wide dynamic range of ~10 decades which is linear from noise floor to saturation. Output impedance is also low for efficiently driving parasitic laden loads.

Lower noise is facilitated by the self-biased operating point. Here the potential at drain terminal 29 is the same as potential at the gate control terminal 27, greatly reducing the pinch-off effect found in conventional analog circuit designs.

The iFET 200, because of the common gate connection over the source channel 23 and the drain channel 25, places a higher than expected voltage on the gate control terminal 27 (or GS) of the source terminal 24 or source channel 23. This higher than expected voltage is responsible for a much thicker and deeper (lower resistance highly ionized) conduction layer, allowing the majority of carriers to avoid the traps in the surface of the crystal lattice, hence– much lower noise similar to the manner in which a junction field effect transistor (or j-FET) conduction channel is located below the surface.

Trans-resistance (r_m) is the“dual” of Trans-conductance (g_m). When you look up Trans- resistance, most of the references are to inductors and capacitors, suggesting that the iFET may be useful in synthesizing inductors.

The iFET works in the following ways: A low noise amplifier requires a low impedance channel. A low impedance channel is low in voltage gain while high in current gain. To establish voltage gain, a second stage, operating as a current to voltage converter, is required. A cascaded pair provides such a configuration. Biasing requirements for a cascaded pair preclude its use at low voltage unless a solution for the biasing problem is found. The iFET provides the solution to this problem through self-biasing of a complementary pair. The impedance of the channel can be designed to accommodate the impedance of the particular signal source driving it (see later section on ratio). Regarding FETs in general, carriers are attracted to the surface by the gate field, a low gate voltage creates a thin surface-layer on the channel (where the conductivity takes place) while a higher gate voltage creates a thicker under-layer due to like charges pushing apart or dispersing. The thin layer of carriers is impeded by the non-uniform surface defects resulting in 1/frequency“pink” electrical noise, while a thicker layer of carriers finds a smoother path below the surface, thus reducing total electrical noise. This indicates that higher gate voltage translates to lower noise. Channel resistance is also lower providing lower frequency flat“white” resistance noise.

Referring to Figure 2, in the iFET 200, the electric field created by the gate voltage Vg on the gate control terminal 27 causes carriers to rise from the substrate 26 into the source channel 23 region converting the semiconductor material to a conductor with a relatively large number of carriers per volume or at saturation, thus establishing a level of conductivity.

Injection current I_inj introduced into the iPort control terminal 21 increases the diffused charge (number of carriers per volume) over and in the source channel 23, thus making the source channel 23 even more conductive. The rate of conductivity change is exponential, similar to that found in“weak inversion.” This exponential rate of conductivity change is due to the low voltage gradient along the source channel 23 (source terminal 24 to iPort control terminal 21 voltage gradient). This is diffusion driven current (exponential) as opposed to square-law voltage driven current.

The iFET exponential relationship between source channel 23 charge and gate voltage 27 provides access to log functionality, where the addition of two log functions is equivalent to multiplication. A reverse anti-log, or reverse-exponential, operation recovers the analog output through the opposing complementary iFET channel. Such exponential relationship may be used for various low noise amplifier applications. The exponential relationship is also responsible for the wider dynamic range of these iFET circuits.

Again, referring to the source region in Figure 1, removing charge (number of carriers per volume) from the iPort control terminal 21 results in reduced conductivity of the semiconductor material in the source channel 23. In this respect, the iPort control terminal 21-to-source terminal 24 connection operates in a manner similar to the base-region of a bipolar transistor (which is exponential): the more control current to the iPort control terminal 21, the more the device conductivity (g_m). The drain channel 25 of the iFET 200 of Figure 1 operates more like a conventional FET, in that the thickness of the drain channel 25 is greater near the iPort control terminal 21 (same thickness as the source channel 23) and tapers as it reaches its diffusion region around the drain terminal 29 (the decreasing voltage differential between drain channel 25 and gate control terminal 27 diminishes the field) establishing the output resistance of the transistor as set by the gate voltage V_g. A lower drain voltage V_d (close to the voltage found on the gate), decreases the drain channel output resistance (thicker channel at the drain diffusion). Along with a thicker conduction layer, this lower drain channel resistance results in lower noise and a high output drive capability to establish the desired drain voltage at the drain terminal 29 with a low impedance drive offered by the thick conduction layer.

Diffusion regions around the source region 24 of the iFET 200, operating at a low voltage, has lower voltage gain but it also has low noise. Diffusion region around the drain terminal 29, operating at a higher voltage, provides the desired voltage gain with a minimal noise contribution, due to the drain voltage being the same as the gate voltage V_g. This voltage equality is contributed by a unique biasing construct, to be explained hereinafter.

Regarding the iPort control terminal, in the case of both the N-channel and P-channel devices, a positive current into either iPort control terminal displaces an equivalent current going through the related drain channel, causing the drain (output) connection to move in a positive voltage direction– thus the non-Inverting nature of both iPort inputs.

The iPorts also operate as a current inverter as opposed to a conventional current mirror. While a single iFET has interesting characteristics on its own, a complementary pair of iFETs (or CiFET) prove to be much more beneficial. Using the opposite semiconductor type iFET as a load device conveniently provides the opposing iFET its bias and in addition has the advantage of balancing out (linearizing) the inherent non-linarites of MOSFET operation. For instance, the high-gain exponential characteristics of the source channel’s super-saturated operation are linearized over an extremely wide dynamic range by the exponential characteristics of the complementary load’s super-saturated source channel.

The resulting complementary device (the seminal CiFET cell) is arguably the highest possible power gain-bandwidth MOSFET amplifier stage possible. For instance, looking into either iPort, the super-saturated source channel input impedance is a relatively low number constant resistance. This converts any input current into a small input voltage, which calculates out to be a very high voltage gain transfer function implemented by the high number r_m trans- resistance. In addition, the sub-surface operation of the super-saturated source channel may operate with the lowest noise possible for any MOS device. The drain channel also maximally operates below its surface defects for low noise. In the end it is all about signal-to-noise ratio.

Figure 4 presents a schematic diagram of a seminal complementary pair of iFETs (or CiFET) of the present invention, and Figure 5 show a diagrammatically similar physical layout abstraction thereof; and, Figure 6 shows three(3) dimensional perspective view and Figure 7 illustrates cross-sectional view at Section AA in Figure 5 or 6. The complementary pairs of iFETs are built entirely from logic components, without analog extensions, while enabling scaling and portability. Both the footprint and the power consumption per gain/bandwidth are drastically reduced from the present state of the art, while retaining superior noise performance.

Referring to Figure 4, the complementary pair of iFETs (or CiFET) 300 comprises P-type iFET (or PiFET) 310 and N-type iFET (or NiFET) 320, comprising input terminal 301 connected to both the gate control terminal 311 of PiFET 310 and the gate control terminal 321 of NiFET 320, function as the common gate terminal 301. CiFET 300 receives power, Power - and Power +, where Power - is connected to the source terminal 322 of NiFET 320 and Power + is connected to the source terminal 312 of PiFET 310. Each of PiFET 310 and NiFET 320 comprises iPort control terminals (313 and 323, respectively) for receiving injection current. The drain terminal 314 of PiFET 310 and the drain terminal 324 of NiFET 320 are combined to provide output 302.

Figure 5 shows the physical layout abstract of the CiFET 300 including PiFET 310 and NiFET 320 devices of Figure 4.

Referring to Figure 5, the CiFET 300 comprising PiFET 310 and NiFET 320, laid out on the substrate (or body B+ 315 and B- 325, respectively) like a mirror image along well border WB’ shown therein; PiFET 310 comprises source terminal S+ 312, drain terminal D+ 314, and iPort control terminal Pi /diffusion region 313, defining source + channel 316 between the source terminal S+ 312 and the iPort control terminal Pi diffusion region 313, and drain channel 317 between the drain terminal D+ 314 and the iPort control terminal Pi diffusion region 313. NiFET 320 comprises source terminal S- 322, drain terminal D- 324, and iPort control terminal Ni / diffusion region 323, defining source– channel 326 between the source terminal S- 322 and the iPort control terminal Ni diffusion region 323, and drain channel 327 between the drain terminal D- 324 and the iPort control terminal Ni diffusion region 323. CiFET 300 further comprises a common gate terminal 301 connecting gate terminals 311 and 321, covering over source + channel 316, drain + channel 317, and source– channel 326 and drain– channel 327. Accordingly, and effectively, the common gate terminal 301 is capacitively coupled to the channels 316, 317, 326, and 327.

Figure 6 is a 3-Dimensional representation of the CiFET physical layout of Figure 5 and Figure 7 is a cross-section AA of Figure 5 or 6. As it can be seen, CiFET 300 includes PiFET 310 and NiFET 320 connected together with well border WB.

Figure 3 shows schematic diagrams of various iFET devices of the present invention. A P-type iFETs (PiFET) 30a and 30b, and an N-type iFETs (NiFET) 30c and 30d are shown. PiFET 30a includes a gate terminal 31a, source terminal 32a, drain terminal 34a and iPort (or PiPort) terminal 33a. PiFET 30b is yet another way of representing a PiFET, including a gate terminal 31b, source terminal 32b, drain terminal 34b and iPort (or PiPort) terminal 33b, and N- body terminal 35b. NiFET 30c includes a gate terminal 31c, drain terminal 34c, source terminal 32c and iPort (or NiPort) terminal 33c. NiFET 30d is yet another way of representing a NiFET, including a gate terminal 31d, drain terminal 34d, source terminal 32d and iPort (or NiPort) terminal 33d, and P-body terminal 35d.

For example, NiFET 30c or 30d represents an n-type iFET (or NiFET) with longer source channel between the drain terminal 34c or 34d and iPort terminal (or NiPort) 33c or 33d, and thus, as it can be seen, NiPort 33c or 33d is shown near the drain terminal 34c or 34d. An example sizing of the NiFET device 30c may be, for drain channel with 2XW_min / L_min while the source channel is W_min / 2XL_min for an iFET ratio of 1/4. This NiFET would allow for higher input iPort resistance for higher gain uses, which is useful for voltage input amplifier applications. Similarly, PiFET 30a or 30b is shown to have PiPort terminal 33a or 33b near the drain terminal 34a or 34b as well, which signifies longer source channel.

While iFET amplifiers can be constructed with minimum sized devices which do provide ample current at the output for very fast response and high accuracy, care must be exercised so that the complementary iFET amplifier does not pass too much current, subjecting it to mechanical failure. The physical layout requires enough contacts and metal for the required DC and transient currents. Figure 8a shows a three (3) stage voltage amplifier (or CiAmp) 600 of a preferred embodiment of the present invention, and Figure 8b shows a symbol diagram of the CiAmp 600. CiAmp 600 includes an inverting input 60in, injection current ports +Pi 60pi and +Ni 60ni, an output 60out, a first CiFET P50a consisting of a first complimentary pair of PiFET Q51a and NiFET Q52a, second CiFET P50b consisting of a second pair of PiFET Q51b and NiFET Q52b, third CiFET P50c consisting of a third pair of PiFET Q51c and NiFET Q52c, which are connected in series where the input of the subsequent pair is fed from the output of the previous pair as shown therein. The input 60in of the multistage amplifier 600 is connected to input 301a of the first CiFET P50a, PiFET Q51a and NiFET Q52a, which are, in turn, connected to the gate ports thereof; the drains from the first pair of PiFET Q51a and NiFET Q52a form output 302a of the first CiFET P50a, which is connected to the input 301b of the second CiFET P50b, PiFET Q51b and NiFET Q52b; then the drains of the second pair of PiFET Q51b and NiFET Q52b form output 302b, which, in turn, is connected to the input 301c of the third CiFET P51c, complementary pair of PiFET Q51c and NiFET Q52c. Drains of the third pair of PiFET Q51c and NiFET Q52c form as output 302c for output 60out of the CiAmp 600. Now, the output of the second CiFET P50b, PiFET Q51b and NiFET Q52b may be connected through roll-off capacitors C51 and C52 as injection current i51a and i52a of the first CiFET P50a, PiFET Q51a and NiFET Q52a.

The circuit in Figure 8 may optionally comprise a“feed-forward” CiFET P50d, PiFET Q51d and NiFET Q52d, for enhanced speed and improved stability. The input of the feed- forward pair P50d of NiFET Q51d and PiFET Q52d are connected to the input 60in of the amplifier 600, and the output 302d of the feed forward pair P50d of NiFET Q51d and NiFET Q52d is joined with the output 302c of the third pair P50c of PiFET Q51c and NiFET Q52c.

The third pair P50c of PiFET Q51c and NiFET Q52c provides the necessary sign inversion for a functional high gain, closed loop amplifier. In addition, a“feed forward” circuit P50d including PiFET Q51d and NiFET Q51d provides early movement on the output (with lower gain) while the first three CiFET stages provide a more accurate output signal (with higher gain) later on.

Upon initial inspection of the circuit configuration, it appears that transistors or PiFET Q51c and NiFET Q52c compete with transistors or PiFET Q51d and NiFET Q52d. However, the ultimate output voltage destination for both paths is the same except with a higher accuracy for the longer (later) path.

All but the input stage could be realized with ordinary MOSFETS, however there is a significant gain and bias point matching advantage when employing iFETs for all stages.

In Figure 8 with feed forward pair P50d, the result is a 3-stage, compensated, high gain amplifier; with“feed forward” for enhanced speed, with a dominantly slow stage Q51b and Q52b for stability.

Because the stages are self-biased to operate at their maximum gain point, this configuration operates at speeds in excess of the logic transition time of the surrounding digital neighbors without employing any analog process extensions.

The entire circuit is constructed with small size devices; so, the footprint is unexpectedly small, the physical circuit layout parasitics are minimized, the speed is greatly enhanced, and the power consumption is extremely small as compared to prior art.

Figure 24 shows a functional or architectural diagram of a two-phase data converter 2000 in accordance with the present invention. The data converter 2000 operates between two phases of a control signal, including“setup” phase 2000a and“enable” phase 2000b. The data converter 2000 comprises a capacitance stack 2010, offset capacitor stack 2011, and an inverting amplifier 2012. The capacitance stack 2010 includes a plurality of flying or sampling capacitors, and the offset capacitor stack 2011 also includes a couple of offset capacitors. The capacitance stack 2010, and offset capacitor stack 2011 are configured differently accordingly to the phase of the control signal as further described below.

During“setup” phase 2000a, the capacitance stack 2010 is configured to sample and store residual inputs 2000in+ and 2000in- (or input voltage therebetween), it further causes the inverting amplifier 2012 to be self-biased by feeding its output back to its input, and causes the offset capacitor stack 2011 to sample and store differential voltage between a reference voltage 2000Ref and the self-biased voltage of the inverting amplifier 2012, and to sample and store differential voltage between an analog ground 2000 and the self-biased voltage of the inverting amplifier 2012.

During“enable” phase 2000bˈ the capacitance stack 2010 is configured differently to provide an integer multiplication or division of the sampled / stored residual input voltage to the offset capacitor stack 2011 to add or subtract therefrom either the differential voltage between a reference voltage 2000Ref and the self-biased voltage of the inverting amplifier 2012 or differential voltage between an analog ground 2000 and the self-biased voltage of the inverting amplifier 2012, depending on a data value of a data bit 2000data for producing the resulting output voltage 2000out at the inverting amplifier 2012, and feedback the output 2000out to the capacitance stack 2010.

Note that the capacitance stack 2010 always separates its analog input signal 2000in+, 2000in- from the rest of the data converter on both operational phases 2000a and 2000b of the controlling clock. This provides bi-directional isolation between input and the rest of the data converter at every stage. Also, note that isolating the capacitance stack 2010 from the rest of the data converter allows the input signal to exceed either power supply rail by up to a diode as diagramed in Figure 24. Only magnitude of the input voltage is used when the input voltage is translated from the voltage input in the“sample” phase 2000a to the internal amplifier circuitry in the“enable” phase 2000b. The amplifier does not see the absolute value of the input voltage, but only sees the voltage difference between the data converter’s input terminals.

This architecture of the two-phase data converter 2000 is a fundamental building block for building various digital to analog and analog to digital converters as shown below.

Figure 9a shows a schematic diagram of a bit-slice of a compact DAC (with ½ gain) 900 including voltage addition capability using a sample and hold amplifier in accordance with the present invention.

The circuit 900 includes a CiAmp 600a, (similar to ones shown in Figures 8a and 8b), voltage input 90in, a first reference 90Ref, a second reference or analog ground 90Agnd, control clock 90CLK and a voltage output 60out. The circuit 900 further comprises two flying capacitors, a first flying capacitor 90fc1 and a second flying capacitor 90fc2, and two offset capacitors, a first offset capacitor 90oc1, and a second offset capacitor 90oc2. Each of the capacitors has a first terminal and a second terminal. The second terminals of the first and second offset capacitors 90oc1 and 90oc2 are connected to the input 60ain of the CiAmp 600a. The circuit 900 further includes a plurality of switches which are operable with a control signal / clock 90CLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 90ss1, 90ss2, 90ss3, 90ss4, 90ss5 and 90ss6, which close during“setup” phase of the control clock 90CLK; and“enable” switches 90es1, 90es2, 90es3, and 90es4, which close during “enable” phase of the control clock 90CLK. Step size of the DAC 900 is represented by the voltage difference between the reference 90Ref and analog ground 90Agnd as shown in Figure 23 which abstractly inter-relates data converter operating voltages including input, output, bias point, reference, saturated, and linear dynamic ranges for both DACs and ADCs. The center of the plot is the self-bias point which is the analog zero input operating point (or CiAmp’s analog zero input operating point). The x-axis represents the amplifier input voltage ±deviation from the self-bias operating point voltage where the CiAmp input continually strives for, with the x-axis extremes representing the power supply voltage at the input.

The Y-axis represents the data converter input and output voltage which is divided into several different regions starting with the“Analog Virtual Ground” center-line through the self- bias point. It can be seen that the transfer curve is a straight line with a very steep slope through the center bias point (representing a very high and linear incremental output/input voltage gain) and remains linear between the“-Reference” and“+Reference” horizontal lines. An example slope may represent a voltage gain of 100 million for the CiAmplifiers used. This is the linear transfer region that facilitates high-resolution conversion steps where the core of the conversion process must operate. This linear region typically covers a little more than half the power supply voltage. It is similar to the transfer function slope of a high-gain inverter, but much steeper. The first two stages of the CiAmp Figure 8a always operate close to this self-bias point where they operate with maximum gain. It is the output stage of the CiAmp that can operate a little outside of the optimum self-bias point and has a little lower large signal gain as the output approaches the power rails which are horizontal lines at Vss and Vdd in Figure 23. The amplifier voltage gain determines how close the amplifier output gets to its target voltage at any one step of the conversion process. For instance, an amplifier gain of 1-million with a target of 1-volt displaces the amplifier input down by 1-microvolt from its self-bias voltage resulting in the amplifier output not reaching its target by the same 1-microvolt. So, keeping the amplifier operating in the linear region for the internal data converter stage operation is important as Figure 23 depicts.

For ADC applications, the analog input is sampled onto its parallel input capacitors during the“setup” clock phase. Because the switches are only used in the sample phase, and not the amplifier, the analog input voltage can operate outside of the power rails by as much as limited by forward biasing the protection diodes or the switch body/well diodes. These extended voltage levels are the bottom and top of plot in Figure 23 with the diode scale indicator on the y- axis scale. The left-most vertical arrows indicate the ADC maximum input voltage range. The right-most vertical arrows indicate the maximum DAC output voltage achievable. The other vertical arrow indicates the chosen linear dynamic operating range. The CiAmp amplifier of Figures 8a and 8b has three gain stages P50a, P50b, and P50c which is normally adequate, but an additional pair of CiFET as shown in Figures 4, 5, 6, and 7 stages can be added (not shown) between the second P50b and third P50c stage to increase the gain if needed for increasing voltage gain. Adding too much gain requires additional roll-off capacitance, thus slowing the amplifier down to maintain unity gain stability.

For bipolar operation, the ±analog signal swing is about the analog virtual ground and for unipolar operation, the analog zero is the– Reference voltage with its maximum at the + Reference voltage.

All analog voltages are referenced to analog ground 90Agnd which is optimally located near the midpoint of the power supply voltage as shown in Figure 23. This self-bias voltage is roughly set by increasing the relative PiFET strength (wider P-channel transistor 316 and 317 in Figure 5) to NiFET strength in the CiFET structure. Operable voltage for reference 90Ref would range from voltage as low as signal to noise ratio may allow, and up to about 80% of the voltage difference from virtual analog ground 90Agnd to the nearest power supply voltage. Preferably, the voltage at the reference 90Ref is about 75% of this voltage difference between analog ground 90Agnd and the nearest power supply voltage as shown in Figure 23, which is on a biased CiFET transfer plot for visualization. This leaves an internal data converter voltage swing of about ½ of the power supply.

Data converter operating voltage may be treated as either unipolar or bipolar, but the individual data converter slice internally operates as a bipolar converter in that its analog voltage is referenced to and symmetrically swings about analog ground Agnd 90Agnd which is positioned near the midpoint of the power supply voltage by means of a self-biased CiFET having its drain output connected to its gate input. Operating internal dynamic range extends from the Agnd midpoint voltage to a Ref 90Ref voltage level above or below the half-scale analog ground Agnd. A 2x sample and hold amplifier at the output of a DAC is well suited to extend voltage swings up to as much as rail-to-rail swings, if needed, while holding the previous DAC output voltage during D-to-A conversions. In DAC applications, the reference voltage 90Ref is summed into individual slice converter-stage outputs when their logic data-bit input is a logical-one, and not summed for logical-zero.

The ADC can have a relatively wider analog input dynamic range of up to a diode outside of the power supply rails. This excess voltage swing can be initially divided by 2, or some other integer, down to the desired ADC operating range as is defined by the -Ref to +Ref reference voltage difference which swings around the Agnd ~midpoint self-bias voltage level. The difference between Ref and Agnd is the quantizing voltage level that the ADC digitizes to. In ADC applications, the analog input voltage is only compared to the midpoint Agnd voltage in order to determine if the analog signal is above or below Agnd. This voltage is where simple inverter-based voltage comparators work best.

The comparator (reference numeral 705 in Figure 13a; reference numerals 705b and 705c in Figure 14b; reference numeral 725 in Figure 15a; and reference numerals 725b and 725c in Figure 16b and other related ADC figures) can be either a chain of inverters long enough for sufficient gain or a feedback Data-Latch comparator as commonly used in the art. The comparator can be enhanced by using CiFETs, 600i3, 600i4 as shown in Figure 13a, and to improve the comparator self-biased gain, noise, and speed properties and the comparator circuit may use a feed-forward 70ff1 and 70ff2 as shown in Figure 13a speedup through a capacitive feed-forward charge/current into iPorts. Additional CiFETs 600i2 and 600i3 can also supplement comparator accuracy and speed by arming all the comparator high-gain trip points to the same highest-gain voltage operating-point, so that the initialized CiFETs all start from the same self-bias-point. A buffer stage 600i2 can provide isolation from the comparator latching transient along with a little gain into the latch 600i3 and 600i4. Timing between the switches 70es3 and 70es4 can also be staggered by a pair of inverter delays to keep the latching transient from feeding back into the comparator analog signal path. An example of this CiFET and feed- forward circuit is included as the comparator in ADC slice in Figures 13a, 14b, 15a, 16b and 17b. Because the comparator trip voltage is always identical for any comparison operation, individual data-bit comparisons are indistinguishable from each other regardless of the analog comparator voltage input, thus circumventing dynamic range induced errors. Any parametric or physical induced layout coupled errors are always performed under identical conditions, thus parasitically balancing these errors out along with cancelling out most power supply injected noise. Using a single critical comparator input voltage, as the only voltage level that matters, makes the comparator always operate precisely the same resulting in identical decisions every time. Useable comparator resolution is defined by open-circuit-gain and limited by any transients that interfere with the input signal or move the trip point. The cleanest and highest gain point is at the self-bias point near middle of the power supply voltage where gains are at their peak and parasitics are best balanced out. The optimum compare operation always equates the exact same trip voltage to the input voltage.

Midpoint based analog signal processing is optimal for CiFET gain, bandwidth, slew- rate, symmetry, and other desired properties, while keeping analog voltages away from the power supply to balance-out and moderate noise injection. The power supply voltage can change, but the midpoint remains the midpoint as derived by the sum of the individual iFET operating threshold voltages when the same exact current passes through both polarity iFET transistors connected in series. The steady-state current has nowhere else to go except through the complementary iFET. An increase in one iFET current is the exact same increase in the complementary iFET current of the CiFET combination.

The CiFET amplifier gain stages are conveniently biased at their own self-bias ~midpoint voltage by temporarily connecting amplifier outputs to their input and remembering the self-bias voltage as charge on capacitors. This self-bias voltage turns out to be a precise steady-state amplifier input voltage target, similar to a differential amplifier offset steady-state target. The instantaneous differences between the CiFET amplifier (CiAmp) self-bias voltage to Agnd and to Ref is stored on two different offset capacitors during the“setup” controlling clock phase where it is stored for immediate inclusion in an analog calculation which may include or not-include the addition or subtraction of the reference voltage as a logical one or zero is processed in the data converter slice. Multiple offset storage capacitors enable multiple choices of addition or subtraction for multiple bit processing per stage while keeping the comparator trip point at the same optimal ~midpoint voltage. Multiple bits per stage or flash converters may be produced with these multiple trip points. Because the capacitor voltages are not changed, but only refreshed at each cycle, very small capacitors are necessary, enabling implementation of one of more bit-slice stages to operate as a flash ADC or DAC converter. The capacitors are multiplied by 2n, where n is an integer, but the comparators and amplifiers do not need to be multiplied. The ladder voltages are generated through the same“setup” and“enable” two-phase clocking to series and parallel reconnect the bank of capacitors. It is just an expansion of these data converter capacitor banks to the limit. A 10-bit (1024) flash ADC or DAC becomes practical.

In an ADC, the sample capacitor bank is charged in parallel from its bit-slice input voltage during the“setup” clock phase and then re-assembled to a series/parallel complement and connected in series with the offset capacitors to form a feedback chain of voltages held on capacitors during the“enable” clock phase. The“enable” configuration maintains a high series impedance on the chain of capacitors retaining their precise charge, thus the exact capacitor voltage is maintained independent of the absolute or relative capacitance values. No matching tolerances are required because each capacitor retains its exact charge during the“enable” clock phase. The amplifier input is high impedance on one end of the capacitor sequence although the amplifier output is low impedance on the other end in order to drive the bit-slice output from the voltage on the other end of the capacitor sequence. This means that precision ADCs are made without any precision parts making them independent of their tolerance drifts, in addition to their ability to sample out 1/f noise at each“setup” to“enable” controlling clock phase.

There is one exception to preserving capacitor charge from“setup” to“enable” which is only in the DAC bit-slice data converter application, and is easily corrected if needed without requiring precision or matched parts. The series connected DAC input sample capacitors have their charge redistributed between them when they are re-connected in parallel during the “enable” clock phase making them matching sensitive even though they are not magnitude sensitive. Since the bit-slice input voltage remains constant during the“sample” phase in DAC applications, these capacitors can re-sample the DAC input voltage to readjust their voltage after being connected in parallel, in effect of double sampling the input voltage. The first sample has the mismatch error form redistributing charge between the parallel connected capacitors. When the capacitors double sample the input voltage the charge redistribution errors are reduced below the error limits. The only place that this error is significant is on the last MSB stage where the full error is included in the DAC output voltage build-up. Each preceding stage this error is divided by two. Since the capacitor voltages do not change by much during the double sampled, they do not need the same length of settling time for the number of settling time-constants to settle to the error bands, thus this resampling may be done within the“setup” controlling clock period by double clocking the stages in question. During“setup” phase of the control clock 90CLK, the plurality of switches 90ss1, 90ss2, 90ss3, 90ss4, 90ss5 and 90ss6, and 90es1, 90es2, 90es3, and 90es4, cause to connect the first and second flying capacitors 90fc1 and 90fc2 in series with the input Vin 90in and analog ground 90Agnd (thus, each of the flying capacitors 90fc1 and 90fc2 would be charged with half (to the degree of capacitor matching for the series sampling capacitor arrangement) of the sampled voltage between the positive voltage input 90in and the analog ground 90Agnd, thus, in effect, the flying capacitors 90fc1 and 90fc2 sample the voltage between the input Vin 90in and analog ground 90Agnd. They further cause the CiAmps 600a to be self-biased by feeding back the output 60aout to the input 60ain of the CiAmp 600a to establish its instantaneous operating point as the DAC 900 samples out 1/f noise and IC parametric variations for their cancellation during the following“enable” clock phase. They yet further cause the analog ground 90Agnd to connect to the first terminal of the second offset capacitor 90oc2; and the first reference 90Ref to connect to the first terminal of the first offset capacitor 90oc1. Any difference between the bias voltage and analog ground 90Agnd would be stored as offset voltage on the offset capacitor 90oc2; while the bias voltage and the reference voltage 90Ref would be stored as another offset voltage on the offset capacitor 90oc1.

During“enable” phase of the control clock 90CLK, charge on and thus voltages across the flying capacitors 90fc1 and 90fc2 are preserved by maintaining a high series impedance on at least one side of all the capacitors, and the plurality of switches 90ss1, 90ss2, 90ss3, 90ss4, 90ss5 and 90ss6, and 90es1, 90es2, 90es3, and 90es4 cause a capacitively coupled connection of the output 60aout to the input 60ain of the CiAmp 600a by parallel connecting the first and second flying capacitor 90fc1 and 90fc2, and further connecting parallelly connected first and second flying capacitors 90fc1 and 90fc2 to either one of the first offset capacitor 90oc1 or second offset capacitor 90oc2 in series. In particular, the output 60aout of the CiAmp 600a is connected to the first terminals of the first and second flying capacitors 90fc1 and 90fc2, which form the analog output voltage 90out of DAC 900, and the second terminals of the first and second flying capacitors 90fc1 and 90fc2 are connected to the first terminal of either one of the first or second offset capacitors 90oc1 or 90oc2 (thus in series) to selectively add the offset voltage thereon based on the value on the data 90Data. Thus, in effect, this rearrangement of the connection structures with the flying capacitors 90fc1 and 90fc2 provide an integer division (i.e. /2) of the sampled voltage thereacross with selectively adding the selected offset voltage (on either one of offset capacitors 90oc1 or 90oc2) depending on the data 90Data. In this regard, preferably, a switch 90ds is a two-way switch, selectively connecting the second terminals of the first and second flying capacitors 90fc1 and 90fc2 to either the first terminal of the first offset capacitor 90oc1 or the first terminal of the second offset capacitor 90oc2, depending on the value of data line 90Data. In further preferred embodiment of the present invention, such selection by the two- way switch 90ds may be made based on a bit value of a binary input number, i.e.“0” or“1”, on the data line 90Data. For example, the two-way switch 90ds connects to the second offset capacitors 90oc2 when the bit value on the data 90Data is”0”; while the two-way switch 90ds connects to the first offset capacitor 90oc1 when the bit value on the data 90Data is”1”.

The resulting output voltage is half of the sampled voltage at the input; however, optionally, such gain may be changed, for example, by having more than two flying capacitors. For example, one third (1/3) times gain may be realized by adding an additional flying capacitor (thus total three flying capacitors). In other words, magnitude of the voltage gain at the output is proportional to the number of flying capacitors.

Figure 10a and 10b illustrate schematic diagrams of a scalable successive-approximation digital to analog converter (DAC) 910 of the present invention, including two bit-slice compact DAC 900b and 900c, as shown in Figure 9a or 9b. The two of the bit-slice compact DAC 900b and 900c are connected together in series, while the output Vout 900cout of the DAC 900c is fed back to the input Vin 900bin of the first bit-slice DAC 900b. Clock 910CLK is fed directly to the clock 900bCLK of the first DAC 900b. Clock 910CLK is inverted by the inverter 910Inv and fed to the clock 900cCLK of the second bit-slice DAC 900c to provide 180° phase shift/difference therebetween.

The DAC 910 receives an analog ground 910Agnd, reference voltage 910Ref, data bit stream 910data, and control signal/clock 910CLK for controlling various components within the DAC 910, including the first bit-slice DAC 900b and the second bit-slice DAC 900c.

Conversion step size of the DAC 910 is represented by the voltage difference between the reference voltage 910Ref and analog ground 910Agnd. Operable voltage for the reference 910Ref is grounded at analog Virtual Ground and its magnitude would range from the voltage as low as where signal to noise ratio may allow, and up to about 40% of the voltage supply where non-linearity becomes significant. Depending on how the capacitors are used, the reference voltage may be either positive or negative. Preferably, the voltage at the reference 910Ref is about 30% of the power supply voltage (which is analog ground floated at near 20% of the power supply voltage) as shown in Figure 23.

The first bit-slice DAC 900b includes CiAmp 600b, and comprises two flying capacitors, a first flying capacitor 91fc1 and a second flying capacitor 91fc2, and two offset capacitors, a first offset capacitor 91oc1, and a second offset capacitor 91oc2, which are connected to the input 60bin of the CiAmp 600b as described previously. The DAC 900b further includes a plurality of switches which are operable with the control signal / clock 910CLK / 900bCLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 91ss1, 91ss2, 91ss3, 91ss4, 91ss5 and 91ss6, which close during“setup” phase of the control clock 910CLK / 900bCLK; and“enable” switches 91es1, 91es2, 91es3, and 91es4, which close during“enable” phase of the control clock 910CLK / 900bCLK. The DAC 900b further comprises initialization switches 91is1 and 91is2, which work on the flying capacitors 91fc1 and 91fc2 to ensure“zero” charge or voltage at the beginning of the data conversion by shortening the first and second terminals of each of the flying capacitors 91fc1 and 91fc2. During the initialization phase, the initialization switches 91is1 and 91is2 (with, for example, additional components (not shown)) may optionally connect the first terminals of flying capacitors 91fc1 and 91fc2 to analog reference 910Ref and the second terminals of the flying capacitors 91fc1 and 91fc2 to analog ground 910Agnd for including a half data-number offset to the final DAC output voltage. In this regard, if the flying capacitors 91fc1 and 91fc2 are initialized by connected to the reference 910Ref, a half-step data value offset in the final DAC output 910out, making the quantization steps center on the intended data value/voltage instead of output at the intended data voltage.

The second bit-slice DAC 900c includes CiAmps 600c, and comprises two flying capacitors, a first flying capacitor 92fc1 and a second flying capacitor 92fc2, and two offset capacitors, a first offset capacitor 92oc1, and a second offset capacitor 92oc2. Each of the capacitors has a first terminal and a second terminal. The second terminals of the first and second offset capacitors 92oc1 and 92oc2 are connected to the output 60cin of the CiAmp 600c. The DAC 900c further includes a plurality of switches which are operable with the control signal / clock inverted 910CLK or 900cCLK that alternates“enable” and“setup” phases repeatedly, including“setup” switches 92ss1, 92ss2, 92ss3, 92ss4, 92ss5 and 92ss6, which close during “enable” phase of the control clock 910CLK (or“setup” phase of the clock 900cCLK); and “enable” switches 92es1, 92es2, 92es3, and 92es4, which close during“setup” phase of the control clock 910CLK (or“enable” phase of the clock 900cCLK).

The DAC 910 processes data from the least significant bit; the first bit-slice DAC 900b processes the odd bits from the least significant bit, and the second bit-slice DAC 900c processes the even bits, which is the second least significant bit.

The DAC 910 would first go through an initialization phase, where the initialization switches 91is1 and 91is2 cause the flying capacitors 91fc1 and 91fc2 to be discharged or“zero” voltage. The control clock 910CLK, then, goes into the opposite“enable” phase for processing the first least significant bit (or first odd bit) of the data through the odd bit data 910od from the data 910data at the first bit-slice 900b.

During the first“setup” phase of the control clock 910CLK / 900bCLK, one of the setup switches, namely 91ss1, is kept open for refraining from accepting input at Vin 900bin from the Vout 900cout, thus in effect, it prevents the flying capacitors 91fc1 and 91fc2 of the first bit- slice DAC 900b from referring from the Vout 900cout of the second DAC 900c.

Then, the control clock 910CLK / 900bCLK phases into“enable” phase for the first bit- slice DAC 900b, thus, clock 900cCLK is in“setup” phase for the second DAC 900c to start processing the second least significant bit (or first even bit) of the data through the even bit data 910ed from the data 910data, while receiving the resulting output through the output Vout 900bout from the first stage DAC 900b. As described above, the first stage bit-slice 900b provides an integer division (i.e. /2) of the sampled voltage at Vin 900bin with addition of half- scale reference 910Ref voltage when the bit value of the odd bit 910od through data 900bData is “1”, while no voltage is added when the value is“0”.

Thereafter, the control clock 910CLK phases into the subsequent“setup” stage, thus, “enable” phase for the second bit-slice DAC 900c, the second bit-slice DAC 900c provides an integer division (i.e. /2) of the sampled voltage at Vin 900cin with addition of half-scale of the reference 910Ref if the bit value of even bit data 910ed through the data 900cData is“1”, or no additional voltage if the value is“0”. Resulting voltage at the output Vout 900cout from the second stage DAC 900c is, then, fed back through switch 91ss1 to the input Vin 900bin of the first stage DAC 900b (which is in“setup” phase) to start processing the third least significant bit (or second odd bit) of the data 900bData through the odd data 910od from the data 910data; further thereafter, the control clock 910CLK phases into“enable” stage, the output Vout 900bout, which is an integer division (i.e. /2) of the sampled voltage at Vin 900bin with addition of the half-scale of the reference 910Ref if the bit value of odd bit data 910od through the data 900cData is“1”, or no additional voltage if the value is“0”, is then fed to the second stage DAC 900c (which is in“setup” phase”) to start processing the fourth least significant bit (or second even bit) of the data 900cData through the even data 910ed from the data 910data.

The above mentioned process may repeat until the entire data bits are processed to produce an approximate-successive voltage output at the output 910out.

Figure 17a and 17b show schematic diagrams of a pipe-line DAC 960 of the present invention, including four (4) bit-slice compact DACs 900e, 900f, 900g and 900h, as shown in Figure 9a or 9b, for processing 4-bits plus a half-bit offset data. The DAC 960 receives an analog ground 960Agnd, reference voltage 960Ref, data bit stream 960data, and a control signal 960CLK for controlling various components within the DAC 960. In a preferred embodiment of the present invention, the clock 960CLK is fed directly to operate the bit-slice compact DACs 900e and 900g, which are for processing“odd” bits, and the clock 960CLK is inverted by the invertor 960inv and fed to control / operate the bit-slice compact DACs 900f and 900h, which are for processing“even” bits. While the figures show four (4) bit DAC, it may be apparent that as many of these stages can be connected together in series as desired forming a scalable data converter. The number of stages, sizing of capacitors, noise floor, and clock speed limit the resolution for any given IC process, but the data converters are highly scalable across IC process nodes.

A few design considerations can be included to enhance these limits, such as voltage scaling, special outer voltage switches with reduced turn-off charge injection, and double sampling the analog voltage input to eliminate matching requirements on flying capacitors used in series sampling for divide operations only.

The first DAC bit-slice 900e includes a CiAmp 600g1, and comprises two flying capacitors, a first flying capacitor 96fc1 and a second flying capacitor 96fc2, and two offset capacitors, a first offset capacitor 96oc1, and a second offset capacitor 96oc2. Each of the capacitors has a first terminal and a second terminal. The second terminals of the first and second offset capacitors 96oc1 and 96oc2 are connected to the input 60g1in of the CiAmp 600g1. The DAC 900e further includes a plurality of switches which are operable with the control signal / clock 900eCLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 96ss1, 96ss2, 96ss3, 96ss4, and 96ss5, which close during“setup” phase of the control clock; and“enable” switches 96es1, 96es2, 96es3, and 96es4, which close during“enable” phase of the control clock 900eCLK. The DAC 960 further comprises two two-way switches or data switches 960ds0 and 960ds1, data switch 960ds0 operates during“setup” phase of the control clock 900eCLK depending on the data value on the offset control bit 960OS of the data stream 960data (used for ½ step offset control), while the data switch 960ds1 operates during“enable” phase of the control clock 900eCLK to select which offset capacitor 96oc1 or 96oc2 is included in the amplifier feedback depending on the data value on bit 1960B1 of the data stream 960data.

The second DAC bit-slice 900f includes CiAmp 600g2, and comprises two flying capacitors, a first flying capacitor 97fc1 and a second flying capacitor 97fc2, and two offset capacitors, a first offset capacitor 97oc1, and a second offset capacitor 97oc2. Each of the capacitors has a first terminal and a second terminal. The second terminals of the first and second offset capacitors 97oc1 and 97oc2 are connected to the input 60g2in of the CiAmp 600g2. The DAC 900f further includes a plurality of switches which are operable with the control signal / clock 900fCLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 97ss1, 97ss2, 97ss3, 97ss4, 97ss5, and 97ss6 which close during“enable” phase of the control clock 900fCLK; and“enable” switches 97es1, 97es2, 97es3, and 97es4, which close during“setup” phase of the control clock 900fCLK. The second DAC 900f further comprises a data switch 960ds2, which operates during“enable” phase of the control clock 900fCLK and depending on the data value on bit 2960B2 of the data stream 960data.

The third DAC bit-slice 900g includes CiAmps 600g3, and comprises two flying capacitors, a first flying capacitor 98fc1 and a second flying capacitor 98fc2, and two offset capacitors, a first offset capacitor 98oc1, and a second offset capacitor 98oc2. Each of the capacitors has a first terminal and a second terminal. The second terminals of the first and second offset capacitors 98oc1 and 98oc2 are connected to the output 60g3in of the CiAmp 600g3. The third DAC 900g further includes a plurality of switches which are operable with the control signal / clock 900gCLK that alternates“setup” and“enable” phases repeatedly, including “setup” switches 98ss1, 98ss2, 98ss3, 98ss4, 98ss5, and 98ss6 which close during“setup” phase of the control clock 900gCLK; and“enable” switches 98es1, 98es2, 98es3, and 98es4, which close during“enable” phase of the control clock 900gCLK. The third DAC 900g further comprises a data switch 960ds3, which would be operated during“enable” phase of the control clock 900gCLK and depending on the data value on bit 3960B3 of the data stream 960data.

The fourth DAC bit-slice 900h includes CiAmps 600g4, and comprises two flying capacitors, a first flying capacitor 99fc1 and a second flying capacitor 99fc2, and two offset capacitors, a first offset capacitor 99oc1, and a second offset capacitor 99oc2. Each of the capacitors has a first terminal and a second terminal. The second terminals of the first and second offset capacitors 99oc1 and 99oc2 are connected to the output 60g4in of the CiAmp 600g4. The DAC 900h further includes a plurality of switches which are operable with the control signal / clock 900hCLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 99ss1, 99ss2, 99ss3, 99ss4, 99ss5, and 99ss6 which close during“enable” phase of the control clock 900hCLK; and“enable” switches 99es1, 99es2, 99es3, and 99es4, which close during“setup” phase of the control clock 900hCLK. The DAC 900h further comprises a data switch 960ds4, which would be operated during“enable” phase of the control clock 900hCLK and depending on the data value on bit 4960B4 of the data stream 960data.

During the operation of the DAC 960, Offset Control bit 960OS and the least significant bit 900B1 of the data stream 960data are processed at the first stage DAC 900e during the first cycle of the control clock 900eCLK (960CLK). As described previously, as phased into“enable” phase from the“setup” phase of the control clock 900eCLK (960CLK), depending on the value of the least significant bit 960B1 at the data 900eData through the data stream 960data, the first DAC 900e adds a half-scale reference voltage 960Ref to an integer division (i.e. / 2) of its input voltage 900ein when the value 960B1 is“1”.

The resulting output voltage is half of the sampled voltage at the input; however, optionally, such gain may be changed, for example, by having more than two flying capacitors. For example, one third (1/3) times gain may be realized by adding an additional flying capacitor (thus total three flying capacitors). In other words, magnitude of the voltage gain at the output is proportional to the number of flying capacitors. Then the resulting voltage at the output 900eout from the first stage DAC 900e would be passed onto the input 900fin of the second stage DAC 900f as the second stage DAC 900f is in “setup” phase of the control clock 900fCLK (inverted control clock 960CLK). The second stage DAC 900f further processes the bit 2900B2 of the data 900fData from the data stream 960data. As it phases into the“enabling” phase from the“setup” phase of the clock 900fCLK (inversion of the control clock 960CLK), depending on the value of the second least significant bit or first even bit 960B2 at the data 900fData through the data 960data, the second DAC 900f adds a half-scale of the ref 960Ref to its divided /2 input voltage 900fin when the value 960B2 is“1”, or does not add voltage if the value is“0”.

The resulting voltage at the output 900fout from the second stage DAC 900f would be passed onto the input 900gin of the third stage DAC 900g as the control clock 900gCLK (960CLK) is in“setup” phase. The third stage DAC 900g further processes the bit 3 900B3 at the data 900gData from the data stream 960data. As it phases into the“enabling” phase from the “setup” phase of the clock 900gCLK (960CLK), depending on the value of the third least significant bit or second least odd bit 960B3 at the data 900gData through the data 960data, the third DAC 900g adds the reference voltage 960Ref to its divided /2 input voltage 900gin when the value 960B3 is“1”, or does not add voltage if the value is“0”.

The resulting voltage at the output 900gout from the third stage DAC 900g would be passed onto the input 900hin of the fourth stage DAC 900h as the fourth stage control clock 900hCLK (inversion of the clock 960CLK) is in the“setup” phase. The fourth stage DAC 900h processes the bit 4900B4 of the data 900hData from the data stream 960data. As it phases into the“enabling” phase from the“setup” phase of the clock 900hCLK (inversion of clock 960CLK), depending on the value of the most significant bit or second least even bit 960B4 at the data 900gData through the data 960data, the fourth DAC 900h adds a the reference voltage 960Ref to its divided /2 input voltage 900hin when the value 960B4 is“1”, or does not add voltage if the value is“0”. The output 900hout from the fourth DAC 900h is the output 960out of the pipe-lined DAC 960.

Figure 11a and 11b show schematic diagrams of a bit-slice of a high precision differential digital to analog converter (DAC) 930 of the present invention. Similar to the bit slice DAC shown in Figures 9a and 9b, the DAC 930 would be a building block for constructing scalable successive-approximation DACs and pipe-line DACs, which will be discussed in the following detail.

The circuit 930 includes two CiAmps including a first CiAmp 600d1 and a second CiAmp 600d2, positive voltage input 930in+, negative voltage input 930in-, analog ground 930Agnd, a reference 930Ref, control clock 930CLK, positive voltage output 930out+ and negative voltage output 930out- in addition to a data control input 930Data. The circuit 930 further includes two flying capacitors including first and second flying capacitors 93fc1 and 93fc2, two offset capacitors including a first offset capacitor 93oc1 and a second offset capacitor 93oc2 for the first CiAmp 600d1; and another two flying capacitors including third and fourth flying capacitors 93fc3 and 93fc4, and another two offset capacitors including a third offset capacitor 93oc3 and a fourth offset capacitor 93oc4 for the second CiAmp 600d2. Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 93oc1 and 93oc2 are connected to the input 60d1in of the first CiAmp 600d1, and the second terminals of the third and fourth offset capacitors 93oc3 and 93oc4 are connected to the input 60d2in of the second CiAmp 600d2. The circuit 930 further includes a plurality of switches which are operable with the control signal clock 930CLK that alternates“setup” and “enable” phases repeatedly, including“setup” switches 93ss1, 93ss2, 93ss3, 93ss4, 93ss5, 93ss6, 93ss7, 93ss8, 93ss9, 93ss10 and 93ss11, which close during“setup” phase of the control clock 930CLK; and“enable” switches 93es1, 93es2, 93es3, 93es4, 93es5, 93es6, 93es7, and 93es8 and data controlled double-pole switches 93ds1, and 93ds2 which close during“enable” phase of the control clock 930CLK.

During“setup” phase of the control clock 930CLK, the plurality of switches 93ss1, 93ss2, 93ss3, 93ss4, 93ss5, 93ss6, 93ss7, 93ss8, 93ss9, 93ss10 and 93ss11, and 93es1, 93es2, 93es3, 93es4, 93es5, 93es6, 93es7, and 93es8, cause to connect the flying capacitors 93fc1, 93fc2, 93fc3 and 93fc4 in series with the positive voltage input 930in+ and the negative voltage input 930in-, such that they sample the analog differential voltage. They further cause the first and second CiAmps 600d1, 600d2 to be self-biased by feeding back the output 60d1out to the input 60d1in of the first CiAmp 600d1, and the output 60d2out to the input 60d2in of the second CiAmp 600d2 for establishing its own instantaneous operating point as it samples out 1/f noise and IC parametric variations. They yet further cause analog ground 930Agnd to connect to the first terminals of the second and fourth offset capacitors 93oc2 and 93oc4; and the reference 930Ref to connect to the first terminals of the first and third offset capacitors 93oc1 and 93oc3. Accordingly, a difference between the biased voltage for the CiAmp 600d1 and analog ground 930Agnd would be stored on the second offset capacitor 93oc2; and a difference between the biased voltage for the CiAmp 600d2 and analog ground 930Agnd would be stored on the fourth offset capacitor 93oc4 as offset voltages; while a difference between the biased voltage for the CiAmp 600d1 and reference 930Ref is stored on the first offset capacitor 93oc1; and a difference between the biased voltage for the CiAmp 600d2 and reference 930Ref is stored on the third offset capacitor 93oc3. All parametric variations of the amplifiers along with their instantons noise voltages is also stored on their respective offset capacitors to be included for their immediate cancellation during the following“enable” clock phase. This cancels out the dominant lower frequency 1/f noise from the analog signal path.

During“enable” phase of the control clock 930CLK, charge on all the capacitors, 93fc1, 93fc2, 93fc3, 93fc4 and 93oc1, 93oc2, 93oc3, 93oc4 is preserved by maintaining high series impedance to retain their sample voltages, and the plurality of switches 93ss1, 93ss2, 93ss3, 93ss4, 93ss5, 93ss6, 93ss7, 93ss8, 93ss9, 93ss10 and 93ss11, and 93es1, 93es2, 93es3, 93es4, 93es5, 93es6, 93es7, and 93es8, cause to capacitively couple the output 60d1out of the CiAmp 600d1 to the input 60d1in by connecting the first and second flying capacitors 93fc1 and 93fc2 in parallel; connecting the output 60d1out to the first terminals of the first and second flying capacitors 93fc1 and 93fc2; and the second terminals of the first and second flying capacitors 93fc1 and 93fc2 to the first terminal of either the first offset capacitor 93oc1 or second offset capacitor 93oc2 in series; and capacitively couple the output 60d2out of the CiAmp 600d2 to the input 60d2in thereof by connecting the third and fourth flying capacitors 93fc3 and 93fc4 in parallel; connecting the output 60d2out to the first terminals of the third and fourth flying capacitors 93fc3 and 93fc4; and the second terminals of the third and fourth flying capacitors 93fc3 and 93fc4 to the first terminal of either the third offset capacitor 93oc3 or second offset capacitor 93oc4 in series.

In particular, the output 60d1out of the CiAmp 600d1 is connected to the first terminals of the first and second flying capacitors 93fc1 and 93fc2, which form the analog output + voltage 930out+ of DAC 930, and the second terminals of the first and second flying capacitors 93fc1 and 93fc2 are connected to the first terminal of either one of the first or second offset capacitors 93oc1 or 93oc2 (thus in series) to selectively add the offset voltage thereon based on the value on the data 930Data. Thus, in effect, this rearrangement of the connection structures with the flying capacitors 93fc1 and 93fc2 provide an integer division (i.e. /2) of the sampled voltage thereacross with selectively adding the selected offset voltage (on either one of offset capacitors 93oc1 or 93oc2) depending on the data 930Data.

Similarly, the output 60d2out of the CiAmp 600d2 is connected to the first terminals of the third and fourth flying capacitors 93fc3 and 93fc3, which form the analog output - voltage 930out- of DAC 930, and the second terminals of the third and fourth flying capacitors 93fc3 and 93fc4 are connected to the first terminal of either one of the third or fourth offset capacitors 93oc3 or 93oc4 (thus in series) to selectively add the offset voltage thereon based on the value on the data 930Data. Thus, in effect, this rearrangement of the connection structures with the flying capacitors 93fc3 and 93fc4 provide an integer division (i.e. /2) of the sampled voltage thereacross with selectively adding the selected offset voltage (on either one of offset capacitors 93oc3 or 93oc4) depending on the data 930Data.

In this regard, some of the enable switches, namely 93ds1 and 93ds2, are preferably two- way switches, to selectively connect the second terminals of the first and second flying capacitors 93fc1 and 93fc2, and the third and fourth flying capacitors 93fc3 and 93fc4, to either the first terminal of the first or second offset capacitor 93oc1 or 93oc2 or the first terminal of the third or fourth offset capacitor 93oc3 or 93oc4 depending on the value presented on the data 930Data.

Figure 12a and 12b illustrate schematic diagrams of a scalable successive-approximation differential DAC 940 of the present invention, including first stage bit-slice differential DAC 930a and second stage bit-slice differential DAC 930b, each of which is the same as the one shown as DAC 930 in Figures 11a and 11b. The differential DAC 940 receives data 940data, reference 940Ref, analog ground 940Agnd, control clock 940CLK, initialization signal 940init, and provides differential voltage outputs, 940out+ and 940out-. The bit-slice DACs 930a and 930b, each includes two CiAmps, namely a first CiAmp 600e1 and a second CiAmp 600e2 for DAC 930a, and a first CiAmp 600f1 and a second CiAmp 600f2 for DAC 930b.

The bit-slice DAC 930a further includes two flying capacitors including first and second flying capacitors 94fc1 and 94fc2, and two offset capacitors including first and second offset capacitors 94oc1 and 94oc2 for the first CiAmp 600e1; and another two flying capacitors including third and fourth flying capacitors 94fc3 and 94fc4, and another two offset capacitors including third and fourth offset capacitors 94oc3 and 94oc4 for the second CiAmp 600e2.

Similarly, the bit-slice DAC 930b further includes two flying capacitors including first and second flying capacitors 95fc1 and 95fc2, and two offset capacitors including first and second offset capacitors 95oc1 and 95oc2 for the first CiAmp 600f1; and another two flying capacitors including third and fourth flying capacitors 95fc3 and 95fc4, and another two offset capacitors including third and fourth offset capacitors 95oc3 and 95oc4 for the second CiAmp 600f2.

Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 94oc1 and 94oc2 are connected to the input 60e1in of the first CiAmp 600e1, and the second terminals of the third and fourth offset capacitors 94oc3 and 94oc4 are connected to the input 60e2in of the second CiAmp 600e2.

Similarly, the second terminals of the first and second offset capacitors 95oc1 and 95oc2 are connected to the input 60f1in of the first CiAmp 600f1, and the second terminals of the third and fourth offset capacitors 95oc3 and 95oc4 are connected to the input 60f2in of the second CiAmp 600f2.

The first bit-slice differential DAC 930a further includes a plurality of switches which are operable with the control signal / clock 940CLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 94ss1, 94ss2, 94ss3, 94ss4, 94ss5, 94ss6, 94ss7, 94ss8, 94ss9, 94ss10 and 94ss11, which close during“setup” phase of the control clock 940CLK; and “enable” switches 94es1, 94es2, 94es3, 94es4, 94es5, 94es6, 94es7, and 94es8 which close during“enable” phase of the control clock 940CLK.

The second bit-slice differential DAC 930b includes a plurality of switches which are also operable with the control signal / clock 940CLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 95ss1, 95ss2, 95ss3, 95ss4, 95ss5, 95ss6, 95ss7, 95ss8, 95ss9, 95ss10 and 95ss11, which close during“enable” phase of the control clock 940CLK; and “enable” switches 95es1, 95es2, 95es3, 95es4, 95es5, 95es6, 95es7, and 95es8 which close during“setup” phase of the control clock 940CLK.

In preferred embodiment of the present invention, an inversion of the control clock 940CLK is fed to the second bit-slice differential DAC 930b, such that control timing of the first DAC 930a and that of the second DAC 930b are out of synch. In a preferred embodiment of the present invention, the phase difference between the first DAC 930a and the second DAC 930b is shifted by 180°.

Step size for digital to analog conversion for the DAC 940 may be determined by the voltage difference between analog ground 940Agnd and the reference 940Ref. The voltage range for the reference 940Ref may range from the voltage as low as where the signal to noise ratio may allow and up to about 40% of the supply voltage. Optionally, 25% of the power supply voltage is supplied to the reference 940Ref.

Data 940data for conversion normally has an even number bit length locating the analog output at the even stage output and the number of clock cycles define the binary resolution which becomes parametrically limited by the data converter performance limits including linearity, offset, and noise. The dual amplifier differential configuration doubles dynamic range and differentially cancels out most non-linearity and offsets from switch turn-off when operating near power supply rails during larger internal analog voltages. When a rail-to-rail output is desired, a final 2x output sample and hold amplifier (not shown) is one comparable approach since it is another data converter bit-slice.

Referring to Figure 12b, during the initialization phase of the DAC 940, initialization 940init causes to operate initialization switches 94is1, 94is2, 94is3 and 94is4 and discharge flying capacitors 94fc1, 94fc2, 94fc3 and 94fc4 to zero voltage.

Referring to Figures 12a, optionally, the initialization switches 940is1 and 940is2 may be provided and cause input Vin+ 930ain+ and input Vin- 930ain- to be connected to analog ground 940Agnd during initialization phase 940init. During subsequent“setup” phases of the control clock 940CLK, the initialization switches 940is1 and 940is2 operate to provide feedbacks from the output Vout+ 930bout+ of the second bit-slice DAC 930b to the input Vin+ 930ain+, and from the output Vout- 930bout-. The first“setup” phase of the control clock 930aCLK / 940CLK after initialization phase of the DAC 940, the first bit-slice DAC 930a converts the least significant bit (or first odd bit) 940od from the data stream 940data at the data 930adata.

As the clock 930aCLK / 940CLK phase into“enable” phase, depending on the value of least significant bit 940od at the data 930adata, the first bit-slice DAC 930a provides an integer division (i.e. /2) of the sampled voltage at Vin+ 930ain+ and Vin- 930ain- with addition of half- scale of reference voltage 930aRef if it is“1”; or zero, if the value is“0”; at Vout+ 930aout+ and Vout- 930aout- as described previously. Since the clock 930bCLK (inversion of the clock 940CLK by the invertor 940Inv) phases into“setup” phase, the second bit-slice DAC 930b starts processing the first even bit 940ed through the data stream 940data at data 930bdata, and samples output voltages 930aout+ and 930aout- at the inputs 930bin+ and 930bin-.

Then, the clock 940CLK phase into“setup” phase, the clock 930bCLK phases into “enable” phase, thus the second bit-slice DAC 930b provides an ingeger division (i.e. /2) of the sampled voltage at Vin+ 930bin+ and Vin- 930bin- with addition of half-scale of reference voltage 930bRef if it is“1”; or zero, if the value is“0”; at Vout+ 930bout+ and Vout- 930bout- as described previously, The resulting voltages at the output Vout+ 930bout+ and Vout- 930bout- are, then, sampled by the first bit-slice DAC 930a at Vin+ 930ain+ and Vin- 930ain-, while the first bit-slice DAC 930a start processing the second odd bit 940od from the data stream 940data at the data 930adata.

The process repeats until all the bits on the data 940data are processed by the DAC 940, and provides the resulting voltage at the output+ 940out+ and output- 940out-.

Figure 18a and 18b illustrate schematic diagrams of a four-bit pipe-line differential DAC 9A0 with offset control of the present invention, including first stage bit-slice differential DAC 930c1, second stage bit-slice differential DAC 930c2, third stage bit-slice DAC 930c3 and fourth stage bit-slice differential DAC 930c4. The differential DAC 9A0 receives data 9A0data, reference 9A0Ref, analog ground 9A0Agnd, control clock 9A0CLK, and provides differential voltage outputs, 9A0out+ and 9A0out-.

In a preferred embodiment of the present invention, the clock 9A0CLK is fed directly to operate the first and third bit-slice compact DACs 930c1 and 930c3, which are for processing “odd” bits, and the clock 9A0CLK is inverted by the invertor 9A0inv and fed to control / operate the second and fourth bit-slice compact DACs 930c2 and 930c4, which are for processing“even” bits. While the figures show four (4) bit DAC, it may be apparent that as many of these stages can be connected together in series as desired forming a scalable data converter. The number of stages, sizing of capacitors, noise floor, and clock speed limit the resolution for any given IC process, but the data converters are highly scalable across IC process nodes. A few design considerations can be included to enhance these limits, such as voltage scaling and special outer voltage switches with reduced turn-off charge injection, and double sampling the analog voltage input to eliminate matching requirements on flying capacitors used in series sampling for divide operations only.

The bit-slice DACs 930c1, 930c2, 930c3 and 930c4, each includes two CiAmps, namely a first CiAmp 600h1 and a second CiAmp 600h2 for DAC 930c1; a first CiAmp 600h3 and a second CiAmp 600h4 for DAC 930c2; a first CiAmp 600h5 and a second CiAmp 600h6 for DAC 930c3; and a first CiAmp 600h7 and a second CiAmp 600h8 for DAC 930c4.

The first bit-slice DAC 930c1 further includes two flying capacitors including first and second flying capacitors 9Afc1 and 9Afc2, and two offset capacitors including first and second offset capacitors 9Aoc1 and 9Aoc2 for the first CiAmp 600h1; and another two flying capacitors including third and fourth flying capacitors 9Afc3 and 9Afc4, and another two offset capacitors including third and fourth offset capacitors 9Aoc3 and 9Aoc4 for the second CiAmp 600h2. Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 9Aoc1 and 9Aoc2 are connected to the input 60h1in of the first CiAmp 600h1, and the second terminals of the third and fourth offset capacitors 9Aoc3 and 9Aoc4 are connected to the input 60h2in of the second CiAmp 600h2.

The second bit-slice DAC 930c2 further includes two flying capacitors including first and second flying capacitors 9Bfc1 and 9Bfc2, and two offset capacitors including first and second offset capacitors 9Boc1 and 9Boc2 for the first CiAmp 600h3; and another two flying capacitors including third and fourth flying capacitors 9Bfc3 and 9Bfc4, and another two offset capacitors including third and fourth offset capacitors 9Boc3 and 9Boc4 for the second CiAmp 600h4. Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 9Boc1 and 9Boc2 are connected to the input 60h3in of the first CiAmp 600h3, and the second terminals of the third and fourth offset capacitors 9Boc3 and 9Boc4 are connected to the input 60h2in of the second CiAmp 600h4.

The third bit-slice DAC 930c3 further includes two flying capacitors including first and second flying capacitors 9Cfc1 and 9Cfc2, and two offset capacitors including first and second offset capacitors 9Coc1 and 9Coc2 for the first CiAmp 600h5; and another two flying capacitors including third and fourth flying capacitors 9Cfc3 and 9Cfc4, and another two offset capacitors including third and fourth offset capacitors 9Coc3 and 9Coc4 for the second CiAmp 600h6. Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 9Coc1 and 9Coc2 are connected to the input 60h5in of the first CiAmp 600h5, and the second terminals of the third and fourth offset capacitors 9Coc3 and 9Coc4 are connected to the input 60h6in of the second CiAmp 600h6.

The fourth bit-slice DAC 930c4 further includes two flying capacitors including first and second flying capacitors 9Dfc1 and 9Dfc2, and two offset capacitors including first and second offset capacitors 9Doc1 and 9Doc2 for the first CiAmp 600h7; and another two flying capacitors including third and fourth flying capacitors 9Dfc3 and 9Dfc4, and another two offset capacitors including third and fourth offset capacitors 9Doc3 and 9Doc4 for the second CiAmp 600h8. Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 9Doc1 and 9Doc2 are connected to the input 60h7in of the first CiAmp 600h7, and the second terminals of the third and fourth offset capacitors 9Doc3 and 9Doc4 are connected to the input 60h8in of the second CiAmp 600h8.

The differential pipe-line DAC 9A0 further includes a plurality of switches which are operable with the control signal / clock 9A0CLK that alternates“setup” and“enable” phases repeatedly, including“setup” switches 9A0ds1; 9Ass1, 9Ass2, 9Ass3, 9Ass4, 9Ass5, 9Ass6, 9Ass7, 9Ass8, 9Ass9, and 9Ass10; 9Bss1, 9Bss2, 9Bss3, 9Bss4, 9Bss5, 9Bss6, 9Bss7, 9Bss8, 9Bss9, 9Bss10 and 9Bss11; 9Css1, 9Css2, 9Css3, 9Css4, 9Css5, 9Css6, 9Css7, 9Css8, 9Css9, 9Css10 and 9Css11; and 9Dss1, 9Dss2, 9Dss3, 9Dss4, 9Dss5, 9Dss6, 9Dss7, 9Dss8, 9Dss9, 9Dss10 and 9Dss11 which close / operate during“setup” phase of the corresponding control clock 930c1CLK, 930c2CLK, 930c3CLK or 930c4CLK; and“enable” switches 9Ads2 and 9Ads3; 9Bds1 and 9Bds2; 9Cds1 and 9Cds2; 9Dds1 and 9Dds2; 9Aes1, 9Aes2, 9Aes3, 9Aes4, 9Aes5, 9Aes6, 9Aes7, and 9Aes8; 9Bes1, 9Bes2, 9Bes3, 9Bes4, 9Bes5, 9Bes6, 9Bes7, and 9Bes8; 9Ces1, 9Ces2, 9Ces3, 9Ces4, 9Ces5, 9Ces6, 9Ces7, and 9Ces8; and 9Des1, 9Des2, 9Des3, 9Des4, 9Des5, 9Des6, 9Des7, and 9Des8; which close / operate during“enable” phase of the corresponding control clock 930c1CLK, 930c2CLK, 930c3CLK or 930c4CLK.

Step size for digital to analog conversion for the DAC 9A0 may be determined based on the voltage presented at the reference 9A0Ref with respect to analog ground 9A0Agnd. In a preferred embodiment of the present invention, the step size is determined by the difference between the reference voltage 9A0Ref and analog ground 9A0Agnd. The voltage range for the reference 9A0Ref may range from the voltage as low as where the signal to noise ratio may allow to about 85% of the supply voltage. Optionally, 25% of the power supply voltage is supplied to the reference 9A0Ref with respect to 9A0Agnd.

Data 9A0data for conversion is a four bit in length with an offset control bit.

In operation, the DAC 9A0 would go through, during“setup” phase of the first cycle of the control clock 9A0CLK / 930c1CLK, processes the offset control bit 9A0OS by sampling, at its input Vin+ 930c1in+, the reference 9A0Ref if the value of the offset control bit 9A0OS is“1” or analog ground 9A0Agnd if the value is“0”, and to process bit 1 9A0B1 of the data stream 9A0data at the first stage DAC 930c1 for producing the resulting voltage therefrom on the outputs 930c1out+ and 930c1out- during following“enable” phase of the control clock 9A0CLK / 930c1CLK, which is an integer division (i.e. /2) of the input voltage between 930c1in+ 930c1in- with addition of a half-scale of the ref 930c1Ref if the data value 930c1data / 9A0B1 is“1” or addition of“zero”, if otherwise.

During”enable” phase of the control clock 9A0CLK / 930c1CLK (thus,“setup” phase for clock 930c2CLK (invert of clock 9A0CLK)), the DAC 9A0 further causes the second bit- slice DAC 930c2 to sample the produced voltages 930c1out+ and 930c1out from the first stage DAC 930c1 at its inputs Vin+ 930c2in+ and Vin- 930c2in-, and to process bit 2 9A0B2 of the data stream 9A0data at the second stage DAC 930c2 for producing the resulting voltage therefrom on the outputs 930c2out+ and 930c2out- during following“enable” phase of the control clock 930c2CLK (invert of clock 9A0CLK).

During the subsequent”setup” phase of the control clock 9A0CLK / 930c3CLK (thus, “enable” phase for clock 930c2CLK (invert of clock 9A0CLK)), the DAC 9A0 causes the third bit-slice DAC 930c3 to sample the produced voltages 930c2out+ and 930c2out-from the second stage DAC 930c2 at its inputs Vin+ 930c3in+ and Vin- 930c3in-, and to process bit 39A0B3 of the data stream 9A0data at the third stage DAC 930c3 for producing the resulting voltage therefrom on the outputs 930c3out+ and 930c3out during the following“enable” phase of the control clock 9A0CLK / 930c3CLK-.

During the subsequent“enable” phase of the control clock 9A0CLK / 930c3CLK (thus, “setup” phase for clock 930c4CLK (invert of clock 9A0CLK)), the DAC 9A0 causes the fourth bit-slice DAC 930c4 to sample the produced voltages 930c3out+ and 930c3out-from the third stage DAC 930c3 at its inputs Vin+ 930c4in+ and Vin- 930c4in-, and to process bit 49A0B4 of the data stream 9A0data at the fourth stage DAC 930c4 for producing the resulting voltage therefrom on the outputs 930c4out+ and 930c4out-.

At the further subsequent“setup” phase of the control clock 9A0CLK (thus,“enable” phase for clock 930c4CLK (invert of clock 9A0CLK)), the output 9A0out+ and 9A0out1, which corresponds to the output 930c4out+ and 930c4out-, respectively, provides the output of the DAC 9A0.

Figures 13a and 13b illustrate schematic diagrams of a bit-slice of analog to digital converter (ADC) 700 of the present invention, including a CiAmp 600i1 with 2 x gain including subtraction capability with feed-forward latch comparator 705. The ADC 700 comprises a CiAmp 600i1, analog ground 700Agnd, voltage input 700in, reference voltage 700Ref, a control clock 700CLK, output 700out and data output 700Data. In a preferred embodiment of the present invention, the reference 700Ref is the ADC half-scale quantizing voltage. The ADC 700 further include the feed-forward latch comparator 705, including a pair of CiAmp 600i3 and 600i4, which are connected in series through a capacitor 70oc5, with an optional gain stage 600i2 including setup switch 70ss9 and offset capacitor 70oc3. Further optionally, the latch comparator 705 further provides a feed-forward path 70ffp, in which the input to the amplifier 600i3 may be capacitively fed forward to PiPort 60i4pi and NiPort 60i4ni of the CiAmp 600i4 through capacitors 70ff1 and 70ff2, respectively.

The ADC 700 further includes a plurality of switches, including“setup” switches 70ss1, 70ss2, 70ss3, 70ss4, 70ss5, 70ss6, and 70ss7, 70ss8, 70ss10, and 70ss11 (and optional 70ss9) which close during“setup” phase of a clock 700CLK; and“enable” switches 70es1, 70es2, 70es3 and 70es4, which close during“enable” phase of the clock 700CLK. The clock 700CLK alternates“setup” and“enable” phases repeatedly for each input it quantizes. The ADC 700 yet further comprises first, second, third, fifth and optional fourth offset capacitors, 70oc1, 70oc2, 70oc4, 70oc5 and 70oc3, respectively. Each of the offset capacitors, 70oc1, 70oc2, 70oc4, 70oc5 and 70oc3, have first and second terminals, and the second terminals of the first and second offset capacitors 70oc1, and 70oc2 are connected to the input 60i1in of the CiAmp 600i1. The ADC 700 further comprises first and second flying capacitors 70fc1, and 70fc2, both of which have first and second terminals.

During“setup” phase of the clock 700CLK, the switches causes the first terminal of the flying capacitors 70fc1, 70fc2 to be connected to the input 700in and the second terminals of the flying capacitors 70fc1, 70fc2 to be connected to the analog ground 700Agnd to sample the input voltage on the flying capacitors 70fc1 and 70fc2; and causing the CiAmp 600i1 to be self-biased by connecting output 60i1out to input 60i1in thereof to establish its instantaneous point as it samples out 1/f noise and IC parametric variations. The difference between the self-biased voltage of the CiAmp 600i1 and the reference 700Ref is stored at the first offset voltage capacitor 70oc1, while the difference between the self-biased voltage of the CiAmp 600i1 and analog ground 700Agnd is stored at the second offset capacitor 70oc2.The switches further causes the first terminal of the offset capacitor 70oc4 to connect to the Analog ground 700Agnd, while the CiAmps 600i3 and 600i4 to be self-biased by connecting output 60i3out to input 60i3in thereof, and connecting output 60i4out to input 60i4in thereof, for each to establish its instantaneous point as it samples out 1/f noise and IC parametric variations onto these offset capacitors for subsequent cancellation during the following“enable” controlling clock phase.

The switches yet further cause the CiAmp 600i2 to be self-biased by connecting its input 60i2in with its output 60i2out.

During“enable” phase of the clock 700CLK, the switches cause the flying capacitors 70fc1 and 70fc2 to be connected in series with the output 60i1out of the CiAmp 600i1, and further connect to either the first offset capacitor 70oc1 or the second offset capacitor 70oc2 in series to the input 60i1in of the CiAmp 600i1. This connection structure of the flying capacitors 70fc1 and 70fc2 provides an integer multiplication (i.e. x2) of the sampled input voltage at input 700in and analog ground 700Agnd with subtraction of the offset voltage stored at the first offset capacitor 70oc1 (i.e. reference 700Ref) or the second offset capacitor 70oc2 (i.e. analog ground 700Agnd).

In this regard, switch 70ds1 is preferably a two-way switch, such that, depending on the value of the output 60i4out, the switch 70ds1 selectively causes to connect either one of the first offset capacitor 70oc1 or the second offset capacitor 70oc2. The converted data 700Data would be produced by comparing Vin 700in against analog ground 700Agnd by providing positive feedback around the latch loop of the CiAmps 600i3 600i4 through the capacitor 70oc5. For example, referring to the latch comparator 705, when input 700in is above half-scale reference or analog ground 700Agnd, switch 70ds1, which is the operated by the output of the latch 60i4out, causes to connect to first flying capacitor 70oc1, and otherwise, the switch 70ds1 causes to connect to the other offset capacitor 70oc2. The ADC 700 provides output voltage at the output 700out, which is the subtraction of either half bias or zero voltage from an integer multiplication (i.e. x2) of the the input voltage at its input 700in and analog ground 700Agnd.

Further quantizing resolution may be attained, for example, by varying flying capacitor voltage references. Furthermore, by increasing the number of offset capacitors and reference terminals using different switching device or switching / connecting structure with the switch 70ds1 positions, a further number of reference levels may be accommodated in accordance with the present invention.

Figures 14a and 14b illustrate schematic diagrams of a successive-approximation analog to digital converter (ADC) 710 of the present invention, including two bit-slice ADCs 700b and 700c, each of which is the same as ADC 700 shown in Figures 13a and 13b, The first bit-slice 700b is for producing odd data bits from the most significant bit, while the second bit-slice ADC 700c is for producing even data bits from the second most significant bit. Control clock 710CLK is fed directly to the clock 700bCLK of the first bit-slice ADC 700b; while the clock 710CLK is inverted by an inverter 710Inv and fed to the clock 700cCLK of the second bit-slice ADC 700c to provide 180° control phase shift. The first and second bit-slice ADCs 700b and 700c are connected in series, where the output 700bout of the first bit-slice ADC 700b is connected to the input 700cin of the second bit-slice ADC 700c.

As described above, each of bit-slice of analog to digital converters (ADC) 700b and 700c, including a CiAmp 600j1 and 600k1, respectively, with 2 x gain including subtraction capability with feed-forward latch comparators 705b and 705c, respectively.

The first bit-slice ADC 700b comprises a CiAmp 600j1, analog ground 700bAgnd, voltage input 700bin, reference voltage 700bRef, a control clock 700bCLK, output 700bout and data output 700bData. Similarly, the second bit-slice ADC 700c comprises a CiAmp 600k1, analog ground 700cAgnd, voltage input 700cin, reference voltage 700cRef, a control clock 700cCLK, output 700cout and data output 700cData.

In a preferred embodiment of the present invention, the references 710Ref / 700bRef / 700cRef are the ADC half-scale quantizing voltage.

The first and second bit-slice ADCs 700b and 700c further include the feed-forward latch comparators 705b and 705c. The comparator 705b includes a pair of CiAmps 600j3 and 600j4, which are connected in series through a capacitor 7boc5, with an optional gain stage 600j2 including setup switch 7bss9 and offset capacitor 7boc3. Similarly, the comparator 705c includes a pair of CiAmps 600k3 and 600k4, which are connected in series through a capacitor 7coc5, with an optional gain stage 600k2 including setup switch 7css9 and offset capacitor 7coc3.

Further optionally, the comparator 705b may provide a feed-forward path 7bffp, in which the input to the amplifier 600j3 may be capacitively fed forward to PiPort 60j4pi and NiPort 60j4ni of the CiAmp 600j4 through capacitors 7bff1 and 7bff2, respectively. Similarly, the comparator 705c may provide a feed-forward path 7cffp, in which the input to the amplifier 600k3 may be capacitively fed forward to PiPort 60k4pi and NiPort 60k4ni of the CiAmp 600k4 through capacitors 7cff1 and 7cff2, respectively.

The ADC 700b further includes a plurality of switches, including“setup” switches 7bss1, 7bss2, 7bss3, 7bss4, 7bss5, 7bss6, 7bss7, 7bss8, 7bss10, and 7bss11 (and optional 7bss9) which close during“setup” phase of a clock 700bCLK; and“enable” switches 7bes1, 7bes2, 7bes3 and 7bes4, which close during“enable” phase of the clock 700bCLK. The clock 700bCLK alternates“setup” and“enable” phases repeatedly for each input it quantizes. The first bit-slice ADC 700b yet further comprises first, second, third, fifth and optional fourth offset capacitors, 7boc1, 7boc2, 7boc4, 7boc5 and 7boc3, respectively. Each of the offset capacitors, 7boc1, 70bc2, 70bc4, 70bc5 and 70bc3, have first and second terminals, and the second terminals of the first and second offset capacitors 70bc1, and 7boc2 are connected to the input 60j1in of the CiAmp 600j1. The first bit-slice ADC 700b further comprises first and second flying capacitors 7bfc1, and 7bfc2, both of which have first and second terminals.

Similarly, the ADC 700c further includes a plurality of switches, including“setup” switches 7css1, 7css2, 7css3, 7css4, 7css5, 7css6, 7css7, 7css8, 7css10, and 7css11 (and optional 7css9) which close during“setup” phase of a clock 700cCLK; and“enable” switches 7ces1, 7ces2, 7ces3 and 7ces4, which close during“enable” phase of the clock 700cCLK. The clock 700cCLK alternates“setup” and“enable” phases repeatedly for each input it quantizes.

The ADC 700c yet further comprises first, second, third, fifth and optional fourth offset capacitors, 7coc1, 7coc2, 7coc4, 7coc5 and 7coc3, respectively. Each of the offset capacitors, 7coc1, 7coc2, 7coc4, 70cc5 and 7coc3, have first and second terminals, and the second terminals of the first and second offset capacitors 7coc1, and 7coc2 are connected to the input 60k1in of the CiAmp 600k1. The second bit-slice ADC 700c further comprises first and second flying capacitors 7cfc1, and 7cfc2, both of which have first and second terminals.

The ADC 710 receives the clock 710CLK, input 710in+, analog ground 710Agnd, reference 710Ref, and sampling control 710samp, and provides data 710Data. Conversion step size of the ADC 710 is represented by the voltage difference between the reference 710Ref and 710Agnd.

At the first“setup” phase of the first control cycle of the control clock 710CLK / 700bCLK, the sampling control 710samp causes the sampling switch 710sw to connect the input 710In+ to the input 700bin of the first bit-slice ADC 700b.

As the control clock 710CLK / 700bCLK phases into“enable” phase, based on the sampled voltage at the input 700bin, the first bit-slice ADC 700b generates the most significant bit at the data 700bData for the first odd bit through odd bit data 710od to the data stream 710Data, and further provides the resulting voltage at its output 700bout, which is an integer multiplication (i.e. x2) of the sampled voltage at the input 700bin and analog ground 700bAgnd with subtraction of the reference 700bRef / 710Ref or zero voltage / analog ground 700bAgnd / 710Agnd depending on the value of the output bit data 700bData. When the control clock 710CLK / 700bCLK is in“enable” phase, the control clock 700cCLK is in“setup” phase, and thus the second bit-slice ADC 700c samples the output 700bout of the first bit-slice ADC 700b at the input 700cin.

The resulting output voltage is twice of the sampled voltage at the input; however, optionally, such gain may be changed, for example, by having more than two flying capacitors. For example, three (3) times gain may be realized by adding an additional flying capacitor (thus total three flying capacitors). In other words, magnitude of the voltage gain at the output is proportional to the number of flying capacitors.

As the control clock 710CLK enters into“setup” / 700cCLK phases into“enable” phase, based on the sampled voltage at the input 700cin, the second bit-slice ADC 700c generates the second most significant bit at the data 700cData for the first even bit through odd bit data 710ed to the data stream 710Data, and further provides the resulting voltage at its output 700cout, which is an integer multiple (i.e. x2) of the sampled voltage at the input 700cin and analog ground 700cAgnd with subtraction of the reference 700cRef / 710Ref or zero voltage / analog ground 700cAgnd / 710Agnd depending on the value of the output bit data 700cData. When the control clock 710CLK is in subsequent“setup” phase(s), the first bit-slice ADC 700b samples the output 700cout of the second bit-slice ADC 700c at the input 700bin.

The above-mentioned process repeats until the desired bit length is obtained.

Figures 19a and 19b illustrate schematic diagrams of a pipe-line ADC 750 of the present invention, including four (4) bit-slice ADCs 700d1, 700d2, 700d3 and 700d4, each of which is the same as bit-slice ADC 700 shown in Figures 13a and 13b, which produces four (4) bit data conversion. The ADC 750 receives the clock 750CLK, input 750in, analog ground 750Agnd, reference 750Ref, and provides data 750Data and output 750out. Conversion step size of the ADC 750 is represented by the voltage difference between the reference 750Ref and 750Agnd.

In a preferred embodiment of the present invention, the clock 750CLK is fed directly to operate the first and third bit-slice compact ADCs 700d1 and 700d3, which are for processing “odd” bits, and the clock 750CLK is inverted by the invertor 750inv and fed to control / operate the second and fourth bit-slice compact ADCs 700d2 and 700d4, which are for processing“even” bits. While the figures show four (4) bit ADC, it may be apparent that as many of these stages can be connected together in series as desired forming a scalable data converter. The number of stages, sizing of capacitors, noise floor, and clock speed limit the resolution for any given IC process, but the data converters are highly scalable across IC process nodes. A few design considerations can be included to enhance these limits, such as voltage scaling and special outer voltage switches with reduced turn-off charge injection.

The first bit-slice ADC 700d1 is for producing the first odd data bit or the most significant bit; the second bit-slice ADC 700d2 is for the second significant bit; the third bit-slice ADC 700d3 is for the third significant bit; and the fourth bit-slice ADC 700d4 is for the least significant bit.

Control clock 750CLK is fed directly to the clocks 700d1CLK and 700d3CLK; while 700d2CLK and 700d4CLK are invert of control clock 750CLK by an inverter 750inv. The four bit-slice ADCs 700d1, 700d2, 700d3 and 700d4 are connected in series, where the output of the previous bit-slice ADC is connected to the input of the subsequent ADC, for example, the output 700d1out of the first bit-slice ADC 700d1 to the input 700d2in of the second bit-slice ADC 700d2; the output 700d2out of the second bit-slice ADC 700d2 to the input 700d3in of the third bit-slice ADC 700d3; and the output 700d3out of the third bit-slice ADC 700d3 to the input 700d4in of the fourth bit-slice ADC 700d4.

As described above, each of bit-slice of analog to digital converters (ADC) 700d1, 700d2, 700d3 and 700d4, including one CiAmp 600m1, 600n1, 600p1 and 600q1, respectively, with 2 x gain including subtraction capability with feed-forward latch comparators 705d1, 705d2, 705d3 and 705d4, respectively.

The first bit-slice ADC 700d1 comprises a CiAmp 600m1, analog ground 700d1Agnd, voltage input 700d1in, reference voltage 700d1Ref, a control clock 700d1CLK, output 700d1out and data output 700d1Data, two flying capacitors, 7d1fc1 and 7d1fc2, two offset capacitors, 7d1oc1 and 7d1oc2,“setup” switches 7d1ss1, 7d1ss2, 7d1ss3, 7d1ss4, 7d1ss5, 7d1ss6 and 7d1ss7 which close during“setup” phase of the control clock 700d1CLK,“enable” switches 7d1es1 and 7d1es2 which close during“enable” phase of the control clock 700d1CLK.

The comparator 705d1 comprises CiAmps 600m3 and 600m4, which are connected in series through a capacitor 7d1oc5,“setup” switches 7d1ss8, 7d1ss10 and 7d1ss11 which close during“setup” phase of the control clock 700d1CLK,“enable” switches 7d1es4 which close during“enable” phase of the control clock, with an optional gain stage 600m2 including setup switch 7d1ss9 (which closes during“setup” phase of the control clock 700d1CLK) and offset capacitor 7d1oc3. Further optionally, the comparator 705d1 may provide a feed-forward path 7d1ffp, in which the input to the amplifier 600m3 may be capacitively fed forward to PiPort 60m4pi and NiPort 60m4ni of the CiAmp 600m4 through capacitors 7d1ff1 and 7d1ff2, respectively.

The second bit-slice ADC 700d2 comprises a CiAmp 600n1, analog ground 700d2Agnd, voltage input 700d2in, reference voltage 700d2Ref, a control clock 700d2CLK, output 700d2out and data output 700d2Data, two flying capacitors, 7d2fc1 and 7d2fc2, two offset capacitors, 7d2oc1 and 7d2oc2,“setup” switches 7d2ss1, 7d2ss2, 7d2ss3, 7d2ss4, 7d2ss5, 7d2ss6 and 7d2ss7 which close during“setup” phase of the control clock 700d2CLK,“enable” switches 7d2es1 and 7d2es2 which close during“enable” phase of the control clock 700d2CLK.

The comparator 705d2 comprises CiAmps 600n3 and 600n4, which are connected in series through a capacitor 7d2oc5,“setup” switches 7d2ss8, 7d2ss10 and 7d2ss11 which close during“setup” phase of the control clock 700d2CLK,“enable” switch 7d2es4 which closes during“enable” phase of the control clock, with an optional gain stage 600n2 including setup switch 7d2ss9 (which closes during“setup” phase of the control clock 700d2CLK) and offset capacitor 7d2oc3. Further optionally, the comparator 705d2 may provide a feed-forward path 7d2ffp, in which the input to the amplifier 600n3 may be capacitively fed forward to PiPort 60n4pi and NiPort 60n4ni of the CiAmp 600n4 through capacitors 7d2ff1 and 7d2ff2, respectively.

The third bit-slice ADC 700d3 comprises a CiAmp 600p1, analog ground 700d3Agnd, voltage input 700d3in, reference voltage 700d3Ref, a control clock 700d3CLK, output 700d3out and data output 700d3Data, two flying capacitors, 7d3fc1 and 7d3fc2, two offset capacitors, 7d3oc1 and 7d3oc2,“setup” switches 7d3ss1, 7d3ss2, 7d3ss3, 7d3ss4, 7d3ss5, 7d3ss6 and 7d3ss7 which close during“setup” phase of the control clock 700d3CLK,“enable” switches 7d3es1 and 7d3es2 which close during“enable” phase of the control clock 700d3CLK.

The comparator 705d3 comprises CiAmps 600p3 and 600p4, which are connected in series through a capacitor 7d3oc5,“setup” switches 7d3ss8, 7d3ss10 and 7d3ss11 which close during“setup” phase of the control clock 700d3CLK,“enable” switches 7d3es4 which closes during“enable” phase of the control clock, with an optional gain stage 600p2 including setup switch 7d3ss9 (which closes during“setup” phase of the control clock 700d3CLK) and offset capacitor 7d3oc3. Further optionally, the comparator 705d3 may provide a feed-forward path 7d3ffp, in which the input to the amplifier 600p3 may be capacitively fed forward to PiPort 60p4pi and NiPort 60p4ni of the CiAmp 600p4 through capacitors 7d3ff1 and 7d3ff2, respectively.

The fourth bit-slice ADC 700d4 comprises a CiAmp 600q1, analog ground 700d4Agnd, voltage input 700d4in, reference voltage 700d4Ref, a control clock 700d4CLK, output 700d4out and data output 700d4Data, two flying capacitors, 7d4fc1 and 7d4fc2, two offset capacitors, 7d4oc1 and 7d4oc2,“setup” switches 7d4ss1, 7d4ss2, 7d4ss3, 7d4ss4, 7d4ss5, 7d4ss6 and 7d4ss7 which close during“setup” phase of the control clock 700d4CLK,“enable” switches 7d4es1 and 7d4es2 which close during“enable” phase of the control clock 700d4CLK.

The comparator 705d4 comprises CiAmps 600q3 and 600q4, which are connected in series through a capacitor 7d4oc5,“setup” switches 7d4ss8, 7d4ss10 and 7d4ss11 which close during“setup” phase of the control clock 700d4CLK,“enable” switches 7d4es4 which closes during“enable” phase of the control clock, with an optional gain stage 600q2 including setup switch 7d4ss9 (which closes during“setup” phase of the control clock 700d4CLK) and offset capacitor 7d4oc3. Further optionally, the comparator 705d4 may provide a feed-forward path 7d4ffp, in which the input to the amplifier 600q3 may be capacitively fed forward to PiPort 60q4pi and NiPort 60q4ni of the CiAmp 600q4 through capacitors 7d4ff1 and 7d4ff2, respectively.

During operation, during“setup” phase of the control clock 750CLK / 700d1CLK, the first bit-slice ADC 700d1 samples the input 750in at the input 700d1in to produce the most significant bit 750B1 at the data 700d1data to the data stream 750data. As the control clock 750CLK / 700d1CLK phases into“enable”, the first bit-slice ADC 700d1 provides the resulting voltage at its output 700d1out, which is an integer multiplication (i.e. x2) of the sampled voltage at the input 700d1in and analog ground 700d1Agnd with subtracting either reference 750Ref / 700d1Ref if the produced bit value 700d1data is“1”, or analog ground 750Agnd / 700d1Agnd, (or zero) if the produced bit value 700d1data is“0”. The first bit-slice ADC 700d1 produces “1” for data 700d1data if the sampled voltage is greater than analog ground 700d1Agnd; otherwise,“0”.

The second bit-slice ADC 700d2 samples the output 700d1out of the first bit-slice ADC 700d1 during the“setup” phase of the control clock 700d2CLK (invert of clock 750CLK) for producing the second most significant bit 750B2 at the data 700d2data to the data stream 750data. As the control clock 700d2CLK phases into“enable”, the second bit-slice ADC 700d2 provides the resulting voltage at the output 700d2out, which is an integer multiplication (i.e. x2) of the sampled voltage at the input 700d2in and analog ground 700d2Agnd with subtracting either reference 700d2Ref if the produced bit value 700d2data is“1”, or analog ground 700d2Agnd (or zero) if the produced bit value 700d2data is“0”. The second bit-slice ADC 700d2 produces“1” for data 700d2data if the sampled voltage is greater than analog ground 700d2Agnd; otherwise,“0”.

The third bit-slice ADC 700d3 samples the output 700d2out of the second bit-slice ADC 700d2 during the“setup” phase of the control clock 700d3CLK/750CLK for producing the third most significant bit 750B3 at the data 700d3data to the data stream 750data. As the control clock 700d3CLK phases into“enable”, the third bit-slice ADC 700d3 provides the resulting voltage at the output 700d3out, which is an integer multiplication (i.e. x2) of the sampled voltage at the input 700d3in and analog ground 700d3Agnd with subtracting either reference 700d3Ref if the produced bit value 700d3data is“1”, or analog ground 700d3Agnd (or zero) if the produced bit value 700d3data is“0”. The third bit-slice ADC 700d3 produces“1” for data 700d3data if the sampled voltage is greater than analog ground 700d3Agnd; otherwise,“0”.

The resulting output voltage is twice of the sampled voltage at the input; however, optionally, such gain may be changed, for example, by having more than two flying capacitors. For example, three (3) times gain may be realized by adding an additional flying capacitor (thus total three flying capacitors). In other words, magnitude of the voltage gain at the output is proportional to the number of flying capacitors. The fourth bit-slice ADC 700d4 samples the output 700d3out of the third bit-slice ADC 700d3 during the“setup” phase of the control clock 700d4CLK (invert of clock 750CLK) for producing the least significant bit 750B4 at the data 700d4data to the data stream 750data. As the control clock 700d4CLK phases into“enable”, the fourth bit-slice ADC 700d4 provides the resulting voltage at the output 700d4out, which is an integer multiplication (i.e. x2) of the sampled voltage at the input 700d4in and analog ground 700d4Agnd with subtracting either reference 700d4Ref if the produced bit value 700d4data is“1”, or analog ground 700d4Agnd (or zero) if the produced bit value 700d4data is“0”. The fourth bit-slice ADC 700d4 produces “1” for data 700d4data if the sampled voltage is greater than analog ground 700d4Agnd; otherwise,“0”.

As it can be seen, pipe-line can be easily scaled to produce more bits, i.e.6, 8, 10, 12 or more, as long as its noise floor allows.

Figures 15a and 15b illustrate schematic diagrams of a bit-slice of differential ADC 720 of the present invention., using two CiAmps 600m1 and 600m2, with 2 x gain including fixed voltage subtraction capability based on output of a latch comparator 725.

The bit-slice ADC 720 includes two CiAmps including a first CiAmp 600m1 and a second CiAmp 600m2 (same as the ones shown in Figures 8a and 8b), control clock 720CLK, positive voltage input 720in+, negative voltage input 720in-, analog ground 720Agnd, reference 720Ref, positive voltage output 720out+ and negative voltage output 720out-.

The bit-slice ADC 720 further includes a first flying capacitor 72fc1, two offset capacitors including a first offset capacitor 72oc1 and a second offset capacitor 72oc2 for the first CiAmp 600m1; and a second flying capacitor 72fc2, and another two offset capacitors including a third offset capacitor 72oc3 and a fourth offset capacitor 72oc4 for the second CiAmp 600m2. Each of the capacitors has a first and second terminal. The second terminals of the first and second offset capacitors 72oc1 and 72oc2 are connected to the input 60m1in of the first CiAmp 600m1, and the second terminals of the third and fourth offset capacitors 72oc3 and 72oc4 are connected to the input 60m2in of the second CiAmp 600m2.

The bit-slice ADC 720 further includes a plurality of switches which are operable with a control signal / clock 720CLK that alternates“setup” and“enable” phases repeatedly, including “setup” switches 72ss1, 72ss2, 72ss3, 72ss4, 72ss5, 72ss6, 72ss7, 72ss8, 72ss9, 72ss10, 72ss11, 72ss12, 72ss13 and 72ss14 which close during“setup” phase of the control clock 720CLK; and “enable” switches 72es1, 72es2, 72es3, 72es4, 72ds1 and 72ds2 which close during“enable” phase of the control clock 720CLK.

The bit-slice ADC 720 futher include the feed-forward latch comparator 725, which is the similar to the feed-forward latch comparator 705 in Figure 13a, including a pair of CiAmp 600m4 and 600m5, which are connected in series through a capacitor 72oc7, with an optional gain stage 600m3 including setup switch 72ss12 and offset capacitor 72oc5. Further optionally, the latch comparator 725 further provides a feed-forward path 72ffp, in which the input to the amplifier 60m4in may be capacitively fed forward to PiPort 60m5pi and NiPort 60m5ni of the CiAmp 600m5 through capacitors 72ff1 and 72ff2, respectively.

During“setup” phase of the control clock 720CLK, the switches cause to connect the positive voltage input 720in+ to the first terminals of the flying capacitors 72fc1 and 72fc2, and the negative voltage input 720in- to the second terminals of the flying capacitors 72fc1 and 72fc2, such that the flying capacitors 72fc1 and 72fc2 samples the analog differential input voltage 720in+ and 720in-. The switches further cause the first and second CiAmps 600m1, 600m2 to be self-biased by feeding back the output 60m1out to the input 60m1in of the first CiAmp 600m1, and the output 60m2out to the input 60m2in of the second CiAmp 600m2, to establish its instantaneous operating point as it samples out 1/f noise and IC parametric variations for subsequent cancellation in the following“enable” controlling clock phase.

The switches yet further cause the analog ground 720Agnd to connect to the first terminals of the second and fourth offset capacitors 72oc2 and 72oc4; and the reference 720Ref to connect to the first terminal of the first and third offset capacitors 72oc1 and 72oc3. In effect, the difference between the self-biased voltage of CiAmp 600m1 and the analog ground 720Agnd is stored on the first offset capacitor 72oc1; the difference between the self-biased voltage CiAmp 600m1 and the reference 720Ref is stored at the second offset capacitor 72oc2; the difference between the self-biased voltage of CiAmp 600m2 and the analog ground 720Agnd is stored on the third offset capacitor 72oc3; and, the difference between the self-biased voltage CiAmp 600m2 and the reference 720Ref is stored at the second offset capacitor 72oc4;

In the comparator 725, input Vin- 720in- is connected to the first terminal the offset capacitor 72oc6; while the CiAmps 600m4 and 600m5 are self-biased by connecting its output 60m4out / 60m5out with its own input 60m4in / 60m6in, respectively. When the optional gain stage 600m3 is present, the gain stage 600m3 is also self-biased by connecting its input 60m3in with its output 60m3out.

During“enable” phase of the control clock 720CLK, the switches cause to capacitively connect the output 60m1out to the input 60m1in of the CiAmp 600m1 by connecting the first flying capacitor 72fc1 and either the first offset capacitor 72oc1 or second offset capacitor 72oc2 in series; and capacitively connecting the output 60m2out to the input 60m2in of CiAmp 600m2 by connecting the second flying capacitor 72fc2 and either the third offset capacitor 72oc3 or fourth offset capacitor 72oc4 in series. In this regard, the switches, namely 72ds1 and 72ds2 are two-way switches, to selectively connect the second terminal of the first flying capacitor 72fc1/72fc2 to either the first terminal of the first/third offset capacitor 72oc1/72oc4 or the first terminal of the second/fourth offset capacitor 72oc2 / 72oc3.

In a further preferred embodiment of the present invention, the two-switches 72ds1 and 72ds2 are controlled based on comparison of the positive input voltage 720in+ with the negative input voltage 720in-, for determining their selections. For example, where the positive voltage input 720in+ is greater than the negative input voltage 720in-, such condition causes the switch 72ds1 to connect the second terminal of the first flying capacitor 72fc1 to the first terminal of the first offset capacitor 72oc1; and the switch 72ds2 to connect the second terminal of the second flying capacitor 72fc2 to the first terminal of the third offset capacitor 72oc3; when the positive voltage input 720in+ is lower than the negative input 720in-, such a condition would cause the the switch 72ds1 to connect the second terminal of the first flying capacitor 72fc1 to the first terminal of the second offset capacitor 72oc2; and the switch 72ds2 to connect the second terminal of the second flying capacitor 72fc2 to the first terminal of the fourth offset capacitor 72oc4. Accordingly, the resulting output voltage between output+ 720out+ and output– 720out- is an integer multiplication (i.e. x2) of the input voltage between input + 720in+ and input– 720in- with subtraction of offset voltages on the first and third offset capacitors 72oc1 and 72oc3 (or reference 720Ref) if the value of data 720Data is“1”, or subtraction of offset voltages on the second and fourth offset capacitors 72oc2 and 72oc4, otherwise.

Figures 16a and 16b illustrate schematic diagrams of a successive-approximation differential ADC 730 of the present invention, including two bit-slice ADCs 720b and 720c, each of which is the same as ADC 720 shown in Figures 15a and 15b, The first bit-slice 720b includes a first comparator 725b for producing odd data bits from the most significant bit, while the second bit-slice ADC 720c includes a second comparator 725c for producing even data bits from the second most significant bit. Control clock 730CLK is fed directly to the clock 720bCLK of the first bit-slice ADC 720b; while the clock 730CLK is inverted by an inverter 730Inv and fed to the clock 720cCLK of the second bit-slice ADC 720c to provide 180° control phase shift. The first and second bit-slice ADCs 720b and 720c are connected in series, where the output 720bout of the first bit-slice ADC 720b is connected to the input 720cin of the second bit-slice ADC 720c.

The ADC 730 receives the clock 730CLK, positive input 730in+, negative input 730in-, analog ground 730Agnd, reference 730Ref, and sampling control 730samp, and provides data 730data. Conversion step size of the ADC 730 is represented by the voltage difference between the reference 730Ref and 730Agnd.

At the first“setup” phase of the first control cycle of the control clock 730CLK / 720bCLK, the sampling control 730samp causes the sampling switch 730sw to connect the positive input 730in+ to the positive input 720bin+, negative input 730in- to the negative input 720bin- of the first bit-slice ADC 720b.

As the control clock 730CLK / 720bCLK phases into“enable” phase, based on the sampled voltage at the positive and negative inputs 720bin+ and 720bin-, the first bit-slice ADC 720b generates the most significant bit at the data 720bdata for the first odd bit through odd bit data 730od to the data stream 730data, and further provides the resulting voltage at its positive and negative outputs 720bout+ and 720bout-, which are an integer multiplication (i.e. x2) of the sampled voltage between the positive and negative inputs 720bin+ and 720bin- with subtraction of the reference 720bRef / 730Ref or zero voltage / analog ground 720bAgnd / 730Agnd depending on the value of the output bit data 720bData. When the control clock 730CLK / 720bCLK is in“enable” phase, the control clock 720cCLK is in“setup” phase, and thus the second bit-slice ADC 720c samples the positive and negative outputs 720bout+ and 720bout- of the first bit-slice ADC 720b at the positive and negative inputs 720cin+ and 720cin-, respectively.

As the control clock 730CLK enters into“setup” / 720cCLK phases into“enable” phase, based on the sampled voltage at the positive and negative inputs 720cin+ and 720cin-, the second bit-slice ADC 720c generates the second most significant bit at the data 720cdata for the first even bit through even bit data 730ed to the data stream 730data, and further provides the resulting voltage at its positive and negative outputs 720cout+ and 720cout-, which are an integer multiple (i.e. x2) of the sampled voltage between the positive and negative inputs 720cout+ and 720cout- with subtraction of the reference 720cRef / 730Ref or zero voltage / analog ground 720cAgnd / 730Agnd depending on the value of the output bit data 720cdata. When the control clock 730CLK is in subsequent“setup” phase(s), the first bit-slice ADC 720b samples the positive and negative outputs 720cout+ and 720cout- of the second bit-slice ADC 720c at the positive and negative inputs 720bin+ and 720bin-, respectively.

The above-mentioned process repeats until the desired bit length is obtained.

Figures 20a and 20b illustrate schematic diagrams of a pipe-line differential ADC 760 of the present invention, including four (4) bit-slice ADCs 720d1, 720d2, 720d3 and 720d4, each of which is the same as bit-slice ADC 720 shown in Figures 15a and 15b, which produces four (4) bit data conversion. The ADC 760 receives the clock 760CLK, positive and negative inputs 760in+ and 760in-, analog ground 760Agnd, reference 760Ref, and provides data 760Data and positive and negative output 760out+ and 760out-. Conversion step size of the ADC 760 is represented by the voltage difference between the reference 760Ref and 760Agnd. In a preferred embodiment of the present invention, the clock 760CLK is fed directly to operate the first and third bit-slice compact ADCs 720d1 and 720d3, which are for processing “odd” bits, and the clock 760CLK is inverted by the invertor 760inv and fed to control / operate the second and fourth bit-slice compact ADCs 720d2 and 720d4, which are for processing“even” bits. While the figures show four (4) bit ADC, it may be apparent that as many of these stages can be connected together in series as desired forming a scalable data converter. The number of stages, sizing of capacitors, noise floor, and clock speed limit the resolution for any given IC process, but the data converters are highly scalable across IC process nodes. A few design considerations can be included to enhance these limits, such as voltage scaling and special outer voltage switches with reduced turn-off charge injection.

The first bit-slice ADC 720d1 is for producing the first odd data bit or the most significant bit; the second bit-slice ADC 720d2 is for the second significant bit; the third bit-slice ADC 720d3 is for the third significant bit; and the fourth bit-slice ADC 720d4 is for the least significant bit.

Control clock 760CLK is fed directly to the clocks 720d1CLK and 720d3CLK; while 720d2CLK and 720d4CLK are invert of 760CLK by an inverter 760inv. The four bit-slice ADCs 720d1, 720d2, 720d3 and 720d4 are connected in series, where the positive and negative outputs of the previous bit-slice ADC are connected to the corresponding positive and negative inputs of the subsequent ADC, for example, the positive and negative outputs 720d1out+ and 720d1out- of the first bit-slice ADC 720d1 are connected to the positive and negative inputs 700d2in+ and 700d2in-, respectively, of the second bit-slice ADC 720d2; the positive and negative output 720d2out+ and 720d2out- of the second bit-slice ADC 720d2 are connected to the positive and negative inputs 720d3in+ and 720d3in-, respectively, of the third bit-slice ADC 720d3; and the positive and negative outputs 720d3out+ and 720d3out- of the third bit-slice ADC 720d3 are connected to the positive and negative inputs 700d4in+ and 700d4in- of the fourth bit-slice ADC 720d4.

The first bit-slice ADC 720d1 comprises a pair of CiAmps 600r1 and 600r2, analog ground 720d1Agnd, positive input 720d1in+, negative input 720d1in-, reference voltage 720d1Ref, a control clock 720d1CLK, positive output 720d1out+, negative output 720d1out-, and data output 720d1Data, two flying capacitors, 72d1fc1 and 72d1fc2, two offset capacitors, 72d1oc1 and 72d1oc2,“setup” switches 72d1ss1, 72d1ss2, 72d1ss3, 72d1ss4, 72d1ss5, 72d1ss6, 72d1ss7, 72d1ss8, 72d1ss9, 72d1ss10, 72d1ss11 and 72d1ss12 which close during “setup” phase of the control clock 720d1CLK,“enable” switches 72d1es1 and 72d1es2 which close during“enable” phase of the control clock 720d1CLK.

The comparator 725d1 comprises CiAmps 600r4 and 600r5, which are connected in series through a capacitor 72d1oc7,“setup” switches 72d1ss13, 72d1ss15 and 72d1ss16 which close during“setup” phase of the control clock 720d1CLK,“enable” switches 72d1es3 and 72d1es4 which close during“enable” phase of the control clock 720d1CLK, with an optional gain stage 600r3 including setup switch 72d1ss14 (which closes during“setup” phase of the control clock 720d1CLK) and offset capacitor 72d1oc5. Further optionally, the comparator 725d1 may provide a feed-forward path 72d1ffp, in which the input to the amplifier 600r4 may be capacitively fed forward to PiPort 60r5pi and NiPort 60r5ni of the CiAmp 600r5 through capacitors 72d1ff1 and 72d1ff2, respectively.

The second bit-slice ADC 720d2 comprises a pair of CiAmps 600s1 and 600s2, analog ground 720d2Agnd, positive input 720d2in+, negative input 720d2in-, reference voltage 720d2Ref, a control clock 720d2CLK, positive output 720d2out+, nagative output 720d2out-, and data output 720d2Data, two flying capacitors, 72d2fc1 and 72d2fc2, two offset capacitors, 72d2oc1 and 72d2oc2,“setup” switches 72d2ss1, 72d2ss2, 72d2ss3, 72d2ss4, 72d2ss5, 72d2ss6, 72d2ss7, 72d2ss8, 72d2ss9, 72d2ss10, 72d2ss11 and 72d2ss12 which close during “setup” phase of the control clock 720d2CLK,“enable” switches 72d2es1 and 72d2es2 which close during“enable” phase of the control clock 720d2CLK.

The comparator 725d2 comprises CiAmps 600s4 and 600s5, which are connected in series through a capacitor 72d2oc7,“setup” switches 72d2ss13, 72d2ss15 and 72d2ss16 which close during“setup” phase of the control clock 720d2CLK,“enable” switches 72d2es3 and 72d2es4 which close during“enable” phase of the control clock 720d2CLK, with an optional gain stage 600s3 including setup switch 72d2ss14 (which close during“setup” phase of the control clock 720d2CLK) and offset capacitor 72d2oc5. Further optionally, the comparator 725d2 may provide a feed-forward path 72d2ffp, in which the input to the amplifier 600s4 may be capacitively fed forward to PiPort 60s5pi and NiPort 60s5ni of the CiAmp 600s5 through capacitors 72d2ff1 and 72d2ff2, respectively.

The third bit-slice ADC 720d3 comprises a pair of CiAmps 600t1 and 600t2, analog ground 720d3Agnd, positive input 720d3in+, negative input 720d3in-, reference voltage 720d3Ref, a control clock 720d3CLK, positive output 720d3out+, nagative output 720d3out-, and data output 720d3Data, two flying capacitors, 72d3fc1 and 72d3fc2, two offset capacitors, 72d3oc1 and 72d3oc2,“setup” switches 72d3ss1, 72d3ss2, 72d3ss3, 72d3ss4, 72d3ss5, 72d3ss6, 72d3ss7, 72d3ss8, 72d3ss9, 72d3ss10, 72d3ss11 and 72d3ss12 which close during “setup” phase of the control clock 720d3CLK,“enable” switches 72d3es1 and 72d3es2 which close during“enable” phase of the control clock 720d3CLK.

The comparator 725d3 comprises CiAmps 600t4 and 600t5, which are connected in series through a capacitor 72d3oc7,“setup” switches 72d3ss13, 72d3ss15 and 72d3ss16 which close during“setup” phase of the control clock 720d3CLK,“enable” switches 72d3es3 and 72d3es4 which close during“enable” phase of the control clock 720d3CLK, with an optional gain stage 600t3 including setup switch 72d3ss14 (which closes during“setup” phase of the control clock 720d3CLK) and offset capacitor 72d3oc5. Further optionally, the comparator 725d3 may provide a feed-forward path 72d3ffp, in which the input to the amplifier 600t4 may be capacitively fed forward to PiPort 60t5pi and NiPort 60t5ni of the CiAmp 600t5 through capacitors 72d3ff1 and 72d3ff2, respectively.

The fourth bit-slice ADC 720d4 comprises a pair of CiAmps 600u1 and 600u2, analog ground 720d4Agnd, positive input 720d4in+, negative input 720d4in-, reference voltage 720d4Ref, a control clock 720d4CLK, positive output 720d4out+, nagative output 720d4out-, and data output 720d4Data, two flying capacitors, 72d4fc1 and 72d4fc2, two offset capacitors, 72d4oc1 and 72d4oc2,“setup” switches 72d4ss1, 72d4ss2, 72d4ss3, 72d4ss4, 72d4ss5, 72d4ss6, 72d4ss7, 72d4ss8, 72d4ss9, 72d4ss10, 72d4ss11 and 72d4ss12 which close during “setup” phase of the control clock 720d4CLK,“enable” switches 72d4es1 and 72d4es2 which close during“enable” phase of the control clock 720d4CLK.

The comparator 725d4 comprises CiAmps 600u4 and 600u5, which are connected in series through a capacitor 72d4oc7,“setup” switches 72d4ss13, 72d4ss15 and 72d4ss16 which close during“setup” phase of the control clock 720d4CLK,“enable” switches 72d4es3 and 72d4es4 which close during“enable” phase of the control clock 720d4CLK, with an optional gain stage 600u3 including setup switch 72d4ss14 (which close during“setup” phase of the control clock 720d4CLK) and offset capacitor 72d4oc5. Further optionally, the comparator 725d4 may provide a feed-forard path 72d4ffp, in which the input to the amplifier 600u4 may be capacitively fed forward to PiPort 60u5pi and NiPort 60u5ni of the CiAmp 600u5 through capacitors 72d4ff1 and 72d4ff2, respectively.

During operation, during“setup” phase of the control clock 760CLK / 720d1CLK, the first bit-slice ADC 720d1 samples the positive and negative inputs 760in+ and 760in- at the corresponding positive and negative inputs 720d1in+ and 720d1in-, respectively to produce the most significant bit 760B1 at the data 720d1data to the data stream 760data. As the control clock 760CLK / 720d1CLK phases into“enable”, the first bit-slice ADC 720d1 provides the resulting voltage at its positive and negative outputs 720d1out+ and 720d1out-, which is an integer multiplication (i.e. x2) of the sampled voltage at the positive and negative inputs 720d1in+ and 720d1in- with subtracting either reference 760Ref / 720d1Ref if the produced bit value 720d1data is“1”, or analog ground 760Agnd / 720d1Agnd, (or zero) if the produced bit value 720d1data is“0”. The first bit-slice ADC 720d1 produces“1” for data 720d1data if the sampled voltage is greater than analog ground 720d1Agnd; otherwise,“0”.

The second bit-slice ADC 720d2 samples the positive and negative outputs 720d1out+ and 720d1out- of the first bit-slice ADC 720d1 during the“setup” phase of the control clock 720d2CLK (invert of clock 760CLK) for producing the second most significant bit 760B2 at the data 720d2data to the data stream 760data. As the control clock 720d2CLK phases into “enable”, the second bit-slice ADC 720d2 provides the resulting voltage at the positive and negative outputs 720d2out+ and 720d2out-, which is an integer multiplication (i.e. x2) of the sampled voltage at the positive and negative inputs 720d2in+ and 720d2in- with subtracting either reference 720d2Ref if the produced bit value 720d2data is“1”, or analog ground 720d2Agnd (or zero) if the produced bit value 720d2data is“0”. The second bit-slice ADC 720d2 produces“1” for data 720d2data if the sampled voltage is greater than analog ground 720d2Agnd; otherwise,“0”.

The third bit-slice ADC 720d3 samples the positive and negative outputs 720d2out+ and 720d2out- of the second bit-slice ADC 720d2 during the“setup” phase of the control clock 720d3CLK/760CLK for producing the third most significant bit 760B3 at the data 720d3data to the data stream 760data. As the control clock 720d3CLK phases into“enable”, the third bit- slice ADC 720d3 provides the resulting voltage at the positive and negative outputs 720d3out+ and 720d3out-, which is an integer multiplication (i.e. x2) of the sampled voltage at the positive and negative inputs 720d3in+ and 720d3in- with subtracting either reference 720d3Ref if the produced bit value 720d3data is“1”, or analog ground 720d3Agnd (or zero) if the produced bit value 720d3data is“0”. The third bit-slice ADC 720d3 produces“1” for data 720d3data if the sampled voltage is greater than analog ground 720d3Agnd; otherwise,“0”.

The fourth bit-slice ADC 720d4 samples the positive and negative outputs 720d3out+ and 720d3out- of the third bit-slice ADC 720d3 during the“setup” phase of the control clock 720d4CLK (invert of clock 760CLK) for producing the least significant bit 760B4 at the data 720d4data to the data stream 760data. As the control clock 720d4CLK phases into“enable”, the fourth bit-slice ADC 720d4 provides the resulting voltage at the positive and negative outputs 720d4out+ and 720d4out-, which is an integer multiplication (i.e. x2) of the sampled voltage at the positive and negative inputs 720d4in+ and 720d4in- with subtracting either reference 720d4Ref if the produced bit value 720d4data is“1”, or analog ground 720d4Agnd (or zero) if the produced bit value 720d4data is“0”. The fourth bit-slice ADC 720d4 produces “1” for data 720d4data if the sampled voltage is greater than analog ground 720d4Agnd; otherwise,“0”.

The resulting output voltage is twice of the sampled voltage at the input in this embodiment at the each stage of the conversion; however, optionally, such gain may be changed, for example, by having more than two flying capacitors. For example, three (3) times gain may be realized by adding an additional flying capacitor (thus total three flying capacitors). In other words, magnitude of the voltage gain at the output is proportional to the number of flying capacitors.

Figure 21 is a representative analog signal and timing diagram 1000 of a 16-bit single- ended successive approximation ADC 710 as shown in Figures 14a and 14b. The plot is divided into 4 regions: 1) the logic level timing is the lower region 1001, 2) both internal analog voltage residues between the two bit-slice stages 1002, 3) ADC logic data out from each of the two bit- slice stages 1003, and 4) the average power consumption 1004.

The X-axis is time running from 18µs to 34µs covering 8 cycles of the 1MHz clock window used for making one 16-bit analog to digital conversion. The sample input voltage logic control signal in 1000 is a half-clock wide. The various trace voltage scales within 1001 are logic 0 and 1 for each trace individually. The ADC input acquires and tracks the analog input voltage during this time window. The instantons aperture time point that is used is at the falling edge of this sample logic signal 1001a. The controlling clock logic signal for the first or Odd bit-slice data converter stage is 1001b. When this clock 1001b is high, this odd bit-slice is put in its “setup” phase of operation and when this clock is low the bit-slice is operated in the“enable” phase of operation to generate its analog residue output 700bout of Figure 14b and pass it to the even bit-slice stage input 700cin.

The first or odd-stage comparator output 710od is 1001c. The comparator decides on whether the input signal 700bin is either above or below half-scale. Half-scale is the Agnd 710Agnd voltage and zero-scale is the Ref voltage 710Ref.

Figure 23 abstractly diagrams these voltage relationships. The comparator waveform 1001c has a bold thick line through the center to cover up the comparator’s“setup” mode, thus focusing on comparator activity. The comparator used for these waveforms is a tracking comparator instead of the latching comparator 705b as shown in Figure 14b. A 6-stage tracking comparator was used for this example because it shows a little more of the activity of the analog voltages being processed bounce a little while the signal propagates through the inverter chain. In any case, the comparator output is accepted or latched at the end of the“setup” phase of the controlling clock. This tracking comparator also doubled the power drain which was included in the top 24µW power drain waveform 1004. The power is also high because a 180nm all-digital IC technology node was used for these examples. Also, note that the 1.8-volt technology works just fine at 1.0-volts and it continues to operate down to a 200mV power supply showing that the CiFET amplifiers are not threshold voltage limited. Nanoscale technologies that are designed to work at 1.0 to 1.2-volts operate much better in all ways.

The second group 1002 of waveforms in Figure 21 are the analog voltage outputs of both the odd 700b and even 700c bit-slice stages overlaid on each other. The voltage scale for the waveform 1002 is ±Ref around Agnd. The dashed part of the waveform is the odd bit-slice residue voltage output 700bout and the dotted part of the waveform is the even residue output 700cout. The thick centerline hides the“setup” phase of the analog voltages where they are at Agnd. Note that when the residue voltage 1002a is below Agnd, the associated comparator output 1001c is driven low and when the residue voltage is above Agnd, the associated comparator output is driven high. The third group 1003 of waveforms is the dashed odd 710od data logic output signal 1003a and the dotted waveform 1001a is the even data output 710ed.

The top waveform 1000 in Figure 21 is the power averaged power consumption of the entire ADC including logic showing a power consumption of about 24µWatts. The average power was not flat at first because of the numerical averaging algorithm.

Figure 22 is a representative analog signal and timing diagram 1100 of a 16-bit differential successive-approximation DAC of Figure 12a and 12b. The plot is divided into 4 regions: 1) the logic level timing is the lower region 1101, 2) both internal analog voltage residues between the two bit-slice stages 1102, 3) Final DAC output voltage 1103 captured by an additional Sample and Hold output buffer stage, and 4) the average power consumption 1104.

The X-axis is time running from 37µs to 54µs covering 8 cycles of the 1MHz clock window for a 16-bit digital to analog conversion. The extra half-cycle is a conversion overlap from one conversion cycle to the adjacent conversion used to initialize the odd conversion stage 930a to either no offset or a half-scale DAC output voltage offset. The initialize conversion 1101a logic input control signal in 1100 is the extra half-clock cycle time. The trace voltage scales within 1101 are logic 0 and 1 for each trace individually.

The individual bit-slice DAC differential outputs 930aout+ to 930aout- (a is odd), and 930bout+ to 930bout- (b is even) are plotted in window 1002, which uses a differential voltage scale centered on Agnd with a ±range going from -2*Ref to +2*Ref which was extended so that the analog transients were not clipped out of the plot. The DAC has higher ring voltage peaks than the ADC of Figure 21 to because the CiAmps were intentionally under-compensated for their extreme voltage gain of about 100 million to better see the analog response. The odd bit- slice analog output is shown as the dashed portion of the composite plot and the even as the dotted portion. The thick centerline is at Agnd midpoint to cover up the“setup” portion of each voltage portion, focusing on the DAC voltage buildup. The odd 1101c and even 1101e data bit inputs control the addition or subtraction of voltage in the DAC voltage buildup sequence. The superimposed direction arrows from these logic signals to the voltage signals point out which data bit is responsible for either a rise or fall step leading into each succeeding DAC voltage plateau. The Offset=0 logic control is passed from the previous data bit if it is desired to include half-scale offset voltage control. The successive approximation DACs of Figures 10a, 10b, 12a, and 12b has this offset hardwired to zero, while the pipeline DACs in Figures 17a, 17b, 18a, and 18b illustrate programmable half-scale offset voltage inclusion in the final DAC output voltage.

The third plot window 1103 is the output voltage update magnified excessively to indicate the ~5µv step precision target and the time at which the new DAC output voltage is updated. This is an extra sample and hold amplifier on the DAC output used to hold the DAC output voltage constant between conversions.

The top waveform 1104 is the average power of the DAC including the control logic and sample and hold output amplifier. It was 11µW for this example. The average power was not flat at first because of the numerical averaging algorithm.

As it can be seen above, the two-phase data converters 2000, 900, 910, 930, 940, 960, 9A0, 700, 710, 720, 730, 750 and 760 of the present invention have a general timing rule to be kept in mind– always maintain isolation between operational phases, i.e.“setup” and“enable” phases, by first opening a“setup” switch before closing an“enable” switch, or vice versa. Since the circuits 2000, 900, 910, 930, 940, 960, 9A0, 700, 710, 720, 730, 750 and 760 operate at logic speed, only an inverter delay is necessary. Also, it is beneficial to drive both the P and N- channel transistors of the transmission-gate switches symmetrically so that turn-off charge coupling errors are maximally canceled by the complementary switch control logic signals. About half of the switch turn-off charge coupling difference is captured on the related capacitances, dictating the size of the capacitors vs precision. The further the internal data converter voltage swing is from the midpoint analog ground“Agnd,” the higher this error contributes. This signal magnitude dependence is not a factor for the offset capacitors since they are always operating at near“Agnd” of a fixed“Ref” voltage. For high-resolution applications, switch charge injection errors become significant at larger internal signal swings along with the reduced gain error contribution at the same large internal signal operating voltages as abstractly shown in Figure 23.

Claims

WHAT IS CLAIMED IS: 1. A charge based digital to analog converter (DAC), receiving an analog input, analog ground, reference for data conversion, and a data bit having a value either one or zero for producing a resulting output voltage, comprising:

a. an inverting amplifier, having input and output;

b. a plurality of flying capacitors;

c. first and second offset capacitors;

d. switches operable with a control signal having first and second phases, wherein,

when the control signal is in the first phase, the switches cause the inverting amplifier to self-bias by connecting the input and output of the inverting amplifier, the plurality of flying capacitors to be connected in series to sample the analog input voltage, the first offset capacitor to store a first differential voltage between the self-biased voltage of the inverting amplifier and the reference, and the second offset capacitor to store a second differential voltage between the self-biased voltage of the inverting amplifier and the analog ground; and

when the control signal is in the second phase, the switches cause the first and second flying capacitors to be connected in parallel to divide the analog input voltage by the number of the plurality of the flying capacitors, and further connect the parallelly connected the plurality of flying capacitors with the first offset capacitor if the data bit is one to add the first offset voltage, or the second offset capacitor if the data bit is zero to add the second differential voltage for providing the output of the DAC, and to form a capacitive feedback from the output to the input of the inverting amplifier for producing the resulting output voltage.

2. The DAC as recited in claim 1, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

3. The DAC as recited in claim 2, wherein each of complimentary pairs of current field- effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

4. The DAC as recited in claim 3, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

5. The DAC as recited in claim 4, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

6. The DAC as recited in claim 1, wherein the number of the plurality of the flying capacitors is two.

7. A charge based successive approximation digital to analog converter (DAC) for even bit length of data for producing a resulting output voltage, comprising:

a first charge based bit-slice digital to analog converter and a second charge based bit- slice digital to analog converter, each of the first and second bit-slice digital to analog converters are operable by a control clock having first and second phases,

the first and second charge based bit-slice digital to analog converters are configured to be operated out of synchronization by 180°, and are connected in series by connecting the output of the first bit-slice digital to analog converter to the input of the second bit-slice digital to analog converter, whereby, for every two bits from the least significant bit of the data, the first bit-slice digital to analog converter processes one less significant bit of the every two bits than the second bit-slice digital to analog converter, each of the every two bits having a value of one or zero,

each of the first and second charge based bit-slice digital to analog converters receives an input, an analog ground, and a reference voltage during the first phase of the control clock; and, during the second phase of the control clock, based on a corresponding bit data of the every two bits, configured to provide an output which is an integer division of the input voltage with addition of either reference voltage when the bit data is one or analog ground or zero when the bit data is zero,

wherein the output of the second bit-slice digital to analog converter is fed back to the input of the first bit-slice digital to analog converter for processing the subsequent two bits of the data or is the resulting output voltage of the DAC.

8. The DAC as recited in claim 7, wherein each of the first and second bit-slice digital to analog converters comprises an inverting amplifier, a plurality of flying capacitors, first and second offset capacitors, and a plurality of switches operable to the control signal.

9. The DAC as recited in claim 8, wherein:

a. when the control signal is in the first phase, the plurality of switches cause to connect the plurality of the flying capacitors in series to sample the input voltage, the inverting amplifier to be self-biased by directly feeding back the output to the input of the inverting amplifier, the first offset capacitor to store a differential voltage between the self-biased voltage of the inverting amplifier and the reference, the second offset capacitor to store a differential voltage between the self-biased voltage of the inverting amplifier and the analog ground;

b. when the control signal is in the second phase, the plurality of switches cause to connect the plurality of the flying capacitors in parallel to divide the sampled input voltage by the number, and further connect the parallelly connected flying capacitors with either the first offset capacitor in series if the bit data is one or the second offset capacitor in series if the bit data is zero, between the input and output of the inverting amplifier for producing the resulting output voltage.

10. The DAC as recited in claim 9, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

11. The DAC as recited in claim 10, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

12. The DAC as recited in claim 11, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

13. The DAC as recited in claim 12, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

14. The DAC as recited in claim 9, wherein the number of the flying capacitors is two.

15. A digital to analog convertor for converting data, comprising a plurality of bit-slice digital to analog convertors (DACs) connected in series, each of the bit-slice digital convertors receives an input voltage, a reference voltage, analog ground, a control clock having first and second phases, and a corresponding data bit having value“1” or“0” for producing a resulting output voltage for the corresponding data bit, a previous one of the DACs processes one less significant bit of the data than a subsequent one, the previous one and the subsequent one of the DACs are operated at 180° phase difference in the control clock, whereby the subsequent one samples the resulting output voltage from the previous one, each of the digital to analog converter comprising:

a. a plurality of flying capacitors;

b. first and second offset capacitors;

c. an inverting amplifier; and d. a plurality of switches operable with a control clock having first and second phases;

wherein, during the first phase of the control clock, the plurality of switches causes the plurality of flying capacitors to be connected in series for storing the input voltage in reference to the analog ground, the inverting amplifier to be self-biased by establishing a direct feedback from the input to output of the inverting amplifier, the first offset capacitor to store a difference between the self-biased voltage of the inverting amplifier and the reference, and the second offset capacitor to store a difference between the self-biased voltage of the inverting amplifier and the analog ground;

during the second phase of the control, the plurality of switches causes the plurality of flying capacitors to be connected in parallel to output an integer division of the sampled input voltage by the number of the flying capacitors, causes to connect the parallelly connected flying capacitors with the first offset capacitor if the value of the corresponding data bit is“1” or second offset capacitor if the value of the corresponding data bit is“0”, in series between the input and the output of the inverting amplifier for producing the resulting output voltage.

16. The DAC as recited in claim 15, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

17. The DAC as recited in claim 16, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

18. The DAC as recited in claim 17, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

19. The DAC as recited in claim 18, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

20. A charge based successive approximation analog to digital converter (ADC) for converting from an analog voltage into an even bit length data, comprising:

a first charge based bit-slice analog to digital converter and a second charge based bit- slice analog to digital converter,

each of the first and second bit-slice analog to digital converters are operable by a control clock having first and second phases, and receives input, analog ground, reference voltage during the first phase of the control clock, and, during the second phase of the control clock, a comparator for comparing the input voltage with the reference voltage and produces a bit value“1” if the input voltage is over the reference, while produce a bit value“0” if the input voltage is lower than the reference, based on the bit value, configured to provide an output which is an integer multiplication of the input voltage with addition of either the reference voltage when the bit value is one or analog ground or zero when the bit data value is zero, wherein the first and second bit-slice analog to digital converters are configured to be operated out of synchronization by 180° phase difference, and are connected in series by connecting the output of the first bit-slice analog to digital converter to the input of the second bit-slice analog to digital converter, whereby, the first bit-slice analog to digital converter produces one more significant bit of the every two bits than the second bit-slice analog to digital converter, and

the output of the second bit-slice analog to digital converter is fed back to the input of the first bit-slice analog to digital converter for processing the subsequent two bits of the data.

21. The ADC as recited in claim 20, wherein each of the first and second bit-slice ADC comprises an inverting amplifier, a plurality of flying capacitors, first and second offset capacitors, and a plurality of switches operable to the control signal.

22. The ADC as recited in claim 21, wherein:

a. when the control signal is in the first phase, the plurality of switches cause to connect the plurality of the flying capacitors in parallel to sample the input voltage, the inverting amplifier to be self-biased by directly feeding back the output to the input of the inverting amplifier, the first offset capacitor to store a differential voltage between the self-biased voltage of the inverting amplifier and the reference, the second offset capacitor to store a differential voltage between the self-biased voltage of the inverting amplifier and the analog ground;

b. when the control signal is in the second phase, the plurality of switches cause to connect the plurality of the flying capacitors in series to multiply the sampled input voltage by the number, and further connect the serially connected flying capacitors to either the first offset capacitor in series when the corresponding bit value is“one” or the second offset capacitor in series when the corresponding bit value is“zero” between the input and output of the inverting amplifier for producing the resulting output voltage.

23. The ADC as recited in claim 22, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

24. The ADC as recited in claim 23, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

25. The ADC as recited in claim 24, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

26. The ADC as recited in claim 25, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

27. The ADC as recited in claim 26, wherein the number of the flying capacitors is two.

28. The ADC as recited in claim 26, wherein the comparator comprises:

a. a first capacitor;

b. a first and second inverting amplifiers capacitively coupled together through a second capacitor; and

c. a plurality of switches operable by the control clock;

wherein during the first phase of the control clock, the switches cause the first and second inverting amplifiers to be self-biased by feeding back an output to an input of the first inverting amplifier and an output to input of the second inverting amplifier, the first capacitor to store differential voltage between the self-biased voltage of the first inverting amplifier and the analog ground;

during the second phase of the control clock, the switches cause the output of the second inverting amplifier to be fed back to the input of the first inverting amplifier, and the input voltage to be capacitively coupled through the first capacitor with the input of the inverting amplifier for producing the corresponding bit date.

29. A charge based analog to digital converter, (ADC), comprising a plurality of bit-slice ADCs connected in series, each of the bit-slice digital convertors receives an input voltage, a reference voltage, analog ground, a control clock having first and second phases, and a corresponding data bit having value“1” or“0” for producing a resulting output voltage for the corresponding data bit, a previous one of the DACs processes one less significant bit of the data than a subsequent one, the previous one and the subsequent one of the DACs are operated at 180° phase difference in the control clock, whereby the subsequent one samples the resulting output voltage from the previous one, each of the digital to analog converter comprising:

a. a plurality of flying capacitors;

b. first and second offset capacitors;

c. an inverting amplifier; and

d. a plurality of switches operable with a control clock having first and second phases;

during the second phase of the control, the plurality of switches causes the plurality of flying capacitors to be connected in parallel to output an integer division of the sampled input voltage by the number of the flying capacitors, causes to connect the parallelly connected flying capacitors with the first offset capacitor if the value of the corresponding data bit is“1” or second offset capacitor if the value of the corresponding data bit is“0”, in series for producing the resulting output voltage.

30. The ADC as recited in claim 29, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

31. The ADC as recited in claim 30, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

32. The ADC as recited in claim 31, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

33. The ADC as recited in claim 32, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

34. A successive approximation differential digital to analog converter (DAC) for converting data having an even number of bits into a resulting output voltage, comprising:

a. a first bit slice differential digital to analog converter, and a second bit slice differential digital to analog converter for processing every two bits from the least significant bit of the data and the first bit slice differential digital to analog converter processes less significant bit of the every two bits than the second bit slice differential digital to analog converter,

each of the first and second bit slice differential digital to analog converters comprises first and second inverting amplifiers, and is operable with a control clock having first and second phases, and,

during the first phase of the control clock, each receives positive and negative inputs for receiving and storing a differential input voltage therebetween, self-biases the first and second inverting amplifiers by feeding an input to an output of each of the first and second inverting amplifier, receives a reference voltage to store a differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier, and receives an analog ground to store a differential voltage between the analog ground and the self-biased voltage at the inverting amplifier; and

during the second phase of the control clock, each receives a corresponding bit of the data to produce a corresponding positive resulting output voltage at the first inverting amplifier by dividing a positive half of the sampled differential input voltage and add the differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier if the corresponding bit is one or the differential voltage between the analog ground and the self-biased voltage at the inverting amplifier if the corresponding bit is zero, and to produce a corresponding negative resulting output voltage at the second inverting amplifier by dividing a negative half of the sampled differential input voltage and add the differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier if the corresponding bit is one or the differential voltage between the analog ground and the self-biased voltage at the inverting amplifier if the corresponding bit is zero;

wherein the first and second bit-slice digital to analog converters are configured to be operated out of synchronization by 180° phase difference, and

the first bit slice differential digital to analog converter and the second bit slice differential digital to analog converter are connected in series by connecting the positive and negative outputs of the first bit slice differential digital to analog converter to the positive and negative inputs of the second bit slice differential digital to analog converter;

during a first phase of a first cycle of the control clock to the first bit slice differential digital to analog converter, the positive and negative inputs of the first bit slice differential digital to analog converter are connected to the analog ground;

during subsequent first phases of the control clock to the first bit slice differential digital to analog converter, the positive and negative inputs of the first bit slice differential digital to analog converter are connected to the positive and negative outputs of the second bit slice differential digital to analog converter for processing subsequent two bits of the data.

35. The DAC as recited in claim 30, wherein the each of the first and second bit slice differential digital to analog converters further comprises a plurality of flying capacitors for storing differential input voltage, a first and second offset capacitors for storing the differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier and the differential voltage between the analog ground and the self-biased voltage at the inverting amplifier, respectively, and plurality of switches.

36. The DAC as recited in claim 31, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

37. The DAC as recited in claim 32, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

38. The DAC as recited in claim 33, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

39. The DAC as recited in claim 34, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

40. A pipe-line differential digital to analog converter (DAC) for converting data having a number of bits into a resulting output voltage, comprising:

a. A corresponding number of bit slice differential digital to analog converters as the number of bits connected in series, each of the plurality of the bit slice differential digital to analog converters comprises first and second inverting amplifiers, and is operable with a control clock having first and second phases, and

during the first phase of the control clock, each receives positive and negative inputs for receiving and storing a differential input voltage therebetween, self- biases the first and second inverting amplifiers by feeding an input to an output of each of the first and second inverting amplifier, receives a reference voltage to store a differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier, and receives an analog ground to store a differential voltage between the analog ground and the self-biased voltage at the inverting amplifier; and

wherein a previous one and a subsequent one of the plurality of the bit-slice digital to analog converters are configured to be operated out of synchronization by 180° phase difference whereby the subsequent bit slice differential digital to analog converter receives the positive and negative outputs of the previous bit slice differential digital to analog converter at the positive and negative inputs of the subsequent bit slice differential digital to analog converter, and

the previous one of the plurality of the bit-slice digital to analog converters processes less significant bit than the subsequent one thereof; during a first phase of a first cycle of the control clock to the first one of the plurality of the bit slice differential digital to analog converter, the positive and negative inputs of the first bit slice differential digital to analog converter are connected to the analog ground.

41. The DAC as recited in claim 36, wherein the each of the plurality of bit slice differential digital to analog converters further comprises a plurality of flying capacitors for storing differential input voltage, a first and second offset capacitors for storing the differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier and the differential voltage between the analog ground and the self-biased voltage at the inverting amplifier, respectively, and plurality of switches.

42. The DAC as recited in claim 37, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

43. The DAC as recited in claim 38, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

44. The DAC as recited in claim 39, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

45. The DAC as recited in claim 40, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

46. A successive approximation differential analog to digital converter (ADC) for converting an differential analog voltage into data having an even number of bits, comprising:

a first bit slice differential analog to digital converter, and a second bit slice differential analog to digital converter for producing every two bits from the most significant bit of the data and the first bit slice differential analog to digital converter produces more significant bit of the every two bits than the second bit slice differential analog to digital converter,

each of the first and second bit slice differential analog to digital converters comprises first and second inverting amplifiers and a comparator, and is operable with a control clock having first and second phases, and,

during the first phase of the control clock, each receives positive and negative inputs for receiving and storing the differential analog input voltage therebetween, self- biases the first and second inverting amplifiers by feeding an input to an output of each of the first and second inverting amplifier, receives a reference voltage to store a differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier, and receives an analog ground to store a differential voltage between the analog ground and the self-biased voltage at the inverting amplifier; and during the second phase of the control clock,

the comparator compares the positive input and negative input voltage and produces a value“1” for a corresponding bit of the data if the positive input voltage is greater than the negative input voltage, or“0” for the corresponding bit of the data if the positive input voltage is less than or equal to the negative input voltage,

according to the produced value of the corresponding bit of the data, the first inverting amplifier produces a positive output voltage by multiply a positive half of the sampled differential input voltage and add the differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier if the corresponding bit is one or the differential voltage between the analog ground and the self-biased voltage at the inverting amplifier if the corresponding bit is zero, and to produce a corresponding negative resulting output voltage at the second inverting amplifier by dividing a negative half of the sampled differential input voltage and add the differential voltage between the reference voltage and the self-biased voltage of the inverting amplifier if the corresponding bit is one or the differential voltage between the analog ground and the self-biased voltage at the inverting amplifier if the corresponding bit is zero;

wherein the first and second bit-slice analog to digital converters are configured to be operated out of synchronization by 180° phase difference, and

the first bit slice differential analog to digital converter and the second bit slice differential analog to digital converter are connected in series by connecting the positive and negative outputs of the first bit slice differential analog to digital converter to the positive and negative inputs of the second bit slice differential analog to digital converter, respectively;

during a first phase of a first cycle of the control clock to the first bit slice differential digital to analog converter, the positive and negative inputs of the first bit slice differential analog to digital converter are connected to the analog ground;

during subsequent first phases of the control clock to the first bit slice differential analog to digital converter, the positive and negative inputs of the first bit slice differential analog to digital converter are connected to the positive and negative outputs of the second bit slice differential analog to digital converter for producing subsequent two bits of the data.

47. The ADC as recited in claim 46, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

48. The ADC as recited in claim 47, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

49. The ADC as recited in claim 48, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

50. The ADC as recited in claim 49, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.

51. A pipe-line differential analog to digital converter (ADC) for converting an differential analog voltage into data having a number of bits, comprising:

a a corresponding number of bit slice differential analog to digital converters to the number of the bits of the data for producing the data from the most significant bit of the data, a previous one of the bit slice differential analog to digital converters produces more significant bit than a subsequent one of the bit slice differential analog to digital converters,

each of the bit slice differential analog to digital converters comprises first and second inverting amplifiers and a comparator, and is operable with a control clock having first and second phases, and,

during the first phase of the control clock, each receives positive and negative inputs for receiving and storing the differential analog input voltage therebetween, self- biases the first and second inverting amplifiers by feeding an input to an output of each of the first and second inverting amplifier, receives a reference voltage to store a differential voltage between the reference voltage and the self-biased voltage thereof, and receives an analog ground to store a differential voltage between the analog ground and the self-biased voltage thereof; and

during the second phase of the control clock, the comparator compares the positive input and negative input voltage and produces a value“1” for a corresponding bit of the data if the positive input voltage is greater than the negative input voltage, or“0” for the corresponding bit of the data if the positive input voltage is less than or equal to the negative input voltage,

wherein the previous and subsequent ones of the bit-slice analog to digital converters are configured to be operated out of synchronization by 180° phase difference, whereby the subsequent one of the bit slice differential analog to digital converters receives the positive and negative outputs of the previous one of the bit slice differential analog to digital converters are the positive and negative inputs of the subsequent one of the bit slice differential analog to digital converters;

during a first phase of a first cycle of the control clock to the first one of the bit slice differential digital to analog converters, the positive and negative inputs of the first one of the bit slice differential analog to digital converters are connected to the analog ground.

52. The ADC as recited in claim 51, wherein the inverter amplifier comprising complimentary pairs of current field-effect transistors.

53. The ADC as recited in claim 52, wherein each of complimentary pairs of current field-effect transistors comprising P-type and N-type current field-effect transistors, having a source terminal of the P-type current field-effect transistor being connected to positive power supply, drain terminal of the P-type and N-type current field-effect transistors being connected together, and a source terminal of the N-type current field-effect transistor being connected to the negative power supply, wherein gate terminals of the P-type and N-type current field-effect transistors are connected together to form an input and the connected gate terminals of the P-type and N-type current field-effect transistors form an output for each pair.

54. The ADC as recited in claim 53, wherein the P-type current field-effect transistor comprises P-type current port for diffusing current between the source and gate terminals of the P-type current field-effect transistor, and N-type current field-effect transistor comprises N-type current port for defusing current between the source and gate terminals of the N-type current field-effect transistor.

55. The ADC as recited in claim 54, wherein the inverting amplifier comprises at least three complementary pairs of the P-type and N-type current field-effect transistors being connected in series by having an output of a previous pair of the at least three complementary pairs being connected to an input of a subsequent pair of the at least three complementary pairs.