JP3821819B2 - AD conversion circuit and DA conversion circuit using capacitive coupling - Google Patents

Description

  The present invention relates to a CMOS logic circuit, an AD conversion circuit, and a DA conversion circuit using capacitive coupling. For example, a logic circuit, an AD conversion circuit, and a DA conversion that are integrated in the same LSI together with photoelectric conversion elements by an image sensor or the like. The present invention relates to a novel circuit capable of reducing the number of circuit elements.

The basic configuration of the CMOS logic circuit uses a relatively large number of CMOS transistor elements as described in, for example, “Basics of MOS Integrated Circuit” (Modern Science Co., 1992.5.30). The AD conversion circuit is described in, for example, “Transistor Technology Special No. 16” (CQ Publication 1991.2.1 2nd Edition). In an AD conversion circuit integrated with a photoelectric conversion element such as an image sensor, a flash AD conversion circuit that can obtain an output simultaneously with application of an input is advantageous. However, such a flash AD conversion circuit has many comparisons. Equipment is required and the circuit scale becomes large. For example, in order to construct an n-bit AD conversion circuit, 2 ⁿ −1 comparators are required.

  On the other hand, research is being conducted on image sensors that enable digital output by forming a CMOS circuit on the same substrate and mounting an on-chip signal processing function. For example, as described in “PROCEEDINGS of SPIE Vol.2745 Infrared Readout Electronics III PP.90-127-19.9, April (1996)”.

Further, Patent Documents 1 and 2 below disclose circuits using capacitance.
JP-A 64-81082 Japanese Patent Laid-Open No. 08-125152 Japanese Patent Laid-Open No. 08-204563

  However, as described above, the current CMOS logic circuit has a large number of elements, and the AD conversion circuit for converting an analog signal detected from the sensor into a digital signal has a large number of elements. Therefore, when a digital circuit using such a circuit is formed on the same substrate as the optical sensor, the fill factor, which is the ratio of the area of the sensor portion to the entire chip area, becomes extremely small. This point is described in, for example, ISSCC 1944 DIGEST OF TECHNICAL PAPERS, pp230.

  Accordingly, an object of the present invention is to provide a CMOS logic circuit in which the number of elements is significantly reduced.

  Another object of the present invention is to provide a CMOS AD conversion circuit that does not require a large number of comparators and can be configured with a small number of elements.

  Another object of the present invention is to provide a flash CMOS AD converter circuit that can be configured with a small number of elements.

  Another object of the present invention is to provide a time-series CMOS AD conversion circuit that can be configured with a small number of elements.

  Another object of the present invention is to provide a CMOS DA conversion circuit that can be configured with a small number of elements.

  Furthermore, another object of the present invention is to provide an image sensor which can be mounted with a digital circuit configured with a small number of elements and can have a high fill factor.

  According to the present invention, a logic circuit that solves the above-described problems has a plurality of input terminals to which a binary input is applied, one electrode connected to each of the plurality of input terminals, and the other electrode connected in common. Further, a plurality of input capacitors having substantially the same capacitance value and a voltage of the common electrode are input, and a threshold value is inverted when a voltage corresponding to logic 1 is applied to a predetermined number of input terminals among the plurality of input terminals. It has the inverter circuit which has.

  By using a capacitive coupling circuit in which a plurality of input capacitors are coupled in common and an input signal is given to each, when a voltage corresponding to logic 1 is applied to a predetermined number of the plurality of inputs, A potential exceeding the inverter threshold can be generated. For example, when the threshold value is set to half of the power supply voltage, the logic circuit becomes a majority circuit.

  In addition, a NAND circuit, an AND circuit, a NOR circuit, and an OR circuit can be generated by applying a fixed potential to a part of the input terminal connected to the input capacitor.

  Furthermore, by developing this logic circuit, logic circuits such as flip-flop circuits and full adders can be configured with a small number of transistors.

As another feature of the present invention, an analog / digital conversion circuit can be configured with an extremely small number of transistors by using a capacitive coupling circuit. An example of the analog-to-digital conversion circuit includes an input terminal to which an analog input is applied and an N (N is a plurality) bit output terminal to which a binary output is applied. N unit circuits each having an input capacitor connected to the input terminal, a first inverter to which the other electrode of the input capacitor is input, and a second inverter connected to the first inverter Provided in parallel, the output of the second inverter of the unit circuit is provided to each of the output terminals, and the inverted output of the output corresponding to each unit circuit is the second of the unit circuit corresponding to the lower bit. The feedback capacitance is fed back to the input of one inverter through the feedback capacitance, and the capacitance value of the feedback capacitance corresponding to the inverted output of the Mth unit circuit (M is an integer) from the most significant bit is fed back. Characterized in that it is a 1/2 ^M times the input capacitance of the unit circuits.

  By applying the inverted signal of the digital output of the upper bit to the inverter input of the lower bit via the feedback capacitor, the comparison potential of the lower bit can be generated by each capacitive coupling circuit. This circuit can be constituted by a CMOS circuit with an extremely small number of transistors, which has not been conventionally available.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.

[Capacitance network]
FIG. 1 is a circuit diagram of a capacitive network illustrating the principle of the present invention. In this example, the voltages V1, V2, and V3 are applied to one electrode of each of the three capacitors C1, C2, and C3, and the other electrode is connected in common. In this case, the voltage value Vx of the common electrode is
Vx = (C1 · V1 + C2 · V2 + C3 · V3) / (C1 + C2 + C3)
It is.

  In this manner, when a capacitance network including a plurality of capacitors is configured, a unique voltage value Vx according to the capacitance ratio can be obtained for the plurality of input voltages V1, V2, and V3.

[CMOS logic circuit using capacitive network]
FIG. 2 is a three-terminal input majority circuit diagram using the above-described capacitance network in the input stage. FIG. 2A shows the circuit, and FIG. 2B shows the truth table. In this majority decision circuit, three inputs A, B, and C are supplied to two-stage CMOS inverters 13 and 14 through substantially equal capacitors 10, 11, and 12, respectively. The CMOS inverters 13 and 14 equalize the β values of the P-channel transistor and the N-channel transistor and equalize the threshold values of both, thereby setting the threshold value Vt at which the output is inverted to half of the power supply Vdd (Vdd / 2 ).

  It is assumed that two voltages of 0 and Vdd are applied to the input terminal in common with the following logic circuits. Therefore, it is assumed that logic 0 is input when the input is 0 voltage (L level) and logic 1 is input when the power supply is Vdd (H level).

  As described with reference to FIG. 1, the common terminal 15 of the capacitive coupling network takes values of 0, Vdd / 3, 2Vdd / 3, and Vdd depending on the number of input logic 1s. Therefore, when the value of the common terminal 15 is 0 and Vdd / 3, the output Z is logic 0 (L level), and when the value of the terminal 15 is 2Vdd / 3 and Vdd, the inverter is inverted and the output Z is logic 1 (H level).

  With such a configuration, as shown in the truth table of FIG. 2B, when two or more inputs become H level (logic 1), the output Z becomes H level (logic 1). When the input A is logic 0, the output Z is an AND output of the inputs B and C. When the input A is logic 1, the output Z is an OR output of the inputs B and C. In this way, a majority circuit can be configured with only three capacitors and a two-stage CMOS inverter.

  FIG. 3 is a weighting majority circuit diagram of a four-terminal input. FIG. 3A shows the circuit, and FIG. 3B shows the truth table. This circuit is also provided with a capacitive coupling circuit in the input stage. The input A is connected to the two-stage CMOS inverters 26 and 27 via two capacitors 21 and 22 and the other inputs B, C and D are connected to one stage of capacitors 23, 24 and 25. Therefore, twice the weight of the other input is added to the input A. These capacities have almost the same capacity value.

  Also in this case, as in FIG. 2, the common terminal 28 takes voltages of 0, Vdd / 5, 2Vdd / 5, 3Vdd / 5, 4Vdd / 5, and Vdd depending on the number of input logic 1s. Therefore, when the input A is 1, if any other input becomes 1, the inverter is inverted and the output Z becomes 1. When the input A is 0, the inverter is inverted in the same manner as any other 3 inputs become 1.

  As shown in FIG. 2 and FIG. 3 described above, when all the capacitors provided in the input stage have the same capacitance, an odd number of capacitors can be provided, so that an inverter having a threshold value of Vdd / 2 can be clearly inverted.

  FIG. 4 is a 2-input NAND / AND circuit diagram. FIG. 4A shows the circuit, and FIG. 4B shows the truth table. In this circuit, two inputs A and B are connected to two-stage CMOS inverters 34 and 35 via equal capacitors 31 and 32. A capacitor 33 having one end connected to the ground is also connected to the common terminal 36. Further, the threshold value of the CMOS inverter is set to Vdd / 2, for example.

  This circuit is equivalent to a circuit in which one input of the three-terminal majority circuit shown in FIG. Therefore, only when both of the two inputs are 1, the terminal 36 becomes 2Vdd / 3, and the inverter is inverted. As a result, the output Z1 of the inverter 34 becomes NAND logic, and the output Z of the inverter 35 becomes AND logic.

  FIG. 5 is a 4-input NAND / AND circuit diagram. In this circuit, seven approximately equal capacitors are connected to the two-stage CMOS inverters 39 and 40. Then, the inputs of the three capacitors among them are grounded. Therefore, as in the circuit of FIG. 4, when all four inputs A to D are 1, the AND output Z is 1 and the NAND output Z1 is 0.

  While the conventional 4-input NAND circuit requires 4 pairs of CMOS transistors and requires a total of 8 (2 × 4) transistors, this circuit example has 7 capacitors and 2 capacitors. A transistor can be used. In this circuit, it is necessary that the inverter 39 has a sharp threshold characteristic that can distinguish between 3 Vdd / 7 and 4 Vdd / 7.

  As is apparent from this circuit example, when a 3-input NAND / AND circuit diagram is formed, two of the five capacitors may be connected to the ground. For N inputs, N-1 of 2N-1 capacitors are connected to ground. In that case, the capacity of the N-1 child can be configured by a capacity whose single capacity value is N-1 times.

  FIG. 6 is a 2-input NOR / OR circuit diagram. FIG. 6A shows the circuit, and FIG. 6B shows the truth table. This circuit is an example in which one input is connected to the power supply Vdd in the three-input majority circuit shown in FIG. Also in this example, the three capacitors have the same capacitance value. Therefore, when one of the two inputs A and B is 1, the value of the common terminal 41 is 2Vdd / 3, and the inverter 42 whose threshold is Vdd / 2 is inverted. That is, when any of the inputs becomes 1, the output Z1 that is the output of the inverter 42 becomes 0. Therefore, the output Z1 is a NOR output, and the output Z is an OR output.

  FIG. 7 is a 3-input NOR / OR circuit diagram. As in FIG. 6, two of the five capacitors are connected to the power supply Vdd. As a result, when at least one of the three inputs becomes 1, the common terminal 44 becomes 3Vdd / 5 and the inverter 45 is inverted. Therefore, the output Z1 is a NOR output, and the output Z is an OR output. In general, in order to construct an N-input NOR / OR circuit diagram, it is only necessary to connect N−1 of the 2 stages of CMOS inverters and 2N−1 capacitors to the power supply Vdd. Similarly, the N−1 capacitors may be constituted by a single capacitor having a capacitance value N−1 times.

  Whereas a conventional three-input NOR circuit requires six (2 × 3) transistors, the embodiment of the present invention can be configured with five capacitors and two transistors. The number can be reduced.

  FIG. 8 is an SR flip-flop circuit diagram. FIG. 8A shows the circuit, and FIG. 8B shows the truth table. The two-input NOR circuit shown in FIG. 6A is arranged in parallel, and each output is connected to the input capacitance of the other NOR circuit and fed back. The set input S is connected to the capacitor 48, the capacitor 49 is connected to the power supply Vdd, and the capacitor 50 is connected to the other output Q. The reset input R is connected to the capacitor 52, the capacitor 53 is connected to the other output / Q, and the capacitor 54 is connected to the power supply Vdd.

  FIG. 8B shows a diagram of the truth table. When the set input S becomes 1, the output Q is set to 1. Further, when the reset input R becomes 1, the output Q is reset to 0. However, in this circuit, unlike the normal SR flip-flop circuit, when both the set input S and the reset input R are 1, both the outputs Q and / Q are forced to 0 by the capacitive coupling circuit without being indefinite. . However, both the R and S inputs normally do not become 1, and there is no problem in terms of function. Since the NOR circuit itself can be configured with a small number of transistors, an RS flip-flop circuit using the NOR circuit can also be configured with a small number of transistors.

  FIG. 9 is an arbiter circuit diagram. FIG. 9A shows the circuit, and FIG. 9B shows the timing chart. In the circuit shown in FIG. 9A, the two-input NAND circuit of FIG. 4A is arranged in parallel, and the respective outputs are connected to the input capacitance of the other NAND circuit and fed back. A request input RQ1 is connected to the capacitor 57, the other output AC2 is connected to the capacitor 58, and a ground potential is connected to the capacitor 59. Similarly, the capacitors 61, 62, and 63 on the inverter 64 side are also connected.

  A timing chart of this circuit is shown in FIG. That is, as the arbiter circuit, the outputs AC1 and AC2 to which the request inputs RQ1 and RQ2 are first input are acknowledged first, and the next request input is not acknowledged to the output until the request input returns to 0. As shown in FIG. 9 (B), both inputs RQ1 and RQ2 are 0 and both outputs AC1 and AC2 are stable at 1. Therefore, when the input RQ1 becomes 1, the input of the inverter 60 becomes 2Vdd / 3 and is inverted, and the output AC1 becomes 0. After that, even when the other input RQ2 becomes 1, the operation of the input RQ1 is not completed, so the output AC2 is not inverted. When the input RQ1 becomes 0, the first operation is finished and the output AC2 is inverted.

  FIG. 10 is a circuit diagram of a tristate buffer. FIG. 10A shows the circuit, and FIG. 10B shows a truth table. In this circuit, a 2-input NAND circuit and a NOR circuit are arranged in parallel, and both outputs are connected to the gates of a P-channel transistor 74 and an N-channel transistor 75 which are output inverters. An input IN is connected to the capacitor 66 on the NAND circuit side, and an output enable signal / OE is connected to the capacitor 67. On the NOR circuit side, the input IN is connected to the capacitor 70 and the output enable signal OE is connected to the capacitor 71.

  According to this circuit configuration, when the output enable signal OE is 1, the input of the inverter 69 is L level and its output H level, and the transistor 74 is turned off. Further, the input of the inverter 73 is H level and the output thereof is L level, and the transistor is turned off. As a result, the output OUT is in a high impedance state. When the output enable signal OE is 0, the output OUT changes according to the state of the input IN, and the inverter circuit composed of the transistors 74 and 75 becomes a buffer circuit.

  FIG. 11 is a coincidence (EQ) circuit and an exclusive OR (EXOR) circuit diagram. FIG. 11A is a circuit diagram, and FIG. 11B is a truth table thereof. In this circuit, the output of the 2-input NAND circuit 77 is given to the input of the inverter 80 by two capacitors 78. A capacitor 79 having one electrode grounded is connected to the input of the inverter 80 (capacitor common connection electrode). As a result, when both the inputs A and B are 1, the output M of the NAND circuit 77 becomes 0 and the input of the inverter 80 becomes L level. When the inputs A and B are not both 1, the output M of the NAND circuit 77 becomes 1, canceling the capacitor 79, and the inverter 80 is inverted when one of the inputs A and B is 1. As a result, when one of the inputs A and B is 1, the output Z1 is 0 and the output Z is 1. When both the inputs A and B are 1 or 0, the output Z1 is 1 and output. Z becomes zero. That is, the output Z1 is a coincidence (EQ) circuit output, and the output Z is an exclusive OR (EXOR) circuit output.

  This circuit uses the output of the NAND circuit 77 whose output is different only when the inputs are 1 and 1 since the truth table of the EXOR circuit is equal to the OR circuit except when the inputs A and B are both 1. The idea is to invert the output of the OR circuit. When the input is other than 1, 1, the output M becomes 1, canceling the capacitor 79, and the inverters 80, 81 are NOR circuits and OR circuits.

  If the NAND circuit 77 is replaced with the NOR circuit 77b of FIG. 6 and the capacitor 79 is connected to the power supply Vdd side (79b), the output Z1 becomes an EXOR output and the output Z becomes a coincidence output. That is, the circuit shown in FIG.

  FIG. 12 is a Schmitt trigger circuit diagram. FIG. 12A is a circuit diagram, and FIG. 12B is an input / output characteristic diagram thereof. In this circuit, the capacitance 83 connected to the input IN has a capacitance value almost twice that of the capacitance 84 connected to the output OUT of the second-stage inverter 86. Accordingly, two capacitors 83 and 84 having different capacitance values are commonly connected, and an input IN is connected to one capacitor, and an output OUT generated via two inverters is connected to the other capacitor.

  If the input IN rises from 0v to the power supply Vdd, the output OUT is initially 0, so that the input VX of the inverter 85 becomes VX = 2VIN / 3 with respect to the voltage VIN of the input IN. Therefore, when the threshold value of the inverter 85 is Vdd / 2, VX = 2VIN / 3 = Vdd / 2, and when VIN = 3Vdd / 4, the inverter 85 is inverted. As a result, the input IN is 3Vdd / 4 to Vdd, and the output OUT is inverted to 1.

  On the other hand, when the input IN drops from Vdd to 0v, the first output OUT is Vdd, so the input VX of the inverter 85 becomes VX = (2VIN + Vdd) / 3 with respect to the voltage VIN of the input IN. Therefore, since the threshold value of the inverter 85 is Vdd / 2, the inverter 85 is inverted when VIN = Vdd / 4 from VX = (2VIN + Vdd) / 3 = Vdd / 2. As a result, the input IN is 0 to Vdd / 4 and the output OUT is inverted to 0.

  Thus, the circuit of FIG. 12 operates as a Schmitt trigger circuit having a dead band of Vdd / 4 to 3Vdd / 4. If the capacity 83 is made larger, the width of the dead zone becomes narrower, and if the capacity 83 is made smaller and approaches the value of the capacity 84, the width of the dead zone becomes wider.

  If the output of the inverter 85 is fed back via the capacitor 84, it has a reverse hysteresis characteristic that it is inverted at a low voltage when the input IN rises and is inverted at a high voltage when it falls.

  FIG. 13 is a clocked RS flip-flop circuit diagram. FIG. 13A is a specific circuit diagram thereof, and FIG. 13B is a block diagram thereof. This circuit diagram is based on the RS flip-flop circuit shown in FIG. 8, and the other output is fed back with capacitors 90 and 95 having capacitance values almost twice as large as the capacitors 88 and 93 on the input side. CP is input with the capacitors 89 and 94 having the same capacitance value as the input capacitors 88 and 93. The set input S is connected via a capacitor 88 and the reset input is connected via a capacitor 93. Capacitors 91 and 96 are both connected to the power supply Vdd. Needless to say, each of the capacitors 90 and 95 may be composed of a single capacitive element.

  In this circuit, when the clock CP is 0, if the output Q is 1, the capacitors 91 and 90 are connected to 1 on the inverter 92 side, so that the input becomes an H level higher than Vdd / 2, and the output / Q becomes 0. Fixed. Further, since the capacitors 95 and 94 are connected to 0 by 0 of the output / Q, the output Q is fixed to 1. When the output Q is 0, the output / Q is fixed to 1 on the contrary. In this fixed state, the output value is fixed regardless of the values of the set input S and the reset input R.

  Therefore, when the clock CP becomes 1, if the output Q is 1, the input of the inverter 92 becomes H level and the output / Q is fixed to 0. Further, the capacitor 95 and the capacitors 94 and 96 are canceled by the output of 0 / Q, and the input of the inverter 97 is L level and the output Q is fixed to 1 by the reset input R of 0. Or it is fixed on the contrary.

  When Q = 1 and / Q = 0, when the reset input R becomes 1, the input of the inverter 97 becomes H level, the output Q is inverted to 0, and the capacitors 90, 91 and 89 are inverted by the inversion of the output Q to 0. And the input of the inverter becomes L level by 0 of the set input R, and the output / Q is also inverted to 1. Conversely, when Q = 0 and / Q = 1, when the set input S becomes 1, the input of the inverter 92 becomes H level and is inverted to invert the output / Q to 0. Since 0 is given to the capacitors 95 and 93, the input of the inverter 97 becomes L level and is inverted and the output Q is set to 1.

  That is, it is possible to realize a clocked RS flip-flop circuit in which the state does not change when the clock CP = 0 and the output Q is set and reset according to the set input S and the reset input R when the clock CP = 1.

  FIG. 14 is a master-slave RS flip-flop circuit diagram. In this circuit example, two stages of the clocked RS flip-flop circuits 98 and 99 of FIG. 13 are provided, the clock signal CP is supplied to the first stage circuit 98, and the same signal CP is supplied to the second stage circuit via the inverter 100. 99. As a result, when the clock CP is 1, the slave circuit 98 is set and reset by the S input and the R input, and the state of the slave circuit 98 is transmitted to the master circuit 99 by inversion of the next clock CP to 0. In this state, the slave circuit 98 is not inverted by the R and S inputs.

  FIG. 15 is a JK flip-flop circuit diagram. In this circuit diagram, the OR circuits 103 and 104 shown in FIG. 6 are provided at the input stage of the master-slave RS flip-flop circuit 102 of FIG. Cross and return. Thus, when both the J and K inputs are 0, if the output Q is 0 and / Q is 1, then S = 0 and R = 1, and the outputs Q and / Q change even with one cycle of the clock CP. do not do. If J = 0 and K = 1, the output of the OR circuit 104 is 1, R = 1, and the output Q is forcibly set to 0 by one cycle of the clock CP. If J = 1 and K = 0, the output of the OR circuit 103 is 1 and S = 1, and the output Q is forcibly set to 1 by one cycle of the clock CP. Further, when J = K = 1, the output Q is inverted to / Q of the previous state. These operations are the same as those of a conventional general JK flip-flop circuit.

  FIG. 16 is a D flip-flop circuit diagram. By inputting a non-inverted or inverted signal of the input D to the S input and R input of the master slave circuit 102, a D flip-flop circuit operation is performed in which the D input value is taken into the output Q by the clock CP = 1.

  FIG. 17 is a T flip-flop circuit diagram. The outputs Q and / Q of the master / slave circuit 102 are fed back to the S input and the R input, respectively. As a result, when the T input is 0, the previous output Q is taken into the output Q, and when the T input is 1, the previous output / Q is taken into the output Q. That is, the output is toggled by the T input.

  FIG. 18 is a full adder circuit diagram. FIG. 18A shows a circuit diagram, and FIG. 18B shows its truth table. First, when any two of the inputs A and B and the carry C from the lower digit are 1, the carry output (carry) Cn becomes 1. That is, a majority circuit. Therefore, the three capacitors 103 and the two inverters 104 and 105 have the same configuration as in FIG. It can be seen from the truth table that the sum output S is an EXOR output of the inputs B and C when the input A is 0, and a coincidence output of the inputs B and C when the input A is 1. Therefore, referring to the circuits of FIGS. 11A and 11C and the majority circuit of FIG. 2, a 3-input majority circuit is arranged in parallel, and one inverted output of the majority circuit is doubled to the other input. A full adder circuit can be realized by feedback with the capacitor 108. That is, when the input A = 0, the output S becomes the EXOR logic as in the circuit of FIG. When the input A = 1, the output S becomes the coincidence logic as in the circuit of FIG.

  In the example of the conventional general full adder, for example, 20 to 30 transistors are required. In this example, however, it is possible to configure with only 8 transistors and 8 capacitors.

  FIG. 19 is an output waveform diagram for confirming the operation of the full adder circuit of FIG. VL is an input level of the inverter 104, and VLL is an input level of the inverter 109. Inputs A, B, and C and outputs Cn and S represent logic 1 (power supply Vdd) and logic 0 (ground) levels, respectively. The operation of the truth table of FIG. 18B is confirmed from this waveform diagram.

  As described above, by using the capacitive coupling circuit in the input stage, various logic circuits, flip-flop circuits, and full adders can be configured by greatly reducing the number of transistors. Therefore, even if these are integrated with an image sensor, an integrated circuit capable of outputting a digital value while ensuring a sufficient sensor area can be realized.

[Flash AD converter]
FIG. 20 is a circuit diagram of a flash AD converter. In this circuit diagram, the analog input VIN is converted into a 3-bit digital output A2 A1 A0. In this circuit configuration, three one-input majority circuits are arranged in parallel, and the inverted output of the majority circuit that outputs the upper bits is weighted by 1/2 and fed back to the lower bit input.

  That is, the input VIN is connected to the inverter 103 via the capacitor 102 for the most significant bit A2. Therefore, when the input VIN> Vdd / 2, the inverter 103 is inverted and the most significant bit A2 is inverted to 1.

Next, for the second bit A1, the input VIN is connected to the inverter 107 via the capacitor 105 whose output is doubled, and the output of the inverter 103 is connected to the inverter 107 via the capacitor 106. That is, the output of the inverter 103 is fed back with a weight of 1/2. As a result, the input of the inverter 107 becomes (2VIN + / A2) / 3. Therefore,
(2VIN + / A2) / 3> Vdd / 2
Thus, the inverter 107 is inverted and the second bit A1 becomes 1. That is,
When A2 = 0, VIN> Vdd / 4 and A1 = 1 (Vdd)
When A2 = 1 (Vdd), VIN> 3Vdd / 4 and A1 = 1 (Vdd)
It becomes.

Further, for the third bit A0, the input VIN is passed through the capacitor 109, the output of the inverter 103 is passed through the capacitor 110, and the output of the inverter 107 is passed through the capacitor 111. 112. That is, the output of the inverter 103 is fed back with a weight of 1/2, and the output of the inverter 106 is fed back with a weight of 1/4. As a result, the input of the inverter 112 becomes (4VIN + 2 / A2 + / A1) / 7. Therefore,
(4VIN + 2 / A2 + / A1) / 7> Vdd / 2
Thus, the inverter 112 is inverted and the third bit A0 becomes 1. That is,
When A2 = 0 and A1 = 0, VIN> Vdd / 8 and A0 = 1
When A2 = 0 and A1 = 1 (Vdd), VIN> 3Vdd / 8 and A0 = 1
When A2 = 1 (Vdd) and A1 = 0, VIN> 5Vdd / 8 and A0 = 1
When A2 = A1 = 1 (Vdd), VIN> 7Vdd / 8 and A0 = 1
It becomes.

  FIG. 21 is a waveform diagram showing the operation of FIG. This waveform diagram shows changes in each node and output bits A2, A1, and A0 when the input VIN changes linearly from 0v to the power supply Vdd. In this example, the input VIN changes twice. As can be understood from this waveform diagram, the inverter 103 inverts with high sensitivity, but the inverter 112 corresponding to the lower bit A0 must detect a slight change in the input V3. Accordingly, the circuit of FIG. 20 can theoretically obtain a more accurate digital output, but it is difficult to guarantee the accuracy of the lower bits due to the inversion sensitivity at the threshold of the inverter.

  Note that the capacitor 102 in FIG. 20 may be omitted. Further, when the capacitors 102, 105, and 109 are configured with substantially the same capacitance value, the capacitors 106 and 110 may have a capacitance value that is ½ that of them, and the capacitor 111 may have a capacitance value that is ¼ that of them. is necessary. That is, for each of the inverters 107 and 112, the inverted output of the output A2 is given with a weight of 1/2, and the inverted output of the output A1 is given with a weight of 1/4.

  As shown in the example of FIG. 20, an AD conversion circuit can be configured with only 12 transistors in a 3-bit AD converter. That is, in the case of N-bit output, an AD converter can be configured with 4N transistors. This number is a very small number of transistors compared to a conventional general AD converter circuit.

  FIG. 22 is an AD conversion circuit diagram for generating a 4-bit digital output and the least significant remainder. This circuit extends the 3-bit AD conversion circuit shown in FIG. 20 to 4 bits, amplifies the voltage V0 corresponding to the remainder of the least significant bit by 31 times with the output buffer amplifier 142, and further lower-order AD conversion. An analog output Vout is generated. Reference numerals 120 to 123 are comparison circuits composed of CMOS inverters, and reference numerals 124 to 127 are CMOS inverters similarly, which are the same as those in FIG. These capacitive coupling networks in the preceding stage are given to the lower bit inverters 121, 122, 123 by weighting the inverted outputs of the respective bits by ½n, as in FIG. In FIG. 22, for the sake of simplicity, the ratio of each capacity is set to C, 2C,. . Shown as 16C.

  In this circuit, in order to simplify the circuit configuration and operation description, the power supply of the inverter is set to + Vds (logic 1) and −Vds (logic 0), and the reference voltage (threshold voltage) is set to 0, unlike the above. Therefore, the full scale is 2 Vds.

Now, the input voltages to the inverters 120 to 123 of each comparator are V4, V3, V2, and V1, and the analog voltage V0 to the lower order of the least significant bit A0 is ignored if the parasitic capacitance is ignored.
V0 = (16 Vin + 8 / A3 + 4 / A2 + 2 / A1 + / A0) / 31
It becomes. A3 to A0 take a value of either + Vds or -Vds. The notation / A is an inverted signal of A. In general, the analog input value Vin for N-bit output is
Vin = An-1 / 2 + An-2 / 2 ² +... + A1 / 2 ^n-1 + A0 / 2 ⁿ
It is.

Therefore, if the upper and lower limits that V0 can take are considered, for example, if Vin = 1 (+ Vds), then A3 A2 A1 A0 = 1111, and / A3 / A2 / A1 / A0 = 0000. A3-/ A0 are all 0 (-Vds),
V0 = (16Vds−15Vds) / 31 = Vds / 31. If Vin = 0 (-Vds), A3 A2 A1 A0 = 0000 and / A3 / A2 / A1 / A0 = 1111, so / A3 to / A0 are all 1 (+ Vds).
V0 = (− 16Vds + 15Vds) / 31 = −Vds / 31. That is, the range of V0 is + Vds / 31 to -Vds / 31.

When this is generalized, V0 = (An-4 / 2 + An-5 / 4 +... + A1 / ^2n-5 + A0 / ^2n-4 ) / ( ^{2n +} 1-1).

Therefore, it is understood that when this voltage V0 is multiplied by 31 (generally (2 ^{n + 1} −1)), V0 becomes an analog value of −Vds to + Vds and can be used as an input Vin for lower bits. The In the case of the general formula of V0, the general formula of Vin is obtained by multiplying by (2 ^{n + 1} −1).

  Therefore, in the present embodiment of FIG. 22, a 31-times amplifier 142 is provided, and the amplified output Vout is used as an input of a lower AD converter.

  23 divides the input Vin of FIG. 22 into −Vds to + Vds into seven equal parts, and outputs A3 to A0 and their inverted values, Vout, and each node V4 to eight values of 0/7 to 7/7. It is a wave form diagram which shows V1. As is apparent from this figure, the analog input value Vout to the lower bits is −Vds at 0/7 = (0000) in the figure, and is logical 0, but rises to close to + Vds at 3/7 = (0110). Further, when 7/7 = (1111), the maximum value increases to + Vds (logic 1).

  FIG. 24 is a 12-bit flash AD converter circuit diagram. In this circuit, the 4-bit AD conversion circuit shown in FIG. 22 is used as one unit ADCU, and the lower input Vout of the unit is used as an analog input of the lower unit ADCU. The feature of this multi-bit AD conversion circuit is that the 4-bit AD conversion circuit is made into one unit, so that the total number of capacitors can be constituted by three times the number of capacitors in the unit. If the circuit of FIG. 22 is simply expanded, the number of capacitors in the capacitive coupling network becomes very large, and it can be avoided that the original purpose of reducing the number of elements cannot be achieved. Further, the second feature point is that a multi-bit AD conversion circuit can be configured without increasing the sensitivity of the inverters 120 to 123 as comparators. If the circuit of FIG. 22 is simply expanded, the inversion sensitivity at the threshold value of the inverter which is a lower comparator is required to be very sharp. However, as in this example, the remainder of each unit is multiplied by 31 and used as the analog input of the next unit, so that the inverter sensitivity in each unit is not required to be so high.

  25, 26, and 27 show waveform diagrams of the 12-bit AD converter circuit of FIG. Similarly to FIG. 23, this waveform diagram also divides -Vds to + Vds into seven equal parts, and shows changes in voltages at the respective outputs and nodes for eight values of 0/7 to 7/7. Vout1 obtained by multiplying the remainder of the most significant 4 bits D11D10D9 D8 by 31 is used as an analog input of the lower bits D7 D6 D5 D4. Further, the remainder Vout2 is used as an analog input of the lower bits D3 D2 D1 D0.

  FIG. 28 shows a 12-bit AD conversion circuit with a rounding function and overflow. In the 12-bit AD conversion circuit shown in FIG. 24, all the digital outputs D11 to D0 are set to 1 with respect to the full scale input. However, in the actual 12-bit AD conversion, if the full scale is 4096, the input values 0 to 4095 correspond to (000000000000) to (111111111111), and the full scale input value 4096 overflows to (1000000000000). Therefore, in the circuit diagram of FIG. 28, the analog output of the least significant bit A0 is rounded (rounded off) so that the overflow is correctly output, and the full adder FA is set to each bit so that the overflow bit OF can be output. to add. The full adder FA has addition inputs A and B, a carry input C, an addition output S, and a carry output CC. The bit of each digital output is input to the addition input A, the addition input B is fixed to 0, and the carry output CC of the lower full adder is connected to the carry input. The analog output of the least significant bit is the remainder of the 12-bit AD converter circuit, and the remainder is rounded off by the comparator 144 and given to the carry input C.

  If the full-scale analog input Vin is given and the digital output is (111111111111), the lowest analog output exceeds the threshold value of the comparator 144, and the input A of the lowest full adder FA is input. 1 and 1 are input to 1 and C, the carry output CC becomes 1 and the addition output S (D0) becomes 0. Similarly, the upper full adder FA has a carry output of 1 and an addition output of 0. As a result, the overflow bit OF is 1 and all remaining digital outputs are 0.

  As the full adder FA used here, the capacitively coupled logic circuit shown in FIG. 18 is used.

  In the AD converter circuits of FIGS. 22, 24, and 28 described above, the gain of the amplifier circuit that amplifies the remainder of the least significant bit greatly affects the precision of the lower bit. That is, the analog value amplified according to the gain of the amplifier circuit 142 becomes the low-order bit analog input. Therefore, if it cannot be amplified with high accuracy, an incorrect analog value is converted. In general, when a monolithic IC is manufactured, the gain of the amplifier circuit is easily affected by the process. Therefore, it is desirable to adopt a structure that is not easily affected by the process. In particular, when the number of bits of the digital output is increased, the accuracy of the gain is particularly required. In this case, for example, a configuration in which the feedback resistance of the voltage follower can be finely adjusted from the outside is one solution. It is.

  Furthermore, the accuracy of AD conversion depends on the characteristics of the inverters 120 to 123 which are comparators. Therefore, it is necessary to increase the power supply voltage accuracy of these inverters and to increase the threshold accuracy, the capacitance value accuracy on the input side, and the like. Further, the parasitic capacitance in the capacitive coupling circuit on the input side cannot be ignored. Therefore, for example, one solution is to form many capacitors of the same unit and perform trimming at the calibration stage.

  From the calculation results, it is important to reduce the transient response by aligning the time constants of the input units and feedback input units having different capacitance values. 23 and 25 show that the transient response occurs between the input values.

  FIG. 29 is a diagram illustrating another circuit example of the 3-bit AD conversion circuit. The same parts as those in the 3-bit AD converter circuit shown in FIG. 20 is different from the example in FIG. 20 in that inverters 150, 152, and 154 having Vdd / 2 + ΔV with a threshold value shifted from Vdd / 2 are provided at the subsequent stage of the inverters 103, 107, and 112. Further, the outputs of the inverters 150, 152, and 154 are used as digital outputs, and the inverted values are generated by the inverters 151, 153, and 155 having the threshold value Vdd / 2 and used as feedback values to the lower order. The capacitive coupling network of the input stage is the same as that in FIG.

  According to this circuit, when the full scale is Vdd (for example, 5 v), the threshold values of the first stage inverters 103, 107, and 112 are Vdd / 2 (2.5 v), and the next stage inverters 150, 152, and 154 are Vdd / It is 2 + ΔV (2.6 v), and further is the final stage inverter Vdd / 2 (2.5 v). Since the threshold value of the second-stage inverter is only required to deviate from Vdd / 2, it may be Vdd / 2−ΔV, for example.

  When the analog input Vin is just 1/2, 1/4, 3/8 or the like of full scale, both the P-channel transistor and the N-channel transistor are turned on by the input of the threshold value of the first-stage inverter. As a result, for example, the output becomes Vdd / 2. Therefore, in the circuit example of FIG. 20, the inverters 104, 108, and 113 similarly output Vdd / 2 according to the output Vdd / 2. Therefore, a normal binary digital output cannot be generated.

  FIG. 30 is a waveform diagram in the case of analog input Vin = Vdd / 8, 2Vdd / 8, 3Vdd / 8, 4Vdd / 8, 5Vdd / 8, 6Vdd / 8, 7Vdd / 8, 8Vdd / 8 in the circuit example of FIG. It is. As shown in the figure, an output of Vdd / 2 is generated for the analog input 4Vdd / 8 and becomes indefinite. As a result, the digital output is not fixed.

  In the circuit of FIG. 29, since the threshold value of the next-stage inverter is shifted, even if the first-stage inverters 103, 107, and 112 generate the Vdd / 2 outputs V11, V21, and V31 with respect to the above analog input, The inverter always produces a digital output of either 1 or 0. In the example of FIG. 29, since the threshold values of the inverters 150, 152, and 154 are shifted from Vdd / 2 + ΔV, the output is always 0. Therefore, the indefinite state as shown in FIGS. 20 and 30 can be avoided.

  FIG. 31 is a waveform diagram for explaining the operation of the circuit of FIG. When the analog input Vin is 4Vdd / 8, the output A2 is fixed to 0. In an actual AD converter circuit, there is little probability that the full scale is exactly 1/2, 1/4, etc., but the possibility of such a malfunction can be eliminated.

  FIG. 32 is a diagram of another example of an AD conversion circuit that generates a 4-bit digital output and a remainder. This circuit expands the AD conversion circuit shown in FIG. 29 to 4 bits, and further amplifies the remainder of the least significant bit to generate a lower-order analog input Vout. Further, in order to eliminate an error due to the parasitic capacitance 169, the amplification factor of the amplifier circuit 168 is slightly corrected.

  In this circuit, as in the case of FIG. 22, the power sources of the inverters 120 to 123, which are comparators, are set to + Vds and −Vds, and the reference voltage (threshold voltage) is set to 0v. Further, the logic 1 is + Vds and the logic 0 is −Vds. Therefore, the same parts as those in FIG. Unlike the case of FIG. 22, in the circuit example of FIG. 32, the threshold values of the next-stage inverters 160 to 163 are shifted from 0v by + ΔV. Further, the amplification factor of the amplifier circuit 168 is corrected to 31 + α. The capacitance value of the parasitic capacitance 169 is assumed to be α times the capacitance 141 (0 <α <1).

In FIG. 32, the method for obtaining the amplification factor is the same as in FIG. However, in FIG. 32, considering the presence of the parasitic capacitance 169 having the capacitance of αC, the remainder V0 is lower than that in the case of FIG. That is,
V0 = (16Vin + 8 / A3 + 4 / A2 + 2 / A1 + / A0) / (31 + α)
It becomes. When the input Vin is 1 (+ Vds),
V0 = (16Vds-15Vds) / (31 + α) = + Vds / (31 + α)
And when the input Vin is 0 (−Vds),
V0 = (− 16Vds + 15Vds) / (31 + α) = − Vds / (31 + α)
It is. Therefore, V0 is in the range of −Vds / (31 + α) to + Vds / (31 + α). Therefore, by multiplying by 31 + α by the amplifier circuit 168, the lower analog input Vout becomes −Vds to + Vds. Generally, it is (2 ^{n + 1} -1 + α) times.

  FIG. 33 is a waveform diagram when 0/7 to 7/7 are input to the circuit diagram of FIG. This is equivalent to the waveform diagram of FIG. 23 for the circuit of FIG. However, although it is not clear from the figure, the lower-order analog value Vout in the case of FIG. 33 has higher accuracy.

  FIG. 34 is a diagram showing an example in which the 4-bit AD converter circuit unit ADCU of FIG. 32 is serially connected for three units to form a 12-bit AD converter circuit. The circuit configuration itself is the same as that of FIG. 24. However, in the example of FIG. 34, the analog inputs Vout1, Vout2, and Vout3 to the lower level of each unit ADCU are amplified with the amplification factor that corrects the parasitic capacitance, and thus more accurate. Becomes a high value.

  35, 36, and 37 are waveform diagrams when 0/8 to 8/8 is applied to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of -Vds to + Vds. In this circuit, since there are three inverters and the threshold value of the second inverter is shifted from 0, it is possible to avoid indefiniteness. Therefore, all the analog inputs Vout1 to Vout1 to the lower order of each 4-bit AD conversion unit are −Vds except when 8/8, and + Vds when 8/8.

  FIGS. 38, 39 and 40 are waveform diagrams when 0/7 to 7/7 and 0/7 are applied to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. What is characteristic in this waveform diagram is that the analog value Vout3 obtained by amplifying the remainder of the least significant bit is Vout3 = for the input of 0/7 as shown by X10 and X20 in the figure in the example of FIG. For the input of −Vds, 7/7, Vout3 = + Vds is generated with high accuracy. On the other hand, in the case of the circuit of FIG. 24, since there is no correction of the parasitic capacitance, accurate Vout3 is not generated as indicated by X1 and X2 in FIG.

  FIG. 41 is a circuit diagram in which a rounding function and an overflow bit OF are added to the 12-bit AD conversion circuit of FIG. This corresponds to FIG. In the example of FIG. 41, each 4-bit AD conversion unit is added with an inverter for preventing uncertainties, the remainder is amplified by an amplification factor considering parasitic capacitance, and is used as a lower analog input, and further rounded. With function and overflow bit. The meaning of having a rounding function and an overflow bit is the same as that described in FIG.

  In FIG. 41, the overflow bit OF becomes 1 for the full-scale analog input, and the remaining 12-bit digital output becomes (000000000000).

[Serial AD converter circuit]
FIG. 42 is a diagram illustrating an example of a serial AD conversion circuit. In this circuit, a sample-and-hold circuit is provided in the preceding stage of the 4-bit AD conversion unit described with reference to FIGS. 22 and 32 to perform 4 × N-bit AD conversion serially. The 4-bit AD conversion unit generates a 4-bit digital output at a time. The lower-order analog input Vout generated as a result is sampled and held by the sample-and-hold circuit, and the next lower-order 4-bit AD conversion is performed.

  The sample hold circuit includes a switch 170, a capacitor CS1, a gain 1 operation amplifier 171, a switch 172, a capacitor CS2, and a gain 1 operation amplifier 173. Further, a switch 174 for holding the analog output Vout to the lower order is provided.

  A case where a 12-bit digital output is obtained using this serial type AD converter will be described. FIG. 43 is an operation timing chart thereof. First, the switch 170 is opened by the pulse of the signal SW1, and the analog input AVin is sampled and held in the capacitor CS1. Then, the switch 172 is turned on by the pulse of the signal SW2, and the analog voltage is held in the capacitor CS2. The voltage value is given as an analog input Vin of the 4-bit AD conversion unit via an operational amplifier 173 having a gain of 1. First, D11D10D9D8 is generated from the upper 4 bits of output.

  Next, the lower analog input Vout obtained by amplifying the remainder turns on the switch 174 by the signal SW3, and the analog input Vout is sampled and held in the capacitor CS1. Thereafter, in the same manner as described above, the pulse signals SW2 and SW3 are alternately added to generate the lower 4-bit digital outputs D7 D6 D5 D4. Further, the analog value Vout obtained by amplifying the remainder is held in the capacitor CS1, and its lower digital output D3 D2 D1 D0 is generated. In this manner, the 12-bit digital output is digitally converted by three sample and hold operations.

  In this circuit configuration, 12 bits are not generated at a time, but 12-bit AD conversion can be performed with a small number of elements. Further, by theoretically increasing the number of sample and hold operations, it can be converted into a multi-bit digital value.

  The operation amplifier is a normal amplifier and a voltage follower circuit. FIG. 44 is a diagram showing a general circuit configuration thereof. This circuit is an all-amplification type operational amplifier. Transistors 175 and 176 are input transistors whose sources are connected to a current source in common, and the respective current values are supplied to the circuit of the output stage. Transistors 178, 179 and 180, 181 are impedance circuits to which constant voltages VB1, VB2 are connected, respectively. As for the operation of this circuit, when the input V + becomes higher, the current becomes smaller, the current on the transistor 176 side becomes larger, and the output Vout (+) side becomes higher. The gain is adjusted to 1.

  FIG. 45 is a diagram of a 1-bit serial AD conversion circuit. This circuit is composed of the sample-and-hold circuit of FIG. 42, a circuit for one bit in the 4-bit AD conversion unit, and a remaining amplifier circuit. 170 is a switch for sampling and holding the analog input AVin, 172 and 174 are alternately turned on to transmit the voltage n1 held in the capacitor CS1 to the capacitor Cs2, and the voltage n7 obtained by amplifying the remainder after AD conversion is sampled in the capacitor Cs1. Hold. Reference numerals 171 and 173 denote operation amplifiers having a gain of 1. These circuits are similar to those in FIG. 42 and operate in the same manner (see FIG. 43).

  A broken line portion in the figure is a 1-bit AD conversion circuit. The output n4 of the comparator 185 is a digital output after AD conversion. This comparator 185 is composed of, for example, a CMOS inverter having a threshold value of Vdd / 2 and a CMOS inverter having a threshold value deviated therefrom, as shown in FIG. Is done. Further, the signal n5 generated via the inverter 186 is coupled to the capacitor 187 to which the input signal n3 is connected via the feedback capacitor 188. The feedback capacitor 188 has a capacitance value that is 1/2 that of the input capacitor 187. The subtracted signal n6 is amplified by an amplifier 189 having a gain (3 + α) obtained by correcting the parasitic capacitance, and the signal n7 is sampled and held in the capacitor Cs1 via the switch 174 for further AD conversion. .

  That is, the analog input AVin is sequentially stored and held in the capacitors Cs 1 and Cs 2 and is supplied to the comparator 185. The output n4 of the comparator 185 first outputs the most significant bit (MSB), and the inverted signal n5 is fed back to the input of the amplifier 189 via the 1/2 capacitor 188. As a result, an analog signal n7 corresponding to the lower bits obtained by subtracting the analog amount corresponding to the MSB from the analog input n3 is output. This signal n7 is sampled and stored in the capacitor Cs1 by the conduction of the switch 174. Then, the lower analog input n3 signal is input by the conduction of the switch 172. Thereafter, similarly, the lower bit output is sequentially output from n4 by switching of the switches 172 and 173.

  The waveform diagram of this circuit is shown in FIGS. FIG. 46 shows an 8-bit digital output when the analog input AVin is 1/7 of the full scale and an 8-bit digital output when the analog input AVin is 3/7 of the full scale. When the pulse signals SW2 and SW3 for conducting the switch are repeatedly turned on and off seven times, an 8-bit output n4 is generated. Since 8 bits is 2 @ 8 = 256, 1/7 of full scale is 256/7 = 36.5, and the 8-bit output is (00100100). For 3/7, the 8-bit output is (01101101).

  FIG. 47 shows a 9-bit output when the analog value = 0, a 9-bit output when the full scale is 2/5, and a 9-bit output when the full scale is 4/5.

  This circuit can be constituted by only a 1-bit AD conversion circuit, a surplus amplification circuit for lower-order AD conversion, and a sample hold circuit. Although it is a very simple circuit, it has the function of a multi-bit AD conversion circuit. However, since the digital output is generated bit by bit by the on / off operation of the switches 172 and 174, it is not a flash type but a serial type.

  The logic circuit and AD conversion circuit in which the number of transistors is reduced using the capacitive coupling circuit has been described above. When AD conversion is performed, a DA conversion circuit is always required. Therefore, a DA conversion circuit that also uses a capacitive coupling circuit will be described below.

[DA conversion circuit using capacitive coupling]
FIG. 48 is a diagram illustrating an example of a serial DA conversion circuit. This DA conversion circuit performs DA conversion of a digital value serially in 4-bit units from the upper bits. The analog output Out of the 4-bit digital-analog conversion circuit DAC is serially added by the adder circuit 221, and the final accumulated analog value is held by the sample hold circuit 223. The 1/16 circuit 220 is a circuit that converts the digital-to-analog converted value of the lower bits to 1/16 of the analog value. A delay circuit 222 delays the analog value of the upper bit by one cycle of the switch signals SW11 and SW12 and supplies it to the adder circuit 221.

  FIG. 49 is a waveform diagram of the serial type DA converter circuit of FIG. In this waveform diagram example, 8-bit digital signals A0 to A7 are converted into an analog signal Aout. First, the upper 4 bits A4 to A7 are first supplied as an input to the digital-analog converter circuit DAC. First, pulse signals SW11 and SW12 are simultaneously applied to the switches 200 and 201, and the analog output voltage Out is held by the capacitors 202 and 203. This capacity 203 has a capacity value 15 times that of the capacity 202. This operation will be described later.

  The analog value n12 held in the capacitor 203 is supplied to the capacitor CD by a gain 1 operation amplifier or a voltage follower. At this stage, since the output of the delay circuit 222 is 0V, the node n13 becomes a voltage about half the analog value n12 due to the capacitive coupling of the two capacitors CD. A capacitor 208 represents a parasitic capacitance, and has a capacitance that is α times (α << 1) the capacitance CD. Then, the amplifier 206 generates a voltage value n14 multiplied by (2 + α).

  Therefore, when the pulse signal SW13 is applied, the voltage value n14 is held in the capacitor Cs4 via the switch 211. Thus, the voltage obtained by analog conversion of the first digital value of the upper 4 bits is held in the capacitor Cs4. By this pulse signal SW13, the capacitor 203 is discharged and reset.

  Next, the lower 4 bits A0 to A3 are given to the digital input, and the pulse signal SW11 is supplied. As a result, the converted analog output Out is held in the capacitor 202. Then, the voltage n11 becomes a voltage n12 that is reduced to 1/16 by the capacitive coupling circuit of the capacitor C, the switch 201, and the capacitor 203 at the timing of the next pulse signal SW12. The voltage n12 is supplied to the capacitor CD through the amplifier 205 having a gain of 1.

  At this time, in the delay circuit 222, the higher-order 4-bit analog value n14 is given to the other capacitor CD through the amplifiers 212 and 215 of gain 1 by the pulse signal SW12. Then, the upper 4-bit analog value and the lower 4-bit analog value multiplied by 1/16 are added by the capacitive coupling circuit CD, and the added value is amplified to n14 and output. Then, with the supply of the pulse signal SW14, the added voltage is held in the capacitor Cs3. That is, the 8-bit analog conversion value is the voltage n15. The voltage value is output as an analog output Aout by the amplifier 210.

  As described above, the circuit of FIG. 38 performs analog conversion by the analog-digital converter DAC in units of 4-bit digital values, and adds the analog values obtained by converting the lower 4 bits serially by 1/16 times. When converting a 12-bit digital value, the analog conversion value of the lowest 4-bit digital value is multiplied by 1/256 by two on / off operations of the switches 200, 201 and 204, and then added by an adder circuit. It is added to the upper 8-bit analog value. Accordingly, the pulse signals SW12 and 13 in the delay circuit 222 are turned on and off twice.

  According to this circuit configuration, the digital-to-analog conversion circuit portion that requires many transistors need only include 4 bits. When converting a multi-bit digital value into an analog value, the digital value is converted serially by 4 bits. Then, the 1/16 circuit 220, the adder circuit 221 and the like for serial conversion are configured with a small number of transistors by using the coupling circuit having the capacitance already described. Therefore, a circuit that converts a multi-bit digital value into an analog value can be configured with a small number of transistor elements even in total.

  FIG. 50 is a diagram illustrating an example of a 1-bit serial digital-analog conversion circuit. This circuit converts the digital input Din into an analog value serially bit by bit from the upper bit and accumulates it, and finally outputs the accumulated analog value Aout.

  The ½ circuit 253, for example, doubles the reference value Vref of 5V by ½ every cycle by the switches 230, 231 and 232 controlled by the pulse signals SW21, 22 and 23. The voltage value n23 multiplied by 1/2 each time is held in the capacitor Cs8 by the data input sample hold circuit 254 according to the digital value Din 1 or 0. The adder circuit 255, the delay circuit 256, and the output sample hold circuit have functions equivalent to the corresponding circuits in the circuit of FIG. That is, the analog value based on the upper bit is delayed by one bit period by the delay circuit and output to the node n29, and the analog value n24 based on the next lower bit is added to the voltage n29 by the adding circuit 255. When the digital value Din of the digit being converted is 0 by the switch 234, the analog value n23 corresponding to the digit is not added, and when the digital value Din is 1, the analog value n23 corresponding to the digit is added. Is done.

  FIG. 51 is a waveform diagram of the 1-bit serial digital-analog conversion circuit. FIG. 52 is an enlarged waveform diagram of the signal n23 therein.

  The operation of the conversion circuit of FIG. 50 will be described with reference to FIGS. The example shown in the waveform diagram of FIG. 51 is an example in which a digital value Din indicating 0V, 2VREF / 5, and 4VREF / 5 is converted. That is, the 9-digit digital input value Din is (000000000) (011001100) (110011001). Therefore, the case where the input value is a digital value corresponding to 4VREF / 5 will be described.

  First, in the 1/2 circuit 253, the transistor 230 is turned on by the pulse signal SW21, and the reference voltage VREF of 5V is held in the capacitor Cs6. Then, by turning off the transistor 230 and turning on the transistor 231 by the pulse signal SW22, the reference voltage VREF is halved by the capacity division of the capacitors Cs6 and 7, and VREF / 2 is held at the node n22. Similarly, the node n23 becomes VREF / 2 by the amplifier 233 having the gain of 1.

  Therefore, in the data input sample hold circuit 254, the voltage n23 is held in the capacitor Cs8 at the timing of the pulse signal SW22 according to the value of the digital value Din of the most significant bit. The held value n24 is transferred to the output of the amplifier 236 and applied to one capacitor CD of the adding circuit 255. Initially, since the voltage value n29 from the delay circuit 256 is zero, the voltage value n24 is approximately halved (˜VREF / 4) by the coupling circuit of the two capacitors CD, and the voltage n25 is (2 + α) by the amplifier 237. Doubled. The output n26 is held in the capacitor Cs10 by the pulse signal SW23.

  Thereafter, the digital value of the next lower bit is applied to the input Din. This time, the capacitor Cs6 that previously held VREF / 2 is combined with the capacitor Cs7 that is cleared by the pulse signal SW23, and VREF / 4 is held in the capacitor Cs7. That is, the analog value corresponding to the second upper bit. In the example in which the corresponding analog value is 4VREF / 5, since the digital value of the second bit is 1, the data input sample hold circuit 254 holds the transistor 234 in the capacitor Cs8 at the timing of the pulse signal SW22.

  The held voltage VREF / 4 is applied to the capacitor CD of the adding circuit 255, and the voltage VREF / 2 of the output n29 of the delay circuit 256, which is delayed by one cycle, is applied to the other capacitor CD and added. The As a result, a voltage value of VREF / 2 + VREF / 4 = 3VREF / 4 is output to the node n26. Then, it is held in the capacitor Cs10 at the timing of the pulse signal SW23.

  By repeating the above operation up to the digital value of the least significant bit, the output sample hold circuit 256 holds the final analog value in the capacitor Cs9 at the timing of the pulse signal SW24. Then, an analog output Aout is generated through an amplifier circuit 239 having a gain of 1.

In this circuit, VREF / 2, VREF / 4... VREF / 2 ^N analog values are sampled and held and added by N digit times of the digital value. Therefore, any digitized digital value can be converted to an analog value by serial operation.

  In this 1-bit serial digital-analog conversion circuit, a capacitor element is mainly used, and a transistor element having a small number of elements is used for an inverter or an amplifier. Therefore, the total number of transistor elements can be reduced. In the 1/2 circuit 253 and the adder circuit 255, the above-described capacitive coupling circuit is used.

[Counter circuit using capacitive coupling and AD conversion circuit using it]
Next, a counter circuit using a capacitive coupling circuit will be described. The counter circuit can constitute a kind of serial type analog-digital conversion circuit in combination with a kind of oscillation circuit driven by a detection current from a photodetector described later. Therefore, it meets the purpose of constructing an AD conversion circuit by effectively using the capacitive coupling circuit of the present invention.

  FIG. 53 is a diagram illustrating an example of a counter circuit using a capacitive coupling circuit. FIG. 54 is a signal waveform diagram thereof. In this example, a pulse signal is continuously supplied to the input terminal Vin, the least significant bit A0 changing from the L level to the H level and from the H level to the L level for each pulse signal Vin, and the same for every two pulse signals Vin. A second-stage bit A1 that changes to L, H, and L, and a third-stage bit A2 that changes similarly for each of the four pulse signals Vin are generated.

  The first-stage circuit 251 generates a pulse signal P1 for every two pulse signals Vin, and the second-stage circuit 252 generates a pulse signal P2 for every four pulse signals Vin, and the third-stage circuit 253. Generates a pulse signal P3 for every eight pulse signals Vin. By supplying this signal P3 to the next stage circuit, the fourth stage bit A3 (not shown) can be generated. These circuits 251, 252, and 253 have the same configuration.

  The first-stage circuit 251 of the counter circuit has a capacitor C1, diodes 255, 256, and a capacitor C2 as a pumping circuit. When the input pulse signal Vin rises, the capacitor C2 is charged via the capacitor C1 and the diode 256. As a result, the node n41 rises. Then, the node n40 is pulled down via the capacitor C1 due to the fall of the input pulse signal Vin, but the diode 256 becomes non-conductive, and the node n40 is supplied with charge from the ground potential via the diode 255. When the input pulse signal Vin rises again, the node n41 is further pulled up.

  In the charge pumping operation using the input pulse signal Vin described above, the potential of the node n41 is determined in accordance with the capacitive coupling ratio of the C1 and C2 energy having the pulse height and width. In this example, the inverters 258 are designed to invert the capacitance values of the capacitors C1 and C2 by two input pulses Vin. The threshold voltage of the inverter 260 is set lower than the threshold voltage of the inverter 258, and the inverter 260 is inverted by one pulse signal Vin.

  Therefore, the inverter 260 is inverted by the potential of the node n41 increased by the first pulse signal Vin, and the output is changed from H level to L level. Accordingly, the output A0 becomes H level. On the other hand, the inverter 258 is inverted by the potential of the node n41 raised by the second pulse signal Vin, and the output P1 of the first stage becomes H level. The transistor 257 is turned on by the H level of the output P1. As a result, the node n41 is lowered to the L level, and the output P1 is also lowered to the L level via the inverters 258 and 259. That is, a pulse signal having a width corresponding to the delay time of the two inverters 258 and 259 is generated at the output P1. Further, the inverter 260 is also inverted, and the first-stage bit A0 returns to the L level.

  As shown in FIG. 54, node n43 rises in the charge pump circuit of the second stage circuit due to the output P1 of the first stage circuit 251. As a result, the inverter 260 is inverted by the same operation, and the bit A1 in the second stage becomes H level.

  The third stage circuit 253 has the same configuration as the first and second stage circuits 251 and 252 and performs the same operation by the pulse signal P2. Thus, a binary digital value obtained by counting the input pulse signal Vin is generated in the counter output A0 A1 A2.

  FIG. 55 is a diagram illustrating another counter circuit example. FIG. 53 is a positive logic type, whereas this counter circuit is a negative logic type, and the operation is the same. In the circuit of FIG. 55, for example, the first stage circuit 270 is provided with a charge pump circuit comprising a capacitor C1, diodes 275, 276 and a capacitor C2.

  The difference from the example of FIG. 53 is that the diode 275 and the capacitor C2 are not connected to the ground potential but are connected to the power supply Vdd, and the input pulse signal Vin is a negative pulse signal. Accordingly, the reset potential of the node n51 is at the H level. The threshold voltage of the inverter 280 is set higher than that of the inverter 278.

  Therefore, the charge pump operation is also reversed, in the reset state, the P-type transistor 277 is turned on, the node n51 is at the H level, and the potential of the node n51 is lowered by the application of the input pulse signal Vin. The threshold value of the inverter 280 is set higher than the threshold value of the inverter 278. The inverter 280 is inverted by the first pulse signal Vin, and the output A0 is inverted to the H level. When the two pulse signals Vin are given, the inverter 278 is inverted and the pulse P1 falls from the H level to the L level. As a result, the transistor 277 becomes conductive and resets the node n51 to the H level.

  Thus, the logic and the charge pump are reversed, but the operation is the same as in FIG. These counter circuits can be simply configured by using a capacitive coupling circuit.

  In the above two counter circuits, inverters having different threshold voltages are used. However, configuring such a circuit requires forming transistors with different characteristics. Therefore, it becomes a burden on the process. Therefore, a counter circuit using inverters having the same threshold voltage is desired.

  FIG. 56 shows still another counter circuit. FIG. 56 is a signal waveform diagram showing the operation.

  FIG. 56 shows a first stage circuit 290 and a second stage circuit 291 of the counter circuit. The configuration of both circuits is almost the same. For example, the configuration of the first-stage circuit 290 will be described. This circuit includes the negative logic type charge pump circuit shown in FIG. For example, the configuration of the capacitor C10, the diodes 292 and 293, the capacitor C12, and the reset transistor 294 is the same as the circuit of FIG. That is, the negative pulse signal Pn obtained by inverting the positive pulse signal Vin causes the node n61 to fall from the reset level H level. The threshold voltage of the inverter 295 is set so that it is inverted when two negative pulses Pn are applied.

  The charge pump circuit including the capacitor C15, the diodes 298 and 299, the capacitor C16, and the reset transistor 300 has the same configuration. The inverter 301 has the same threshold voltage as the other inverters 295, 297 and the like. However, the inverter 301 needs to be inverted by one pulse signal Pn, and the connection direction of the capacitor C16 is different from that of the capacitor C12. That is, the capacitor C16 is connected to the ground side.

  Further, the inverter 297 needs to be inverted by one pulse signal of the node n62 that is inverted by the two pulse signals Pn. Therefore, the input section has a capacitive coupling circuit composed of capacitors C11, C13, and C14, and constitutes a majority circuit together with the inverter 297. Therefore, when both the pulse signal Pn and the node n62 become H level, the node n64 is lowered and the P-type reset transistor 294 is driven to return the node n61 to the reset level of H level.

  Therefore, the inverter 295 is inverted by the two pulse signals Pn (inverted pulse signal of the input positive pulse signal Vin) to form the pulse signal Pn to the next stage. The inverter 301 side has the same threshold voltage, but by changing the configuration of the capacitor C16 and appropriately setting the capacitance value, it is inverted by one negative pulse signal Pn to generate the counter output An. . Inverter 297 drives reset transistor 294.

  The operation of the circuit will be described with reference to FIG. A positive input pulse signal Vin is continuously input. Then, a negative pulse signal Pn is supplied to the first stage circuit 290 via the inverter 302. In the first charge pump circuit including the capacitor C10, the diodes 292 and 293 and the capacitor C12, and the reset transistor 294, the nodes n60 and n61 at the H level are reduced via the diode 293 due to the fall of the pulse signal Pn. . However, at this time, the inverter 295 is not inverted. On the other hand, in the second charge pump circuit composed of the capacitor C15, the diodes 298 and 299, the capacitor C16, and the reset transistor 300, the node n66 having the H level similarly decreases, but the capacitance ratio between the capacitors C15 and C16 is appropriately set By setting (for example, C15> C16), the node n66 becomes lower than the threshold voltage level of the inverter 301. As a result, the inverter 301 is inverted and the counter output An becomes H level.

  When the second pulse signal Pn is given, the node n61 further falls and the inverter 295 is inverted. As a result, the reset transistor 300 is turned on by the next stage input pulse Pn + 1 changed to the L level, and the node n66 is reset to the H level. As a result, the output An becomes L level. At the same time, the potential of the capacitor C14 becomes H level due to the change of the node n62 to H level, and the inverter 297 is inverted by the majority logic with the signal Pn returned to H level to generate the L level output n64. The reset transistor 294 is driven by this L level, and the node n61 returns to the H level again. Therefore, an L pulse signal having a width corresponding to the delay time of the inverters 295 and 297 is provided at the node n61. Similarly, the signal Pn is a pulse signal having a relatively short width.

  The second-stage circuit 291 also performs the same operation using the input negative pulse signal Pn. Therefore, when two input pulse signals Vin are given, the output An + 1 becomes H level, and when four input signal Vin is given, it becomes L level. Although not shown in FIG. 56, the output An + 2 is generated by the same operation in the third-stage circuit.

  As described above, in the counter circuit of FIG. 56, since the inverter threshold values are made equal, it is possible to realize a circuit without a burden on the process. Then, a counter circuit is realized with a small number of transistors using a charge pump circuit or a majority circuit using a capacitive coupling circuit.

  An AD converter circuit using the counter circuit described above will be described. FIG. 58 shows an example of such an AD converter circuit. This AD conversion circuit generates an input pulse signal to the counter by discharging a node of a capacitor by a detection current by a photodiode PD, for example, and charging by a reset transistor. Then, using the fact that the frequency of the input pulse signal changes according to the magnitude of the current value that changes according to the light intensity detected by the photodiode PD, a counter value that is incremented within a predetermined time is output as a digital output.

  FIG. 59 is a diagram showing changes in the nodes n80 and n81 when the light intensity is relatively low. FIG. 60 is a diagram illustrating changes in the nodes n80 and n81 when the light intensity is relatively high. The circuit operation will be described using both figures.

  First, a detection current corresponding to the intensity of the light 320 irradiated to the photodiode PD is generated. A constant voltage Vref is applied to the gate of the N-type transistor 310. The capacitor 311 is charged from the P-type reset transistor 312 and discharged by the detection current of the photodiode PD. The inverter 313 is set to an appropriate threshold voltage. The input pulse signal is generated at the node n81 and supplied to the counter 315.

  Assume that the node n80 is at the H level. In this state, when the light 320 is incident, the photodiode PD generates a current corresponding to the light intensity. Accordingly, the charge in the capacitor 311 is discharged. Eventually, when the voltage at the node n80 falls below the threshold voltage Vth of the inverter 313, the inverter 313 is inverted, and the node n81 is inverted to the L level. The reset level transistor 312 is turned on by the L level pulse, charges the capacitor 311 and raises the node n80 to the H level. Thereby, inverter 313 is inverted again and node n81 is set to H level.

  Accordingly, a negative pulse is generated at the node n81, and the pulse width is determined by the delay time of the inverters 313 and 314, the charging time by the transistor 312 and the like. Further, the pulse interval is determined by the discharge speed determined according to the magnitude of the detected current. Therefore, as shown in FIG. 59, when the detection current is small, the frequency of the pulse signal becomes low. Also, as shown in FIG. 60, the frequency of the pulse signal increases when the detection current is large.

  The counter 315 is constituted by, for example, a negative logic type counter circuit shown in FIGS.

  The example of FIG. 58 is a negative logic type, and the node n80 becomes H level when reset, and the capacitance is discharged by the detection current. This configuration can also be configured as a positive logic type. Although not described with reference to the drawings, the capacitor 311 is connected to the power supply Vdd side, the reset transistor is connected to the ground side, and the detection current from the photodiode PD is charged to the capacitor. In such a configuration, the node n81 generates a positive pulse signal.

  The AD converter circuit of FIG. 58 can be configured using a capacitive coupling circuit. Although it is not a flash type, the current analog value can be converted into a digital value by counting pulse signals corresponding to the detected current within a certain time.

  FIG. 61 is a diagram showing an example of an integrated circuit in the case where the above-described analog-digital conversion circuit and other logic circuits are formed on the same chip as the photodetector element. In this example, a photodetector PD for four pixels is provided on the chip 400. An analog / digital conversion circuit ADC is provided adjacent to the photodetector PD, and a digital output Dout of each pixel is generated.

  FIG. 62 is a diagram showing another example of an integrated circuit when an analog-digital conversion circuit and other logic circuits are similarly formed on the same chip as the photodetector element. In this example, the photodetector elements PD for four pixels are provided on the chip 400, and their analog outputs are supplied to the analog / digital conversion circuit ADC in time series by the gate transistors 411 to 416 via the multiplexer circuit MPX. The converted digital output Dout is output to the outside. Each gate transistor is driven in time series by a shift register SR or the like.

  In the integrated circuit shown in FIGS. 61 and 62, the logic circuit using the capacitive coupling circuit, the AD conversion circuit, etc. described in the above embodiment are used, so that these circuits are configured with a small number of transistor elements. can do. Accordingly, the area of the photo detector can be increased accordingly.

[Improved analog-digital conversion circuit]
FIG. 63 is a diagram showing a further improved analog-digital conversion circuit. This AD conversion circuit is an improved version of the flash AD conversion circuit shown in FIGS.

In the flash type AD converter circuit shown in FIGS. 20, 22, 29 and 32, it is not a big problem when the number of bits of the digital output is small, but when the number of bits is as large as 8 bits or 16 bits, for example. Therefore, the required capacitance value becomes very large, which is an adverse effect of integration with the photoelectric conversion element. For example, paying attention to the case of FIG. 32, in order to generate a 4-bit digital output, the capacitance value in the capacitive coupling circuit portion, excluding the portion that generates the remainder,
(2C + C) + (4C + 2C + C) + (8C + 4C + 2C + C) = 25C
Requires a capacity value of. Furthermore, when this becomes 8 bits,
(2C + C) + (4C + 2C + C) + (8C + 4C + 2C + C) +
(16C + 8C + 4C + 2C + C) +
(32C + 16C + 8C + 4C + 2C + C) +
(64C + 32C + 16C + 8C + 4C + 2C + C) +
(128C + 64C + 32C + 16C + 8C + 4C + 2C + C) = 501C
Requires a capacity value of.

  Such an enormous capacitance value occupies a large area of the integrated circuit, which is not preferable. In order to solve this point, the circuit of FIG. 32 uses the operational amplifier circuit 168 to calculate the remainder every 4 bits and uses it as the input of the next 4-bit AD converter circuit. . However, the use of the operational amplifier circuit 168 is not preferable because it leads to an increase in the number of elements.

  The improved AD converter circuit shown in FIG. 63 has an 8-bit digital output, but by dividing the capacitive coupling circuit into a main array and a sub-array and coupling both arrays with capacitance, the overall capacitance value is markedly reduced. Can be reduced.

  63 converts the analog input Vin into 8-bit digital outputs A7 to A0. The circuit for obtaining the upper 4 bits A7 to A4 for the analog input Vin is the same as the conversion circuit shown in FIGS. That is, the most significant bit A7 is determined whether or not the analog input Vin is greater than the threshold voltage Vt by the inverter 511 which is a comparator directly or via a capacitor C (not shown), and the output is inverted by the inverter 512 and output. A7 is generated. 29 and 32, the inverter 512 has a threshold value slightly higher or lower than the threshold value Vt of the inverter 511 (0V in the example of FIG. 32 and Vt = Vdd / 2 in the example of FIG. 63). Then, the inverted value of the most significant bit A7 is fed back to the capacitive coupling circuits 540 and 541 of the next bit A6 by the capacitor 541.

  In order to obtain the next bit A6, the capacitive coupling circuit couples the input Vin via the capacitor 540 having the capacitance value 2C and the inverted value / A7 of the higher bit A7 via the capacitor 541 having the capacitance value C. Accordingly, the inverted bit / A7 of the upper bit A7 is added with a weight of 1/2 to the input Vin. Therefore, the next bit A6 is obtained by comparing whether the value is larger or smaller than the threshold value Vt by the inverter 514 as a comparator. These operating principles are as already described. Similarly, bits A5 and A4 are obtained.

  In the improved AD converter circuit shown in FIG. 63, in the circuit for obtaining the lower 4 bits A3 to A0, the capacitive coupling circuit is divided into a main array and a subarray, and both are coupled by a capacitor. For example, in the circuit for obtaining the output bit A3, the main array in which the input Vin and the inverted bits of the output bits A7 to A5 are coupled by the capacitors 549, 550, 551, and 552, and the inverted bit of the output bit A4 are coupled by the capacitor 554. Are connected by a capacitor 553. On the subarray side, a reference voltage Vref is coupled to the subarray side via a capacitor 555. The capacitance values of the capacitors 549 to 555 are ratios as illustrated.

  FIG. 64 is a diagram in which only the circuit portion for obtaining the output bit A3 is extracted. As understood from this figure, the voltage at the capacitive coupling point Vy3 on the subarray SA side is coupled to the capacitive coupling point Vx3 on the main array MA side via the coupling capacitor 553. On the sub-array SA side, the inverted bit / A4 of the output bit A4 is coupled through the capacitor 554 having the capacitance value 2C, and thus the relationship between the capacitor 553 (C), the capacitor 554 (2C), and the capacitor 555 (C). Thus, the voltage Vy3 is coupled with a weight of 2C / 4C = 1/2. On the main array MA side, the voltage Vy3 is coupled to the voltage Vx3 through the capacitor 553 with a weight of 1/8. The input Vin is weight 1, bit / A7 is weight 1/2, bit / A6 is weight 1/4, bit / A5 is weight 1/8, and voltage Vy3 is also weight 1/8. Therefore, bit / A4 is combined with a weight of 1/16.

  Similarly, in the capacitive coupling circuit of the output bit A2, the main array composed of the capacitors 556 to 559 and the sub array composed of the capacitors 561 to 563 are coupled via the capacitor 560. In the capacitive coupling circuit of the output bit A1, a main array composed of capacitors 564 to 567 and a sub-array composed of capacitors 569 to 572 are coupled by a capacitor 568.

  FIG. 65 is a diagram showing a coupling circuit for A0 of the least significant bit. That is, the main array MA composed of capacitors 573 to 576 for coupling the input Vin and the bits / A7, / A6, / A5, and the subarray SA composed of capacitors 578 to 582 for coupling the bits / A4 to / A1 and the reference voltage Vref. Are coupled by a capacitor 577. The voltage Vx0 is supplied to the inverter 532 that is a comparator.

  In order to understand the improved AD converter circuit of FIG. 63, the voltage Vx0 is obtained by calculation using the capacitive coupling circuit of the output bit A0 of FIG. 65 as an example. From the relationship between the main array potential Vx0 and the subarray potential Vy0, and the relationship between the input Vin and each of the bits A7 to A0, the following three equations are established.

上記の３つの式を解くことで電位Ｖx0は、
５１１Ｖx0＝２５４Ｖｄｄ＋Ｖｒｅｆ＋Ａ０・Ｖｄｄ
として求められる。但し、Ａｎ・Ｖｄｄ＋／Ａｎ・Ｖｄｄ＝Ｖｄｄ（ｎは１〜７）である。

By solving the above three equations, the potential Vx0 is
511Vx0 = 254Vdd + Vref + A0 · Vdd
As required. However, An * Vdd + / An * Vdd = Vdd (n is 1-7).

Therefore, if the threshold voltage Vt of the comparator 532 is Vt = Vdd / 2, and further Vref = Vdd,
Vx0 = (510Vt + A0 · 2Vt) / 511
It is. Therefore, when the potential Vx0 when the input Vin is at a level where A0 = 0 and when the input Vin is at a level where A0 = 1 is obtained,
(1) When the input Vin is at a level where A0 = 0, Vx0 = (510/511) Vt
(2) When the input Vin is at a level where A0 = 1, Vx0 = (512/511) Vt
It is.

  That is, regarding the least significant bit A0, the potential Vx0 is 0 or 1 depending on whether the threshold voltage Vt is 510/511 or 512/511.

If Vref = Vdd / 2,
Vx0 = (509Vt + A0 · 2Vt) / 511
It is. Therefore, when the potential Vx0 when the input Vin is A0 = 0 and A0 = 1 is obtained,
(1) When the input Vin is A0 = 0, Vx0 = (509/511) Vt
(2) When the input Vin is A0 = 1, Vx0 = (511/511) Vt
It is.

  That is, regarding the least significant bit A0, the potential Vx0 is 0 or 1 depending on whether the threshold voltage Vt is 509/511 or 511/511.

  Therefore, for the least significant bit A0, a digital value is obtained by detecting a 2/511 difference in the threshold voltage Vt. Theoretically, the least significant bit of 8 bits is Vin / 256 (= 2Vin / 512), which is understood to be almost the theoretical value. The main array and sub-array circuits shown in FIG. 65 interfere with each other via the capacitor 577, and therefore cannot agree with the theoretical value at all. However, this degree can be adjusted by devising the circuit.

  It is desirable that the inverters 511, 514, 517, 520, 523, 526, 529, and 532, which are the comparators of the AD converter circuit shown in FIG. 63, have characteristics that are inverted as accurately as possible with the threshold voltage Vt. Therefore, by using an auto-zero type inverter for these inverter circuits, the inversion operation can be performed with high accuracy.

  FIG. 66 is a diagram illustrating an example of the auto-zero inverter circuit. FIG. 67 is a diagram showing characteristics of the auto-zero inverter circuit of FIG. The circuit shown in FIG. 66 includes a short-circuit transistor 604 that short-circuits their input V1 and output V2 to a CMOS inverter composed of transistors 600 and 601, a transistor 605 that supplies a reference voltage VR to the input Vin, and a compensation capacitor CVT. And an inverter (532 in FIG. 65) to which are added, and an inverter for inversion thereof. The inverter for inversion is composed of transistors 602 and 603.

  In the first-stage inverter, the input V1 and the output V2 of the inverter are short-circuited by the H level of the reset clock φR, so that their potentials are the potential VL1 corresponding to the point L1 on the short-circuit straight line L shown in FIG. Become. At this time, since the reference potential VR is applied to the input Vin, charges corresponding to the difference ΔV between the voltage VL1 and the reference potential VR which is the reference voltage are accumulated in the compensation capacitor CVT.

  That is, the point L1 shown in FIG. 67 is accurately shifted up and down from Vdd / 2 due to variations in the characteristics of the inverter. Therefore, the potential VL1 is also shifted up and down from Vdd / 2. Thus, by using VR = Vdd / 2 as the reference potential, the compensation capacitor CVT can always store charges corresponding to the voltage difference between the inverter inversion potential VL1 and VR = Vdd / 2. When an arbitrary potential is applied to the input Vin from such a reset state, the inverter always inverts the input Vin accurately at the level of Vdd / 2.

  Therefore, when the auto-zero inverter shown in FIG. 66 is used, the analog input Vin is applied after resetting by the reset signal φR.

Looking again at the improved flash AD converter circuit of FIG. 63, as described above, the capacitive coupling circuit portion for the lower bits is divided into the main array and the sub-array, and the two are coupled by capacitance. The capacity value is
(2C + C) + (4C + 2C + C) + (8C + 4C + 2C + C) +
(8C + 4C + 2C + C + C + 2C + C) +
(8C + 4C + 2C + C + C + 4C + 2C + C) +
(8C + 4C + 2C + C + C + 8C + 4C + 2C + C) +
(8C + 4C + 2C + C + C + 16C + 8C + 4C + 2C + C) = 145C
It is. Compared to the above-described 501C, it is about 1/3. This tendency becomes more significant as the number of bits increases.

  FIG. 68 is a diagram showing the operating characteristics of an AD conversion circuit equivalent to the circuit of FIG. 63 and having 6-bit digital outputs A5 to A0. In this example, for the 6-bit digital outputs A5 to A0, the lower-order bits A2, A1 and A0 use the capacitive coupling circuit separated into the main array and the subarray. The operating characteristic diagram of FIG. 68 shows changes in the respective digital outputs A5 to A0 when the analog input Vin is changed from 0 V to Vdd. In general, it is shown that the digital outputs A5 to A0 are reversed in order. However, as indicated by reference numerals 610 and 611 in the figure, the H level period in the lower bits A0 and A1 is shorter than the other H level periods because of the interference between the main array and the sub-array described above. It seems to be due to an error due to.

  FIG. 69 shows an example of an improved analog-digital conversion circuit, which is a serial AD conversion circuit. FIG. 45 shows an example of a serial AD converter circuit. However, in this example, many operational amplifier circuits must be used. In the example of the AD converter circuit shown in FIG. 69, the operational amplifier circuit is not used as much as possible, and is all composed of a capacitor, a transistor and an inverter.

  In the circuit example of FIG. 69, the operational amplifier circuit 611 is only used in the circuit 609 that samples and holds the analog input Vin. That is, the transistor 610 is turned on by the sample hold signal SH1, and the capacitor Cs is charged according to the voltage of the analog input Vin. As a result, the electrode of the capacitor Cs holds the voltage of the analog input Vin.

  The capacitors 612, 613, 614, and 615 constitute a capacitive coupling circuit. The input Vin is coupled by a capacitor 612 having a capacitance value of 8C, the bit / A3 is coupled by a capacitor 613 having a capacitance value of 4C, and the bit / A2 is coupled by a capacitor 614 having a capacitance value of 2C, and the bit / A1. Are coupled by a capacitor 615 having a capacitance value C. Therefore, the respective bits / A3 to / A1 are coupled to the input Vin with weights of 1/2, 1/4, and 1/8.

  That is, by sequentially opening the switches SW1, SW2, and SW3, the capacitive coupling circuit for each bit shown in FIG. 63 is sequentially formed, and each digital bit output is generated as the output Data.

  The serial AD converter circuit of FIG. 69 uses the odd-zero inverter shown in FIG. 66 as the comparator 620. That is, the inverter 624, the short-circuit transistor 622, the transistor 621 that applies the reference potential Vref, and the compensation capacitor CVT are configured. The transistor 625 is driven by the clock SH2 and samples the output of the inverter 624 into the capacitor Csh. The held voltage is inverted by the inverter 626 and output as a digital output to the output terminal Data.

  The most significant bit A3 is sampled by the switch 627 and held in the capacitor Csh, and its inverted value / A3 is coupled through the capacitor 613 by the switch 629. As a result, the next bit A2 is generated at the output Data. Similarly, the bit A2 is sampled by the switch 631 and held in the capacitor Csh, and its inverted value / A2 is coupled through the capacitor 614 by the switch 633. As a result, the next bit A1 is generated at the output Data. The same applies to the next bit A0.

  FIG. 70 is a timing chart of each control clock showing the serial conversion operation. In this figure, the analog input Vin is sequentially converted into 4-bit digital values A3, A2, A1, and A0 in cycles t1 to t6. First, at cycle t1, a reset signal φR is applied to reset the auto-zero inverter 620 and charge the compensation capacitor CVT. At the same time, the reset signals R1, R2, and R3 of the respective bits are set to the H level, and the reference voltage Vref (= Vdd / 2) is applied to the electrodes of the capacitors 613, 614, and 615 through the transistors 630, 634, and 638. This voltage value is a neutral potential in the capacitive coupling circuit.

  Therefore, first, when the sample hold signal SH1 is set to H level in the cycle t2, the voltage of the input Vin is held in the capacitor Cs, and the output of the operational amplifier 611 is applied with the input potential. The potential is applied to the inverter 620 via the capacitor 612, and a comparison is made as to whether it is higher or lower than the reference potential Vref (= Vdd / 2). Then, in cycle t3, the output of the inverter 620 is sampled and held in the capacitor Csh by the H level of another sample and hold signal SH2, and the most significant bit A3 is output to the output Data.

  Next, at cycle t4, the switch signal SW1 becomes H level, the transistor 627 is turned on, and the output bit A3 is sampled and held in the capacitor Csh. At the same time, the reset signal R1 becomes L level, and the inverted bit of the most significant bit A3 is applied to the capacitor 613 by the H level of the signal H1. A voltage generated according to the weighting by the capacitive coupling circuit composed of the capacitors 612 and 613 is generated at the node Vx, and the next bit A2 is similarly generated at the output Data.

  Next, at cycle t5, the switch signal SW2 becomes H level, the transistor 631 becomes conductive, and the output bit A2 is sampled and held in the capacitor Csh. At the same time, the reset signal R2 becomes L level. Then, a potential of the next bit is generated at the node Vx by the capacitive coupling circuit including the capacitors 612, 613, and 614, and the bit A1 is generated at the output Data by the sample hold signal SH2.

  Finally, in cycle t6, the potential of the bit A0 is generated at the node Vx by the capacitive coupling circuit of the capacitors 612 to 615, and the output bit A0 is generated at the output Data by the sample hold signal SH2. At this time, the output bit A3 is held in the capacitor Csh by the switch SW1, the output bit A2 is held in the capacitor Csh by the switch SW2, and the output bit A1 is held in the capacitor Csh by the switch SW3.

  As described above, a 4-bit digital value is converted in cycles t1 to t6 in FIG.

  FIG. 71 shows a serial type analog-digital conversion circuit capable of generating an 8-bit digital value. In this circuit example, the capacitive coupling circuit portion is divided into a main array MA and a sub-array SA as shown in FIG. 63, and these are coupled by capacitance, thereby preventing an increase in overall capacitance value due to the increase in the number of bits. To do.

  In the AD conversion circuit example shown in FIG. 71, the capacitors 612 to 615 and the capacitors 640 to 645 are equivalent to the capacitive coupling circuit shown in FIG. However, in the case of FIG. 71, since it is a serial type, the inverted value of the upper bit is applied in time series, and when detecting the least significant bit, the circuit configuration is exactly the same as in FIG. . Capacitors 612 to 615 constitute a main array MA, and inverted values of upper bits A7, A6, A5 are applied to the respective capacitors, and the potential at the connection point is expressed as Vx. Capacitors 641 to 645 constitute sub-array SA, and inverted values of lower bits A4, A3, A2 and A1 are applied, respectively, and the potential at the connection point is expressed as Vy. These two arrays MA and SA are coupled via a capacitor 640.

  In the circuit example of FIG. 71, the circuit to which the upper bits A7, A6, A5 are fed back is the same as in FIG. 69, and corresponding elements are denoted by the same reference numbers. The circuit to which the lower bits A 4, A 3, A 2, A 1 are fed back constitutes a sub-array SA coupled by the capacitor 640. In the conversion operation, as described with reference to FIG. 69, the inverter 620 is first reset by the reset signal φR, and the nodes of the respective feedback circuits are similarly reset to the neutral level by the reset signals R1 to R7. After the analog input Vin is sampled and held in the capacitor Cs by the sample and hold signal SH1, the switch signals SW1 to SW7, the signals H1 to H7, and the reset signals R1 to R7 are synchronized with the timing of the second sample and hold signal SH2. And serially converts the upper bits into digital values.

  72 and 73 show control signals φR, SH1, SH2, SW1 to SW7, R1 to R7, an input Vin and an output to show the operation of the serial AD converter circuit of FIG. 71 configured with a 6-bit output. It is a timing chart figure with Data. FIG. 72 shows a change in the output data when the input Vin is “0” to “9” among 64 gradations of 6 bits. On the other hand, FIG. 73 shows a change in the output data when the input Vin is “63” to “54” out of 64 gradations of 6 bits.

  In the case of FIG. 72, when the input Vin is “0” to “9”, the sample hold signal SH2 becomes H level 6 times, so that the digital output is converted from “000000” to “001001”. .

  In the case of FIG. 73, when the input Vin is “63” to “54”, the respective sample and hold signals SH2 are changed to the H level six times, thereby changing the digital output from “111111” to “110110”, respectively. Converted.

  The serial AD converter circuit shown in FIG. 71 is configured by an inverter, a transistor, and a capacitor, except that a part of the operational amplifier circuit 611 is used for the input portion. In addition, the capacitive coupling circuit has a configuration in which the main array MA and the sub-array SA are divided into units of the capacitor 640 in spite of the multi-bit digital output, and the total capacitance value is reduced, and the integration is reduced. make it easier. In addition, by using the auto-zero inverter 620, the threshold value of the comparison operation for conversion to each digital value can be set to Vdd / 2 which is exactly half of the power supply Vdd. Alternatively, it can be set at an arbitrary potential Vref.

  As described above, according to the present invention, various logic circuits, AD conversion circuits, DA conversion circuits, and counter circuits can be configured with a small number of transistors by using a capacitive coupling circuit.

  Therefore, by using these circuits, the area of the peripheral circuit can be suppressed in an LSI in which the image sensor and its peripheral AD conversion circuit and arithmetic circuit are mounted on the same substrate. Therefore, an LSI having a high sensor fill factor can be configured.

1 is a circuit diagram of a capacitive network illustrating the principle of the present invention. FIG. 3 is a majority circuit diagram of a three-terminal input using a capacitance network for an input stage. It is a four-terminal input weighting majority circuit diagram. It is a 2-input NAND, NOR circuit diagram. FIG. 4 is a 4-input NAND / NOR circuit diagram. It is a 2-input NOR / OR circuit diagram. 3 is a 3-input NOR / OR circuit diagram. FIG. It is RS flip-flop circuit diagram. It is an arbiter circuit diagram. It is a tri-state buffer circuit diagram. It is an EQ circuit and an EXOR circuit diagram. It is a Schmitt trigger circuit diagram. It is a clocked RS flip-flop circuit diagram. It is a master slave RS flip-flop circuit diagram. It is a JK flip-flop circuit diagram. It is a D flip-flop circuit diagram. It is a T flip-flop circuit diagram. It is a full addition circuit diagram. FIG. 19 is an output waveform diagram for confirming the operation of the full adder circuit of FIG. 18. It is a circuit diagram of a flash type AD converter. It is a wave form diagram which shows the operation | movement of FIG. It is an AD conversion circuit diagram for generating a 4-bit digital output and a remainder. FIG. 23 is a waveform diagram of FIG. 22. It is a 12-bit flash AD conversion circuit diagram. FIG. 25 is a waveform diagram (1) of FIG. 24. It is a wave form diagram (2) of FIG. It is a wave form diagram (3) of FIG. This is a 12-bit AD conversion circuit with a rounding function and overflow. It is a figure which shows the other circuit example of a 3 bit AD conversion circuit. FIG. 21 is a waveform diagram of FIG. 20. FIG. 30 is a waveform diagram of FIG. 29. It is a figure of the other example of the AD converter circuit which produces | generates a 4-bit digital output and a remainder. It is a wave form diagram of FIG. It is a figure which shows the example made into 12 bit AD converter circuit. FIG. 35 is a waveform diagram (1) when 0/8 to 8/8 is given to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. FIG. 35 is a waveform diagram (2) when 0/8 to 8/8 is given to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. FIG. 35 is a waveform diagram (3) when 0/8 to 8/8 is given to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. FIG. 35 is a waveform diagram (1) when 0/7 to 7/7 and 0/7 are given to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. FIG. 35 is a waveform diagram (2) when 0/7 to 7/7 and 0/7 are given to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. FIG. 35 is a waveform diagram (3) when 0/7 to 7/7 and 0/7 are given to the analog input of the 12-bit AD converter circuit of FIG. 34 in the range of −Vds to + Vds. FIG. 35 is a circuit diagram in which a rounding function and an overflow bit OF are added to the 12-bit AD conversion circuit of FIG. 34. It is a figure which shows the example of a serial type AD converter circuit. FIG. 43 is a timing chart of FIG. 42. FIG. 44 is a diagram illustrating an example of an operation amplifier circuit in FIG. 43. It is a figure which shows the example of a 1-bit serial type AD converter circuit. FIG. 46 is a waveform diagram of the AD conversion circuit of FIG. 45. FIG. 46 is a waveform diagram of the AD conversion circuit of FIG. 45. It is a figure which shows the example of a serial type DA converter circuit. FIG. 49 is a waveform diagram of the DA converter circuit of FIG. 48. It is a figure which shows the example of a 1 bit serial digital analog conversion circuit. It is a wave form diagram of a 1 bit serial digital analog conversion circuit. It is an enlarged waveform figure of signal n23. It is a figure which shows the example of the counter circuit using a capacitive coupling circuit. FIG. 54 is a signal waveform diagram of FIG. 53. It is a figure which shows another counter circuit example. Furthermore, it is a figure which shows another counter circuit example. FIG. 57 is a signal waveform diagram of FIG. 56. It is a figure which shows the AD conversion circuit using a counter circuit. FIG. 59 is a signal waveform diagram of the circuit of FIG. 58. FIG. 59 is a signal waveform diagram of the circuit of FIG. 58. It is a figure which shows an example of an integrated circuit at the time of forming an analog digital conversion circuit and another logic circuit on the same chip | tip as a photodetector element. It is a figure which shows an example of an integrated circuit at the time of forming an analog digital conversion circuit and another logic circuit on the same chip | tip as a photodetector element. It is a figure which shows the further improved type analog-digital conversion circuit. It is the figure which extracted only the circuit part which calculates | requires bit A3. Furthermore, it is a figure which shows the coupling circuit of A0 of the least significant bit. It is a figure which shows the example of an auto zero type inverter circuit. It is a figure which shows the characteristic of an auto zero type inverter circuit. FIG. 64 is a diagram showing the operating characteristics of an AD converter circuit equivalent to the circuit of FIG. 63 and having 6-bit digital outputs A5 to A0. This is an example of an improved analog-to-digital conversion circuit and a successive approximation AD conversion circuit. FIG. 70 is a timing chart of each control clock showing the serial conversion operation of FIG. 69. This is a serial type analog-digital conversion circuit capable of generating an 8-bit digital value. FIG. 72 is a timing chart of the serial AD converter circuit of FIG. 71 configured with 6-bit output. FIG. 72 is a timing chart of the serial AD converter circuit of FIG. 71 configured with 6-bit output.

Explanation of symbols

ADCU Analog / digital conversion circuit unit Vin Analog input D0 Digital output FA Full adder circuit OF Overflow output

Claims (4)

In the counter circuit that counts the supplied input pulse signal,
A charge pump circuit having a charge / discharge capacity charged or discharged by the input pulse signal, wherein a potential of one electrode of the charge / discharge capacity is increased or decreased from a reset level by the input pulse signal;
A first inverter that inverts and generates a count output by increasing or decreasing the potential of the one electrode of the charge pump circuit;
A second inverter that generates an output pulse to the next stage by inverting by increasing or decreasing the potential of the one electrode of the charge pump circuit in response to an input pulse signal greater than the number required to invert the first inverter When,
A unit circuit having a reset transistor that returns the one electrode to a reset level by an inverted signal of the output of the second inverter is connected across a plurality of stages, and the output pulse of the unit circuit of the previous stage is connected to the unit circuit of the next stage. A counter circuit provided as an input pulse signal.   The counter circuit according to claim 1, wherein the pulse signal of the pulse oscillation circuit having a frequency corresponding to the light intensity from the light detection element is given as an input pulse signal of the counter circuit. circuit. In the counter circuit that counts the supplied input pulse signal,
A first charge / discharge capacity charged or discharged by the input pulse signal, wherein the potential of one electrode of the first charge / discharge capacity is increased or decreased from a reset level by the input pulse signal; A charge pump circuit;
A first inverter that inverts and generates a count output by increasing or decreasing the potential of the one electrode of the first charge pump circuit;
A second charge / discharge capacity charged or discharged by the input pulse signal, and the second pulse charge / discharge capacity is increased or decreased from a reset level by the input pulse signal. A charge pump circuit;
In response to an input pulse signal larger than the number required for the inversion of the first inverter, a first output pulse to be inverted is generated by increasing or decreasing the potential of the one electrode of the second charge pump circuit. Two inverters,
A first reset transistor for returning one electrode of the first charge / discharge capacitance to a reset level by an inverted signal of the output of the second inverter; and an second inverted signal of the output of the second inverter. A unit circuit having a second reset transistor for returning one electrode of the discharge capacity to the reset level is connected over a plurality of stages, and an output pulse of the previous unit circuit is given as an input pulse signal of the next unit circuit A counter circuit characterized by that.   4. A counter circuit according to claim 3, wherein a pulse signal of a pulse oscillation circuit having a frequency corresponding to the light intensity from the light detection element is given as an input pulse signal of the counter circuit. circuit.

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