CN111491118B - Programmable gain amplifier circuit for image sensor - Google Patents
Programmable gain amplifier circuit for image sensor Download PDFInfo
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- CN111491118B CN111491118B CN202010381462.8A CN202010381462A CN111491118B CN 111491118 B CN111491118 B CN 111491118B CN 202010381462 A CN202010381462 A CN 202010381462A CN 111491118 B CN111491118 B CN 111491118B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
- H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
- H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The invention discloses a programmable gain amplifier circuit for an image sensor, which comprises an operational transconductance amplifier, wherein an inverting input end of the operational transconductance amplifier is connected with an image sensor signal through a sampling capacitor, a feedback capacitor, a switch and a plurality of adjusting capacitors which are mutually connected in parallel are connected between the inverting input end and an output end of the operational transconductance amplifier, the adjusting capacitors are respectively connected with double signal channels, each double signal channel is composed of two groups of signal channels, each adjusting capacitor is connected to the sampling capacitor through a corresponding first group of signal channels in common, and each adjusting capacitor is connected to the output end of the operational transconductance amplifier in common through a corresponding second group of signal channels. The invention can eliminate the influence of interference introduced by parasitic capacitance and can provide various amplification factors according to requirements.
Description
Technical Field
The invention relates to the field of gain amplification circuits of image sensors, in particular to a programmable gain amplifier circuit for an image sensor.
Background
Image sensors are the core of image acquisition devices, mainly used in digital cameras and industrial, media, medical, consumer electronics. With the increasing demand for cameras, camcorders, multimedia handsets, the image sensor market is growing rapidly. At present, the solid-state image sensor mainly includes two image sensors of a CCD and a CMOS. CCD image sensors have been widely used due to their high fill factor and low fixed pattern noise. But the application of the CMOS transistor is limited due to the defects of multiple voltages, high power consumption, low speed, difficulty in integration with the CMOS process and the like. The CMOS process is gradually becoming the mainstream process of the image sensor due to its characteristics of low power consumption, low operating voltage, high integration level, and the like. However, the signal amplitude of the pixel output in the CMOS image sensor may vary greatly under different scenes, and in order to adapt to the variation of the signal intensity, the signal intensity is usually adjusted by a Programmable Gain Amplifier (PGA) before the pixel output signal enters an Analog-to-Digital Converter (ADC), so as to meet the requirement of a larger dynamic range of the signal. Meanwhile, the PGA can suppress large signals, and for small signals, the noise of a rear module can be suppressed by amplifying effective signals, so that the integral signal-to-noise ratio is improved.
As shown in fig. 1, when a reset signal of a pixel comes in, a switch Sf is closed, the reset signal is sampled onto a sampling capacitor Cs, when a pixel valid signal comes in, the switch Sf is opened, charges on the sampling capacitor Cs are transferred onto a feedback capacitor Cf, and a final output signal is Vo ═ Cs (Vr-Vs)/Cf, where Vr is the reset signal of the pixel, Vs is the pixel valid signal, and Cs/Cf is a gain of the PGA.
Fig. 2 is an implementation of a PGA circuit, in which a plurality of capacitors C1-C4 are connected in series with switches S1-S4, and then connected in parallel with each other to form a feedback capacitor Cf, and the change of the feedback Cf in fig. 1 is implemented by selecting on or off of switches S1-S4. The following problems exist in this circuit:
1. when the switches S1-S4 are in an open state, the right sides of the capacitors C1-C4 are suspension points, and are easily interfered by clock signals coupled by parasitic capacitors at the suspension points, so that charges stored at negative input points of an Operational Transconductance Amplifier (OTA) are affected, and the amplification precision and linearity of the PGA are affected.
2. For a larger PGA amplification factor, such as a gain of 16 times, the size ratio of Cs/Cf is 16, and since the value of the feedback capacitor Cf is affected by parasitics and process variations, the value of the feedback capacitor Cf cannot be too small, otherwise the amplification accuracy is greatly affected. The corresponding sampling capacitance Cs becomes large. If it is necessary to provide an amplification gain of 0.5 times, i.e., to attenuate a signal by half when a large signal is input, the maximum value in the variable range of the feedback capacitance Cf is twice the sampling capacitance Cs, so that the total PGA capacitance area may be 3 times the sampling capacitance Cs, and it is difficult to realize a large capacitance value within the width of one pixel, resulting in an excessively large chip area.
Disclosure of Invention
The invention aims to provide a PGA circuit for an image sensor, which solves the problems that the PGA circuit in the prior art is easily influenced by a parasitic capacitance coupling signal and needs a larger chip area to realize the PGA circuit.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the utility model provides a PGA circuit for image sensor, includes the OTA, and its inverting input passes through sampling capacitor and inserts the image sensor signal, is connected with feedback capacitor and the switch that connects in parallel each other between its inverting input, the output, its characterized in that: the image sensor further comprises a plurality of adjusting capacitors, one end of each adjusting capacitor is connected to the inverting input end of the OTA in common, the other end of each adjusting capacitor is connected with a double-signal channel, each double-signal channel is composed of two groups of signal channels, the two groups of signal channels corresponding to each adjusting capacitor are selectively switched on or off under the control of an external register, the other group of signal channels are switched off when one group of signal channels are switched on, the other end of each adjusting capacitor is connected to one end, connected to the image sensor signal, of the sampling capacitor in common through the corresponding first group of signal channels, and the other end of each adjusting capacitor is connected to the output end of the OTA in common through the corresponding second group of signal channels.
The PGA circuit for an image sensor, comprising: two groups of signal channels corresponding to each adjusting capacitor are respectively composed of switches, one end of each of the two groups of switches is connected to the other end of the corresponding adjusting capacitor in common, the other end of the first group of switches corresponding to each adjusting capacitor is connected to one end of the sampling capacitor connected to the image sensor signal in common, and the other end of the second group of switches corresponding to each adjusting capacitor is connected to the output end of the OTA in common.
The PGA circuit for an image sensor, comprising: two groups of signal channels corresponding to each adjusting capacitor are formed by switches of an equivalent single-pole double-throw switch structure, the input end of the equivalent single-pole double-throw switch structure is connected with the other end of the corresponding adjusting capacitor, one output end of the equivalent single-pole double-throw switch structure is connected to one end, connected with an image sensor signal, of the sampling capacitor in a shared mode, and the other output end of the equivalent single-pole double-throw switch structure is connected to the output end of the OTA in a shared mode.
The PGA circuit for an image sensor, comprising: different gains are realized by adjusting the proportion of the sampling capacitor and the feedback capacitor.
The PGA circuit for an image sensor, comprising: different gains are realized by adjusting the number of the capacitors.
The invention discloses a PGA circuit used in an image sensor, which is used for amplifying an analog signal output by a pixel in the image sensor and inhibiting the influence of post-stage noise on a system. The invention can perform analog correlated double sampling on the signals output by the pixels, namely, the reset signals and the effective signals of the pixels are subtracted, thereby eliminating the Fixed Pattern Noise (FPN) of the pixel signals, eliminating the influence of interference introduced by parasitic capacitance and providing various amplification factors according to the requirement.
Drawings
FIG. 1 is a schematic diagram of a PGA circuit;
FIG. 2 is a circuit block diagram of one implementation of the prior art;
fig. 3 is a circuit configuration diagram of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 3, a PGA circuit for an image sensor includes an OTA, an inverting input terminal of the OTA is connected to an image sensor signal through a sampling capacitor Cs, a feedback capacitor Cf and a switch Sf which are connected in parallel with each other are connected between the inverting input terminal and an output terminal of the OTA, and a plurality of adjustment capacitors C5-C8, one ends of the adjustment capacitors C5-C8 are connected to the inverting input terminal of the OTA in common, the other ends of the adjustment capacitors C5-C8 are connected to dual signal channels S5-S8, the dual signal channels S5-S8 are respectively formed by two groups of signal channels, two groups of signal channels corresponding to each adjustment capacitor C5-C8 are selectively turned on or off under the control of an external register, and when one group of the signal channels is turned on, the other group of the signal channels is turned off. The other end of each adjusting capacitor C5-C8 is respectively connected to one end of the sampling capacitor Cs connected to the image sensor signal through a corresponding first group of signal channels in a common mode, and the other end of each adjusting capacitor C5-C8 is respectively connected to the output end of the operational transconductance amplifier OTA through a corresponding second group of signal channels in a common mode.
Two groups of signal channels corresponding to each adjusting capacitor C5-C8 are respectively formed by switches, one end of each switch is connected to the other end of the corresponding adjusting capacitor C5-C8 in a common mode, the other end of a first group of switches corresponding to each adjusting capacitor C5-C8 is connected to one end, connected with the image sensor signal, of the sampling capacitor Cs in a common mode, and the other end of a second group of switches corresponding to each adjusting capacitor C5-C8 is connected to the output end of the OTA in a common mode.
Two groups of signal channels corresponding to each adjusting capacitor C5-C8 are formed by switches of an equivalent single-pole double-throw switch structure, the input end of the equivalent single-pole double-throw switch structure is connected with the other end of the corresponding adjusting capacitor C5-C8, one output end of the equivalent single-pole double-throw switch structure is connected to one end, connected with the image sensor signal, of the sampling capacitor Cs in common, and the other output end of the equivalent single-pole double-throw switch structure is connected to the output end of the OTA in common.
The invention realizes different gains through the number of the adjusting capacitors C5-C8.
In the invention, each adjusting capacitor C5-C8 is respectively connected with a double-signal channel S5-S8, the double-signal channel is respectively composed of two switches, the two switches are drawn in a dotted line frame and can be equivalent to a single-pole double-throw switch structure, four double-signal channels S5-S8 composed of equivalent single-pole double-throw switch structures are drawn in the figure 3, one output end of each equivalent single-pole double-throw switch structure is connected to the left side of a sampling Cs, and the other output end of each equivalent single-pole double-throw switch structure is connected to the output end of an OTA. Each tuning capacitor is therefore connected either in parallel with the sample Cs or in parallel with the feedback capacitor Cf. The advantages of this structure are:
1. each of the tuning capacitors C5-C8 is not floating, thereby avoiding interference introduced by floating points.
2. The capacitance value of the sampling Cs can be supplemented by adjusting the capacitance values of the capacitors C5-C8, so that the sampling Cs can be amplified at a high magnification without being amplified greatly. For an amplification gain of 0.5 times, the total capacity value of Cf + C1+ C2+ C3+ C4 is only required to be twice of the sample Cs. The overall capacitance is greatly reduced.
3. In FIG. 3, the four dual-signal channels S5-S8 are controlled by control signals Reg [1] -Reg [4], respectively, and when the dual-signal channel is set to 1, the right plate of the corresponding adjusting capacitor is connected to the left node of the sampling Cs, and the value of the sampling Cs is increased.
4. The capacitance value of the capacitor can be selected according to the requirement of gain, for example, the simplest capacitance ratio is: the sampling capacitance Cs is 4 times, the adjusting capacitance C5 is 1 time, the adjusting capacitance C6 is 1 time, the adjusting capacitance C7 is 2 times, the adjusting capacitance C8 is 4 times, and the feedback capacitance Cf is 0, and the achievable gains are shown in table 1:
TABLE 1 gain TABLE 1
| Reg[4:1] | Cs to Cf capacitance ratio | Multiple of |
| 0000 | 4/(1+1+2+4) | 0.5 |
| 0100 | (4+2)/(1+1+4) | 1 |
| 1000 | (4+4)/(1+1+2) | 2 |
| 1100 | (4+4+2)/(1+1) | 5 |
| 1110 | (4+4+2+1)/1 | 11 |
Table 1 only shows four combinations, and other combinations are not listed. If the capacitance is set to 30 times the sampling capacitance Cs, 8 times the adjusting capacitance C5, 12 times the adjusting capacitance C6, 15 times the adjusting capacitance C7, 15 times the adjusting capacitance C8, and 10 times the feedback capacitance Cf, the gain that can be achieved is as shown in table 2:
TABLE 2 gain Table two
| Reg[4:1] | Cs to Cf capacitance ratio | Magnification factor |
| 0000 | 30/(8+12+15+15+10) | 0.5 |
| 1000 | (30+15)/(10+8+12+15) | 1 |
| 1100 | (30+15+15)/(10+8+12) | 2 |
| 1110 | (30+12+15+15)/(10+8) | 4 |
| 1111 | (30+8+12+15+15)/10 | 8 |
If an adjusting capacitor C9 and a corresponding dual signal channel S5 are added, a gain increased by 16 times at first level can be realized, and the values of the capacitors can be calculated as follows: the PGA gains of 0.5, 1, 2, 4, 8, and 16 times can be achieved by setting the sampling capacitance Cs to 510 times, the adjustment capacitance C5 to 255 times, the adjustment capacitance C6 to 255 times, the adjustment capacitance C7 to 204 times, the adjustment capacitance C8 to 136 times, the adjustment capacitance C9 to 80 times, and the feedback capacitance Cf to 90 times.
The embodiments of the present invention are described only for the preferred embodiments of the present invention, and not for the purpose of limiting the spirit and scope of the present invention, and various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the design concept of the present invention shall fall within the protection scope of the present invention, and the technical contents of the present invention as claimed are all described in the claims.
Claims (5)
1. The programmable gain amplifier PGA circuit for the image sensor comprises an operational transconductance amplifier OTA, wherein the inverting input end of the operational transconductance amplifier OTA is connected with the image sensor signal through a sampling capacitor, and a feedback capacitor and a switch which are connected in parallel are connected between the inverting input end and the output end of the operational transconductance amplifier OTA, and the programmable gain amplifier PGA circuit is characterized in that: the device comprises an operational transconductance amplifier OTA, a plurality of adjusting capacitors and a sampling capacitor, wherein one end of each adjusting capacitor is connected to the inverting input end of the operational transconductance amplifier OTA in common, the other end of each adjusting capacitor is connected with a double-signal channel, the double-signal channel is composed of two groups of signal channels, the two groups of signal channels corresponding to each adjusting capacitor are selectively switched on or off under the control of an external register, the other group of signal channels are switched off when one group of signal channels are switched on, the other end of each adjusting capacitor is connected to one end, connected with an image sensor signal, of the sampling capacitor in common through a corresponding first group of signal channels, and the other end of each adjusting capacitor is connected to the output end of the operational transconductance amplifier OTA in common through a corresponding second group of signal channels; through the dual signal path, each adjusting capacitor is connected with the sampling capacitor in parallel or connected with the feedback capacitor in parallel.
2. The PGA circuit of claim 1, wherein: two groups of signal channels corresponding to each adjusting capacitor are respectively composed of switches, one end of each group of switches is connected to the other end of the corresponding adjusting capacitor in common, the other end of the first group of switches corresponding to each adjusting capacitor is connected to one end of the sampling capacitor connected to the image sensor signal in common, and the other end of the second group of switches corresponding to each adjusting capacitor is connected to the output end of the operational transconductance amplifier OTA in common.
3. The programmable gain amplifier PGA circuit for an image sensor according to claim 1, wherein: two groups of signal channels corresponding to each adjusting capacitor are formed by switches of an equivalent single-pole double-throw switch structure, the input end of the equivalent single-pole double-throw switch structure is connected with the other end of the corresponding adjusting capacitor, one output end of the equivalent single-pole double-throw switch structure is connected to one end of the sampling capacitor connected to the image sensor signal in common, and the other output end of the equivalent single-pole double-throw switch structure is connected to the output end of the operational transconductance amplifier OTA in common.
4. The programmable gain amplifier PGA circuit for an image sensor according to claim 1, wherein: different gains are realized by adjusting the proportion of the sampling capacitor and the feedback capacitor.
5. The programmable gain amplifier PGA circuit for an image sensor according to claim 1, wherein: different gains are realized by adjusting the number of the capacitors.
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| CN112468746B (en) * | 2020-11-13 | 2023-04-07 | 中国电子科技集团公司第二十四研究所 | Focal plane digital pixel gain fine-tuning circuit |
| US11653112B2 (en) * | 2020-11-23 | 2023-05-16 | Raytheon Company | Analog voting with outlier suppression |
| CN113271076B (en) * | 2021-04-26 | 2023-03-31 | 歌尔微电子股份有限公司 | Gain-variable operational amplification circuit and electronic equipment |
| CN114051107B (en) * | 2021-10-28 | 2023-09-22 | 西安微电子技术研究所 | Dual-mode fine gain configuration method of CMOS image sensor |
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