WO2017101573A1 - 像素电路及其驱动方法、驱动电路、显示装置 - Google Patents

像素电路及其驱动方法、驱动电路、显示装置 Download PDF

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WO2017101573A1
WO2017101573A1 PCT/CN2016/101752 CN2016101752W WO2017101573A1 WO 2017101573 A1 WO2017101573 A1 WO 2017101573A1 CN 2016101752 W CN2016101752 W CN 2016101752W WO 2017101573 A1 WO2017101573 A1 WO 2017101573A1
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Prior art keywords
voltage
pixel
capacitor
transistor
discharge
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PCT/CN2016/101752
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English (en)
French (fr)
Inventor
张衎
张斌
陈鹏名
王光兴
张强
董殿正
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to EP16856463.1A priority Critical patent/EP3392870B1/en
Priority to US15/521,666 priority patent/US10049634B2/en
Publication of WO2017101573A1 publication Critical patent/WO2017101573A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Definitions

  • the invention belongs to the technical field of pixel circuit driving, and relates to a pixel circuit and a driving method thereof, and a driving circuit and a display device based on the pixel circuit array formed by the pixel circuit.
  • a thin film transistor (TFT) array is disposed on the glass substrate of the display.
  • the TFT array is generally composed of a plurality of pixel circuits arranged in rows and columns, and corresponding pixel circuits are disposed corresponding to each pixel, and the pixel circuits provide corresponding pixel voltages to control each The display of pixels.
  • the existing pixel circuit is generally a 1T1C structure, that is, based on a transistor (for example, TFT) plus a capacitor, the gate signal (Gate) provided by the gate driver is used to control the transistor T to be turned on or off, and the capacitor C is controlled by the source driver.
  • the device charges based on the data signal (Data) to reach a certain pixel voltage value. This pixel voltage can be used to drive the liquid crystal of the corresponding pixel.
  • the pixel circuit needs to provide pixel voltages of different sizes, that is, gray scale voltages.
  • the supply of different gray scale voltages is usually achieved by the Gamma circuit and the source driver of the TFT array.
  • a plurality of fixed tie voltages are required to be given by a Gamma circuit, and then finely divided by a plurality of gamma resistors inside the source driver to obtain a plurality of digital voltage values (ie, Gamma reference voltages), for example, a voltage value of 6 Bit.
  • Digital to analog conversion is then applied to the capacitance of the corresponding pixel circuit to produce a corresponding pixel voltage.
  • the biggest problem with the driving of such a pixel circuit is that it causes a large logic power consumption and a driving circuit of a relatively complicated TFT array; and, since the gray scale voltage of the RGB sub-pixels must be shared, an 8-bit voltage value control cost is realized. Higher, and the algorithm is complex and the debugging cycle is long.
  • One of the objects of various embodiments of the present invention is to avoid using a gamma resistor to drive a pixel circuit and reduce the driving power consumption of the pixel circuit.
  • the present invention provides the following technical solutions:
  • a pixel circuit (100) for providing a pixel voltage for providing a pixel voltage, the pixel circuit being located in a Nth row of a pixel circuit array (10), the pixel circuit comprising: a capacitor (C); a capacitor charging transistor (T1) for charging the capacitor (C), the gate terminal of the capacitor charging transistor (T1) is electrically connected to the gate line (110) of the (N-1)th row; the first capacitor discharge transistor ( T2), the gate terminal thereof is electrically connected to the gate line (120) of the Nth row; and the second capacitor discharge transistor (T3) whose gate terminal is electrically connected to the data line (130); the capacitor is in the capacitor charging transistor (T1) is charged to a first voltage greater than the pixel voltage when turned on; the capacitor (C) is coupled in series with the first capacitor discharge transistor (T2) and the second capacitor discharge transistor (T3) to form a discharge circuit, The capacitor is discharged when the first capacitor discharge transistor and the second capacitor discharge transistor (T3) are turned on to lower the voltage across the capacitor (C)
  • a pixel circuit reduces the voltage from the first voltage to the pixel voltage by controlling at least a discharge time (T- discharge ) of the capacitor (C).
  • the data line (130) of a data signal is pulse width modulated signal, by the pulse width modulated signal to control the second capacitor discharge transistor (T3) to control the opening time of the discharge time (T release ).
  • the pixel circuit controls the degree of opening of the second capacitor discharge transistor (T3) by controlling at least the voltage of the data line (130), thereby achieving reduction from the first voltage The pixel voltage.
  • the first voltage in a positive frame, is twice the liquid crystal molecular deflection reference voltage (2Vcom), and the pixel voltage is a positive frame pixel voltage; in a negative frame, The first voltage is a liquid crystal molecular deflection reference voltage (Vcom), and the pixel voltage is a negative frame pixel voltage.
  • 2Vcom liquid crystal molecular deflection reference voltage
  • Vcom liquid crystal molecular deflection reference voltage
  • the drain terminal of the capacitor charging transistor (T1) is electrically connected to the first end of the capacitor, and the source end of the first capacitor discharge transistor (T2) The first end of the capacitor is electrically connected, and the drain end of the first capacitor discharge transistor (T2) is electrically connected to the source end of the second capacitor discharge transistor (T3).
  • the pixel circuits (100) are respectively disposed corresponding to R sub-pixels, G sub-pixels, and B sub-pixels of RGB pixels, thereby providing respective independent R sub-pixels, G sub-pixels, and B sub-pixels, respectively.
  • the pixel voltage is respectively disposed corresponding to R sub-pixels, G sub-pixels, and B sub-pixels of RGB pixels, thereby providing respective independent R sub-pixels, G sub-pixels, and B sub-pixels, respectively.
  • the pixel voltage is respectively disposed corresponding to R sub-pixels, G sub-pixels, and B sub-pixels of RGB pixels, thereby providing respective independent R sub-pixels, G sub-pixels, and B sub-pixels, respectively.
  • the first row of pixel circuits in the pixel circuit array may have the same circuit structure as the pixel circuits of the other rows, and wherein the gate terminal of the capacitive charging transistor in the pixel circuit of the first row receives the STV signal ( The start signal of a frame of image).
  • a driving method of the above pixel circuit including:
  • Charging phase turning on the charging transistor (T1) by a gate signal (Gate(N-1)) of the gate line (110) of the (N-1)th row, thereby charging the capacitor to be larger than a first voltage of the pixel voltage;
  • a discharge phase a data signal (Data) of the first capacitor discharge transistor (T2) being turned on and passing through the data line (130) by a gate signal (GateN) of a gate line (120) of the Nth row
  • the second capacitor discharge transistor (T3) is turned on, and the capacitor (C) is discharged to lower the voltage across the first voltage from the first voltage to the pixel voltage;
  • Holding phase the capacitor charging transistor (T1) is turned off and at least one of the first capacitor discharging transistor (T2) and the second capacitor discharging transistor (T3) is turned off to keep the pixel voltage level substantially constant.
  • the first voltage in a positive frame, is twice the liquid crystal molecular deflection reference voltage (2Vcom) biased on the common electrode, and the pixel voltage is a positive frame pixel voltage;
  • the first voltage is equal to the liquid crystal molecular deflection reference voltage (Vcom) biased on the common electrode, the pixel voltage being a negative frame pixel voltage.
  • the reduction from the first voltage to the pixel voltage is achieved by controlling at least the discharge time (T- discharge ) of the capacitor (C).
  • the data line (130) of a data signal is pulse width modulated signal, by the pulse width modulated signal to control the second capacitor discharge transistor (T3) to control the opening time of the discharge time (T release ).
  • the degree of turn-on of the second capacitor discharge transistor (T3) is controlled by controlling at least the voltage of the data line (130), thereby achieving a reduction from the first voltage
  • the pixel voltage is described.
  • the time of the charging phase and/or the discharging phase is on the order of microseconds.
  • a driving circuit for a pixel circuit array comprising any one of the above-described pixel circuits arranged in rows and columns, wherein the driving circuit includes :
  • a pixel voltage control module configured to provide the data line (130) with the second capacitor discharge transistor (T3) turned on to discharge the voltage across the capacitor (C) from the first voltage A data signal (Data) that falls to the pixel voltage.
  • the pixel voltage control module (50) includes a pulse width controller (520) for outputting a pulse width modulation signal, and a pulse width of the pulse width modulation signal is configured to control the The discharge time (T discharge ) of the capacitor (C).
  • the pixel voltage control module (50) includes a level shifter (530) for controlling a magnitude of a high level of the pulse width modulated signal to control the second capacitive discharge transistor ( The degree of opening of T3).
  • the pixel voltage control module (50) further includes: a shift register (510) for at least a received digital drive signal and temporarily storing; and an output buffer (540) for at least And outputting the pulse width modulation signal.
  • a driving circuit according to still another embodiment of the present invention, wherein the charging power source (20) includes a third transistor (P1) and a fourth transistor (P2), the third transistor (P1) and the fourth transistor (P2) The mutually complementary transistors, the drain terminal of the third transistor (P1) and the drain terminal of the fourth transistor (P2) are electrically connected to an output end of the charging power source (20), the third transistor (P1) The gate terminal and the gate terminal of the fourth transistor (P2) are controlled by a polarity inversion control signal.
  • the third transistor (P1) in a positive frame, is turned on and is input twice as long as the liquid crystal molecule deflection reference voltage (2Vcom) biased on the common electrode; in the negative frame, the first The four transistors (P2) are turned on and are input to the liquid crystal molecules biased by the common electrode to deflect the reference voltage (Vcom).
  • 2Vcom liquid crystal molecule deflection reference voltage
  • a display device comprising: a pixel circuit array including a plurality of the above-described pixel circuits arranged in rows and columns; and the above-described driving circuit.
  • the technical effect of the embodiment provided by the present invention is that the driving circuit of the pixel circuit array does not
  • the gamma resistor needs to be set correspondingly, the structure is simple, the driving circuit is easier to implement, and the power consumption of the driving process is low.
  • the charging phase first charges the capacitor C to a voltage higher than the pixel voltage, and can generate an overdrive effect on the liquid crystal of the corresponding pixel to a certain extent, thereby facilitating the liquid crystal response.
  • FIG. 1 is a schematic diagram showing the basic structure of a pixel circuit in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a driving principle of a pixel circuit in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing the principle of using a pulse width modulation technique to control a pixel voltage in an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a driving circuit of a pixel circuit array in accordance with an embodiment of the present invention.
  • FIG. 5 is a block diagram showing the structure of a pixel voltage control module according to an embodiment of the invention.
  • FIG. 1 is a schematic diagram showing the basic structure of a pixel circuit according to an embodiment of the invention.
  • FIG. 1 illustrates a pixel circuit 100 that mainly includes a capacitor C and transistors T1-T3.
  • the plurality of pixel circuits 100 may form an array of pixel circuits, for example, a pixel circuit array formed on a TFT glass substrate, which may be one of core components for forming a display panel, and may control the liquid crystal module.
  • Each pixel circuit 100 can control the display of a single pixel or sub-pixel, specifically providing a corresponding pixel voltage through the capacitor C to control the gray level of a single pixel or sub-pixel.
  • the capacitor C may be an equivalent capacitor (also referred to as a "liquid crystal capacitor”) formed by a pixel electrode on the TFT substrate and a common electrode on a CF (color film) substrate above the TFT substrate. Therefore, it is a storage capacitor provided in the pixel circuit.
  • the pixel electrode can be understood as the first end of the capacitance C of the pixel circuit 100 of the embodiment of the present invention.
  • the common electrode for forming the other end (second end) of the capacitor C has a predetermined voltage Vcom (as shown in FIG. 1) which is a liquid crystal molecule deflection reference voltage, which is a pixel voltage pole of the pixel electrode. Provide a reference for sex.
  • the pixel voltage of the pixel electrode is greater than Vcom, the pixel voltage is a positive polarity voltage, and if the pixel voltage of the pixel electrode is less than Vcom, the pixel voltage is a negative polarity voltage.
  • Both the pixel electrode and the common electrode can be formed by patterning of an ITO material.
  • the pixel circuit 100 may be one of the units of the pixel circuit array constituting the L rows and the X columns.
  • the pixel circuit 100 is located in the Nth row of the array, and N is less than or equal to L.
  • N is less than or equal to L.
  • the pixel circuit The specific location of 100 in the array of pixel circuits is not limiting.
  • the transistor T1 is a capacitor charging transistor, and the drain end thereof is electrically connected to the first end of the capacitor C, that is, the pixel electrode is connected, and the gate terminal thereof is electrically connected to the gate line (or scan line) 110 of the (N-1)th row, and the source terminal thereof is electrically connected.
  • the external charging power supply includes transistors P2 and P1 connected in series, transistors P2 and P1 are complementary transistors, and the gate terminals of transistors P2 and P1 are connected with POL (polarity inversion control) signal, so that transistor P1 is turned off when transistor P2 is turned on, and the transistor is turned off. Transistor P2 is turned off when P1 is turned on.
  • a voltage of 2Vcom is input from the source terminal of the transistor P1, and a voltage Vcom is input from the source terminal of the transistor P2.
  • the drain terminal of transistor P2 and the drain terminal of transistor P1 are electrically coupled together and form the output of charging power source 20.
  • the charging power source 20 outputs a charging voltage of 2Vcom
  • the transistor P2 is turned on, it outputs a charging voltage of Vcom.
  • Transistor T1 is controlled by signal Gate(N-1) transmitted by gate line 110.
  • the transistor T1 When the transistor T1 is turned on, it indicates that the capacitor charging phase is entered, so that the capacitor C can be charged from the charging power source 20. At this time, the source terminal of the transistor T1 can be connected to the output of the external charging power source 20.
  • the transistor P1 of the charging power source When the transistor P1 of the charging power source is turned on, the source terminal of the transistor T1 is connected to the voltage 2Vcom and the first end of the capacitor C can be charged to a voltage level of about 2Vcom.
  • the transistor P2 of the charging power source When the transistor P2 of the charging power source is turned on, the transistor T1 is turned on. The source is connected to the voltage Vcom and can charge the first end of the capacitor C to a voltage level of about Vcom. Thus, the first end of capacitor C can be charged to a voltage level of Vcom or 2Vcom.
  • the transistors T2 and T3 are capacitor discharge transistors, and the gate terminal of the transistor T2 is electrically connected to the gate line (or scan line) 120 of the Nth row, and the source terminal is electrically connected to the first end of the capacitor C, and the drain thereof The terminal is electrically connected to the source end of the discharge transistor T3; the drain end of the transistor T3 is With the ground GND, the gate terminal of the transistor T3 is electrically connected to the data line 130. Therefore, the capacitor C is connected in series with the capacitor discharge transistor T2 and the capacitor discharge transistor T3 to form a discharge circuit. When both of the capacitor discharge transistors T2 and T3 are turned on, the capacitor C can be discharged via the discharge circuit.
  • Transistor T2 is controlled by signal GateN transmitted by gate line 120, which is controlled by data signal Data transmitted by data line 130.
  • signal GateN transmitted by gate line 120
  • data signal Data transmitted by data line 130.
  • both the transistor T2 and the transistor T3 are turned on, it indicates that the pixel circuit 100 enters the discharge phase, and further controls the discharge time and/or the discharge speed of the capacitor C by controlling the turn-on time or the turn-on degree of the capacitor discharge transistor T3.
  • the voltage of the capacitor C after discharge that is, the pixel voltage can be controlled.
  • the specific principle of controlling the pixel voltage by controlling the discharge process will be described in detail in the latter driving principle.
  • the degree of opening of the transistor T3 can be expressed by the magnitude of its equivalent resistance R, that is, the degree of opening of the transistor T3 reflects the magnitude of its equivalent resistance R, and the higher the degree of opening, the smaller the equivalent resistance.
  • the capacitor C and the resistor including the equivalent resistor R form an RC discharge circuit, and the smaller the equivalent resistance R is, the larger the degree of opening of the transistor T3 is, and the faster the discharge speed is.
  • FIG. 2 is a schematic diagram showing the driving principle of a pixel circuit according to an embodiment of the invention.
  • the operation of the pixel circuit of the embodiment shown in Fig. 1 and its driving method will be exemplified in conjunction with Figs. 1 and 2.
  • the dual frame signal is used to drive the liquid crystal cell, that is, each pixel of the liquid crystal cell is alternately driven using a positive frame and a negative frame, which is advantageous in avoiding cell retention and eventually causing image permanent deterioration.
  • a positive electric field is applied to the pixel to perform positive polarity driving.
  • the pixel electrode is biased with a positive polarity voltage, that is, a voltage that is biased larger than the common electrode voltage Vcom; in the negative frame, a negative electric field is applied to the pixel.
  • the negative polarity drive is performed, and at this time, the pixel electrode is biased with a negative polarity voltage, that is, a voltage biased to be smaller than the common electrode voltage Vcom.
  • FIG. 2(a) shows pixel voltage control in the case of a negative frame in which a negative frame pixel voltage, that is, a negative polarity voltage can be obtained.
  • the gate terminal of the charging transistor T1 is electrically connected to the gate line 110 of the (N-1)th row, it is biased by the signal Gate(N-1) as shown in FIG. 2(a), and the gate terminal of the transistor T1. Biasing a high level at time t1 causes transistor T1 to turn on, indicating that it is entering the charging phase. At time t2, the signal Gate(N-1) goes low, the transistor T1 is turned off, and the charging phase ends.
  • the charging power source 20 outputs a voltage Vcom, and the first end of the capacitor C is charged from 0V to the voltage Vcom, and the voltage Vcom is greater than the negative polarity voltage obtained after the capacitor finally needs to be discharged.
  • the signal GateN is at a low level, and the discharge circuit of the capacitor C is not turned on.
  • the signal GateN of the gate line 120 becomes a high level
  • the transistor T2 is turned on
  • the signal Data of the data line 130 becomes a high level
  • the transistor T3 is turned on. , indicating that the discharge phase is started, and the discharge circuit is turned on, so that the first end of the capacitor C starts to discharge from the voltage Vcom.
  • the signal Data of the data line 130 goes low, the transistor T3 is turned off, the discharge ends, the capacitor C is discharged to a predetermined negative frame pixel voltage (which is less than Vcom), and thereafter t3 to t5
  • the negative frame pixel voltage is substantially maintained, thereby generating a negative polarity drive for the corresponding pixel, enabling the liquid crystal to flip.
  • the difference between the negative frame pixel voltage and the voltage Vcom determines the degree of inversion of the liquid crystal molecules, thereby controlling the gray scale of the pixel.
  • the discharge time, i.e. T put, in this embodiment, by controlling the discharge time T discharge length can be controlled discharge charge amount in the capacitor C, which can control the size of the negative frame pixel voltage, so You can control to get the desired negative frame pixel voltage.
  • the driving process mainly includes a charging phase of the t1 to t2 time period, a discharging phase of the t2 to t3 time period, and a t3 to t5 time period of the holding phase.
  • FIG. 2(b) it indicates pixel voltage control in the case of a positive frame to obtain a positive frame pixel voltage, that is, a positive polarity voltage.
  • the working principle is basically the same as in the case of the negative frame, that is, the charging phase including the time period from t1 to t2, the discharging phase in the t2 to t3 time period, and the t3 to t5 time period are the holding phases. The difference is that in the charging phase, the charging power source 20 outputs a voltage of 2Vcom, and the first end of the capacitor C is charged from 0V to the voltage 2Vcom, that is, the pixel electrode is charged to the voltage 2Vcom, and the voltage 2Vcom is greater than the capacitor C. Positive frame pixel voltage.
  • the voltage at the first end of capacitor C drops from 2Vcom to a predetermined positive frame pixel voltage that is greater than the voltage Vcom of the common electrode, which can be set in the range of Vcom to 2Vcom. And at the subsequent t3 to t5, the positive frame pixel voltage is substantially maintained, thereby generating a positive polarity drive for the corresponding pixel, enabling the liquid crystal to flip.
  • the difference between the positive frame pixel voltage and Vcom determines the degree of inversion of the liquid crystal molecules, thereby controlling the gray scale of the pixel.
  • the data signal Data for the pulse width modulated signal using pulse width modulation techniques based on the charge voltage, the predetermined voltage or the like obtained by the pixel to modulate the pulse width to control the length of the discharge time T, the capacitor discharge The pixel voltage obtained later is a predetermined pixel voltage.
  • FIG. 3 is a schematic diagram showing the principle of using a pulse width modulation technique to control a pixel voltage according to an embodiment of the present invention.
  • V 1 is the charging voltage of the pixel electrode is charged
  • V 21 is the pixel voltage of the pixel electrode corresponding to the data signals Data1 obtained after the controlled discharge process
  • V 22 as the pixel voltage of the pixel electrode after corresponding data signals Data2 control the discharge process obtained
  • the pixel voltage is the charging voltage of the pixel electrode is charged
  • V 21 is the pixel voltage of the pixel electrode corresponding to the data signals Data1 obtained after the controlled discharge process
  • V 22 as the pixel voltage of the pixel electrode after corresponding data signals Data2 control the discharge process obtained
  • V 23 for the corresponding pixel electrode data signal Data3 obtained after the controlled discharge process
  • the data signal Data may control the magnitude of the voltage to control an opening degree of high capacitive discharge transistor T3, thereby controlling the rate of discharge, discharge the capacitor
  • the resulting pixel voltage is a predetermined pixel voltage.
  • High voltage magnitude of the data signal Data may also be adjusted based on the set charge voltage, the predetermined voltage of the pixel obtained, like the discharge time T release.
  • the liquid crystal in the liquid crystal cell corresponding to the pixel circuit 100, the liquid crystal can be alternately flipped under the driving of the positive frame pixel voltage and the negative frame pixel voltage, so as to prevent the liquid crystal from being biased for too long under the same polarity voltage, thereby causing the characteristics thereof. damage.
  • the pixel circuit 100 of the embodiment shown in FIG. 1 may be corresponding to the pixel or sub-pixel setting of the display panel. For example, for each RGB pixel, each R sub-pixel, G sub-pixel, and B sub-pixel is respectively disposed as shown in FIG. 1 .
  • the pixel voltages of the pixel circuits 100 and the three pixel circuits 100 respectively provided to the R sub-pixels, the G sub-pixels, and the B sub-pixels may be the same or different. In the case where the pixel voltages supplied to the R sub-pixel, the G sub-pixel, and the B sub-pixel are the same, it is not necessary to perform voltage debugging on the basis of the common gamma voltage in order to obtain a predetermined sub-pixel transmittance.
  • FIG. 4 is a schematic diagram of a driving circuit of a pixel circuit array according to an embodiment of the invention
  • FIG. 5 is a block diagram showing a module structure of a pixel voltage control module according to an embodiment of the invention. 4 and 5, it will be understood that the driving control of the pixel circuit 100 of the embodiment of the present invention becomes easier to implement and the driving power consumption is lower.
  • the pixel circuit array 10 is arranged by a pixel circuit 100 of L rows ⁇ X columns. Forming, which may be formed on the TFT substrate, the structure of each pixel circuit 100 is substantially or completely the same as that of the pixel circuit 100 shown in FIG. 1, for illustrative purposes, wherein one of the N rows shown in FIG. 1 is given. Pixel circuit 100.
  • the corresponding pixel circuit array 10 is provided with a gate driving module 30, which respectively outputs L gate signals to the gate lines of the L rows, wherein Gate N represents the gate signals outputted in the Nth row gate lines (eg As shown in Fig. 2, Gate (N-1) indicates that the gate signal of the gate line of the (N-1)th row is output (as shown in Fig. 2).
  • the gate driving module 30 may be coupled to a timing controller (not shown) of the driving circuit and input signals such as stv (start signal of one frame image), cpv (column clock signal), and the like.
  • the corresponding pixel circuit array 10 is further provided with a pixel voltage control module 50, which respectively outputs X data signals Data to the data lines of the X columns, and the pixel voltage control module 50 and the timing controller of the driving circuit (not shown)
  • a digital signal such as sth (start signal of line data), cph (line clock signal), load (data signal output control signal), and the like are coupled and input.
  • pixel voltage control module 50 primarily includes shift register 510, pulse width controller 520, level shifter 530, and output buffer 540.
  • the shift register 510 can receive external sth, cph, load, etc. digital drive signals and temporarily store them, and can also receive Mini LVDS (Low Voltage Differential Signal) signals.
  • PWM controller 520 may also receive Mini LVDS (Low Voltage Differential Signaling) signal, and generating a pulse width modulated signal a discharge time, reflecting the pulse width modulated signal is a data signal
  • Data T control shift register 510 receives a discharge signal from the .
  • the pulse width modulation signal is level-converted in the level shifter 530, for example, to perform boost conversion, thereby obtaining a pulse width modulation signal of a predetermined level, that is, the data signal Data as shown in FIG.
  • the output buffer 540 outputs to the corresponding data line.
  • the driving control principle of the driving circuit for each pixel circuit in the pixel circuit array 10 is similar to that of FIG. 2.
  • the gate driving module 30 provides the gate signals Gate(N-1), Gate N, and the charging power source 20 provides Vcom or 2Vcom, and the pixel voltage is controlled.
  • Module 50 provides a data signal Data, such as a pulse width modulatable data signal Data. Thereby, each pixel circuit in the pixel circuit array 10 can be controlled to obtain a corresponding pixel voltage.
  • the driving circuit may include a charging power source 20, which is controlled by the signal POL and outputs a charging voltage of Vcom or 2Vcom; a specific structural example of the charging power source 20 is shown in FIG. 1 and will not be described herein. It should be understood that according to the capacitance C in the pixel circuit 100, it is required in the charging phase. To different charging voltages, the charging power source 20 can be configured to provide a charging voltage different from Vcom or 2Vcom.
  • the magnitude of the high level of the data signal Data may be predetermined, that is, the degree of opening of the transistor T3 in the discharge phase is substantially fixed, and the data based on the pulse width modulation is fixed when the degree of opening is fixed.
  • the signal Data is used to control the discharge time so that a pixel voltage level of a predetermined size can be achieved.
  • the level of the high level of the output data signal Data can also be controlled by the level shifter 530, so that the degree of opening of the transistor T3 in the control pixel circuit 100 can be adjusted, and the discharge rate can be controlled.
  • the discharge process can be finely controlled within a certain discharge time, and a pixel voltage level of a predetermined size is obtained from the charging voltage.
  • the degree of opening of the transistor T3 can be expressed by its equivalent resistance R.
  • the capacitor C and the resistor including the equivalent resistor R form an RC discharge circuit, and the smaller the equivalent resistance R, the transistor The greater the degree of opening of T3, the faster the discharge speed.
  • the equivalent resistance or impedance R of the transistor T3 at different gate-level biases can be obtained by software simulation, and the transistor T3 can be calculated at different turn-on times and/or different gate voltages. Under the condition, the capacitor C is discharged from a predetermined charging voltage to obtain a corresponding pixel voltage, and the pixel voltage control module 50 can control the output data signal Data based on the calculation result.
  • the deflection time of the liquid crystal in the liquid crystal cell driven by the pixel circuit array 10 is on the order of milliseconds, while the charging phase (eg, t1-t2) and the discharging phase described in the above embodiments ( For example, the time of t2-t3) is much smaller than the deflection time of the liquid crystal, for example, on the order of microseconds. Therefore, the charging and discharging processes in the pixel circuit of the embodiment of the present invention do not conflict with the yaw driving control of the liquid crystal.
  • the capacitor C is first charged to a voltage higher than the pixel voltage, and to some extent, an overdrive effect can be generated on the liquid crystal of the corresponding pixel, thereby facilitating the liquid crystal response.
  • the pixel circuit array 10 formed by the pixel circuits 100 of the above embodiment and the corresponding driving circuit can be used to form a display panel, and is particularly suitable for application to an ADS panel or In the TN panel.

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Abstract

提供一种像素电路及其驱动方法、驱动电路和显示装置，属于像素电路驱动技术领域。该像素电路（100）包括：电容（C）、电容充电晶体管（T1）、第一电容放电晶体管（T2）、第二电容放电晶体管（T3）；其中，该电容（C）在所述电容充电晶体管（T1）被开启时被充电至大于所述像素电压的第一电压；该电容（C）与第一电容放电晶体管（T2）、第二电容放电晶体管（T3）串联形成放电电路，该电容（C）在该第一电容放电晶体管（T2）和第二电容放电晶体管（T3）开启时被放电以使该电容（C）的两端电压从第一电压降至所述像素电压。本像素电路的像素电路阵列的驱动电路不需要对应设置Gamma电阻，结构简单，并且驱动功耗低。

Description

像素电路及其驱动方法、驱动电路、显示装置
相关申请的交叉引用
本申请要求于2015年12月16日向中国专利局提交的专利申请201510939086.9的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本发明属于像素电路驱动技术领域，涉及一种像素电路及其驱动方法、以及基于该像素电路形成的像素电路阵列的驱动电路和显示装置。
背景技术
显示器的玻璃基板上设置有薄膜晶体管(TFT)阵列，TFT阵列一般由若干按行和列排列的像素电路构成，对应每个像素设置相应的像素电路，像素电路提供相应的像素电压从而控制每个像素的显示。
现有的像素电路一般为1T1C结构，即基于一晶体管(例如TFT)加一电容形成，通过栅极驱动器提供的栅极信号(Gate)来控制晶体管T开启或关闭，电容C通过源极驱动控制器基于数据信号(Data)来进行充电，从而达到某一像素电压值。该像素电压可以用来驱动相应像素的液晶。
为实现不同的灰阶，像素电路需要提供不同大小的像素电压，即灰阶电压。而不同的灰阶电压的提供通常是由TFT阵列的Gamma电路和源驱动器实现的。具体地，需要通过Gamma电路给出多个固定的绑点电压，然后通过源驱动器内部的诸多个Gamma电阻进行精细分压，得到多个数字电压值(即Gamma参考电压)例如6Bit的电压值，然后进行数模转换，施加到相应像素电路的电容上以产生相应的像素电压。
这种像素电路的驱动的最大问题是会导致较大的逻辑功耗以及较复杂的TFT阵列的驱动电路；并且，由于RGB子像素的灰阶电压必须是共用的，实现8bit的电压值控制成本更高，且算法复杂、调试周期长。
发明内容
本发明的各实施例的目的之一在于，避免使用Gamma电阻来驱动像素电路，降低像素电路的驱动功耗。
为实现以上目的或者其他目的，本发明提供以下技术方案：
按照本发明的一方面，提供一种像素电路(100)，用于提供像素电压，该像素电路位于像素电路阵列(10)的第N行，该像素电路包括：电容(C)；电容充电晶体管(T1)，其用于为所述电容(C)充电，所述电容充电晶体管(T1)的栅端与第(N-1)行的栅线(110)电连接；第一电容放电晶体管(T2)，其栅端与第N行的栅线(120)电连接；以及第二电容放电晶体管(T3)，其栅端与数据线(130)电连接；所述电容在所述电容充电晶体管(T1)被开启时被充电至大于所述像素电压的第一电压；所述电容(C)与第一电容放电晶体管(T2)、第二电容放电晶体管(T3)串联形成放电电路，所述电容在所述第一电容放电晶体管和所述第二电容放电晶体管(T3)开启时被放电以使所述电容(C)的两端电压从所述第一电压降至所述像素电压。N为大于或等于2的整数。
根据本发明的一实施例的像素电路，通过至少控制所述电容(C)的放电时间(T放)来实现从所述第一电压降至所述像素电压。
在一些实施例中，所述数据线(130)的数据信号为脉宽调制信号，通过脉宽调制信号控制所述第二电容放电晶体管(T3)的开启时间从而控制所述放电时间(T放)。
根据本发明的又一实施例的像素电路，通过至少控制所述数据线(130)的电压来控制所述第二电容放电晶体管(T3)的开启程度，从而实现从所述第一电压降至所述像素电压。
根据本发明的还一实施例的像素电路，在正帧时，所述第一电压为2倍于液晶分子偏转参考电压(2Vcom)，所述像素电压为正帧像素电压；在负帧时，所述第一电压为液晶分子偏转参考电压(Vcom)，所述像素电压为负帧像素电压。
在之前所述任一实施例的像素电路中，所述电容充电晶体管(T1)的漏端与所述电容的第一端电连接，所述第一电容放电晶体管(T2)的源端与所述电容的第一端电连接，所述第一电容放电晶体管(T2)的漏端与所述第二电容放电晶体管(T3)的源端电连接。
在一些实施例中，所述像素电路(100)被分别对应RGB像素的R亚像素、G亚像素和B亚像素而设置，从而分别为R亚像素、G亚像素和B亚像素提供相应独立的所述像素电压。
在本发明的实施例中，像素电路阵列中的第1行像素电路可以具有与其它行的像素电路相同的电路结构，并且其中第1行像素电路中的电容充电晶体管的栅端接收STV信号(一帧图像的起始信号)。
按照本发明的又一方面，提供一种以上所述像素电路的驱动方法，包括：
充电阶段：通过所述第(N-1)行的栅线(110)的栅极信号(Gate(N-1))使所述充电晶体管(T1)开启，从而将所述电容充电至大于所述像素电压的第一电压；
放电阶段：通过所述第N行的栅线(120)的栅极信号(GateN)使所述第一电容放电晶体管(T2)开启、并通过所述数据线(130)的数据信号(Data)使所述第二电容放电晶体管(T3)开启，所述电容(C)放电使其两端电压从第一电压降至所述像素电压；
保持阶段：所述电容充电晶体管(T1)关闭且所述第一电容放电晶体管(T2)和第二电容放电晶体管(T3)的至少一个关闭，以保持该像素电压大小基本不变。
根据本发明一实施例的驱动方法，在正帧时，所述第一电压为2倍于公共电极上所偏置的液晶分子偏转参考电压(2Vcom)，所述像素电压为正帧像素电压；在负帧时，所述第一电压等于公共电极上所偏置的液晶分子偏转参考电压(Vcom)，所述像素电压为负帧像素电压。
根据本发明又一实施例的驱动方法，通过至少控制所述电容(C)的放电时间(T放)来实现从所述第一电压降至所述像素电压。
在一些实施例中，所述数据线(130)的数据信号为脉宽调制信号，通过脉宽调制信号控制所述第二电容放电晶体管(T3)的开启时间从而控制所述放电时间(T放)。
根据本发明还一实施例的驱动方法，通过至少控制所述数据线(130)的电压来控制所述第二电容放电晶体管(T3)的开启程度，从而实现从所述第一电压降至所述像素电压。
在之前所述任一实施例驱动方法中，所述充电阶段和/或放电阶段的时间在微秒数量级。
按照本发明的还一方面，一种像素电路阵列的驱动电路，该像素电路阵列包括按行和列排列的多个以上实施例所述及的任一种像素电路，其中所述驱动电路，包括：
充电电源(20)，其用于提供将所述电容(C)充电至大于所述像素电压的第一电压的充电电压；
栅驱动模块(30)，其用于为所述栅线(110，120)提供栅极信号；
像素电压控制模块(50)，其被配置为向所述数据线(130)提供使所述第二电容放电晶体管(T3)开启进而使所述电容(C)的两端电压从第一电压放电降至所述像素电压的数据信号(Data)。
根据本发明一实施例的驱动电路，所述像素电压控制模块(50)包括脉宽控制器(520)，其用于输出脉宽调制信号，脉宽调制信号的脉冲宽度被配置用来控制所述电容(C)的放电时间(T放)。
在一些实施例中，所述像素电压控制模块(50)包括电平转换器(530)，其用于控制所述脉宽调制信号的高电平的大小以控制所述第二电容放电晶体管(T3)的开启程度。
在一些实施例中，所述像素电压控制模块(50)还包括：移位寄存器(510)，其至少用于接收的数字驱动信号并暂时地存储；和输出缓存器(540)，其至少用于输出所述脉宽调制信号。
根据本发明又一实施例的驱动电路，其中，所述充电电源(20)包括第三晶体管(P1)和第四晶体管(P2)，所述第三晶体管(P1)和第四晶体管(P2)相互为互补型晶体管，所述第三晶体管(P1)的漏端和所述第四晶体管(P2)的漏端均电连接所述充电电源(20)的输出端，所述第三晶体管(P1)的栅端和所述第四晶体管(P2)的栅端受极性翻转控制信号控制。
在一些实施例中，在正帧时，所述第三晶体管(P1)开启并被输入2倍于公共电极上所偏置的液晶分子偏转参考电压(2Vcom)；在负帧时，所述第四晶体管(P2)开启并被输入公共电极上所偏置的液晶分子偏转参考电压(Vcom)。
按照本发明的再一方面，提供一种显示装置，其包括：像素电路阵列，其包括按行和列排列的多个以上所述及的像素电路；以及以上所述及的驱动电路。
本发明提供的实施例的技术效果是，像素电路阵列的驱动电路不 需要对应设置Gamma电阻，结构简单，驱动电路更容易实现，并且驱动过程功耗低。并且，充电阶段首先将电容C充电至一高于像素电压的电压，在一定程度上可以对相应像素的液晶产生过驱(overdrive)效果，从而有利于加快液晶响应。
附图说明
从结合附图的以下详细说明中，将会使本发明的上述和其他目的及优点更加完整清楚。
图1是按照本发明一实施例的像素电路的基本结构示意图。
图2是按照本发明一实施例的像素电路的驱动原理示意图。
图3是本发明实施例使用脉宽调制技术来控制像素电压的原理示意图。
图4是按照本发明一实施例的像素电路阵列的驱动电路示意图。
图5是按照本发明一实施例的像素电压控制模块的模块结构示意图。
具体实施方式
现在将参照附图更加完全地描述本发明，附图中示出了本发明的示例性实施例。但是，本发明可按照很多不同的形式实现，并且不应该被理解为限制于这里阐述的实施例。相反，提供这些实施例使得本公开变得彻底和完整，并将本发明的构思完全传递给本领域技术人员。附图中，相同的标号指代相同的元件或部件，因此，将省略对它们的描述。
图1所示为按照本发明一实施例的像素电路的基本结构示意图。在该实施例中，图1示意出了一个像素电路100，像素电路100主要包括电容C、晶体管T1-T3。多个像素电路100可形成像素电路阵列，例如，形成在TFT玻璃基板上的像素电路阵列，该像素电路阵列可以是用来形成显示面板的核心部件之一，可以控制液晶模块。每个像素电路100可以控制单个像素或亚像素的显示，具体通过电容C提供相应的像素电压来控制单个像素或亚像素的灰阶。
电容C可以是由TFT基板上的像素电极与TFT基板上方的CF(彩膜)基板上的公共电极形成的等效电容(也称作“液晶电容”)，也可 以是设置于像素电路中的存储电容。该像素电极可以理解为本发明实施例的像素电路100的电容C的第一端。在该实施例中，用于形成电容C的另一端(第二端)的公共电极具有预定的电压Vcom(如图1所示)，其为液晶分子偏转参考电压，为像素电极的像素电压极性提供参考。如果像素电极的像素电压大于Vcom，该像素电压为正极性电压，如果像素电极的像素电压小于Vcom，该像素电压为负极性电压。像素电极和公共电极均可以通过ITO材料构图形成。
继续如图1所示，该像素电路100可以是构成L行X列的像素电路阵列的其中一个单元，像素电路100位于阵列的第N行，N小于等于L，但是，应当理解到，像素电路100在像素电路阵列中的具体位置不是限制性的。
晶体管T1为电容充电晶体管，其漏端电连接电容C的第一端，即连接像素电极，其栅端电连接第(N-1)行的栅线(或扫描线)110，其源端电连接外部的充电电源20。外部的充电电源包括串联的晶体管P2和P1，晶体管P2和P1为互补型晶体管，晶体管P2和P1的栅端均连接POL(极性翻转控制)信号，这样，晶体管P2开启时晶体管P1关闭，晶体管P1开启时晶体管P2关闭。从晶体管P1的源端输入电压2Vcom，从晶体管P2的源端输入电压Vcom。晶体管P2的漏端和晶体管P1的漏端电连接在一起并形成充电电源20的输出端。在晶体管P1开启时，充电电源20输出2Vcom的充电电压，在晶体管P2开启时输出Vcom的充电电压。
晶体管T1受栅线110传输的信号Gate(N-1)所控制。在晶体管T1开启时，表示进入电容充电阶段，从而可以从充电电源20对电容C进行充电，此时，晶体管T1的源端可接入外部的充电电源20的输出。当充电电源的晶体管P1导通时，晶体管T1的源端被接入电压2Vcom并可以将电容C的第一端充电至约2Vcom的电压水平，当充电电源的晶体管P2导通时，晶体管T1的源端被接入电压Vcom并可以将电容C的第一端充电至约Vcom的电压水平。因此，电容C的第一端可以被充电至Vcom或2Vcom的电压水平。
继续如图1所示，晶体管T2和T3为电容放电晶体管，晶体管T2的栅端电连接第N行的栅线(或扫描线)120，其源端电连接电容C的第一端，其漏端电连接放电晶体管T3的源端；晶体管T3的漏端可 以接地GND，晶体管T3的栅端电连接数据线130。因此，电容C与电容放电晶体管T2、电容放电晶体管T3串联形成放电电路，在电容放电晶体管T2和T3均开启时，对电容C可经由该放电电路进行放电。晶体管T2受栅线120传输的信号GateN所控制，晶体管T3受数据线130传输的数据信号Data所控制。在该实施例中，在晶体管T2和晶体管T3均开启时，表示像素电路100进入放电阶段，进一步通过控制电容放电晶体管T3的开启时间或开启程度来控制电容C的放电时间和/或放电速度，从而能控制放电后的电容C的电压，即像素电压。通过控制放电过程来控制像素电压的具体原理将在其后驱动原理中示例详细说明。
晶体管T3的开启程度可以以其等效电阻R大小来表示，即晶体管T3的开启程度反映其等效电阻R的大小，开启程度越高，其等效电阻越小。在放电电路中，电容C与包括该等效电阻R的电阻形成RC放电电路，等效电阻R越小，表示晶体管T3的开启程度越大，放电速度越快。
图2所示为按照本发明一实施例的像素电路的驱动原理示意图。结合图1和图2，示例说明图1所示实施例的像素电路的工作原理以及其驱动方法。在该实施例中，使用双帧信号来驱动液晶单元，也即使用正帧和负帧来交替驱动液晶单元的每个像素，这有利于避免像元滞留和最终导致图像永久性变差。在正帧时，对像素施加正电场而进行正极性驱动，此时，像素电极被偏置正极性电压，即被偏置大于公共电极电压Vcom的电压；在负帧时，对像素施加负电场而进行负极性驱动，此时，像素电极被偏置负极性电压，即被偏置小于公共电极电压Vcom的电压。
如图2(a)所示，其表示负帧情况下的像素电压控制，其中可以得到负帧像素电压，即负极性电压。首先，由于充电晶体管T1的栅端电连接第(N-1)行的栅线110，从而其被偏置如图2(a)所示的信号Gate(N-1)，晶体管T1的栅端在t1时刻偏置高电平而使得晶体管T1开启，表示进入充电阶段。在t2时刻，信号Gate(N-1)变为低电平，晶体管T1关闭，充电阶段结束。在t1到t2时间段，充电电源20输出电压Vcom，电容C的第一端从0V被充电至电压Vcom，电压Vcom大于电容最终需要放电后得到的负极性电压。并且在t1到t2时间段， 信号GateN为低电平，电容C的放电电路不导通。
同时在t2时刻，在逐行扫描的情况下，栅线120的信号GateN变为高电平，晶体管T2开启，并且，在t2时刻，数据线130的信号Data变为高电平，晶体管T3开启，表示开始进入放电阶段，放电电路导通，从而电容C的第一端从电压Vcom开始放电。
在t3时刻，数据线130的信号Data变为低电平，晶体管T3关闭，放电结束，电容C被放电至某一预定的负帧像素电压(其小于Vcom)，并且在其后t3至t5时刻，该负帧像素电压被基本保持，从而对相应的像素产生负极性驱动，使能液晶翻转。负帧像素电压相对于电压Vcom的差值决定液晶分子的翻转程度，从而控制该像素的灰阶。
因此，t2时刻至t3时刻为放电时间，即T放，在该实施例中，通过控制放电时间T放的长短，可以控制电容C的放电电荷量，从而可以控制负帧像素电压的大小，因此，可以控制得到预定想要的负帧像素电压。
以上图2(a)所示的负帧情形下，驱动过程主要包括t1至t2时间段的充电阶段、t2至t3时间段的放电阶段、t3至t5时间段为保持阶段。
如图2(b)所示，其表示正帧情况下像素电压控制，以得到正帧像素电压，即正极性电压。其工作原理与负帧情况下基本相同，也即，包括t1至t2时间段的充电阶段、t2至t3时间段的放电阶段、t3至t5时间段为保持阶段。所不同的是，在充电阶段，充电电源20输出电压2Vcom，电容C的第一端从0V充电至电压2Vcom，即像素电极被充电至电压2Vcom，电压2Vcom大于电容C放电后的预定想要得到的正帧像素电压。在放电阶段，电容C的第一端的电压从2Vcom下降至预定想要的正帧像素电压，该正帧像素电压大于公共电极的电压Vcom，其可以在Vcom至2Vcom的范围内设置。并且在其后t3至t5时刻，该正帧像素电压被基本保持，从而对相应的像素产生正极性驱动，使能液晶翻转。正帧像素电压相对于Vcom的差值决定液晶分子的翻转程度，从而控制该像素的灰阶。
在一实施例中，数据信号Data为脉宽调制信号，其使用脉宽调制技术来基于充电电压、预定得到的像素电压等来对脉宽进行调制，从而控制T放的时间长短，使电容放电后得到的像素电压为预定得到的像素电压。
图3所示为本发明实施例使用脉宽调制技术来控制像素电压的原理示意图。如图3所示，Data1、Data2和Data3为脉冲形式的数据信号，它们分别具有不同的脉宽T1、T2、T3，V1为像素电极的被充电后的充电电压，V21为对应数据信号Data1控制放电过程后得到的像素电极的像素电压，V22为对应数据信号Data2控制放电过程后得到的像素电极的像素电压，V23为对应数据信号Data3控制放电过程后得到的像素电极的像素电压。可以看到，在数据信号Data1、Data2和Data3被调制为具有不同脉宽的情况下，可以控制得到相应的不同像素电压。应当理解，以上仅是示例调制得到三个不同脉宽的数据信号而得到3个不同的像素电压，根据示例教导，在建立的电容C的放电模型的基础上，可以根据脉宽调制技术获得更多的像素电压。因此，只需要控制数据信号的脉宽即可实现，更多像素电压获得变得更简单。
在又一实施例中，在放电时间T放固定的情况下，也可以控制数据信号Data的高电平的电压大小来控制电容放电晶体管T3的开启程度，从而控制放电的速度，使电容放电后得到的像素电压为预定得到的像素电压。数据信号Data的高电平的电压大小也可以基于充电电压、预定得到的像素电压、放电时间T放等来调节设置。
在以上实施例中，像素电路100对应的液晶单元中，其液晶可以在正帧像素电压和负帧像素电压驱动下交替翻转，避免液晶在同一极性电压下偏置时间过久而导致其特性破坏。
图1所示实施例的像素电路100可以对应显示面板的像素或亚像素设置，例如，对于每个RGB像素，对应每个R亚像素、G亚像素、B亚像素分别设置如图1所示的像素电路100，三个像素电路100分别独立给R亚像素、G亚像素、B亚像素提供的像素电压可以相同或不相同。在向R亚像素、G亚像素、B亚像素提供的像素电压相同的情形中，无需为了得到预定亚像素透过率而在共同gamma电压基础上进行电压调试。
图4所示为按照本发明一实施例的像素电路阵列的驱动电路示意图，图5所示为按照本发明一实施例的像素电压控制模块的模块结构示意图。结合图4和图5将理解本发明实施例的像素电路100的驱动控制变得更容易实现且驱动功耗更低。
如图4所示，像素电路阵列10由L行×X列的像素电路100排列 形成，其可以形成在TFT基板上，每个像素电路100的结构与图1所示的像素电路100基本或完全相同，为示例说明，其中给出了图1所示的位于第N行的一个像素电路100。
驱动电路中，对应像素电路阵列10设置有栅驱动模块30，其分别输出L个栅极信号至L行的栅线上，其中Gate N即表示输出在第N行栅线的栅极信号(如图2所示)，Gate(N-1)即表示输出在第(N-1)行栅线的栅极信号(如图2所示)。栅驱动模块30可以与驱动电路的计时控制器(图中未示出)耦接并被输入诸如stv(一帧图像的起始信号)、cpv(列时钟脉冲信号)等信号。
对应像素电路阵列10还设置有像素电压控制模块50，其分别输出X个数据信号Data至X列的数据线上，像素电压控制模块50可以与驱动电路的计时控制器(图中未示出)耦接并被输入诸如sth(行数据的开始信号)、cph(行时钟脉冲信号)、load(数据信号输出控制信号)等数字信号。
参见图5，在该实施例中，像素电压控制模块50主要地包括移位寄存器510、脉宽控制器520、电平转换器530和输出缓存器540。移位寄存器510可以接收外部的sth、cph、load等数字驱动信号并暂时地存储，还可以接收Mini LVDS(低压差分信号)信号。脉宽控制器520也可以接收Mini LVDS(低压差分信号)信号，并且从移位寄存器510接收信号来生成脉宽调制信号，脉宽调制信号的脉宽反映被数据信号Data控制的放电时间T放。在实施例中，脉宽调制信号在电平转换器530中进行电平转换，例如进行升压转换，从而得到预定电平的脉宽调制信号，即如图2所示的数据信号Data，并经过输出缓存器540输出至相应的数据线上。
驱动电路对像素电路阵列10中每个像素电路的驱动控制原理如图2类似，栅驱动模块30提供栅极信号Gate(N-1)、Gate N，充电电源20提供Vcom或2Vcom，像素电压控制模块50提供数据信号Data，例如脉宽可调制的数据信号Data。从而可以对像素电路阵列10中各个像素电路进行控制，得到相应的像素电压。
驱动电路可包括充电电源20，其受信号POL控制并输出Vcom或2Vcom的充电电压；充电电源20的具体结构示例如图1所示，在此不再赘述。应当理解，根据像素电路100中的电容C在充电阶段需要得 到的不同大小的充电电压，可以配置充电电源20来提供不同于Vcom或2Vcom的充电电压。
在一实施例中，数据信号Data的高电平的大小可以是预定不变的，也即晶体管T3在放电阶段的开启程度是基本固定，在开启程度固定的情况下，基于脉冲宽度调制的数据信号Data来控制放电时间，从而可以达到预定大小的像素电压水平。在其他替代性实施例中，也可以通过电平转换器530来控制输出的数据信号Data的高电平的大小，从而可以调节控制像素电路100中的晶体管T3的开启程度，进而可以控制放电速度，可以在一定放电时间内精细控制放电过程，从充电电压得到预定大小的像素电压水平。
在本文中，晶体管T3的开启程度可以以其等效电阻R大小来表示，在放电电路中，电容C与包括该等效电阻R的电阻形成RC放电电路，等效电阻R越小，表示晶体管T3的开启程度越大，放电速度越快。基于晶体管T3参数等，可以通过软件模拟得到晶体管T3在其栅端在不同大小电平偏置下的等效电阻或阻抗R，进而可以计算到晶体管T3在不同开启时间和/或不同栅极电压条件下电容C从某一预定充电电压放电得到相应的像素电压，像素电压控制模块50可以基于此计算结果来控制输出数据信号Data。
因此，将理解到，在像素电路阵列10的外围驱动电路中，并不需要提供不同大小的Gamma参考电压，因此，不需要设置复杂的Gamma电阻来驱动像素电路阵列10，不需要提供不同的绑点电压，当然也可以不设置Gamma电路，驱动电路更容易实现，电路结构简单，并且运行的逻辑功耗也将得到大大的降低。
进一步需要说明的是，在TFT-LCD中，像素电路阵列10所驱动的液晶单元中的液晶的偏转时间在毫秒数量级，而以上实施例所述的充电阶段(例如t1-t2)、放电阶段(例如t2-t3)的时间远小于液晶的偏转时间，例如在微秒数量级，因此，本发明实施例的像素电路中的充电和放电过程并不会与液晶的偏转驱动控制相冲突，相反地，充电阶段首先将电容C充电至一高于像素电压的电压，在一定程度上可以对相应像素的液晶产生过驱(overdrive)效果，从而有利于加快液晶响应。
以上实施例的像素电路100排列形成的像素电路阵列10、以及对应的驱动电路可以用来形成显示面板，尤其地适用应用于ADS面板或 TN面板中。
以上示例主要说明了本发明的像素电路及其驱动方法和驱动电路。尽管只对其中一些本发明的实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (21)

  1. 一种像素电路(100)，用于提供像素电压，该像素电路位于像素电路阵列(10)的第N行，该像素电路包括：
    电容(C)；
    电容充电晶体管(T1)，其用于为所述电容(C)充电，所述电容充电晶体管(T1)的栅端与第(N-1)行的栅线(110)电连接；
    第一电容放电晶体管(T2)，其栅端与第N行的栅线(120)电连接；以及
    第二电容放电晶体管(T3)，其栅端与数据线(130)电连接；
    其中，所述电容在所述电容充电晶体管(T1)被开启时被充电至大于所述像素电压的第一电压；所述电容(C)与第一电容放电晶体管(T2)、第二电容放电晶体管(T3)串联形成放电电路，所述电容在所述第一电容放电晶体管(T2)和所述第二电容放电晶体管(T3)开启时被放电以使所述电容(C)的两端电压从所述第一电压降至所述像素电压；
    其中，N为大于或等于2的整数。
  2. 如权利要求1所述的像素电路，其中通过至少控制所述电容(C)的放电时间(T放)来实现从所述第一电压降至所述像素电压。
  3. 如权利要求2所述的像素电路，其中所述数据线(130)的数据信号为脉宽调制信号，通过脉宽调制信号控制所述第二电容放电晶体管(T3)的开启时间从而控制所述放电时间(T放)。
  4. 如权利要求1所述的像素电路，其中通过至少控制所述数据线(130)的电压来控制所述第二电容放电晶体管(T3)的开启程度，从而实现从所述第一电压降至所述像素电压。
  5. 如权利要求1所述的像素电路，其中，在正帧时，所述第一电压为2倍于液晶分子偏转参考电压(2Vcom)，所述像素电压为正帧像素电压；在负帧时，所述第一电压为液晶分子偏转参考电压(Vcom)，所述像素电压为负帧像素电压。
  6. 如权利要求1所述的像素电路，其中所述电容充电晶体管(T1)的漏端与所述电容的第一端电连接，所述第一电容放电晶体管(T2)的源端与所述电容的第一端电连接，所述第一电容放电晶体管(T2) 的漏端与所述第二电容放电晶体管(T3)的源端电连接。
  7. 如权利要求1所述的像素电路，其中所述像素电路(100)被分别对应RGB像素的R亚像素、G亚像素和B亚像素而设置，从而分别为R亚像素、G亚像素和B亚像素提供相应独立的所述像素电压。
  8. 如权利要求1所述的像素电路，其中所述像素电路阵列(10)中的第1行像素电路具有与其它行的像素电路相同的电路结构，并且其中第1行像素电路中的电容充电晶体管(T1)的栅端接收STV信号。
  9. 一种如权利要求1所述像素电路的驱动方法，包括：
    充电阶段：通过所述第(N-1)行的栅线(110)的栅极信号(Gate(N-1))使所述电容充电晶体管(T1)开启，从而将所述电容充电至大于所述像素电压的第一电压；
    放电阶段：通过所述第N行的栅线(120)的栅极信号(Gate N)使所述第一电容放电晶体管(T2)开启、并通过所述数据线(130)的数据信号(Data)使所述第二电容放电晶体管(T3)开启，所述电容(C)放电使其两端电压从第一电压降至所述像素电压；
    保持阶段：所述电容充电晶体管(T1)关闭且所述第一电容放电晶体管(T2)和第二电容放电晶体管(T3)的至少一个关闭，以保持该像素电压大小基本不变。
  10. 如权利要求9所述的驱动方法，其中，在正帧时，所述第一电压为2倍于公共电极上所偏置的液晶分子偏转参考电压(2Vcom)，所述像素电压为正帧像素电压；在负帧时，所述第一电压等于公共电极上所偏置的液晶分子偏转参考电压(Vcom)，所述像素电压为负帧像素电压。
  11. 如权利要求9所述的驱动方法，其中通过至少控制所述电容(C)的放电时间(T放)来实现从所述第一电压降至所述像素电压。
  12. 如权利要求11所述的驱动方法，其中所述数据线(130)的数据信号为脉宽调制信号，通过脉宽调制信号控制所述第二电容放电晶体管(T3)的开启时间从而控制所述放电时间(T放)。
  13. 如权利要求9所述的驱动方法，其中通过至少控制所述数据线(130)的电压来控制所述第二电容放电晶体管(T3)的开启程度，从而实现从所述第一电压降至所述像素电压。
  14. 如权利要求9所述的驱动方法，其中所述充电阶段和/或放电 阶段的时间在微秒数量级。
  15. 一种像素电路阵列的驱动电路，该像素电路阵列包括按行和列排列的多个如权利要求1至8中任一项所述的像素电路，其中所述驱动电路，包括：
    充电电源(20)，其用于提供将所述电容(C)充电至大于所述像素电压的第一电压的充电电压；
    栅驱动模块(30)，其用于为所述栅线(110，120)提供栅极信号；
    像素电压控制模块(50)，其被配置为向所述数据线(130)提供使所述第二电容放电晶体管(T3)开启进而使所述电容(C)的两端电压从第一电压放电降至所述像素电压的数据信号(Data)。
  16. 如权利要求15所述的驱动电路，其中所述像素电压控制模块(50)包括脉宽控制器(520)，其用于输出脉宽调制信号，其中，脉宽调制信号的脉冲宽度被配置用来控制所述电容(C)的放电时间(T放)。
  17. 如权利要求16所述的驱动电路，其中所述像素电压控制模块(50)包括电平转换器(530)，其用于控制所述脉宽调制信号的高电平的大小以控制所述第二电容放电晶体管(T3)的开启程度。
  18. 如权利要求17所述的驱动电路，其中所述像素电压控制模块(50)还包括：
    移位寄存器(510)，其至少用于接收数字驱动信号并暂时地存储；和
    输出缓存器(540)，其至少用于输出所述脉宽调制信号。
  19. 如权利要求15所述的驱动电路，其中所述充电电源(20)包括第三晶体管(P1)和第四晶体管(P2)，所述第三晶体管(P1)和第四晶体管(P2)相互为互补型晶体管，所述第三晶体管(P1)的漏端和所述第四晶体管(P2)的漏端均电连接所述充电电源(20)的输出端，所述第三晶体管(P1)的栅端和所述第四晶体管(P2)的栅端受极性翻转控制信号控制。
  20. 如权利要求19所述的驱动电路，其中，在正帧时，所述第三晶体管(P1)开启并被输入2倍于公共电极上所偏置的液晶分子偏转参考电压(2Vcom)；在负帧时，所述第四晶体管(P2)开启并被输入公共电极上所偏置的液晶分子偏转参考电压(Vcom)。
  21. 一种显示装置，包括：
    像素电路阵列，其包括按行和列排列的多个如权利要求1至8中任一项所述的像素电路；以及如权利要求15至20中任一项所述的驱动电路。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405424B (zh) 2015-12-16 2018-12-28 京东方科技集团股份有限公司 像素电路及其驱动方法、驱动电路、显示装置
CN106297706B (zh) 2016-09-01 2017-10-31 京东方科技集团股份有限公司 像素单元、显示基板、显示设备、驱动像素电极的方法
CN107301847B (zh) * 2017-06-29 2018-08-28 惠科股份有限公司 一种显示面板的驱动方法、驱动装置及显示装置
US10345667B1 (en) * 2017-12-29 2019-07-09 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device
CN108766377B (zh) * 2018-05-22 2020-12-18 京东方科技集团股份有限公司 显示面板和显示装置
CN111696464B (zh) * 2019-03-13 2022-03-18 重庆京东方显示技术有限公司 信号线电容补偿电路和显示面板
CN111477192B (zh) * 2020-05-25 2022-04-15 京东方科技集团股份有限公司 调节方法、调节模组和显示装置
CN112201213B (zh) * 2020-10-22 2022-11-04 昆山龙腾光电股份有限公司 像素电路与显示装置
WO2023102996A1 (zh) * 2021-12-07 2023-06-15 惠州华星光电显示有限公司 显示器的驱动方法及显示器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6172663B1 (en) * 1995-03-14 2001-01-09 Sharp Kabushiki Kaisha Driver circuit
US20100123693A1 (en) * 2008-11-14 2010-05-20 Kabushiki Kaisha Toshiba Data line driver
CN104050940A (zh) * 2014-03-12 2014-09-17 友达光电股份有限公司 液晶显示器的像素电路及其控制方法
CN104537997A (zh) * 2015-01-04 2015-04-22 京东方科技集团股份有限公司 一种像素电路及其驱动方法和显示装置
CN105405424A (zh) * 2015-12-16 2016-03-16 京东方科技集团股份有限公司 像素电路及其驱动方法、驱动电路、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060021055A (ko) * 2004-09-02 2006-03-07 삼성전자주식회사 액정 표시 장치, 액정 표시 장치용 구동 장치 및 방법
US20070166417A1 (en) 2005-11-29 2007-07-19 Palu Afa K Formulation and Methods for Use of Morinda Citrifolia Seed Oil
KR20080066308A (ko) * 2007-01-12 2008-07-16 삼성전자주식회사 표시패널, 이의 검사방법 및 이의 제조방법
JP5238230B2 (ja) * 2007-11-27 2013-07-17 ルネサスエレクトロニクス株式会社 ドライバ及び表示装置
CN101963728A (zh) * 2009-07-24 2011-02-02 瀚宇彩晶股份有限公司 液晶显示器
CN102063878A (zh) * 2009-11-17 2011-05-18 群康科技(深圳)有限公司 液晶显示装置
TWI534789B (zh) * 2013-09-13 2016-05-21 國立交通大學 一種主動矩陣顯示器裝置的畫素電路及其驅動方法
CN105047166A (zh) 2015-08-28 2015-11-11 深圳市华星光电技术有限公司 液晶显示面板驱动方法及液晶显示装置
CN105096807B (zh) * 2015-09-06 2017-09-29 京东方科技集团股份有限公司 时序控制单元、显示面板及驱动方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6172663B1 (en) * 1995-03-14 2001-01-09 Sharp Kabushiki Kaisha Driver circuit
US20100123693A1 (en) * 2008-11-14 2010-05-20 Kabushiki Kaisha Toshiba Data line driver
CN104050940A (zh) * 2014-03-12 2014-09-17 友达光电股份有限公司 液晶显示器的像素电路及其控制方法
CN104537997A (zh) * 2015-01-04 2015-04-22 京东方科技集团股份有限公司 一种像素电路及其驱动方法和显示装置
CN105405424A (zh) * 2015-12-16 2016-03-16 京东方科技集团股份有限公司 像素电路及其驱动方法、驱动电路、显示装置

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