WO2017092286A1 - 恒压输出电路、反激开关电源及其电子设备 - Google Patents

恒压输出电路、反激开关电源及其电子设备 Download PDF

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Publication number
WO2017092286A1
WO2017092286A1 PCT/CN2016/086524 CN2016086524W WO2017092286A1 WO 2017092286 A1 WO2017092286 A1 WO 2017092286A1 CN 2016086524 W CN2016086524 W CN 2016086524W WO 2017092286 A1 WO2017092286 A1 WO 2017092286A1
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WIPO (PCT)
Prior art keywords
circuit
output
fot
constant voltage
comparator
Prior art date
Application number
PCT/CN2016/086524
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English (en)
French (fr)
Inventor
陈建忠
杨寄桃
Original Assignee
深圳创维－Rgb电子有限公司
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Filing date
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Application filed by 深圳创维－Rgb电子有限公司 filed Critical 深圳创维－Rgb电子有限公司
Priority to AU2016310326A priority Critical patent/AU2016310326B2/en
Priority to US15/494,818 priority patent/US9948191B2/en
Publication of WO2017092286A1 publication Critical patent/WO2017092286A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the field of power circuits, in particular to a constant voltage output circuit, a flyback switching power supply and an electronic device thereof.
  • the high-voltage electrolytic capacitor causes the current in the circuit to lead the voltage, so that the current and voltage cannot be supplied in the same phase, resulting in wasted power.
  • the main object of the present invention is to provide a constant voltage output circuit, a flyback switching power supply, and an electronic device thereof.
  • the utility model aims to realize the function of stably outputting a constant voltage signal by the constant voltage output circuit after the high voltage electrolytic capacitor is omitted.
  • the present invention provides a constant voltage output circuit including a power supply circuit, LM-FOT (Line-modulated) Fixed-Off-Time, line voltage modulation fixed off time) control circuit, switching circuit, transformer;
  • LM-FOT Line-modulated
  • Fixed-Off-Time Line voltage modulation fixed off time
  • An output end of the power circuit is respectively connected to a first input end of the LM-FOT control circuit and one end of a primary winding of the transformer; and a control end of the LM-FOT control circuit and a receiving circuit of the switch circuit a terminal connection, a second input end of the LM-FOT control circuit is connected to an output end of the switch circuit; an input end of the switch circuit is connected to another end of a primary winding of the transformer; One end of the secondary winding is an output end of the constant voltage output circuit, and the other end of the secondary winding of the transformer is grounded; the LM-FOT control circuit controls the fixed switching of the switching circuit according to a voltage signal output by the power supply circuit Break time, realize the constant voltage output of the entire constant voltage output circuit.
  • the constant voltage output circuit further includes a sampling circuit; a signal collecting end of the sampling circuit is connected to an output end of the power circuit, and a sampling signal output end of the sampling circuit and the LM-FOT control circuit The first input is connected.
  • the constant voltage output circuit further includes a constant voltage feedback circuit; an input end of the constant voltage feedback circuit is connected to an output end of the constant voltage output circuit, and an output end of the constant voltage feedback circuit and the LM - The feedback terminal of the FOT control circuit is connected.
  • the constant voltage output circuit further includes a voltage stabilizing circuit; one end of the voltage stabilizing circuit is connected to one end of the secondary winding of the transformer, and the other end of the voltage stabilizing circuit is the constant voltage output circuit Output.
  • the switch circuit includes a first enhancement type NMOS transistor, a first resistor; a drain of the first enhancement type NMOS transistor is an input end of the switch circuit, and a gate of the first enhancement type NMOS transistor is a gate a controlled end of the switching circuit, a source of the first enhancement type NMOS transistor is connected to one end of the first resistor; a connection node of the first enhancement type NMOS transistor and the first resistor is At the output of the switching circuit, the other end of the first resistor is grounded.
  • the LM-FOT control circuit includes a multiplier, an LM-FOT modulator, a flip-flop, a driver first comparator, and a first capacitor; a first input of the multiplier is the LM-FOT control circuit a first input end, the first output of the multiplier is coupled to an inverting input of the first comparator, and a connection node of the multiplier and the first comparator is used to introduce a first reference a second output of the multiplier connected to the second signal end of the LM-FOT modulator;
  • the non-inverting input terminal of the first comparator is a second input end of the LM-FOT control circuit, and the output end of the first comparator is respectively connected to a fourth signal end of the LM-FOT modulator a second signal end of the flip-flop is connected; a first signal end of the LM-FOT modulator is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the LM-FOT modulator is The three signal terminals are connected to the first signal end of the flip flop; the output end of the flip flop is connected to one end of the driver, and the other end of the driver is the control end of the LM-FOT control circuit.
  • the LM-FOT control circuit further includes a second comparator; an inverting input terminal of the second comparator is configured to introduce a second reference voltage, and a non-inverting input terminal of the second comparator A non-inverting input of a comparator is coupled, and an output of the second comparator is coupled to a fifth signal terminal of the LM-FOT modulator.
  • a second comparator an inverting input terminal of the second comparator is configured to introduce a second reference voltage, and a non-inverting input terminal of the second comparator A non-inverting input of a comparator is coupled, and an output of the second comparator is coupled to a fifth signal terminal of the LM-FOT modulator.
  • the LM-FOT control circuit further includes a third comparator; a non-inverting input of the third comparator is configured to introduce a third reference voltage, and an inverting input end of the third comparator is the LM a feedback terminal of the FOT control circuit, the output of the third comparator being coupled to the second input of the multiplier.
  • a third comparator a non-inverting input of the third comparator is configured to introduce a third reference voltage
  • an inverting input end of the third comparator is the LM a feedback terminal of the FOT control circuit, the output of the third comparator being coupled to the second input of the multiplier.
  • the present invention also provides a flyback switching power supply including the above-described constant voltage output circuit, the constant voltage output circuit including a power supply circuit, LM-FOT (Line-modulated Fixed-Off-Time, line voltage modulation fixed off time) control circuit, switching circuit, transformer;
  • LM-FOT Line-modulated Fixed-Off-Time, line voltage modulation fixed off time
  • An output end of the power circuit is respectively connected to a first input end of the LM-FOT control circuit and one end of a primary winding of the transformer; and a control end of the LM-FOT control circuit and a receiving circuit of the switch circuit a terminal connection, a second input end of the LM-FOT control circuit is connected to an output end of the switch circuit; an input end of the switch circuit is connected to another end of a primary winding of the transformer; One end of the secondary winding is an output end of the constant voltage output circuit, and the other end of the secondary winding of the transformer is grounded; the LM-FOT control circuit controls the fixed switching of the switching circuit according to a voltage signal output by the power supply circuit Break time, realize the constant voltage output of the entire constant voltage output circuit.
  • the constant voltage output circuit further includes a sampling circuit; a signal collecting end of the sampling circuit is connected to an output end of the power circuit, and a sampling signal output end of the sampling circuit and the LM-FOT control circuit The first input is connected.
  • the constant voltage output circuit further includes a constant voltage feedback circuit; an input end of the constant voltage feedback circuit is connected to an output end of the constant voltage output circuit, and an output end of the constant voltage feedback circuit and the LM - The feedback terminal of the FOT control circuit is connected.
  • the constant voltage output circuit further includes a voltage stabilizing circuit; one end of the voltage stabilizing circuit is connected to one end of the secondary winding of the transformer, and the other end of the voltage stabilizing circuit is the constant voltage output circuit Output.
  • the switch circuit includes a first enhancement type NMOS transistor, a first resistor; a drain of the first enhancement type NMOS transistor is an input end of the switch circuit, and a gate of the first enhancement type NMOS transistor is a gate a controlled end of the switching circuit, a source of the first enhancement type NMOS transistor is connected to one end of the first resistor; a connection node of the first enhancement type NMOS transistor and the first resistor is At the output of the switching circuit, the other end of the first resistor is grounded.
  • the LM-FOT control circuit includes a multiplier, an LM-FOT modulator, a flip-flop, a driver first comparator, and a first capacitor; a first input of the multiplier is the LM-FOT control circuit a first input end, the first output of the multiplier is coupled to an inverting input of the first comparator, and a connection node of the multiplier and the first comparator is used to introduce a first reference a second output of the multiplier connected to the second signal end of the LM-FOT modulator;
  • the non-inverting input terminal of the first comparator is a second input end of the LM-FOT control circuit, and the output end of the first comparator is respectively connected to a fourth signal end of the LM-FOT modulator a second signal end of the flip-flop is connected; a first signal end of the LM-FOT modulator is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the LM-FOT modulator is The three signal terminals are connected to the first signal end of the flip flop; the output end of the flip flop is connected to one end of the driver, and the other end of the driver is the control end of the LM-FOT control circuit.
  • the LM-FOT control circuit further includes a second comparator; an inverting input terminal of the second comparator is configured to introduce a second reference voltage, and a non-inverting input terminal of the second comparator A non-inverting input of a comparator is coupled, and an output of the second comparator is coupled to a fifth signal terminal of the LM-FOT modulator.
  • a second comparator an inverting input terminal of the second comparator is configured to introduce a second reference voltage, and a non-inverting input terminal of the second comparator A non-inverting input of a comparator is coupled, and an output of the second comparator is coupled to a fifth signal terminal of the LM-FOT modulator.
  • the LM-FOT control circuit further includes a third comparator; a non-inverting input of the third comparator is configured to introduce a third reference voltage, and an inverting input end of the third comparator is the LM a feedback terminal of the FOT control circuit, the output of the third comparator being coupled to the second input of the multiplier.
  • a third comparator a non-inverting input of the third comparator is configured to introduce a third reference voltage
  • an inverting input end of the third comparator is the LM a feedback terminal of the FOT control circuit, the output of the third comparator being coupled to the second input of the multiplier.
  • the present invention also provides an electronic device which is an adapter, a liquid crystal display, a projector or a medical device, and the electronic device includes the above-described flyback switching power supply.
  • the constant voltage output circuit provided by the invention eliminates the high voltage electrolytic capacitor, improves the power factor of the power source, and saves the electric energy.
  • the LM-FOT control circuit controls the on/off of the switch circuit by means of a fixed off time, the constant voltage output function of the entire constant voltage output circuit is realized.
  • the constant voltage output circuit provided by the present invention has the characteristics of stable output voltage.
  • FIG. 1 is a schematic diagram of functional modules of a first embodiment of a constant voltage output circuit of the present invention
  • FIG. 2 is a schematic diagram of functional modules of a second embodiment of a constant voltage output circuit of the present invention.
  • FIG. 3 is a schematic diagram of functional modules of a third embodiment of a constant voltage output circuit of the present invention.
  • FIG. 4 is a schematic diagram of functional modules of a fourth embodiment of a constant voltage output circuit of the present invention.
  • FIG. 5 is a circuit schematic structural diagram of a constant voltage output circuit of the present invention.
  • Fig. 6 is a structural diagram of a specific implementation circuit of a constant voltage output circuit of the present invention.
  • the present invention provides a constant voltage output circuit including a power supply circuit 11, an LM-FOT control circuit 12, a switching circuit 13, and a transformer 14.
  • An output end of the power supply circuit 11 is respectively connected to a first input end of the LM-FOT control circuit 12 and one end of a primary winding of the transformer 14; a control end of the LM-FOT control circuit 12 and the a controlled end of the switching circuit 13 is connected, a second input of the LM-FOT control circuit 12 is connected to an output of the switching circuit 13; an input of the switching circuit 13 and a primary winding of the transformer 14
  • the other end of the transformer 14 has one end connected to the output terminal of the constant voltage output circuit, and the other end of the secondary winding of the transformer 14 is grounded.
  • the LM-FOT control circuit controls the fixed off time of the switch circuit according to a voltage signal outputted by the power circuit to realize a constant voltage output function of the entire constant voltage output circuit.
  • the power circuit 11 when the constant voltage output circuit is activated, the power circuit 11 outputs a first voltage signal to a first input end of the LM-FOT control circuit 12, and the LM-FOT control circuit 12 is activated,
  • the control terminal of the LM-FOT control circuit 12 outputs a second voltage signal to the controlled terminal of the switching circuit 13, which is activated.
  • one end of the primary winding of the transformer 14 obtains a first voltage signal output by the power supply circuit 11, and since the other end of the primary winding of the transformer 14 is connected to the input end of the switching circuit 13, Therefore, when the switching circuit 13 is activated, the switching circuit 13 forms an oscillating circuit with the primary winding of the transformer 14, so that the current flowing through the switching circuit 13 gradually increases.
  • the output terminal of the switching circuit 13 When the current value flowing through the switching circuit 13 increases to a certain extent, the output terminal of the switching circuit 13 outputs a third voltage signal to the second input end of the LM-FOT control circuit 12, the LM- The FOT control circuit 12 controls the switch circuit 13 to turn off according to the third voltage signal outputted from the output terminal of the switch circuit 13 and record the off time of the switch circuit 13, when the switch circuit 13 is turned off. After the preset value, the LM-FOT control circuit 12 again controls the switch circuit to open, so that the switch circuit 13 continuously repeats the above-described process of opening and closing.
  • the constant voltage output circuit provided by the invention eliminates the high voltage electrolytic capacitor, improves the power factor of the power source, and saves the electric energy.
  • the LM-FOT control circuit controls the on/off of the switching circuit in a fixed off time manner, the function of the constant voltage output of the entire constant voltage output circuit is realized.
  • the constant voltage output circuit provided by the present invention has the characteristics of stable output voltage.
  • the constant voltage output circuit provided by the present invention further includes a sampling circuit 15.
  • the signal collecting end of the sampling circuit 15 is connected to the output end of the power supply circuit 11, and the sampling signal output end of the sampling circuit 15 is connected to the first input end of the LM-FOT control circuit 12.
  • the sampling circuit is added to the constant voltage output circuit, and the input voltage of the constant voltage output circuit can be subjected to voltage division processing, thereby reducing the voltage value input to the LM-FOT control circuit and reducing The possibility of damage to electrical components in the constant voltage output circuit.
  • the constant voltage output circuit provided by the present invention further includes a voltage stabilizing circuit 16; an input end of the voltage stabilizing circuit 16 is connected to one end of the secondary winding of the transformer 14, the voltage regulator The output of circuit 16 is the output of the constant voltage output circuit. Since the constant voltage output circuit provided by the present invention eliminates the high voltage electrolytic capacitor, the voltage ripple of the constant voltage signal outputted through one end of the secondary winding of the transformer 14 is large, and therefore, in the constant voltage output circuit. The voltage stabilizing circuit 16 is added to reduce the voltage ripple outputted from the output terminal of the constant voltage output circuit, thereby making the constant voltage signal outputted by the constant voltage output circuit more stable.
  • the constant voltage output circuit provided by the present invention further includes a constant voltage feedback circuit 17; the input end of the constant voltage feedback circuit 17 is connected to the output end of the constant voltage output circuit, the constant The output of the voltage feedback circuit 17 is connected to the feedback terminal of the LM-FOT control circuit.
  • the input end of the constant voltage feedback circuit 17 receives the constant voltage signal outputted from the output end of the constant voltage output circuit, The output end of the constant voltage feedback circuit 17 supplies a sampling signal of the changed constant voltage signal outputted from the output end of the constant voltage output circuit to the feedback end of the LM-FOT control circuit 12, the LM-FOT
  • the control circuit 12 controls the operating state of the switching circuit 13 based on the signal received at its feedback terminal to cause the constant voltage output circuit to output a normal constant voltage.
  • FIG. 5 is a circuit schematic diagram of a constant voltage output circuit provided by the present invention.
  • the power circuit includes an AC power source, an EMI filter, and a rectifier bridge.
  • An output end of the alternating current power source is coupled to an input end of the EMI filter; a first output end of the EMI filter is coupled to a first input end of the rectifier bridge, and a second output end of the EMI filter Connected to the second input end of the rectifier bridge; the negative output end of the rectifier bridge is grounded, and the positive output end of the rectifier bridge is the output end of the power supply circuit 11 .
  • the AC power source When the power circuit 11 is activated, the AC power source outputs a constant peak AC voltage.
  • the alternating voltage signal is a sinusoidal signal having a peak value of 110V or 220V.
  • An input end of the EMI filter receives an AC voltage signal output by the AC power source, and the EMI filter filters out clutter of an AC voltage signal output by the power source, and an output of the EMI filter is filtered out The AC voltage signal after the clutter is delivered to the rectifier bridge.
  • the rectifier bridge rectifies the AC voltage signal received by the rectifier bridge to output a voltage signal such that the negative half cycle signal of the AC voltage signal is inverted to a positive half cycle and the positive half cycle signal is unchanged.
  • the LM-FOT control circuit 12 includes a multiplier K, an LM-FOT modulator T, a flip-flop Q, a driver D, a first comparator U1, and a first capacitor C1.
  • the flip-flop Q is selected as an RS. trigger.
  • the first input end of the multiplier K is a first input end of the LM-FOT control circuit 12, and the first output end of the multiplier K is connected to an inverting input end of the first comparator U1.
  • the connection node of the multiplier K and the first comparator U1 is used to introduce a first reference voltage REF1, and the non-inverting input terminal of the first comparator U1 is a second input of the LM-FOT control circuit 12 end.
  • the second output end of the multiplier K is connected to the second signal end of the LM-FOT modulator T, and the first signal end of the LM-FOT modulator T is connected to one end of the first capacitor C1.
  • the other end of the first capacitor C1 is grounded.
  • a third signal end of the LM-FOT modulator T is connected to an S terminal of the RS flip-flop Q, and a fourth signal end of the LM-FOT modulator T is respectively connected to an R end of the RS flip-flop Q,
  • the output of the first comparator U1 is connected.
  • An output end of the RS flip-flop Q is connected to one end of the driver D, and the other end of the driver D is a control end of the LM-FOT control circuit 12.
  • the first input terminal of the multiplier K receives the voltage signal output by the power supply circuit 11, and the multiplier K performs the voltage signal received by the first input terminal thereof.
  • the amplification process is followed by a second output of the multiplier K to a second signal terminal of the LM-FOT modulator T.
  • the LM-FOT modulator T controls the output of the RS flip-flop Q to output a high level according to a voltage signal received by the second signal terminal thereof to control the switching circuit 13 to be turned on.
  • the first capacitor C1 starts to be charged, and when the first capacitor C1 is fully charged, the voltage value received by the non-inverting input terminal of the first comparator U1 is higher than the first reference voltage REF1.
  • the output end of the first comparator U1 outputs a high level signal, the R terminal of the RS flip-flop Q is triggered, and the output terminal of the RS flip-flop Q outputs a low level to control the switching circuit 13 to be turned off.
  • the first capacitor C1 starts to discharge, and when the voltage across the first capacitor C1 is 0, the LM-FOT modulator T controls the switching circuit 13 to open, and the above process is continuously repeated. Since the size of the first capacitor C1 is fixed, the charging time and the discharging time are also fixed. Therefore, the function of the LM-FOT control circuit 12 is to control the switching of the switching circuit 13 by a fixed off time.
  • the LM-FOT control circuit 12 further includes a second comparator U2; an inverting input terminal of the second comparator U2 is used to introduce a second reference voltage REF2, and an in-phase input of the second comparator U2 The terminal is connected to the non-inverting input of the first comparator U1, and the output of the second comparator U2 is connected to the fifth signal terminal of the LM-FOT modulator T.
  • the output of the second comparator U2 When the voltage value received by the non-inverting input of the second comparator U2 is higher than the second reference voltage REF2, the output of the second comparator U2 outputs a high level signal to the LM-FOT modulation.
  • the LM-FOT modulator T controls the output end of the RS flip-flop Q to output a low level according to a high level signal received by the fifth signal terminal thereof to control the switch circuit 13 shuts down.
  • the second comparator U2 can prevent the high voltage from burning out the electronic components in the circuit and has the function of protecting the circuit.
  • the LM-FOT control circuit 12 further includes a third comparator U3; the non-inverting input of the third comparator U3 is used to introduce a third reference voltage REF3, and the input end of the third comparator U3 is At the feedback end of the LM-FOT control circuit 12, the output of the third comparator U3 is coupled to the second input of the multiplier K.
  • the output end of the third comparator U3 When the voltage value received by the non-inverting input terminal of the third comparator U3 is higher than the third reference voltage REF3, the output end of the third comparator U3 outputs a high level signal to the multiplier K.
  • the multiplier K amplifies the high level signal received by the second input terminal thereof, and then sends the signal to the LM-FOT modulator T via the second output end of the multiplier K.
  • the LM-FOT modulator T increases the off time of the switching circuit 13 according to the high level signal received by the second signal terminal thereof.
  • the LM-FOT modulator T receives the low power according to the second signal end thereof.
  • the flat signal reduces the off time of the switching circuit 13.
  • the third comparator U3 can assist the LM-FOT control circuit 12 to perform switching control on the switch circuit 13.
  • the switch circuit 13 includes a first enhancement type NMOS transistor Q1, a first resistor R1, a drain of the first enhancement type NMOS transistor Q1, an input end of the switch circuit 13, and a first enhancement type NMOS transistor Q1.
  • the gate is the controlled end of the switching circuit 13, the source of the first NMOS transistor Q1 is connected to one end of the first resistor R1; the other end of the first resistor R1 is grounded.
  • the switch circuit 13 When the switch circuit 13 is activated, the gate of the first enhancement type NMOS transistor Q1 receives a high level signal, and the first enhancement type NMOS transistor Q1 is turned on, the first enhancement type NMOS transistor Q1.
  • the transformer 14 constitutes an oscillating circuit. Then, the current flowing through the first resistor R1 gradually increases, and the voltage value outputted by the connection node of the first enhancement type NMOS transistor Q1 and the first resistor R1 also increases, when the voltage value
  • the LM-FOT control circuit 12 controls the switching circuit 13 to turn off when it is increased above the first reference voltage REF1. After the fixed off time described above, the LM-FOT control circuit 12 controls the switch circuit 13 to open.
  • the switching circuit 13 is configured to form an oscillating circuit with the transformer 14 to realize a constant voltage output from one end of the secondary winding of the transformer 14.
  • the voltage stabilizing circuit 16 includes a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12; a second enhanced NMOS transistor Q2, a third capacitor C3, and a first controllable voltage regulator W1;
  • the model of the controllable voltage regulator W1 is TL431.
  • the drain of the second enhancement type NMOS transistor Q2 is an input terminal of the voltage stabilization circuit 16.
  • the source of the second enhancement type NMOS transistor Q2 is respectively connected to one end of the ninth resistor R9 and the eleventh resistor R11, the second enhancement type NMOS transistor Q2, the ninth resistor R9, the The connection node of the eleventh resistor R11 is the output terminal of the voltage stabilizing circuit 16.
  • the gate of the second enhancement type NMOS transistor Q2 is respectively connected to the other end of the ninth resistor R9, one end of the tenth resistor R10, and the cathode of the first controllable voltage regulator W1.
  • the other end of the tenth resistor R10 is connected to the other end of the third capacitor C3, and the other end of the tenth resistor R10 is opposite to the other end of the eleventh resistor R11 and the twelfth resistor R12.
  • One end of the first controllable voltage regulator W1 is connected to the reference pole.
  • the other end of the twelfth resistor R12 is connected to the anode of the first controllable voltage regulator W1, and the first controllable voltage regulator W1 and the second connection node of the twelfth resistor R12 are grounded. .
  • the current flowing through the eleventh resistor R11 and the twelfth resistor R12 becomes large. Since the current flowing between the drain and the source of the second enhancement type NMOS transistor Q2 is constant, the current flowing through the ninth resistor R9 and the first controllable voltage regulator W1 is changed. Small, the cathode voltage of the first controllable regulated voltage source W1 is decreased, and the voltage difference between the gate and the source of the second enhanced NMOS transistor Q2 is decreased, and flows through the second enhanced type. The current between the drain and the source of the NMOS transistor Q2 decreases, the current flowing through the eleventh resistor R11 and the twelfth resistor R12 decreases, and the output voltage of the output terminal of the voltage regulator circuit 16 Reduced.
  • the current flowing through the ninth resistor R9 and the first controllable voltage stabilizing source W1 becomes larger, and the first controllable
  • the cathode voltage of the regulated source W1 increases, and the voltage difference between the gate and the source of the second enhanced NMOS transistor Q2 increases, flowing through the drain and source of the second enhanced NMOS transistor Q2.
  • the current between the poles increases, and the current flowing through the eleventh resistor R11 and the twelfth resistor R12 increases, and the output voltage value of the output terminal of the voltage stabilizing circuit 16 increases.
  • the voltage stabilizing circuit 16 when the voltage value outputted by the output end of the constant voltage output circuit changes, the voltage stabilizing circuit 16 can perform the voltage value output by the constant voltage output circuit. The adjustment is made to ensure that the voltage value outputted from the output of the constant voltage output circuit is constant.
  • the transformer 14 and the voltage stabilizing circuit 16 further include a third diode D3, an inductor L, a fourth capacitor C4, and a fifth capacitor C5.
  • An anode of the third diode D3 is connected to one end of the secondary winding of the transformer 14, and a cathode of the third diode D3 is respectively connected to one end of the inductor L and the anode of the fourth capacitor C4. connection.
  • the other end of the inductor L is connected to the anode of the fifth capacitor C5, and the connection node of the inductor L and the fifth capacitor C5 is connected to the input end of the voltage stabilizing circuit 16.
  • the cathode of the fourth capacitor C4 is respectively connected to the other end of the secondary winding of the transformer 14 and the cathode of the fifth capacitor C5, and the connection node of the fourth capacitor C4 and the fifth capacitor C5 is grounded. .
  • the third diode D3 filters out a small amplitude clutter signal in the constant voltage signal
  • the fourth capacitor C4 constitutes a band pass filter for filtering the high frequency clutter signal and the low frequency clutter signal in the constant voltage signal, and increasing the inductance L, so that the output signal can be made more gentle.
  • the constant voltage feedback circuit 17 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8; a second capacitor C2, an optocoupler U4, and a second controllable voltage regulator W2;
  • the model of the second controllable voltage regulator W2 is TL421.
  • the fourth signal end of the optocoupler U4 is connected to the power source, the third signal end of the optocoupler U4 is the output end of the constant voltage feedback circuit 17, and the first signal end and the fifth end of the optocoupler U4 are One end of the resistor R5 is connected, and the other end of the fifth resistor R5 is connected to the power source.
  • the second signal end of the optocoupler U4 is respectively connected to one end of the sixth resistor R6 and the second controllable voltage regulator W2. Cathode connection.
  • the other end of the sixth resistor R6 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to one end of the seventh resistor R7 and the second controllable voltage regulator W2.
  • the other end of the seventh resistor R7 is connected to the connection node of the inductor L and the fifth capacitor C5.
  • the other end of the eighth resistor R8 and the anode of the second controllable voltage regulator W2 are grounded.
  • the seventh resistor R7 and the eighth resistor R8 are used to collect a constant voltage signal outputted from one end of the inductor L.
  • the constant voltage feedback circuit 17 is configured to collect a constant voltage signal outputted from one end of the inductor L and pass the light.
  • the coupling U4 is transmitted to the LM-FOT control circuit 12, so that the LM-FOT control circuit 12 adjusts the operating state of the switching circuit 13 according to the constant voltage signal collected by the constant voltage feedback circuit 17, so that the inductance L
  • the constant voltage signal outputted at one end is more stable.
  • the alternating current power source When the constant voltage output circuit is activated, the alternating current power source outputs a sine wave signal, and the EMI filter performs filtering processing on the sine wave signal output by the alternating current power source, and then sends the sinusoidal wave signal to the rectifier bridge, the rectifier bridge The filtered sine wave signal is rectified and the first voltage signal is output.
  • the first input terminal of the multiplier K in the LM-FOT control circuit 12 obtains the first voltage signal, the LM-FOT control circuit 12 is activated, and the other end of the driver D of the LM-FOT control circuit 12 outputs The second voltage signal.
  • the gate of the first enhancement mode NMOS transistor Q1 in the switch circuit 13 obtains the second voltage signal, and the switch circuit 13 is activated.
  • one end of the primary winding of the transformer 14 obtains a first voltage signal outputted from the entire output end of the rectifier bridge in the power supply circuit 11, since the other end of the primary winding of the transformer 14 and the switch
  • the drain of the first enhancement type NMOS transistor is connected in the circuit 13, so that when the switch circuit 13 is activated, the first enhancement type NMOS transistor Q1 and the primary winding of the transformer 14 form an oscillation circuit, the oscillation The circuit causes the current flowing between the first resistor R1 of the switching circuit 13 and the drain and the source of the first enhancement mode NMOS transistor Q1 to gradually increase, and the sampled voltage value of the first resistor R1 of the switch circuit 13 Gradually increase.
  • connection node of the first resistor R1 of the switch circuit 13 and the first enhancement mode NMOS transistor Q1 outputs a third voltage signal to the non-inverting input terminal of the first comparator U1 of the LM-FOT control circuit 12.
  • the third voltage signal outputted by the first resistor R1 of the switch circuit and the connection node of the first enhancement type NMOS transistor Q1 The voltage value is greater than the first reference voltage value REF1.
  • the R terminal of the RS flip-flop Q is at a high level, the output terminal of the RS flip-flop Q outputs a low level, and the switch circuit 13 is turned off.
  • the fourth signal end of the LM-FOT modulator T receives the high level signal outputted by the output end of the first comparator U1, and the LM-FOT modulator T records the first The timing of the high level signal outputted by the output of the comparator U1 starts to charge the first capacitor C1, and the voltage across the first capacitor C1 increases.
  • the sampling circuit 15 sends a sampling signal of the first voltage signal output by the power circuit 11 to the multiplier K of the LM-FOT control circuit 12, and the sampling signal of the first voltage signal passes through the multiplier K.
  • the switch circuit 13 After being amplified, it is sent to the first input terminal of the LM-FOT modulator T, when the voltage value across the first capacitor C1 is increased to be equal to the voltage value obtained by the second signal terminal of the LM-FOT modulator T.
  • the third signal terminal of the LM-FOT modulator T outputs a signal to the S terminal of the RS flip-flop Q, the output terminal of the RS flip-flop Q outputs a high-level signal, and the switch circuit 13 is turned on. The process of turning on and off the switching circuit 13 is repeated according to the above principle, so that the entire constant voltage output circuit outputs a constant voltage.
  • the output load when the output load is too heavy, the current flowing through the first resistor R1 in the switch circuit 13 increases, and the voltage across the first resistor R1 also increases.
  • the output of the second comparator U2 outputs a high level to trigger
  • the LM-FOT modulator T ceases to operate, causing the LM-FOT control circuit 12 to enter a protection state, and the constant voltage output circuit stops operating. It can be seen that the second comparator U2 is added to the LM-FOT control circuit 12, and the LM-FOT control circuit 12 can be overload protected.
  • the input end of the constant voltage feedback circuit 17 acquires the low voltage value and samples the low voltage value. After the amplification process, it is sent to the inverting input terminal of the third comparator U3 of the LM-FOT control circuit 12. At this time, the output end of the third comparator U3 of the LM-FOT control circuit 12 outputs a high level and is amplified by the multiplier K and then sent to the second signal end of the LM-FOT modulator T.
  • the LM-FOT modulator T increases the duty ratio of the on-time of the first enhancement mode NMOS transistor Q1 according to the error signal received by the second signal terminal. Since the first enhancement type NMOS transistor Q1 has an extended on-time under the control of the LM-FOT modulator T, the voltage value outputted from the output terminal of the constant voltage output circuit becomes large.
  • the LM-FOT control circuit 12 controls the turn-on time of the first enhancement type NMOS transistor Q1 according to the feedback signal of the constant voltage feedback circuit 17. The decrease is made to further reduce the voltage value output by the constant voltage output circuit.
  • the third comparator U3 is added to the LM-FOT control circuit 12, and the constant voltage feedback circuit 17 is added to the constant voltage output circuit, so that the constant voltage output circuit can be The constant voltage signal output at the output is more stable.
  • the present invention adopts the FOT control mode to realize the constant voltage output of the constant voltage output circuit, and the FOT control mode is the switching power supply operating frequency adjustable, the fixed off time peak current control, In the case where the input voltage duty ratio of the constant voltage output circuit is different, the inductance L current of the output terminal maintains a steady state, and the present invention fixes the off time by the first capacitor C1 in the LM-FOT control circuit 12. Therefore, when the capacitance value of the first capacitor C1 in the LM-FOT control circuit 12 is set, the input voltage range of the constant voltage output circuit is also set.
  • the constant voltage output circuit adds the sampling circuit 15 so that the LM-FOT control circuit 12 simultaneously controls the switching circuit 13 according to the AC input voltage and the signal output from the sampling signal output terminal of the sampling circuit 15. Fixed off time.
  • the sampling circuit 15 is configured to sample the rectified AC mains voltage, and when the mains voltage becomes high, the connection node of the third resistor R3 and the fourth resistor R4 of the sampling circuit outputs a high level signal,
  • the high level signal is amplified by the multiplier K of the LM-FOT control circuit 12 and sent to the first signal end of the LM-FOT modulator T, and the LM-FOT multiplier K receives according to the first signal end thereof.
  • the high level signal is extended to extend the off time of the first enhancement mode NMOS transistor Q1, and the turn-on time of the first enhancement mode NMOS transistor Q1 is shortened, so that the entire constant voltage output circuit has a current under an excessive input voltage. The distortion becomes small to improve the reliability of the operation of the constant voltage output circuit.
  • the invention provides another embodiment of the constant voltage output circuit.
  • FIG. 6 is a structural diagram of a specific implementation circuit of a constant voltage output circuit provided by the present invention.
  • the constant voltage output circuit includes the above-mentioned switch circuit 13, the constant voltage feedback circuit 17, the voltage stabilization circuit 16, the power supply circuit 18, the transformer 19, the LM-FOT control chip 20, and the thirteenth resistor R13 and the fourteenth resistor R14.
  • the model number of the LM-FOT control chip 20 is L4984.
  • the first output end of the power circuit 18 is respectively connected to one end of the fifteenth resistor R15, one end of the twenty-third resistor R23, and one end of the first primary winding of the transformer 19;
  • a second output of the circuit 18 is coupled to one end of the thirteenth resistor R13.
  • the other end of the fifteenth resistor R15 is connected to one end of the sixteenth resistor R16, and the other end of the sixteenth resistor R16 is respectively connected to the emitter of the third NPN transistor Q3, the sixth
  • the positive electrode of the capacitor C6 and the VCC pin terminal of the LM-FOT control chip 20 are connected.
  • the other end of the thirteenth resistor R13 is respectively connected to a PFC-OK pin end of the LM-FOT control chip 20, one end of the fourteenth resistor R14, and the other end of the fourteenth resistor R14 is grounded.
  • the other end of the sixth capacitor C6 is grounded.
  • the collector of the third NPN transistor Q3 is connected to one end of the seventeenth resistor R17, and the base of the third NPN transistor Q3 is opposite to one end of the nineteenth resistor R19 and the fifth
  • the cathode of the Zener diode D5 is connected; the other end of the nineteenth resistor R19 and the anode of the fifth Zener diode D5 are grounded.
  • the connection node of the seventeenth resistor R17 and the eighteenth resistor R18 is connected to the cathode of the fourth diode D4 and the anode of the eighth capacitor C8, respectively.
  • the anode of the eighth capacitor C8 is grounded, the anode of the fourth diode D2 is connected to one end of the second primary winding of the transformer 19, and the other end of the second primary winding of the transformer 19 is grounded.
  • the other end of the twenty-third R23 resistor is connected to one end of the twenty-fourth resistor R24, and the other end of the twenty-fourth resistor R24 is respectively connected to one end of the second twelve resistor R22,
  • the MULT pin terminal of the LM-FOT control chip 20 is connected.
  • the GATE pin end of the LM-FOT control chip 20 is connected to the controlled end of the switch circuit 13; the TIME pin end of the LM-FOT control chip 20 is connected to one end of the seventh capacitor C7. The other end of the seventh capacitor C7 is grounded; the INV pin end of the LM-FOT control chip 20 is connected to one end of the twentieth resistor R20, and the other end of the twentieth resistor R20 is respectively One end of the twenty-first resistor R21 is connected to the output end of the constant voltage feedback circuit 17, and the other end of the twenty-first resistor R21 is grounded; the CS pin end of the LM-FOT control chip 20 and the first One end of the twenty-five resistor R25 is connected.
  • the other end of the twenty-fifth resistor R25 is connected to the output end of the switch circuit 13, and the input end of the switch circuit 13 is connected to the other end of the first primary winding of the transformer 19.
  • One end of the secondary winding of the transformer 19 is connected to the anode of the third diode D3, and the cathode of the third diode D3 is respectively connected to one end of the inductor L and the positive pole of the fourth capacitor C4.
  • Connecting, the other end of the inductor L is respectively connected to the anode of the fifth capacitor C5 and the input end of the voltage stabilizing circuit 16; the other end of the secondary winding of the transformer 19, and the fourth capacitor C4
  • the negative electrode and the negative electrode of the fifth capacitor C5 are grounded.
  • the first output end of the power supply circuit 18 outputs a first voltage signal to one end of the first primary winding of the transformer 19.
  • the fifteenth resistor R15, the sixteenth resistor R16, and the sixth capacitor C6 constitute a pre-start circuit of the LM-FOT control chip 20, the fifteenth resistor R15 and the sixteenth resistor R16 charges the sixth capacitor C6.
  • the LM-FOT control chip 20 starts to start working, and the first enhanced NMOS transistor Q1 is controlled to be turned on, and then the transformer The second primary winding of 19 can output a VCC voltage to the fourth diode D4 and the eighth capacitor C8.
  • the eighteenth resistor R18 and the nineteenth resistor R19 control the base voltage of the third NPN transistor Q3 according to the charging voltage of the eighth capacitor C8, so that the collector of the third NPN transistor Q3 A constant voltage is output.
  • the seventeenth resistor R17 functions as a current limiting resistor
  • the fifth Zener diode D5 serves as a voltage stabilizing protection diode of the third NPN transistor Q3 when the voltage of the VCC pin terminal of the LM-FOT control chip 20 is After stabilization, the LM-FOT control chip 20 operates normally.
  • the LM-FOT control chip 20 controls the transformer 19 to oscillate such that the second primary winding output VCC of the transformer 19 provides a stable operating voltage for the LM-FOT control chip 20, and the transformer 19 is
  • the LM-FOT control chip 20 outputs a constant voltage of 12V under the control of the control chip 20.
  • the constant voltage outputted from one end of the secondary winding of the transformer 19 is filtered by the voltage stabilizing circuit 16 and outputted to supply power to the external electronic device, such as powering the television.
  • the thirteenth resistor R13 and the fourteenth resistor R14 form a voltage dividing sampling circuit, and the connection node of the thirteenth resistor R13 and the fourteenth resistor R14 inputs the sampled voltage to the LM-
  • the PFC-OK pin terminal of the FOT control chip 20 serves as an input undervoltage detection function of the constant voltage output circuit, and can set an input overvoltage and undervoltage protection. For example, when the commercial voltage is less than 65V, the LM-FOT control chip 20 stops working. When the commercial power returns to 85V, the LM-FOT control chip 20 is turned on. When the commercial power voltage is greater than 310V, the LM-FOT control chip 20 stops working.
  • the TIME pin end of the LM-FOT control chip 20 is connected to one end of the seventh capacitor C7 for setting a fixed off time.
  • the fixed turn-off time is implemented by: when the first enhancement type NMOS transistor Q1 is turned on, the sampled voltage of the first resistor R1 is gradually increased, when the sampling voltage of the first resistor R1 is greater than
  • the GATE pin terminal output control signal of the LM-FOT control chip 20 controls the switch circuit 13 to make the first enhanced NMOS transistor Q1 is turned off, and at the same time, the LM-FOT control chip 20 records the timing at which the first enhancement type NMOS transistor Q1 is turned off.
  • the LM-FOT control chip 20 charges the seventh capacitor C7 such that the voltage across the seventh capacitor C7 gradually increases.
  • the MULT pin terminal of the LM-FOT control chip 20 obtains the first voltage signal outputted by the first output section of the power circuit through the second twelve resistor R22. After the voltage across the seventh capacitor C7 increases to be equal to the voltage across the second twelve resistor R22, the fixed off time ends, and the GATE pin of the LM-FOT control chip 20 is turned back.
  • the first enhancement type NMOS transistor Q1 is turned on. The process of turning on and off the switching circuit 13 described above is repeated to achieve constant voltage output of the constant voltage output circuit.
  • the off time is fixed when the input voltage of the constant voltage output circuit is within a certain range.
  • the mains voltage has a large deviation, 110V, 220V, etc. If the operating frequency of the switching power supply is between 60-80KHZ, the fixed off-time is unchanged. In the low-voltage area, the power supply works normally, and in the high-voltage area, The on-current of the constant voltage output circuit will suddenly increase distortion, and the sudden increase of the on-current will cause damage to the device. Therefore, the input line voltage adjustment technique is adopted, that is, the fixed on-time is modulated by detecting the line voltage magnitude.
  • the line voltage adjustment technology is implemented by: forming a line voltage sampling circuit by the twenty-third resistor R23, the twenty-fourth resistor R24, and the second twelve resistor R23 for sampling and rectifying The AC mains voltage, when the mains voltage becomes high, the line voltage sampling circuit samples a high level signal and sends it to the MULT pin end of the LM-FOT control chip 20, the LM-FOT control chip 20 extending the off time of the first enhancement mode NMOS transistor Q1 according to the sampled high level signal, shortening the on time of the first enhancement mode NMOS transistor Q1, so that the constant voltage output circuit is at a high input voltage The lower current distortion becomes smaller to improve the reliability of the constant voltage output circuit.
  • the LM-FOT control chip 20 stops operating, the LM-FOT control chip 20 enters a protection state, and the constant voltage output circuit stops operating.
  • the constant voltage output circuit provided by the invention eliminates the large electrolytic capacitor, avoids the current lead voltage in the circuit, and makes the mains and the current supply in the same phase. Compared with the prior art, the power factor of the power source is improved, and the actual power of the utility power is saved. .
  • Working in a fixed off time mode such that the output state of the constant voltage output circuit is not affected by the operating frequency of the constant voltage output circuit and the duty ratio of the input voltage thereof, and the output voltage of the constant voltage output circuit is improved.
  • Voltage modulation is used to fix the off time, so that the constant voltage output circuit can operate under the condition that the input mains voltage is too high, which improves the reliability of the constant voltage output circuit.
  • the present invention also provides a flyback switching power supply and an electronic device thereof, which is an adapter, a liquid crystal display, a projector or a medical device.
  • the flyback switching power supply includes the above-mentioned constant voltage output circuit, and the constant voltage output circuit includes the technical solution in the implementation of any of the above embodiments.
  • the detailed circuit composition structure can be referred to FIG. 1 to FIG. 6 , and details are not described herein.

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Abstract

一种恒压输出电路，包括电源电路（11）、LM-FOT控制电路（12）、开关电路（13）和变压器（14）。电源电路的输出端分别与LM-FOT控制电路的第一输入端、变压器原边绕组的一端连接；LM-FOT控制电路的控制端与开关电路的受控端连接；LM-FOT控制电路的第二输入端与开关电路的输出端连接；开关电路的输入端与变压器原边绕组的另一端连接；变压器副边绕组的一端用于输出恒压信号。LM-FOT控制电路根据AC输入电压及电源电路输出的电压信号控制开关电路的固定关断时间，实现恒压输出电路的恒压输出。还提供了一种反激开关电源及其电子设备。通过采用上述恒压输出电路，省去了高压电解电容，提高了电源功率因素，节省了电能。

Description

恒压输出电路、反激开关电源及其电子设备
技术领域
本发明涉及电源电路领域，特别涉及恒压输出电路、反激开关电源及其电子设备。
背景技术
目前大多数反激开关电源采用PWM控制的工作方式实现恒压输出。由于传统的PWM控制是固定频率的峰值电流控制，当占空比大于50%，输入电压一定且负载条件一定时，虽然电感峰值检测电流是恒定的，但是电感电流会出现一个扰动 ，导致下一周期更大的扰动 ，形成了电流震荡造成系统输出电压不稳定。因此，生产所述反激开关电源都需要高压电解电容对整流后的电压进行滤波，以使反激开关电源输出的电压稳定。
该高压电解电容会使电路中电流超前电压，导致电流电压不能同相位供电，造成电能浪费。
发明内容
本发明的主要目的为提供一种恒压输出电路、反激开关电源及其电子设备。旨在省去高压电解电容后，实现所述恒压输出电路稳定输出恒压信号的功能。
为实现上述目的，本发明提供了一种恒压输出电路，所述恒压输出电路包括电源电路、LM-FOT（Line-modulated Fixed-Off-Time，线电压调制固定关断时间）控制电路、开关电路、变压器；
所述电源电路的输出端分别与所述LM-FOT控制电路的第一输入端、所述变压器的原边绕组的一端连接；所述LM-FOT控制电路的控制端与所述开关电路的受控端连接，所述LM-FOT控制电路的第二输入端与所述开关电路的输出端连接；所述开关电路的输入端与所述变压器的原边绕组的另一端连接；所述变压器的副边绕组的一端为所述恒压输出电路的输出端，所述变压器的副边绕组的另一端接地；所述LM-FOT控制电路根据电源电路输出的电压信号控制所述开关电路的固定关断时间，实现整个恒压输出电路的恒压输出。
优选的，所述恒压输出电路还包括采样电路；所述采样电路的信号采集端与所述电源电路的输出端连接，所述采样电路的采样信号输出端与所述LM-FOT控制电路的第一输入端连接。
优选的，所述恒压输出电路还包括恒压反馈电路；所述恒压反馈电路的输入端与所述恒压输出电路的输出端连接，所述恒压反馈电路的输出端与所述LM-FOT控制电路的反馈端连接。
优选的，所述恒压输出电路还包括稳压电路；所述稳压电路的一端与所述变压器的副边绕组的一端连接，所述稳压电路的另一端为所述恒压输出电路的输出端。
优选的，所述开关电路包括第一增强型NMOS管，第一电阻；所述第一增强型NMOS管的漏极为所述开关电路的输入端，所述第一增强型NMOS管的栅极为所述开关电路的受控端，所述第一增强型NMOS管的源极与所述第一电阻的一端连接；所述第一增强型NMOS管与所述第一电阻的连接结点为所述开关电路的输出端，所述第一电阻的另一端接地。
优选的，所述LM-FOT控制电路包括倍增器、LM-FOT调制器、触发器、驱动器第一比较器以及第一电容；所述倍增器的第一输入端为所述LM-FOT控制电路的第一输入端，所述倍增器的第一输出端与所述第一比较器的反相输入端连接，所述倍增器与所述第一比较器的连接结点用于引入第一参考电压，所述倍增器的第二输出端与所述LM-FOT调制器的第二信号端连接；
所述第一比较器的同相输入端为所述LM-FOT控制电路的第二输入端，所述第一比较器的输出端分别与所述LM-FOT调制器的第四信号端、所述触发器的第二信号端连接；所述LM-FOT调制器的第一信号端与所述第一电容的一端连接，所述第一电容的另一端接地；所述LM-FOT调制器的第三信号端与所述触发器的第一信号端连接；所述触发器的输出端与所述驱动器的一端连接，所述驱动器的另一端为所述LM-FOT控制电路的控制端。
优选的，所述LM-FOT控制电路还包括第二比较器；所述第二比较器的反相输入端用于引入第二参考电压，所述第二比较器的同相输入端与所述第一比较器的同相输入端连接，所述第二比较器的输出端与所述LM-FOT调制器的第五信号端连接。
优选的，所述LM-FOT控制电路还包括第三比较器；所述第三比较器的同相输入端用于引入第三参考电压，所述第三比较器的反相输入端为所述LM-FOT控制电路的反馈端，所述第三比较器的输出端与所述倍增器的第二输入端连接。
此外，为实现上述目的，本发明还提供了一种反激开关电源，所述反激开关电源包括上述的恒压输出电路，所述恒压输出电路包括电源电路、LM-FOT（Line-modulated Fixed-Off-Time，线电压调制固定关断时间）控制电路、开关电路、变压器；
所述电源电路的输出端分别与所述LM-FOT控制电路的第一输入端、所述变压器的原边绕组的一端连接；所述LM-FOT控制电路的控制端与所述开关电路的受控端连接，所述LM-FOT控制电路的第二输入端与所述开关电路的输出端连接；所述开关电路的输入端与所述变压器的原边绕组的另一端连接；所述变压器的副边绕组的一端为所述恒压输出电路的输出端，所述变压器的副边绕组的另一端接地；所述LM-FOT控制电路根据电源电路输出的电压信号控制所述开关电路的固定关断时间，实现整个恒压输出电路的恒压输出。
优选的，所述恒压输出电路还包括采样电路；所述采样电路的信号采集端与所述电源电路的输出端连接，所述采样电路的采样信号输出端与所述LM-FOT控制电路的第一输入端连接。
优选的，所述恒压输出电路还包括恒压反馈电路；所述恒压反馈电路的输入端与所述恒压输出电路的输出端连接，所述恒压反馈电路的输出端与所述LM-FOT控制电路的反馈端连接。
优选的，所述恒压输出电路还包括稳压电路；所述稳压电路的一端与所述变压器的副边绕组的一端连接，所述稳压电路的另一端为所述恒压输出电路的输出端。
优选的，所述开关电路包括第一增强型NMOS管，第一电阻；所述第一增强型NMOS管的漏极为所述开关电路的输入端，所述第一增强型NMOS管的栅极为所述开关电路的受控端，所述第一增强型NMOS管的源极与所述第一电阻的一端连接；所述第一增强型NMOS管与所述第一电阻的连接结点为所述开关电路的输出端，所述第一电阻的另一端接地。
优选的，所述LM-FOT控制电路包括倍增器、LM-FOT调制器、触发器、驱动器第一比较器以及第一电容；所述倍增器的第一输入端为所述LM-FOT控制电路的第一输入端，所述倍增器的第一输出端与所述第一比较器的反相输入端连接，所述倍增器与所述第一比较器的连接结点用于引入第一参考电压，所述倍增器的第二输出端与所述LM-FOT调制器的第二信号端连接；
所述第一比较器的同相输入端为所述LM-FOT控制电路的第二输入端，所述第一比较器的输出端分别与所述LM-FOT调制器的第四信号端、所述触发器的第二信号端连接；所述LM-FOT调制器的第一信号端与所述第一电容的一端连接，所述第一电容的另一端接地；所述LM-FOT调制器的第三信号端与所述触发器的第一信号端连接；所述触发器的输出端与所述驱动器的一端连接，所述驱动器的另一端为所述LM-FOT控制电路的控制端。
优选的，所述LM-FOT控制电路还包括第二比较器；所述第二比较器的反相输入端用于引入第二参考电压，所述第二比较器的同相输入端与所述第一比较器的同相输入端连接，所述第二比较器的输出端与所述LM-FOT调制器的第五信号端连接。
优选的，所述LM-FOT控制电路还包括第三比较器；所述第三比较器的同相输入端用于引入第三参考电压，所述第三比较器的反相输入端为所述LM-FOT控制电路的反馈端，所述第三比较器的输出端与所述倍增器的第二输入端连接。
此外，为实现上述目的，本发明还提供了一种电子设备，所述电子设备为适配器、液晶显示器，投影仪或医疗器械，所述电子设备包括上述的反激开关电源。
本发明提供的恒压输出电路省去了高压电解电容，提高了电源功率因素，节省了电能。此外，由于所述LM-FOT控制电路采用固定关断时间的方式控制所述开关电路的通断，从而实现整个恒压输出电路的恒压输出功能。当所述恒压输出电路的工作频率或者其输入电压的占空比发生变化时，所述恒压输出电路的输出状态不会受到其影响。因此，本发明提供的恒压输出电路具有输出电压稳定的特点。
附图说明
图1为本发明恒压输出电路第一实施例的功能模块示意图；
图2为本发明恒压输出电路第二实施例的功能模块示意图；
图3为本发明恒压输出电路第三实施例的功能模块示意图；
图4为本发明恒压输出电路第四实施例的功能模块示意图；
图5为本发明恒压输出电路的电路原理结构图；
图6为本发明恒压输出电路的具体实施电路的结构图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
如图1所示，本发明提供了一种恒压输出电路，所述恒压输出电路包括电源电路11、LM-FOT控制电路12、开关电路13、变压器14。
所述电源电路11的输出端分别与所述LM-FOT控制电路12的第一输入端、所述变压器14的原边绕组的一端连接；所述LM-FOT控制电路12的控制端与所述开关电路13的受控端连接，所述LM-FOT控制电路12的第二输入端与所述开关电路13的输出端连接；所述开关电路13的输入端与所述变压器14的原边绕组的另一端连接；所述变压器14的副边绕组的一端为所述恒压输出电路的输出端，所述变压器14的副边绕组的另一端接地。
所述LM-FOT控制电路根据电源电路输出的电压信号控制所述开关电路的固定关断时间，实现整个恒压输出电路的恒压输出的功能。
具体地，当所述恒压输出电路启动时，所述电源电路11输出第一电压信号至所述LM-FOT控制电路12的第一输入端，所述LM-FOT控制电路12启动，所述LM-FOT控制电路12的控制端输出第二电压信号至所述开关电路13的受控端，所述开关电路13启动。与此同时，所述变压器14的原边绕组的一端获得所述电源电路11输出的第一电压信号，由于所述变压器14的原边绕组的另一端与所述开关电路13的输入端连接，因此，当所述开关电路13启动时，所述开关电路13与所述变压器14的原边绕组形成振荡电路，使得流经所述开关电路13的电流逐渐增大。当流经所述开关电路13的电流值增大到一定程度时，所述开关电路13的输出端输出第三电压信号至所述LM-FOT控制电路12的第二输入端，所述LM-FOT控制电路12根据所述开关电路13的输出端输出的第三电压信号控制所述开关电路13关断并记录所述开关电路13的关断时间，当所述开关电路13的关断时长达到预设值后，所述LM-FOT控制电路12再次控制所述开关电路打开，使得所述开关电路13连续重复上述打开与关断的过程。
本发明提供的恒压输出电路省去了高压电解电容，提高了电源功率因素，节省了电能。此外，由于所述LM-FOT控制电路采用固定关断时间的方式控制所述开关电路的通断，从而实现整个恒压输出电路的恒压输出的功能。当所述恒压输出电路的工作频率或者其输入电压占空比发生变化时，所述恒压输出电路的输出状态不会受到其影响。因此，本发明提供的恒压输出电路具有输出电压稳定的特点。
进一步的，如图2所示，本发明提供的恒压输出电路还包括采样电路15。所述采样电路15的信号采集端与所述电源电路11的输出端连接，所述采样电路15的采样信号输出端与所述LM-FOT控制电路12的第一输入端连接。
由于当所述恒压输出电路的输入电压值过大时，可能会损坏所述恒压输出电路内的电气元件。因此，在所述恒压输出电路中增加所述采样电路，可以将所述恒压输出电路的输入电压进行分压处理，从而减小输入至所述LM-FOT控制电路的电压值，减小所述恒压输出电路中电气元件损坏的可能性。
进一步的，如图3所示，本发明提供的恒压输出电路还包括稳压电路16；所述稳压电路16的输入端与所述变压器14的副边绕组的一端连接，所述稳压电路16的输出端为所述恒压输出电路的输出端。由于本发明提供的恒压输出电路省去了高压电解电容，经所述变压器14的副边绕组的一端输出的恒压信号的电压纹波较大，因此，需在所述恒压输出电路中加入稳压电路16以减小所述恒压输出电路的输出端输出的电压纹波，从而使所述恒压输出电路输出的恒压信号更加稳定。
进一步的，如图4所示，本发明提供的恒压输出电路还包括恒压反馈电路17；所述恒压反馈电路17的输入端与所述恒压输出电路的输出端连接，所述恒压反馈电路17的输出端与所述LM-FOT控制电路的反馈端连接。
当所述恒压输出电路的输出端所输出的恒压信号发生异常时，所述恒压反馈电路17的输入端接收到所述恒压输出电路的输出端输出的发生变化的恒压信号，所述恒压反馈电路17的输出端将所述恒压输出电路的输出端输出的发生变化的恒压信号的采样信号输送至所述LM-FOT控制电路12的反馈端，所述LM-FOT控制电路12根据其反馈端接收到的信号控制所述开关电路13的工作状态，使所述恒压输出电路输出正常的恒定电压。
具体地，如图5所示，图5为本发明提供的恒压输出电路的电路原理图。
其中，所述电源电路包括交流电源、EMI滤波器、整流桥。所述交流电源的输出端与所述EMI滤波器的输入端连接；所述EMI滤波器的第一输出端与所述整流桥的第一输入端连接，所述EMI滤波器的第二输出端与所述整流桥的第二输入端连接；所述整流桥的负输出端接地，所述整流桥的正输出端为所述电源电路的11输出端。
当所述电源电路11启动时，所述交流电源输出一定峰值的交流电压。优选的，所述交流电压信号为正弦波信号，其峰值为110V或者220V。所述EMI滤波器的输入端接收到所述交流电源输出的交流电压信号，所述EMI滤波器滤去所述电源输出的交流电压信号的杂波，所述EMI滤波器的输出端将滤去杂波后的交流电压信号输送至所述整流桥。所述整流桥将其接收到的交流电压信号进行整流处理，以输出波形如同所述交流电压信号中负半周信号翻转到正半周而正半周信号不变的电压信号。
所述LM-FOT控制电路12包括倍增器K、LM-FOT调制器T、触发器Q、驱动器D、第一比较器U1、第一电容C1；本实施例中，所述触发器Q选用RS触发器。
所述倍增器K的第一输入端为所述LM-FOT控制电路12的第一输入端，所述倍增器K的第一输出端与所述第一比较器U1的反相输入端连接，所述倍增器K与所述第一比较器U1的连接结点用于引入第一参考电压REF1，所述第一比较器U1的同相输入端为所述LM-FOT控制电路12的第二输入端。所述倍增器K的第二输出端与所述LM-FOT调制器T的第二信号端连接，所述LM-FOT调制器T的第一信号端与所述第一电容C1的一端连接，所述第一电容C1的另一端接地。
所述LM-FOT调制器T的第三信号端与所述RS触发器Q的S端连接，所述LM-FOT调制器T的第四信号端分别与所述RS触发器Q的R端、所述第一比较器U1的输出端连接。所述RS触发器Q的输出端与所述驱动器D的一端连接，所述驱动器D的另一端为所述LM-FOT控制电路12的控制端。
当所述LM-FOT控制电路12启动时，所述倍增器K的第一输入端接收到上述电源电路11输出的电压信号，所述倍增器K将其第一输入端接收到的电压信号进行放大处理后由所述倍增器K的第二输出端输送至所述LM-FOT调制器T的第二信号端。所述LM-FOT调制器T根据其第二信号端接收到的电压信号控制所述RS触发器Q的输出端输出高电平以控制所述开关电路13打开。与此同时，所述第一电容C1开始充电，当所述第一电容C1充满电时，所述第一比较器U1的同相输入端所接收的电压值高于所述第一参考电压REF1，所述第一比较器U1的输出端输出高电平信号，所述RS触发器Q的R端受到触发，所述RS触发器Q的输出端输出低电平以控制所述开关电路13关断。与此同时，所述第一电容C1开始放电，当所述第一电容C1两端电压为0时，所述LM-FOT调制器T控制所述开关电路13打开，连续重复上述过程。由于所述第一电容C1的大小固定，其充电时间与放电时间也随之固定，因此，该LM-FOT控制电路12的功能就是通过固定关断时间控制所述开关电路13的开关。
进一步的，所述LM-FOT控制电路12还包括第二比较器U2；所述第二比较器U2的反相输入端用于引入第二参考电压REF2，所述第二比较器U2的同相输入端与所述第一比较器U1的同相输入端连接，所述第二比较器U2的输出端与所述LM-FOT调制器T的第五信号端连接。
当所述第二比较器U2的同相输入端所接收到的电压值比所述第二参考电压REF2高时，所述第二比较器U2的输出端输出一高电平信号至LM-FOT调制器T的第五信号端，所述LM-FOT调制器T根据其第五信号端接收到的高电平信号控制所述RS触发器Q的输出端输出低电平，以控制所述开关电路13关断。根据所述第二比较器U2的运行原理可知，所述第二比较器U2能够防止高压烧坏电路中的电子元器件，具有保护电路的功能。
进一步的，所述LM-FOT控制电路12还包括第三比较器U3；所述第三比较器U3的同相输入端用于引入第三参考电压REF3，所述第三比较器U3的输入端为所述LM-FOT控制电路12的反馈端，所述第三比较器U3的输出端与所述倍增器K的第二输入端连接。
当所述第三比较器U3的同相输入端所接收的电压值高于所述第三参考电压REF3时，所述第三比较器U3的输出端输出一高电平信号至所述倍增器K的第二输入端，所述倍增器K将其第二输入端接收到的高电平信号进行放大处理后经所述倍增器K的第二输出端输送至所述LM-FOT调制器T的第二信号端，所述LM-FOT调制器T根据其第二信号端接收到的高电平信号增大所述开关电路13的关断时间。
同理，当所述第三比较器U3的同相输入端所接收的电压值低于所述第三参考电压REF3时，所述LM-FOT调制器T根据其第二信号端接收到的低电平信号减小所述开关电路13的关断时间。根据所述第三比较器U3的运行原理可知，所述第三比较器U3能够辅助所述LM-FOT控制电路12对所述开关电路13进行开关控制。
所述开关电路13包括第一增强型NMOS管Q1，第一电阻R1；所述第一增强型NMOS管Q1的漏极为所述开关电路13的输入端，所述第一增强型NMOS管Q1的栅极为所述开关电路13的受控端，所述第一NMOS管Q1的源极与所述第一电阻R1的一端连接；所述第一电阻R1的另一端接地。
当所述开关电路13启动时，所述第一增强型NMOS管Q1的栅极接收到一高电平信号，所述第一增强型NMOS管Q1导通，所述第一增强型NMOS管Q1与变压器14构成振荡电路。尔后，流经所述第一电阻R1的电流逐渐增大，所述第一增强型NMOS管Q1与所述第一电阻R1的连接结点输出的电压值也随之增大，当该电压值增大到高于上述第一参考电压REF1时，所述LM-FOT控制电路12控制所述开关电路13关断。经上述固定关断时间后，所述LM-FOT控制电路12控制所述开关电路13打开。根据所述开关电路13的运行原理可知，所述开关电路13用于与变压器14构成振荡电路，以实现所述变压器14的副边绕组的一端输出恒定电压。
所述稳压电路16包括第十电阻R10、第十一电阻R11、第十二电阻R12；第二增强型NMOS管Q2、第三电容C3、第一可控稳压源W1；本实施例中，所述可控稳压源W1的型号为TL431。
所述第二增强型NMOS管Q2的漏极为所述稳压电路16的输入端。所述第二增强型NMOS管Q2源极分别与所述第九电阻R9、所述第十一电阻R11的一端连接，所述第二增强型NMOS管Q2、所述第九电阻R9、所述第十一电阻R11的连接结点为所述稳压电路16的输出端。
所述第二增强型NMOS管Q2的栅极分别与所述第九电阻R9的另一端、所述第十电阻R10的一端、所述第一可控稳压源W1的阴极连接。所述第十电阻R10的另一端与所述第三电容C3的另一端连接，所述第十电阻R10的另一端分别与所述第十一电阻R11的另一端、所述第十二电阻R12的一端、所述第一可控稳压源W1的参考极连接。所述第十二电阻R12的另一端与所述第一可控稳压源W1的阳极连接，所述第一可控稳压源W1与所述第十二电阻R12的第二连接结点接地。
当所述稳压电路16的输出端输出电压值变大时，流经所述第十一电阻R11、所述第十二电阻R12的电流变大。由于流经所述第二增强型NMOS管Q2的漏极与源极之间的电流恒定，因此，此时流经所述第九电阻R9、所述第一可控稳压源W1的电流变小，所述第一可控稳压源W1的阴极电压减小，所述第二增强型NMOS管Q2的栅极与源极之间的电压差值减小，流经所述第二增强型NMOS管Q2的漏极与源极之间的电流减小，流经所述第十一电阻R11、所述第十二电阻R12的电流减小，所述稳压电路16的输出端输出电压值减小。
同理，当所述稳压电路16的输出端输出的电压值变小时，流经所述第九电阻R9、所述第一可控稳压源W1的电流变大，所述第一可控稳压源W1的阴极电压增大，所述第二增强型NMOS管Q2的栅极与源极之间的电压差值增大，流经所述第二增强型NMOS管Q2的漏极与源极之间的电流增大，流经所述第十一电阻R11、所述第十二电阻R12的电流增大，所述稳压电路16的输出端输出电压值增大。
根据所述稳压电路16的运行原理可知，当所述恒压输出电路的输出端输出的电压值发生变化时，所述稳压电路16可以将式所述恒压输出电路输出的电压值进行调整，从而确保所述恒压输出电路的输出端输出的电压值恒定。
此外，所述变压器14与所述稳压电路16之间还包括第三二极管D3、电感L、第四电容C4、第五电容C5。所述第三二极管D3的阳极与所述变压器14的副边绕组的一端连接，所述第三二极管D3的阴极分别与所述电感L的一端、所述第四电容C4的正极连接。所述电感L的另一端与所述第五电容C5的正极连接，所述电感L与所述第五电容C5的连接结点与所述稳压电路16的输入端连接。所述第四电容C4的负极分别与所述变压器14的副边绕组的另一端、所述第五电容C5的负极连接，所述第四电容C4与所述第五电容C5的连接结点接地。
当所述变压器14的副边绕组的一端输出恒压信号时，所述第三二极管D3滤去所述恒压信号中幅值较小的杂波信号，所述第四电容C4、第五电容C5构成一带通滤波器，以滤去所述恒压信号中的高频杂波信号和低频杂波信号，增加电感L，可以使输出信号更加平缓。
所述恒压反馈电路17包括第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8；第二电容C2、光耦U4、第二可控稳压源W2；本实施例中，所述第二可控稳压源W2的型号为TL421。所述光耦U4的第四信号端连接电源、所述光耦U4的第三信号端为所述恒压反馈电路17的输出端，所述光耦U4的第一信号端与所述第五电阻R5的一端连接，所述第五电阻R5的另一端接电源，所述光耦U4的第二信号端分别与所述第六电阻R6的一端、所述第二可控稳压源W2的阴极连接。所述第六电阻R6的另一端与所述第二电阻R2的一端连接，所述第二电阻R2的另一端分别与所述第七电阻R7的一端、所述第二可控稳压源W2的参考极、所述第八电阻R8的一端连接，所述第七电阻R7的另一端与所述电感L与所述第五电容C5的连接结点连接。所述第八电阻R8的另一端、所述第二可控稳压源W2的阳极接地。
所述第七电阻R7、第八电阻R8用于采集所述电感L的一端输出的恒压信号，所述恒压反馈电路17用于采集所述电感L的一端输出的恒压信号并经光耦U4传送至所述LM-FOT控制电路12，以便所述LM-FOT控制电路12根据所述恒压反馈电路17采集的恒压信号调整所述开关电路13的运行状态，使得所述电感L的一端输出的恒压信号更稳定。
以下，是本实施例提供的上述恒压输出电路的工作过程：
当所述恒压输出电路启动时，所述交流电源输出一正弦波信号，所述EMI滤波器将所述交流电源输出的正弦波信号进行滤波处理后输送至所述整流桥，所述整流桥将所述经滤波处理后的正弦波信号进行整流处理并输出第一电压信号。所述LM-FOT控制电路12中倍增器K的第一输入端获得所述第一电压信号，所述LM-FOT控制电路12启动，所述LM-FOT控制电路12中驱动器D的另一端输出第二电压信号。所述开关电路13中第一增强型NMOS管Q1的栅极获得所述第二电压信号，所述开关电路13启动。
与此同时，所述变压器14的原边绕组的一端获得所述电源电路11中整流桥的整输出端输出的第一电压信号，由于所述变压器14的原边绕组的另一端与所述开关电路13中第一增强型NMOS管的漏极连接，因此，当所述开关电路13启动时，所述第一增强型NMOS管Q1与所述变压器14的原边绕组形成振荡电路，所述振荡电路使得流经所述开关电路13中第一电阻R1以及第一增强型NMOS管Q1的漏极与源极之间的电流逐渐增大，所述开关电路13的第一电阻R1的采样电压值逐渐增大。所述开关电路13的第一电阻R1与第一增强型NMOS管Q1的连接结点输出第三电压信号至所述LM-FOT控制电路12中第一比较器U1的同相输入端。当流经所述开关电路13中第一电阻R1的电流值增大到一定程度时，所述开关电路的第一电阻R1与第一增强型NMOS管Q1的连接结点输出的第三电压信号的电压值大于所述第一参考电压值REF1。所述RS触发器Q的R端为高电平，所述RS触发器Q的输出端输出低电平，所述开关电路13断开。
此时，所述LM-FOT调制器T的第四信号端接收到所述第一比较器U1的输出端输出的高电平信号，所述LM-FOT调制器T记录接收到所述第一比较器U1的输出端输出的高电平信号的时刻，并开始对所述第一电容C1充电，所述第一电容C1两端的电压增大。此外，所述采样电路15将所述电源电路11输出的第一电压信号的采样信号输送至所述LM-FOT控制电路12的倍增器K，所述第一电压信号的采样信号经倍增器K放大后输送至LM-FOT调制器T的第一输入端，当所述第一电容C1两端的电压值增大到与所述LM-FOT调制器T的第二信号端获取的电压值相等时，所述LM-FOT调制器T的第三信号端输出信号至所述RS触发器Q的S端，所述RS触发器Q的输出端输出高电平信号，所述开关电路13导通。依照上述原理重复所述开关电路13打开与关断的过程，实现整个恒压输出电路输出恒定电压的目的。
进一步的，当输出负载过重时，流经所述开关电路13中第一电阻R1的电流增大，所述第一电阻R1两端的电压也随之增大。当所述第一电阻R1两端的电压值大于所述LM-FOT控制电路12中第二比较器U2的第二参考电压REF2时，所述第二比较器U2的输出端输出高电平以触发所述LM-FOT调制器T停止运作，使得所述LM-FOT控制电路12进入保护状态，所述恒压输出电路停止工作。由此可见，在所述LM-FOT控制电路12中增加所述第二比较器U2，可以对该LM-FOT控制电路12起到过载保护的作用。
进一步的，当所述恒压输出电路的输出端输出的电压值变低时，所述恒压反馈电路17的输入端获取所述变低的电压值并对所述变低的电压值进行采样放大处理后输送至所述LM-FOT控制电路12的第三比较器U3的反相输入端。此时，所述LM-FOT控制电路12的第三比较器U3的输出端输出高电平并经所述倍增器K放大后输送至所述LM-FOT调制器T的第二信号端，所述LM-FOT调制器T根据其第二信号端接收到的误差信号增大所述第一增强型NMOS管Q1的开通时间的占空比。由于所述第一增强型NMOS管Q1在所述LM-FOT调制器T的控制下开通时间延长了，因此，所述恒压输出电路的输出端输出的电压值会变大。
同理，当所述恒压输出电路输出的电压值变大时，所述LM-FOT控制电路12根据所述恒压反馈电路17的反馈信号控制所述第一增强型NMOS管Q1的开通时间减小，进而使所述恒压输出电路输出的电压值变小。由此可见，在所述LM-FOT控制电路中12增加所述第三比较器U3，以及在所述恒压输出电路中增加所述恒压反馈电路17，能够使所述恒压输出电路的输出端输出的恒压信号更加稳定。
进一步的，由于本发明采用FOT的控制方式实现所述恒压输出电路的恒压输出，而所述FOT的控制方式是开关电源工作频率可调，固定关断时间的峰值电流控制，在所述恒压输出电路输入电压占空比不同的情况下，输出端的电感L电流保持稳定状态，且本发明是通过所述LM-FOT控制电路12中第一电容C1来固定所述关断时间。因此，当所述LM-FOT控制电路12中第一电容C1的电容值大小设定后，所述恒压输出电路的输入电压范围也随之设定。
由于市电电压大小偏差较大，有110V，有220V等。若所述恒压输出电路的工作频率在60-80KHZ之间，预设的固定关断时间不变，在低压区，所述恒压输出电路电源工作正常，而在高压区，所述恒压输出电路的开通电流会发生突增畸变，该电流突增畸变现象会造成器件的损坏，在此需采用输入线电压调节技术，通过检测输入所述LM-FOT控制电路12的电压大小来调制固定导通时间，即LM（Line-modulated，线电压调制）技术。因此，本发明提供的恒压输出电路增加了采样电路15，使得所述LM-FOT控制电路12同时根据AC输入电压及所述采样电路15的采样信号输出端输出的信号控制所述开关电路13的固定关断时间。
所述采样电路15用于采样整流后的交流市电电压，当市电电压变高时，所述采样电路的第三电阻R3与第四电阻R4的连接结点输出高电平信号，所述高电平信号经过所述LM-FOT控制电路12的倍增器K放大后输送至所述LM-FOT调制器T的第一信号端，所述LM-FOT倍增器K根据其第一信号端接收到的高电平信号延长所述第一增强型NMOS管Q1的关断时间，缩短所述第一增强型NMOS管Q1的开通时间，使整个恒压输出电路在输入电压过高的条件下电流畸变变小，以提高所述恒压输出电路工作的可靠性。
为了更好的说明本发明的思想，本发明给出了所述恒压输出电路的另一实施例。
如图6所示，图6为本发明提供的恒压输出电路的一个具体实施电路结构图。所述恒压输出电路包括上述开关电路13、上述恒压反馈电路17、上述稳压电路16、电源电路18、变压器19、LM-FOT控制芯片20；第十三电阻R13、第十四电阻R14、第十五电阻R15、第十六电阻R16、第十七电阻R17、第十八电阻R18、第十九电阻R19、第二十电阻R20、第二十一电阻R21、第二十二电阻R22、第二十三电阻R23、第二十四电阻R24、第二十五电阻R25；第六电容C6、第七电容C7、第八电容C8；第四二极管D4、第五稳压二极管D5、第三NPN型三极管Q3。其中，所述LM-FOT控制芯片20的型号为L4984。
所述电源电路18的第一输出端分别与所述第十五电阻R15的一端、所述第二十三电阻R23的一端、所述变压器19的第一原边绕组的一端连接；所述电源电路18的第二输出端与所述第十三电阻R13的一端连接。所述第十五电阻R15的另一端与所述第十六电阻R16的一端连接，所述第十六电阻R16的另一端分别与所述第三NPN型三极管Q3的发射极、所述第六电容C6的正极、所述LM-FOT控制芯片20的VCC引脚端连接。所述第十三电阻R13的另一端分别与所述LM-FOT控制芯片20的PFC-OK引脚端、所述第十四电阻R14的一端连接，所述第十四电阻R14的另一端接地，所述第六电容C6的另一端接地。
所述第三NPN型三极管Q3的集电极与所述第十七电阻R17的一端连接，所述第三NPN型三极管Q3的基极分别与所述第十九电阻R19的一端、所述第五稳压二极管D5的阴极连接；所述第十九电阻R19的另一端以及所述第五稳压二极管D5的阳极接地。所述第十七电阻R17与所述第十八电阻R18的连接结点分别与所述第四二极管D4的阴极、所述第八电容C8的正极连接。所述第八电容C8的负极接地，所述第四二极管D2的阳极与所述变压器19的第二原边绕组的一端连接，所述变压器19的第二原边绕组的另一端接地。所述第二十三R23电阻的另一端与所述第二十四电阻R24的一端连接，所述第二十四电阻R24的另一端分别与所述第二十二电阻R22的一端、所述LM-FOT控制芯片20的MULT引脚端连接。
所述LM-FOT控制芯片20的GATE引脚端与所述开关电路13的受控端连接；所述LM-FOT控制芯片20的TIME引脚端与所述第七电容C7的一端连接，所述第七电容C7的另一端接地；所述LM-FOT控制芯片20的INV引脚端与所述第二十电阻R20的一端连接，所述第二十电阻R20的另一端分别与所述第二十一电阻R21的一端、所述恒压反馈电路17的输出端连接，所述第二十一电阻R21的另一端接地；所述LM-FOT控制芯片20的CS引脚端与所述第二十五电阻R25的一端连接。
所述第二十五电阻R25的另一端与所述开关电路13的输出端连接，所述开关电路13的输入端与所述变压器19的第一原边绕组的另一端连接。所述变压器19的副边绕组的一端与所述第三二极管D3的阳极连接，所述第三二极管D3的阴极分别与所述电感L的一端、所述第四电容C4的正极连接；所述电感L的另一端分别与所述第五电容C5的正极、所述稳压电路16的输入端连接；所述变压器19的副边绕组的另一端、所述第四电容C4的负极以及所述第五电容C5的负极接地。
具体的，当所述恒压输出电路启动时，所述电源电路18的第一输出端输出第一电压信号至所述变压器19的第一原边绕组的一端。与此同时，所述第十五电阻R15、第十六电阻R16、第六电容C6构成所述LM-FOT控制芯片20的预启动电路，所述第十五电阻R15以及所述第十六电阻R16对所述第六电容C6充电，当所述第六电容C6电压升高后，所述LM-FOT控制芯片20开始启动工作，控制所述第一增强型NMOS管Q1打开，然后所述变压器19的第二原边绕组便可输出VCC电压至所述第四二极管D4以及第八电容C8。
所述第十八电阻R18、所述第十九电阻R19根据所述第八电容C8的充电电压控制所述第三NPN型三极管Q3的基极电压，使所述第三NPN三极管Q3的集电极输出恒定的电压。所述第十七电阻R17作为限流电阻，所述第五稳压二极管D5作为所述第三NPN型三极管Q3的稳压保护二极管，当所述LM-FOT控制芯片20的VCC引脚端电压稳定后，所述LM-FOT控制芯片20正常工作。所述LM-FOT控制芯片20控制所述变压器19振荡，使得所述变压器19的第二原边绕组输出VCC为所述LM-FOT控制芯片20提供稳定的工作电压，所述变压器19在所述LM-FOT控制芯片20的控制下输出恒定的电压12V。所述变压器19的副边绕组的一端输出的恒定电压经所述稳压电路16滤除纹波后输出，为外界电子设备供电，比如为电视机供电。
进一步的，所述第十三电阻R13和第十四电阻R14构成分压取样电路，所述第十三电阻R13与第十四电阻R14的连接结点将取样后的电压输入至所述LM-FOT控制芯片20的PFC-OK引脚端，作为所述恒压输出电路的输入欠压检测功能，可设置输入过欠压保护，如当市电电压小于65V时，所述LM-FOT控制芯片20停止工作，当市电恢复至85V后所述LM-FOT控制芯片20开启工作，当市电电压大于310V时，所述LM-FOT控制芯片20停止工作。
所述LM-FOT控制芯片20的TIME引脚端与所述第七电容C7的一端连接，用于设置固定关断时间。所述固定关断时间的实现方式是：当所述第一增强型NMOS管Q1打开时，所述第一电阻R1的取样的电压逐渐增大，当所述第一电阻R1的取样电压大于所述LM-FOT控制芯片20的CS引脚端内部的参考电压时，所述LM-FOT控制芯片20的GATE引脚端输出控制信号控制所述开关电路13，使所述第一增强型NMOS管Q1关断，与此同时，所述LM-FOT控制芯片20记录所述第一增强型NMOS管Q1关断的时刻。一方面，所述LM-FOT控制芯片20对所述第七电容C7充电，使得所述第七电容C7两端的电压逐渐增大。另一方面，所述LM-FOT控制芯片20的MULT引脚端通过所述第二十二电阻R22获得所述电源电路第一输出段输出的第一电压信号。当所述第七电容C7两端的电压增大到等于所述第二十二电阻R22两端的电压后，所述固定关断时间结束，所述LM-FOT控制芯片20的GATE引脚端返转使所述第一增强型NMOS管Q1开通。不断重复上述开关电路13打开与关断的过程，实现所述恒压输出电路的恒压输出。
由于根据上一实施例内容可知，当所述恒压输出电路的输入电压在一定范围内时，所述关断时间是固定的。而市电电压大小偏差较大，有110V，有220V等，若开关电源的工作频率在60-80KHZ之间，固定关断时间不变，在低压区，电源工作正常，而在高压区，所述恒压输出电路的开通电流会发生突增畸变，且该开通电流的突增畸变现象会造成器件的损坏。因此，需采用输入线电压调节技术，即通过检测线电压大小来调制固定导通时间。所述线电压调节技术的实现方式是：由所述第二十三电阻R23、所述第二十四电阻R24、所述第二十二电阻R23构成线电压取样电路，用于取样经整流后的交流市电电压，当市电电压变高时，所述线电压取样电路取样到高电平信号并输送至所述LM-FOT控制芯片20的MULT引脚端，所述LM-FOT控制芯片20根据所述取样的高电平信号延长所述第一增强型NMOS管Q1的关断时间，缩短所述第一增强型NMOS管Q1的开通时间，使得所述恒压输出电路在高输入电压下电流畸变变小，以提高所述恒压输出电路可靠性。
进一步的，当所述恒压输出电路的输出负载过重时，所述第一电阻R1两端的电压增大，当所述第一电阻R1两端的电压值大于所述LM-FOT控制芯片20的CS引脚端的内部参考电压值时，所述LM-FOT控制芯片20停止工作，所述LM-FOT控制芯片20进入保护状态，所述恒压输出电路停止工作。
本发明提供的恒压输出电路省去了大电解电容，避免了电路中电流超前电压，使市电与电流同相位供电，相对于现有技术，提高了电源功率因素，节省了市电实际电能。采用固定关断时间方式工作，使得所述恒压输出电路的输出状态不受所述恒压输出电路的工作频率以及其输入电压占空比的影响，提高了所述恒压输出电路输出电压的稳定性。采用电压调制来固定关断时间，使得所述恒压输出电路可在输入市电电压过高的情况下运作，提高了所述恒压输出电路的可靠性。
本发明还提供了一种反激开关电源以及其电子设备，所述电子设备为适配器、液晶显示器，投影仪或医疗器械。所述反激开关电源包括上述的恒压输出电路，该恒压输出电路包括实施上述任一实施例中的技术方案，其详细电路组成结构可参照图1至图6，在此不作赘述，由于采用了上述电源电路的方案，本发明相较于现有技术而言，生产成本更低，可靠性更强。
以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种恒压输出电路，其特征在于，所述恒压输出电路包括电源电路、LM-FOT控制电路、开关电路、变压器；
    所述电源电路的输出端分别与所述LM-FOT控制电路的第一输入端、所述变压器的原边绕组的一端连接；所述LM-FOT控制电路的控制端与所述开关电路的受控端连接，所述LM-FOT控制电路的第二输入端与所述开关电路的输出端连接；所述开关电路的输入端与所述变压器的原边绕组的另一端连接；所述变压器的副边绕组的一端为所述恒压输出电路的输出端，所述变压器的副边绕组的另一端接地；
    所述LM-FOT控制电路根据电源电路输出的电压信号控制所述开关电路的固定关断时间，实现所述恒压输出电路中变压器的副边绕组的一端输出恒定电压的功能。
  2. 如权利要求1所述的恒压输出电路，其特征在于，所述恒压输出电路还包括采样电路；所述采样电路的信号采集端与所述电源电路的输出端连接，所述采样电路的采样信号输出端与所述LM-FOT控制电路的第一输入端连接。
  3. 如权利要求1所述的恒压输出电路，其特征在于，所述恒压输出电路还包括恒压反馈电路；所述恒压反馈电路的输入端与所述恒压输出电路的输出端连接，所述恒压反馈电路的输出端与所述LM-FOT控制电路的反馈端连接。
  4. 如权利要求1所述的恒压输出电路，其特征在于，所述恒压输出电路还包括稳压电路；所述稳压电路的一端与所述变压器的副边绕组的一端连接，所述稳压电路的另一端为所述恒压输出电路的输出端。
  5. 如权利要求1所述的恒压输出电路，其特征在于，所述开关电路包括第一增强型NMOS管，第一电阻；
    所述第一增强型NMOS管的漏极为所述开关电路的输入端，所述第一增强型NMOS管的栅极为所述开关电路的受控端，所述第一增强型NMOS管的源极与所述第一电阻的一端连接；所述第一增强型NMOS管与所述第一电阻的连接结点为所述开关电路的输出端，所述第一电阻的另一端接地。
  6. 如权利要求1所述的恒压输出电路，其特征在于，所述LM-FOT控制电路包括倍增器、LM-FOT调制器、触发器、驱动器、第一比较器以及第一电容；
    所述倍增器的第一输入端为所述LM-FOT控制电路的第一输入端，所述倍增器的第一输出端与所述第一比较器的反相输入端连接，所述倍增器与所述第一比较器的连接结点用于引入第一参考电压，所述倍增器的第二输出端与所述LM-FOT调制器的第二信号端连接；
    所述第一比较器的同相输入端为所述LM-FOT控制电路的第二输入端，所述第一比较器的输出端分别与所述LM-FOT调制器的第四信号端、所述触发器的第二信号端连接；所述LM-FOT调制器的第一信号端与所述第一电容的一端连接，所述第一电容的另一端接地；所述LM-FOT调制器的第三信号端与所述触发器的第一信号端连接；所述触发器的输出端与所述驱动器的一端连接，所述驱动器的另一端为所述LM-FOT控制电路的控制端。
  7. 如权利要求6所述的恒压输出电路，其特征在于，所述LM-FOT控制电路还包括第二比较器；所述第二比较器的反相输入端用于引入第二参考电压，所述第二比较器的同相输入端与所述第一比较器的同相输入端连接，所述第二比较器的输出端与所述LM-FOT调制器的第五信号端连接。
  8. 如权利要求7所述的恒压输出电路，其特征在于，所述LM-FOT控制电路还包括第三比较器；所述第三比较器的同相输入端用于引入第三参考电压，所述第三比较器的反相输入端为所述LM-FOT控制电路的反馈端，所述第三比较器的输出端与所述倍增器的第二输入端连接。
  9. 一种反激开关电源，其特征在于，所述反激开关电源包括如权利要求1所述的恒压输出电路，所述恒压输出电路包括电源电路、LM-FOT控制电路、开关电路、变压器；
    所述电源电路的输出端分别与所述LM-FOT控制电路的第一输入端、所述变压器的原边绕组的一端连接；所述LM-FOT控制电路的控制端与所述开关电路的受控端连接，所述LM-FOT控制电路的第二输入端与所述开关电路的输出端连接；所述开关电路的输入端与所述变压器的原边绕组的另一端连接；所述变压器的副边绕组的一端为所述恒压输出电路的输出端，所述变压器的副边绕组的另一端接地；
    所述LM-FOT控制电路根据电源电路输出的电压信号控制所述开关电路的固定关断时间，实现所述恒压输出电路中变压器的副边绕组的一端输出恒定电压的功能。
  10. 如权利要求9所述的反激开关电源，其特征在于，所述恒压输出电路还包括采样电路；所述采样电路的信号采集端与所述电源电路的输出端连接，所述采样电路的采样信号输出端与所述LM-FOT控制电路的第一输入端连接。
  11. 如权利要求9所述的反激开关电源，其特征在于，所述恒压输出电路还包括恒压反馈电路；所述恒压反馈电路的输入端与所述恒压输出电路的输出端连接，所述恒压反馈电路的输出端与所述LM-FOT控制电路的反馈端连接。
  12. 如权利要求9所述的反激开关电源，其特征在于，所述恒压输出电路还包括稳压电路；所述稳压电路的一端与所述变压器的副边绕组的一端连接，所述稳压电路的另一端为所述恒压输出电路的输出端。
  13. 如权利要求9所述的反激开关电源，其特征在于，所述开关电路包括第一增强型NMOS管，第一电阻；
    所述第一增强型NMOS管的漏极为所述开关电路的输入端，所述第一增强型NMOS管的栅极为所述开关电路的受控端，所述第一增强型NMOS管的源极与所述第一电阻的一端连接；所述第一增强型NMOS管与所述第一电阻的连接结点为所述开关电路的输出端，所述第一电阻的另一端接地。
  14. 如权利要求9所述的反激开关电源，其特征在于，所述LM-FOT控制电路包括倍增器、LM-FOT调制器、触发器、驱动器、第一比较器以及第一电容；
    所述倍增器的第一输入端为所述LM-FOT控制电路的第一输入端，所述倍增器的第一输出端与所述第一比较器的反相输入端连接，所述倍增器与所述第一比较器的连接结点用于引入第一参考电压，所述倍增器的第二输出端与所述LM-FOT调制器的第二信号端连接；
    所述第一比较器的同相输入端为所述LM-FOT控制电路的第二输入端，所述第一比较器的输出端分别与所述LM-FOT调制器的第四信号端、所述触发器的第二信号端连接；所述LM-FOT调制器的第一信号端与所述第一电容的一端连接，所述第一电容的另一端接地；所述LM-FOT调制器的第三信号端与所述触发器的第一信号端连接；所述触发器的输出端与所述驱动器的一端连接，所述驱动器的另一端为所述LM-FOT控制电路的控制端。
  15. 如权利要求14所述的反激开关电源，其特征在于，所述LM-FOT控制电路还包括第二比较器；所述第二比较器的反相输入端用于引入第二参考电压，所述第二比较器的同相输入端与所述第一比较器的同相输入端连接，所述第二比较器的输出端与所述LM-FOT调制器的第五信号端连接。
  16. 如权利要求15所述的反激开关电源，其特征在于，所述LM-FOT控制电路还包括第三比较器；所述第三比较器的同相输入端用于引入第三参考电压，所述第三比较器的反相输入端为所述LM-FOT控制电路的反馈端，所述第三比较器的输出端与所述倍增器的第二输入端连接。
  17. 一种电子设备，所述电子设备为适配器、液晶显示器，投影仪或医疗器械，其特征在于，所述电子设备包括如权利要求9所述的反激开关电源。
PCT/CN2016/086524 2015-11-30 2016-06-21 恒压输出电路、反激开关电源及其电子设备 WO2017092286A1 (zh)

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