WO2017091963A1 - 一种信息处理方法及装置 - Google Patents
一种信息处理方法及装置 Download PDFInfo
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- WO2017091963A1 WO2017091963A1 PCT/CN2015/096047 CN2015096047W WO2017091963A1 WO 2017091963 A1 WO2017091963 A1 WO 2017091963A1 CN 2015096047 W CN2015096047 W CN 2015096047W WO 2017091963 A1 WO2017091963 A1 WO 2017091963A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
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- the present invention relates to the field of computer technologies, and in particular, to an information processing method and apparatus.
- timing related requirements such as executing a specified task after a specified time, and periodically performing a specified task every specified time interval.
- the timing of the time comes from the timing interrupt, through the technique of timing interrupt, compare the task to the time, and then execute the specified function to achieve the purpose.
- the timer interrupt source periodically issues an interrupt to the processor through the bus, and when the processor receives the interrupt, compares the task to the time, and then performs the specified task.
- timer In the art, it is common to support a component of software and/or hardware that performs a specified function or task after a specified time or at a fixed period, referred to as a timer.
- the timer has a high-precision timer and a low-precision timer, which are relative concepts.
- the accuracy of a low-precision timer is generally in the order of milliseconds (ms)
- the precision of a high-precision timer is in the order of nanoseconds (ns) or microseconds (us).
- the implementation of the timer adopts the software time wheel mode. Specifically, a time wheel is constructed in the software, and the time interval of each time slot, that is, the timing precision, is configured. Then add the periodic timed task and the one-timed timed task to the task list of each time slot.
- the processor receives the timer interrupt and interrupts the current task. The frequency of the interrupt is timing precision.
- the interrupt processing function pushes the current position of the software time wheel to rotate one space, and the tasks in the current list of the task list are taken out one by one.
- the timer precision is high, for example, at the 10us level, the interrupts come very frequently, and each interrupt requires the processor to perform interrupt processing.
- the timer has high precision, but the timing tasks mounted on the time wheel may not be many, so too frequent terminals will seriously affect the performance of the system.
- the embodiment of the invention provides an information processing method and device, which are used to solve the existing technology.
- an embodiment of the present invention provides an information processing method, including:
- a message is sent to the processing module to cause the processing module to interrupt the current task and process the timed task.
- the current task when receiving the timer interrupt, the current task is not interrupted first, but the current time grid is first determined whether there is a timing task, and the processing module interrupts the current task and processes only when there is a timing task.
- the solution in the embodiment of the present invention can reduce the waste of processing resources and improve system performance, as compared with the prior art, as long as the timing interrupt is received, and the current task is interrupted regardless of whether there is a timing task.
- the method further includes:
- the timed task list on each time grid is operated.
- the solution in the embodiment of the present invention can flexibly configure the timed task on the time grid, and is convenient to be applied to multiple application scenarios.
- an electronic device including:
- the hardware time wheel is configured to receive the timer interrupt, and determine whether there is a timing task in the current time grid, and send a message to the processor when there is a timing task;
- the processor is configured to interrupt a current task and process the timing task according to the message.
- the processor is further configured to send an operation request to the hardware time wheel;
- the hardware time wheel is further configured to operate on the timed task list on each time grid according to the operation request.
- an embodiment of the present invention provides a hardware time wheel, including:
- a receiving interface for receiving a timing interrupt
- a task management component comprising a memory and a controller
- the memory is configured to store a time grid and a timed task list corresponding to each time grid
- the controller is configured to determine whether there is a timing task in the current time grid; Sending a message to the processor through the sending interface, so that the processor interrupts the current task and processes the timing task.
- the receiving interface is further configured to receive an operation request sent by the processor
- the controller is further configured to operate, according to the operation request, a timing task linked list corresponding to each time frame.
- an embodiment of the present invention provides a processor, including:
- the hardware time wheel is used to determine whether there is a timing task in the current time frame, and when there is a timed task, send a message to the control module;
- At least one processing core At least one processing core
- the control module is configured to control the at least one processing core to interrupt a current task and process the timing task.
- the technical solution in this embodiment facilitates circuit layout because the hardware time wheel and the control module are integrated in the processor.
- control module is further configured to send an operation request to the hardware time slot
- the hardware time wheel is further configured to operate on a timed task list of each time grid according to the operation request.
- an embodiment of the present invention provides an electronic device, including:
- a memory for storing data required by the processor to operate.
- the operation request is to delete a scheduled task, add a timing task, Modify one or more operational requests in a scheduled task.
- FIG. 1 is a structural diagram of an electronic device according to an embodiment of the present invention.
- FIG. 2 is a structural diagram of a hardware time wheel according to an embodiment of the present invention.
- FIG. 3 is a flowchart of an information processing method according to an embodiment of the present invention.
- FIG. 4 is a schematic diagram of interaction of internal components of a hardware time wheel and interaction with external components according to an embodiment of the present invention
- FIG. 5 is a structural diagram of a processor according to an embodiment of the present invention.
- the embodiments of the present invention provide an information processing method and apparatus, which are used to solve the technical problem of system performance degradation caused by frequent interruptions in the prior art.
- FIG. 1 is a structural diagram of an electronic device according to an embodiment of the present invention.
- the electronic device includes a hardware time wheel 10 and a processor 20.
- the hardware time wheel 10 and the processor 20 can be connected via a bus.
- the hardware time wheel 10 and the processor 20 may not be a bus structure, but may be other structures, such as a star structure, which is not specifically limited in this application.
- the processor 20 may be a central processing unit or an application specific integrated circuit (ASIC), and may be used in one or more applications.
- the integrated circuit executed by the control program may be a hardware circuit developed using a Field Programmable Gate Array (FPGA), which may be a baseband processor.
- FPGA Field Programmable Gate Array
- the processor 20 may include at least one processing core, such as the processing core 1 and the processing core 2 in FIG.
- the electronic device can also include a memory.
- the memory may include a read only memory (English: Read Only Memory, ROM for short), a random access memory (English: Random Access Memory, RAM for short), and a disk storage.
- the memory is used to store data required by the processor 20 to operate.
- the number of memories can be one or more.
- the hardware time wheel 10 includes a receiving interface 101, a task management component 102, and a transmitting interface 103.
- Task management component 102 includes a memory and a controller. The memory is used to store the time grid and the timed task list corresponding to each time grid.
- the receiving interface 101 and the sending interface 103 may be a bus interface, or may be other interfaces, specifically related to the transmission mode of the timed interrupt, the connection structure between the hardware time wheel 10 and the processor 20.
- the receiving interface 101 and the sending interface 103 can be implemented by using various forms of hardware structures, which are well known to those skilled in the art, and therefore are not described herein.
- Each time grid can be an array, and the timed task list corresponding to each time grid is stored in the corresponding array.
- the timed task stored in the array may include a task name and a function corresponding to the task, or may be a task name and an entry address of a function corresponding to the task.
- time grid can also be implemented in other forms, which is not specifically limited in this application.
- a timed interrupt will be generated and the next time frame will be skipped.
- the number of time slots is configurable for design implementation.
- the number of time slots is usually a power of two, for example, 1024.
- FIG. 3 is a flowchart of an information processing method in an embodiment of the present invention. As shown in FIG. 3, the method includes:
- Step 11 Receive a timer interrupt
- Step 12 Determine whether there is a timing task on the current time grid
- Step 13 When there is a timed task, send a message to the processing module, so that the processing module interrupts the current task and processes the timed task.
- the timing interrupt is generated according to the timing precision.
- the timing precision is 100 us, then a timer interrupt is generated every 100 us.
- the timer interrupt is input to the hardware time wheel 10, specifically, for example, a timer interrupt input to the receiving interface 101. Therefore, the receiving interface 101 is for receiving a timer interrupt.
- step 12 is performed to determine whether there is a timing task on the current time grid.
- this step is performed, for example, by hardware time wheel 10.
- the controller of the task management component 102 receives the timer interrupt through the receiving interface 101, it acquires the address of the next array of the current array, and the next array corresponds to the current time grid. Then it is determined whether a timed task is stored in the array. This case is applicable to the case where the interruption occurs first and then the movement of the time grid is performed.
- the controller of the task management component 102 when the controller of the task management component 102 receives the timer interrupt through the receiving interface 101, it acquires the address of the current array and determines whether a timer task is stored in the array. This situation applies to the first time the cell beats and then waits for the interrupt to occur. For example, after each step 12 is executed, it jumps to the next array and then waits for the next timer interrupt to arrive.
- step 12 Since it is not possible to add a timing task to each time frame, the judgment in step 12 is performed. If the timed list corresponding to the time grid is not empty, it means that there is a timed task on the current time grid to be executed. Otherwise, it means that there is no timed task to execute in the current time grid.
- step 13 When there is a timed task, step 13 is performed, that is, a message is sent to the processing module, so that the processing module interrupts the current task and processes the timed task.
- step 13 is performed by the hardware time wheel 10.
- the processing module in step 13 is the processor 20.
- the task management component 102 sends a message to the processor 20 via the transmit interface 103 to cause the processor 20 to interrupt the current task and process the timed task.
- the message may include a name of the scheduled task and a task function corresponding to the task.
- the processor 20 can directly execute the task function in the message.
- the message may include a name of the scheduled task and an entry address of the task function corresponding to the task.
- the processor 20 may first acquire the task function by using the entry address of the task function in the message, and then execute the task function.
- timing tasks when there are multiple timing tasks, they may be executed in order according to the task order.
- FIG. 4 is a diagram of interaction between the hardware time wheel 10 and the external environment and internal components according to an embodiment of the present invention.
- time slots T0 to Tn are stored on the memory, and n is a positive integer.
- the controller receives the timer interrupt through the receive interface 101.
- the controller determines that the current time grid is the time grid T0.
- the time frame T0 exists, for example, in the form of an array, and the controller obtains the address of the array on the memory. Then read the timed task list in the array. Then determine whether there is a timing task in the timed task list. In this example, there are three timed tasks corresponding to the time frame T0, which are task 1 to task 3. Therefore, the controller sends a message to the processor 20 through the transmission interface 103.
- the message includes a task function corresponding to each task.
- the task function of the three tasks may be carried in one message, or the task function corresponding to one task may be carried in each message, and then three messages are sent to the processor 20.
- the current time frame is T1. Assuming that there is no timed task on the time grid T1, the controller will not send a message to the processor 20, then the processor 20 will continue to process the current task without interruption, so that the processing resources will not be wasted, thereby improving the system. performance.
- the hardware time wheel first determines whether there is a timed task on the current time frame, and only when there is a timed task, the message is sent to the processor, and the processor interrupts the current task and processes the current task. Timed tasks. Compared with the prior art, after each timed interrupt is generated, the solution in the embodiment of the present invention can achieve high-precision timing and improve system performance.
- the method further includes: receiving an operation request of the processing module; and according to the operation request, each time The timing task list on the grid operates.
- the operation request may be any one or more operation requests, such as adding a timing task, deleting a timing task, and modifying a timing task.
- the operation request may include a type of operation, and may further include a time grid corresponding to the operation request.
- the processing module is the processor 20.
- the body that receives the operation request and operates on the timing list on each time grid according to the operation request is the hardware time wheel 10.
- the controller receives the operation request sent by the processor 20 through the receiving interface 10, for example, performs a timing task on the time frame T0 (for example, task 1 in FIG. 4). Deleted operation request.
- the controller obtains the address of the time frame T0 on the memory and deletes the task 1 in the timed task list.
- the processor 20 directly accesses the memory of the task management component 102, and directly deletes, adds, or modifies the task corresponding to the time grid.
- FIG. 5 is a structural diagram of a processor 30 according to an embodiment of the present invention.
- the processor 30 includes an interrupt interface 301, a hardware time wheel 302, at least one processing core 304, and a control module 303.
- the interrupt interface 301 is an interrupt pin.
- the interrupt interface 301 is configured to perform step 11, that is, receive a timer interrupt.
- the structure of the hardware time wheel 302 is similar to that of FIGS. 2 and 4, except that the receiving interface of the hardware time wheel 302 only needs to match the interrupt interface 301.
- the type of the transmission interface only needs to match the control module 303.
- the hardware time wheel 302 is used to perform steps 12 to 13, that is, whether the current time frame is There are timed tasks that send messages to the processing module when there are timed tasks.
- the processing module in step 13 is the control module 303.
- the control module 303 is configured to control the at least one processing core 304 to interrupt the current task and process the timing task.
- the processor when receiving the timer interrupt, the processor does not need to immediately interrupt the current task as in the prior art, but first determines whether there is a timing task on the current time grid, only in the When there is a timed task, the current task execution timed task will be interrupted. When there is no timed task in the current time grid, there is no need to interrupt the current task, and the current task can be continued, so the processing resources of the processor are saved, and the system performance is improved.
- the hardware time wheel 302 and the control module 303 are integrated in the processor 30, so that the layout of the system circuit is more convenient and convenient to use.
- control module 303 is further configured to send an operation request to the hardware time wheel 302.
- the hardware time wheel 302 is further configured to operate the timed task list of each time frame according to the operation request.
- the operation request in this example has the same meaning as the operation request described above, and details are not described herein again.
- an embodiment of the present invention further provides an electronic device.
- the electronic device includes the processor 30 and memory described in FIG. 5 and its embodiments.
- the memory is used to store data required by the processor 30 to operate.
- the number of memories can be one or more.
- the memory can include ROM, RAM, and disk storage. These memories are coupled to the processor 30 via a bus.
- the electronic device may be a user side device or a network side device.
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Abstract
本发明提供一种信息处理方法及装置。该方法包括：接收定时中断；判断在当前时间格上是否有定时任务；在有定时任务时，发送消息给处理模块，以使所述处理模块中断当前任务并处理所述定时任务。通过该方法，能够避免没有必要的任务中断，提高系统性能。
Description
本发明涉及计算机技术领域，尤其涉及一种信息处理方法及装置。
在软件系统中，有何定时相关的需求，例如在指定时间后执行指定任务，每间隔指定时间就周期性执行指定任务。定时的时间根源来自于定时中断，通过对定时中断的技术，比较任务是否到时，然后执行指定函数来达成目的。举例来说，定时中断源通过总线向处理器定时发中断，处理器在接收到中断时，比较任务是否到时，然后执行指定任务。
在本技术领域，通常将支持在指定时间后或固定周期时，执行指定函数或任务的软件和/或硬件的组件称为定时器。定时器有高精度定时器和低精度定时器之分，二者是相对的概念。通常，低精度定时器的精度一般为毫秒(ms)级别，高精度定时器的精度为纳秒(ns)或微秒(us)级别。
在现有技术中，定时器的实现方式采用的是软件时间轮方式，具体的，在软件中构造一个时间轮，配置时间轮每格的时间间隔，即定时精度。然后将周期定时任务、一次性定时任务添加在时间轮每格的任务链表中。处理器接收定时器中断并中断当前任务，中断的频率为定时精度。中断处理函数推动软件时间轮的当前位置转动一格，将当前格的任务链表中的任务取出逐个执行。
当定时器精度高时，例如10us级别时，中断来的非常频繁，每个中断都需要处理器进行中断处理。然而，实际上，定时器精度高，但是时间轮上挂载的定时任务可能并不多，所以过于频繁的终端会严重影响系统的性能。
发明内容
本发明实施例提供一种信息处理方法及装置，用以解决现有技术中存在
的中断频繁导致的系统性能下降的技术问题。
第一方面，本发明实施例提供一种信息处理方法，包括：
接收定时中断；
判断在当前时间格上是否有定时任务；
在有定时任务时，发送消息给处理模块，以使所述处理模块中断当前任务并处理所述定时任务。
因为在本发明实施例中，在接收到定时中断时，先不中断当前任务，而是先判断当前时间格上是否有定时任务，只有在有定时任务时，处理模块才会中断当前任务并处理定时任务，所以相较于现有技术中只要接收到定时中断，不管是否有定时任务就中断当前任务的方案而言，本发明实施例中的方案能够降低处理资源的浪费，提高系统性能。
结合第一方面，在第一方面的第一种可能的实现方式中，所述方法还包括：
接收所述处理模块的操作请求；
根据所述操作请求，对每个时间格上的定时任务链表进行操作。
因此，本发明实施例中的方案能够对时间格上的定时任务进行灵活的配置，便于应用到多种应用场景中。
第二方面，本发明实施例提供一种电子设备，包括：
硬件时间轮，用于接收定时中断，并判断在当前时间格上是否有定时任务，在有定时任务时，发送消息给处理器；
所述处理器，用于根据所述消息中断当前任务并处理所述定时任务。
结合第二方面，在第二方面的第一种可能的实现方式中，所述处理器还用于发送操作请求给所述硬件时间轮；
所述硬件时间轮还用于根据所述操作请求，对每个时间格上的定时任务链表进行操作。
第三方面，本发明实施例提供一种硬件时间轮，包括：
接收接口，用于接收定时中断；
发送接口；
任务管理组件，包括存储器和控制器，所述存储器用于存储时间格和每个时间格对应的定时任务链表；所述控制器用于判断在当前时间格上是否有定时任务；在有定时任务时，通过所述发送接口发送消息给处理器，以使所述处理器中断当前任务并处理所述定时任务。
结合第三方面，在第三方面的第一种可能的实现方式中，所述接收接口还用于接收所述处理器发送的操作请求；
所述控制器还用于根据所述操作请求对所述每个时间格对应的定时任务链表进行操作。
第四方面，本发明实施例提供一种处理器，包括：
中断接口，用于接收定时中断；
硬件时间轮，用于判断在当前时间格上是否有定时任务，在有定时任务时，发送消息给控制模块；
至少一个处理核心；
所述控制模块，用于控制所述至少一个处理核心中断当前任务并处理所述定时任务。
本实施例中的技术方案除了能够达到第一方面中的方法所能达到的技术效果之外，因为将硬件时间轮和控制模块集成在处理器中，所以便于电路布局。
结合第四方面，在第四方面的第一种可能的实现方式中，所述控制模块还用于向所述硬件时间轮发送操作请求；
所述硬件时间轮还用于根据所述操作请求对每个时间格的定时任务链表进行操作。
第五方面，本发明实施例提供一种电子设备，包括：
如第四方面或第四方面的第一种可能的实现方式中所述的处理器；
存储器，用于存储所述处理器工作时所需的数据。
在一些可能的实现方式中，操作请求为删除定时任务、增加定时任务、
修改定时任务中的一种或多种操作请求。
图1为本发明实施例提供的一种电子设备的结构图；
图2为本发明实施例提供的一种硬件时间轮的结构图；
图3为本发明实施例提供的一种信息处理方法的流程图；
图4为本发明实施例提供的一种硬件时间轮内部元件的交互以及与外部元件的交互示意图；
图5为本发明实施例提供的一种处理器的结构图。
本发明实施例提供一种信息处理方法及装置，用以解决现有技术中存在的中断频繁导致的系统性能下降的技术问题。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供的一种信息处理方法。该方法可以应用于一种电子设备。该电子设备例如为用户侧设备，也可以是网络侧设备。如图1所示，为本发明实施例提供的一种电子设备的结构图。该电子设备包括硬件时间轮10和处理器20。硬件时间轮10和处理器20可以通过总线进行连接。当然，在实际运用中，硬件时间轮10和处理器20之间可以不是总线结构，而可以是其它结构，例如星型结构，本申请不作具体限定。
可选的，处理器20具体可以是中央处理器、特定应用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)，可以是一个或多个用于
控制程序执行的集成电路，可以是使用现场可编程门阵列(英文：Field Programmable Gate Array，简称：FPGA)开发的硬件电路，可以是基带处理器。
可选的，处理器20可以包括至少一个处理核心，例如图1中的处理核心1和处理核心2。
进一步，电子设备还可以包括存储器。存储器可以包括只读存储器(英文：Read Only Memory，简称：ROM)、随机存取存储器(英文：Random Access Memory，简称：RAM)和磁盘存储器。存储器用于存储处理器20运行时所需的数据。存储器的数量可以是一个或多个。
接下来请参考图2所示，为硬件时间轮10一种可能的实现结构图。如图2所示，硬件时间轮10包括接收接口101、任务管理组件102和发送接口103。任务管理组件102包括存储器和控制器。存储器用于存储时间格和每个时间格对应的定时任务链表。
可选的，接收接口101和发送接口103可以是总线接口，也可以是其它接口，具体与定时中断的传输方式、硬件时间轮10和处理器20之间的连接结构相关。
可选的，接收接口101和发送接口103可以采用多种形式的硬件结构实现，该部分内容为本领域技术人员所熟知的内容，所以在此不再赘述。
每个时间格可以是一个数组，每个时间格对应的定时任务链表存储在对应的数组中。
可选的，数组中存储的定时任务可以包括任务名称和任务对应的函数，也可以是任务名称和任务对应的函数的入口地址。
在实际运用中，时间格也可以通过其它形式实现，本申请不作具体限定。
可选的，对应一个定时精度，就会产生一个定时中断，就会跳到下一个时间格。
可选的，时间格的数量是可以配置的，便于设计实现，时间格的数量通常为2的幂，例如为1024。
接下来请参考如图3所示，为本发明实施例中的信息处理方法的流程图。如图3所示，该方法包括：
步骤11：接收定时中断；
步骤12：判断在当前时间格上是否有定时任务；
步骤13：在有定时任务时，发送消息给处理模块，以使所述处理模块中断当前任务并处理所述定时任务。
具体的，在实际运用中，定时中断按照定时精度产生，例如定时精度为100us，那么每隔100us就产生一个定时中断。
当产生定时中断时，定时中断输入至硬件时间轮10，具体的，例如定时中断输入至接收接口101。因此，接收接口101用于接收定时中断。
接下来执行步骤12，即判断在当前时间格上是否有定时任务。在实际运用中，例如由硬件时间轮10执行该步骤。
举例来说，任务管理组件102的控制器在通过接收接口101接收到定时中断时，获取当前数组的下一数组的地址，下一数组即对应当前时间格。然后判断该数组中是否存储有定时任务。该种情况适用于先有中断产生，再进行时间格的移动的情况。
再例如，任务管理组件102的控制器在通过接收接口101接收到定时中断时，获取当前数组的地址，并判断该数组中是否存储有定时任务。该种情况适用于先进行时间格的跳动，然后等待中断产生的情况。例如在每次执行完步骤12之后，就跳到下一数组，然后等待下一个定时中断的到来。
因为可能不是每个时间格都添加了定时任务，所以要进行步骤12中的判断。如果时间格对应的定时任务链表不为空，那么就表示当前时间格上有定时任务需要执行，反之，就表示当前时间格上没有定时任务要执行。
在有定时任务时，执行步骤13，即发送消息给处理模块，以使所述处理模块中断当前任务并处理所述定时任务。
在没有定时任务时，就等待下一个定时中断的到来，反复执行步骤11至步骤12。
当该方法应用于前述图1所示的电子设备中时，步骤13由硬件时间轮10来执行。步骤13中的处理模块即为处理器20。当硬件时间轮10的结构如图2所示时，任务管理组件102通过发送接口103发送消息给处理器20，以使处理器20中断当前任务并处理所述定时任务。
可选的，所述消息可以包括定时任务的名称和任务对应的任务函数。对应的，处理器20可以直接执行消息中的任务函数。
可选的，所述消息可以包括定时任务的名称和任务对应的任务函数的入口地址。对应的，处理器20可以通过消息中的任务函数的入口地址先获取任务函数，再执行该任务函数。
可选的，当定时任务有多个时，可以按照任务顺序依次执行。
接下来请参考图4所示，为本发明实施例提供的一种硬件时间轮10与外界交互以及内部元件之间的交互图。如图4所示，存储器上存储有时间格T0至Tn，n为正整数。
控制器通过接收接口101接收定时中断。然后控制器确定当前时间格为时间格T0。时间格T0例如是数组的形式存在的，那么控制器就获取该数组在存储器上的地址。然后读取该数组中的定时任务链表。然后判断该定时任务链表中是否有定时任务。在本例中，时间格T0对应的定时任务有3个，分别为任务1至任务3。因此，控制器通过发送接口103发送消息给处理器20。可选的，消息中包含各个任务对应的任务函数。可选的，可以在一个消息中承载3个任务的任务函数，也可以是每个消息中承载一个任务对应的任务函数，然后发3个消息给处理器20。
当再次接收到定时中断时，当前时间格为T1。假设时间格T1上没有定时任务，那么控制器就不会发消息给处理器20，那么处理器20就会继续处理当前任务，并不会发生中断，所以就不会浪费处理资源，进而提高系统性能。
由以上描述可以看出，本发明实施例中先由硬件时间轮判断当前时间格上是否有定时任务，只有在有定时任务时，才发消息给处理器，处理器才会中断当前任务并处理定时任务。相较于现有技术中每次定时中断产生后，不
管当前时间格上是否有定时任务，处理器都要中断当前任务的方案而言，本发明实施例中的方案既能达到高精度定时，又能提高系统性能。
可选的，为了能够对时间格对应的定时任务进行灵活的操作，以适应更多的应用场景，该方法还包括：接收所述处理模块的操作请求；根据所述操作请求，对每个时间格上的定时任务链表进行操作。
可选的，所述操作请求可以是添加定时任务、删除定时任务、修改定时任务中的任意一种或多种操作请求。
可选的，所述操作请求可以包括操作的类型，进一步可以包括操作请求对应的时间格。
可选的，当该方法应用于图1所述的电子设备时，所述处理模块为处理器20。接收操作请求和根据操作请求对每个时间格上的定时链表进行操作的主体为硬件时间轮10。
当硬件时间轮10为图2及图4所示的结构时，控制器通过接收接口10接收处理器20发送的操作请求，例如为对时间格T0进行定时任务(例如图4中的任务1)删除的操作请求。控制器获取到时间格T0在存储器上的地址，并删除定时任务链表中的任务1。
当然，在实际运用中，也可以是由处理器20直接访问任务管理组件102的存储器，直接对时间格对应的任务进行删除、增加或修改。
可选的，图3所示的方法还可以应用于一种处理器。请参考图5所示，为本发明实施例提供的一种处理器30的结构图。如图5所示，该处理器30包括：中断接口301、硬件时间轮302、至少一个处理核心304和控制模块303。
当处理器30为芯片形式时，中断接口301为中断引脚。中断接口301用于执行步骤11，即接收定时中断。
硬件时间轮302的结构与图2和图4类似，不同的是，硬件时间轮302的接收接口只要与中断接口301匹配即可。发送接口的类型只要与控制模块303匹配即可。
硬件时间轮302用于执行步骤12至步骤13，即判断在当前时间格上是否
有定时任务，在有定时任务时，发送消息给处理模块。在本例中，步骤13中的处理模块即为控制模块303。
控制模块303用于控制至少一个处理核心304中断当前任务并处理所述定时任务。
由以上描述可以看出，在本发明实施例中，处理器在接收到定时中断时，不需要像现有技术那样立即中断当前任务，而是先判断当前时间格上是否有定时任务，只有在有定时任务时，才会中断当前任务执行定时任务。而当当前时间格上没有定时任务时，就不需要中断当前任务，可以继续执行当前任务，所以节约了处理器的处理资源，提高了系统性能。
进一步，在本实施例中，硬件时间轮302和控制模块303集成在处理器30中，所以更利于系统电路的布局，便于使用。
可选的，控制模块303还用于向硬件时间轮302发送操作请求，硬件时间轮302还用于根据所述操作请求对每个时间格的定时任务链表进行操作。本例中的操作请求与前述描述的操作请求的含义相同，在此不再赘述。
可选的，本发明实施例还提供一种电子设备。该电子设备包括图5及其实施例中所述的处理器30以及存储器。存储器用于存储处理器30工作时所需的数据。
存储器的数量可以是一个或多个。存储器可以包括ROM、RAM和磁盘存储器。这些存储器通过总线与处理器30相连接。
可选的，该电子设备可以是用户侧设备，也可以是网络侧设备。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
Claims (9)
- 一种信息处理方法，其特征在于，包括：接收定时中断；判断在当前时间格上是否有定时任务；在有定时任务时，发送消息给处理模块，以使所述处理模块中断当前任务并处理所述定时任务。
- 如权利要求1所述的方法，其特征在于，所述方法还包括：接收所述处理模块的操作请求；根据所述操作请求，对每个时间格上的定时任务链表进行操作。
- 一种电子设备，其特征在于，包括：硬件时间轮，用于接收定时中断，并判断在当前时间格上是否有定时任务，在有定时任务时，发送消息给处理器；所述处理器，用于根据所述消息中断当前任务并处理所述定时任务。
- 如权利要求3所述的电子设备，其特征在于，所述处理器还用于发送操作请求给所述硬件时间轮；所述硬件时间轮还用于根据所述操作请求，对每个时间格上的定时任务链表进行操作。
- 一种硬件时间轮，其特征在于，包括：接收接口，用于接收定时中断；发送接口；任务管理组件，包括存储器和控制器，所述存储器用于存储时间格和每个时间格对应的定时任务链表；所述控制器用于判断在当前时间格上是否有定时任务；在有定时任务时，通过所述发送接口发送消息给处理器，以使所述处理器中断当前任务并处理所述定时任务。
- 如权利要求5所述的硬件时间轮，其特征在于，所述接收接口还用于接收所述处理器发送的操作请求；所述控制器还用于根据所述操作请求对所述每个时间格对应的定时任务链表进行操作。
- 一种处理器，其特征在于，包括：中断接口，用于接收定时中断；硬件时间轮，用于判断在当前时间格上是否有定时任务，在有定时任务时，发送消息给控制模块；至少一个处理核心；所述控制模块，用于控制所述至少一个处理核心中断当前任务并处理所述定时任务。
- 如权利要求7所述的处理器，其特征在于，所述控制模块还用于向所述硬件时间轮发送操作请求；所述硬件时间轮还用于根据所述操作请求对每个时间格的定时任务链表进行操作。
- 一种电子设备，其特征在于，包括：如权利要求7或8所述的处理器；存储器，用于存储所述处理器工作时所需的数据。
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