WO2017090207A1

WO2017090207A1 - Optical receiver, optical communication device and control method

Info

Publication number: WO2017090207A1
Application number: PCT/JP2015/083491
Authority: WO
Inventors: 芦田　哲郎; 大介三田; 雅樹野田
Original assignee: 三菱電機株式会社
Priority date: 2015-11-27
Filing date: 2015-11-27
Publication date: 2017-06-01
Also published as: JPWO2017090207A1; CN107027336A; JP6524255B2

Abstract

An optical receiver (1) is provided with: a light receiving element (11) that converts an optical signal which is intermittently received as an optical packet into a current signal; a separation circuit (13) that separates a control signal which is inputted from outside and in which information indicating a time at which the light receiving element receives the head of the optical packet and information indicating the transmission rate of the optical packet are superimposed into a reset signal and a rate select signal, and outputs the reset signal and the rate select signal; and a receiver (12) that converts the current signal into a voltage signal, switches a time constant in response to the reset signal, and switches a frequency response characteristic in response to the rate select signal.

Description

Optical receiver, optical communication apparatus and control method

The present invention relates to an optical receiver, an optical communication apparatus, and a control method in an optical receiver in an optical communication system.

In recent years, transmission rates have been increased in optical communication systems. On the other hand, it is desired to continue using an existing system that has not been speeded up, and it is necessary to coexist a new system that has been speeded up and an old system that is an existing system. At that time, the optical transceiver of the OLT (Optical Line Terminal), which is the base station in the optical access system, is required to be multi-rate to accommodate the old and new systems, and for any light reception level signal Is required to have both a high-speed response and a high continuous resistance with the same sign.

Patent Document 1 discloses an invention that can realize optimum frequency response characteristics for different transmission rates by switching the internal feedback resistance value of the preamplifier by a rate switching signal that is an external signal. Yes.

In the optical communication system, the OLT receives packets transmitted from each ONU (Optical Network Unit) intermittently, that is, in bursts. Therefore, in the OLT optical receiver 1, stable control is desired, and a high-speed response at the start of packet reception is desired. In Patent Document 2, when the control converges, a high continuous resistance with the same sign is realized by using a low-speed time constant, and a high-speed response is realized by switching to a high-speed time constant when a reset signal is input from the outside. is doing.

JP 2010-166216 A International Publication No. 2012/137299

When realizing both multi-rate and high-speed response using the above-described conventional technology, both a rate switching signal for switching the transmission rate and a reset signal for switching to a fast time constant are required. On the other hand, in recent years, in order to reduce the cost of the optical access system, it is required to increase the mounting density of the optical transceivers and reduce the size of the optical transceivers. When the optical transceiver is mounted as an optical module mounted on a substrate, in order to reduce the size of the optical transceiver, the board and the optical module are miniaturized, and the connector that connects the optical module and an external interface substrate Reducing the number of input / output pins in the unit is also a major issue. Therefore, the optical receiver is required to realize both multi-rate and high-speed response while avoiding a large hardware scale.

The present invention has been made in view of the above, and it is an object of the present invention to obtain an optical receiver capable of realizing a high-speed response to a burst signal and compatibility with a plurality of transmission rates while avoiding an increase in size of hardware. Objective.

In order to solve the above-described problems and achieve the object, an optical receiver according to the present invention includes a light receiving element that converts an optical signal intermittently received as an optical packet into a current signal, and a control input from the outside. A separation circuit that separates the signal into a first signal that indicates a time at which the head of the optical packet is received and a second signal that indicates a transmission rate of the optical packet, and outputs the first signal and the second signal; . The control signal is a signal in which information indicating the time at which the light receiving element receives the head of the optical packet and information indicating the transmission rate of the optical packet are superimposed. An optical receiver according to the present invention includes a receiver that converts a current signal into a voltage signal, switches a time constant according to a first signal, and switches a frequency response characteristic according to a second signal. .

The optical receiver according to the present invention has an effect that it is possible to realize a high-speed response to a burst signal and compatibility with a plurality of transmission rates while avoiding an increase in size of hardware.

1 is a diagram illustrating a configuration example of an optical receiver according to a first embodiment. FIG. 3 illustrates a configuration example of a receiver in the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a gain control circuit according to the first embodiment. The figure which shows the structural example of the optical communication system of Embodiment 1. FIG. FIG. 3 illustrates a configuration example of a processing circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a control circuit according to the first embodiment. FIG. 3 is a timing chart illustrating an example of each signal in the optical receiver according to the first embodiment. FIG. 5 is a diagram illustrating a configuration example of a separation circuit of an optical receiver according to a second embodiment. FIG. 4 is a timing chart illustrating an example of a control signal, a rate select signal, and a reset signal according to the second embodiment. Flowchart illustrating an example of a control signal generation procedure according to the second embodiment The figure which shows the circuit structural example of an edge detection circuit when an edge detection circuit is used as a rising edge detection circuit The figure which shows the circuit structural example of an edge detection circuit when an edge detection circuit is made into a falling edge detection circuit The figure which shows the circuit structural example of an edge detection circuit when an edge detection circuit is used as a both-edge detection circuit FIG. 6 is a diagram illustrating an example of an input signal to an operational amplifier and a signal output from the edge detection circuit in the edge detection circuit according to the second embodiment. FIG. 6 is a timing chart illustrating an example of each signal when a falling detection circuit is used as the edge detection circuit according to the second embodiment. FIG. 6 is a timing chart illustrating an example of each signal when both edge detection circuits are used as the edge detection circuit according to the second embodiment. Timing chart showing an example of each signal in the optical receiver of the third embodiment Flowchart showing an example of a control signal generation procedure according to the third embodiment Timing chart showing an example of each signal in the optical receiver of the fourth embodiment FIG. 6 is a diagram illustrating a configuration example of a separation circuit according to a fourth embodiment. FIG. 6 is a timing chart illustrating an example of each signal in the separation circuit of the fourth embodiment. The figure which shows the structural example of the isolation | separation circuit of Embodiment 4 which added the circuit which masks the 2nd pulse with respect to a reset signal.

Hereinafter, an optical receiver 1, an optical communication apparatus, and a control method according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of an optical receiver 1 according to the first embodiment of the present invention. As shown in FIG. 1, the optical receiver 1 according to the first embodiment includes a light receiving element 11, a receiver 12, and a separation circuit 13. The optical receiver 1 according to the first embodiment is an optical receiver 1 that receives optical packets in a burst manner. As will be described later, the optical receiver 1 according to Embodiment 1 is mounted on, for example, an OLT that is an optical communication device.

The light receiving element 11 is an element that converts a received optical signal, that is, a received light signal into a current signal and outputs it, and is, for example, an APD (Avalanche Photo Diode) or a PD (Photo Diode). The receiver 12 converts the current signal output from the light receiving element 11 into a voltage signal.

The separation circuit 13 receives a control signal, which will be described later, input from the outside, a reset signal that is a first signal used for switching the time constant in the receiver 12 and a second signal used for switching the frequency response characteristic in the receiver 12. And a reset signal and a rate select signal are input to the receiver 12. The control signal is a signal in which the time when the optical receiver 1 receives the head of the optical packet, that is, the information indicating the time when the light receiving element 11 receives the head of the optical packet and the information indicating the transmission rate of the optical packet are superimposed. is there. The reset signal is a signal indicating the time when the head of the optical packet received by the optical receiver 1 is received.

The rate select signal is a signal indicating the transmission rate of the optical signal received by the optical receiver 1, that is, the transmission rate of the signal input to the receiver 12. In the first embodiment, the transmission rate of the optical signal received by the optical receiver 1 is the bit rate # 1 that is the first transmission rate and the bit rate # that is the second transmission rate that is higher than the first transmission rate. 2 and 2 types are included. Therefore, the rate select signal is, for example, a binary signal indicating either a value indicating the bit rate # 1 or a value indicating the bit rate # 2.

The reset signal is a signal input from the separation circuit 13 and is a signal for instructing initialization, that is, resetting of the optical receiver 1. The reset signal is, for example, a value indicating reset every time reception of an optical packet is started.

The control signal only needs to be generated so that the reset signal and the rate select signal can be separated from the control signal, and the specific format of the control signal is not particularly limited. Specific examples of the control signal will be described in the second and subsequent embodiments. For example, when the optical receiver 1 is mounted on the OLT, the control signal is input to the optical receiver 1 from a control unit that controls an ONU in the OLT.

The receiver 12 includes an amplifier and a control circuit that controls the amplifier, and is configured such that control parameters in the amplifier in the receiver 12 can be changed according to the reset signal and the rate select signal. The control parameters include a frequency characteristic parameter that is a parameter corresponding to the frequency response characteristic of the receiver 12 and a time constant of a control circuit in the receiver 12. The frequency characteristic parameters are, for example, the feedback resistance value and the open loop gain described in Patent Document 1, and are changed according to the rate select signal. Further, the control circuit of the receiver 12 can change the time constant according to the reset signal, for example, by the method described in Patent Document 2.

The optimum frequency response characteristic in the operation of the receiver 12 varies depending on the transmission rate of the signal input to the receiver 12. The receiver 12 can change the frequency response parameter as described above, and the first frequency response parameter, which is a frequency response parameter for realizing an optimal frequency response characteristic for the bit rate # 1, and the bit rate It is assumed that a second frequency response parameter that is a frequency response parameter for realizing an optimal frequency response characteristic for # 2 can be set.

FIG. 2 is a diagram illustrating a configuration example of the receiver 12 according to the first embodiment. The receiver 12 shown in FIG. 2 includes an inverting amplifier 121 that is a variable gain inverting amplifier, a resistor 122 that is a first resistor, a resistor 123 that is a second resistor, and a MOS (Metal Oxide Semiconductor) transistor 124. And a gain control circuit 125 and a convergence determination circuit 126. The gain control circuit 125 performs automatic gain control on the inverting amplifier 121. The convergence determination circuit 126 determines the convergence of control by the gain control circuit 125. The MOS transistor 124 of the receiver 12 shown in FIG. 2 is turned on or off according to a rate select signal that is a signal indicating the transmission rate of the signal input to the receiver 12.

The resistor 122, the resistor 123, and the MOS transistor 124 constitute a feedback resistor unit. The resistance value of the feedback resistor section, that is, the feedback resistance value changes according to the on / off state of the MOS transistor 124 serving as a switch. The frequency response characteristic depends on the feedback resistance value. Further, as described above, the optimum frequency response characteristic in the operation of the receiver 12 varies depending on the transmission rate of the signal input to the receiver 12. Therefore, the optimum feedback resistance value varies depending on the transmission rate of the signal input to the receiver 12. In the receiver 12 shown in FIG. 2, the resistance values of the resistor 122 and the resistor 123 and the resistance value of the MOS transistor 124 are optimal for the bit rate # 2 when the MOS transistor 124 is turned on. And the resistance value of the feedback resistor when the MOS transistor 124 is off is set to an optimum value for the bit rate # 1. The MOS transistor 124 is turned on when the value of the rate select signal is a value indicating the bit rate # 2, and the MOS transistor 124 is turned off when the value of the rate select signal is a value indicating the bit rate # 1. Thus, an optimum feedback resistance value can be used according to the transmission rate. Thereby, an optimal frequency response characteristic can be realized according to the transmission rate.

FIG. 3 is a diagram illustrating a configuration example of the gain control circuit 125 according to the first embodiment. The gain control circuit 125 shown in FIG. 3 includes a high-speed time constant circuit 127, a low-speed time constant circuit 128, a switch 129, an arithmetic circuit 130, and a logic circuit 131 that is a D-flip flop. The high-speed time constant circuit 127 is a circuit that averages the signal output from the inverting amplifier 121 with the first time constant. The low-speed time constant circuit 128 is a circuit that averages the signal output from the inverting amplifier 121 with a second time constant longer than the first time constant. The switch 129 outputs one of a signal output from the high speed time constant circuit 127 and a signal output from the low speed time constant circuit 128 to the arithmetic circuit 130 based on the reset signal and the convergence determination signal. Based on the signal output from the switch 129, the arithmetic circuit 130 generates a gain control signal according to a predetermined control logic for automatically controlling the gain of the inverting amplifier 121, and the generated gain control signal is inverted. To 121.

The convergence determination circuit 126 detects the convergence of the automatic gain control based on the signal output from the gain control circuit 125, generates a convergence determination signal that is a signal indicating whether the convergence is detected, and generates the generated convergence. A determination signal is input to the logic circuit 131. As the convergence determination circuit 126, for example, a circuit obtained by removing a logic circuit from the convergence determination circuit described in Patent Document 2 can be used.

The logic circuit 131 generates a time constant switching signal for switching the time constant circuit selected by the switch 129 based on the reset signal and the convergence determination signal, and outputs the generated time constant switching signal to the switch 129. The logic circuit 131 sets the time constant switching signal to a value instructing to select the high-speed time constant circuit 127 when the reset signal has a value instructing reset. Further, the logic circuit 131 sets the time constant switching signal to a value instructing to select the low-speed time constant circuit 128 when the convergence determination signal has a value instructing convergence detection. With the above operation, when the optical receiver 1 starts receiving an optical packet, the first time constant that is a high-speed time constant is set, and when the control is converged, the second time constant that is a low-speed time constant is set. The Thereby, the receiver 12 can implement | achieve a high same sign continuous proof stress and a high-speed response.

2 and FIG. 3 are examples, and the configuration of the receiver 12 is not limited to the example of FIG. The receiver 12 may be any receiver 12 that performs switching of frequency response characteristics based on the rate select signal and operation based on the reset signal. For example, the receiver 12 may have a function of performing automatic offset control of the preamplifier, and the time constant in the automatic offset control may be switched based on the reset signal. Further, in the examples of FIGS. 2 and 3, the example in which the reset signal is used to set a time constant suitable for the start of optical packet reception, that is, a high-speed time constant when the time constant can be switched has been described. . The operation of setting a time constant suitable for starting reception of an optical packet can be referred to as an initialization operation in the receiver 12. The reset signal is not limited to switching of the time constant, and may be an operation for initializing the operation in the receiver 12. Further, in FIG. 2, the example in which the feedback resistance value and the open loop gain are changed by the rate select signal has been described, but the control parameters to be changed based on the rate select signal are not limited to these.

The separation circuit 13 separates a control signal (described later) input from the outside into a reset signal and a rate select signal, and inputs the reset signal and the rate select signal to the receiver 12. The reset signal is a signal indicating the head of the optical packet received by the optical receiver 1. The rate select signal is a signal that instructs the receiver 12 whether to set the first frequency response parameter or the second frequency response parameter as the frequency response parameter. The control signal is generated so that the reset signal and the rate select signal can be separated from the control signal.

The optical receiver 1 according to Embodiment 1 is mounted on, for example, an OLT in an optical communication system. FIG. 4 is a diagram illustrating a configuration example of the optical communication system according to the first embodiment. As shown in FIG. 4, the optical communication system 60 according to the first embodiment includes an OLT 50 and

ONUs

51, 52, and 53. The OLT 50 is connected to the

ONUs

51, 52, and 53 via an optical star coupler and an optical fiber that is a transmission path. In FIG. 4, the number of ONUs is three, but the number of ONUs is not limited to this.

The OLT 50 assigns upstream communication bandwidth to the

ONUs

51, 52, and 53, and grasps the reception time of the optical packet transmitted from each ONU. The OLT 50 and the

ONUs

51, 52, and 53 operate according to a protocol (hereinafter referred to as a PON protocol) in a PON (Passive Optical Network) system. As the PON protocol, for example, a protocol conforming to the GE-PON standard of IEEE (Institute of Electrical and Electronics Engineers) or the G-PON standard of ITU-T (International Telecommunication Union Telecommunication Standardization Sector) can be used. .

The OLT 50 includes the optical receiver 1 according to the first embodiment, the optical transmitter 2, and the control unit 3. The optical receiver 1 converts an optical signal received from each ONU through an optical fiber, that is, a received light signal into a voltage signal and outputs the voltage signal to the control unit 3. The optical transmitter 2 converts a transmission signal transmitted to each ONU generated by the control unit 3 into an optical signal, and transmits the optical signal to each ONU via an optical fiber.

The control unit 3 generates a transmission signal to be transmitted to each ONU according to the PON protocol, outputs the transmission signal to the optical transmitter 2, and complies with the PON protocol for the signal received from each ONU via the optical receiver 1. Implement the process. In addition, the control unit 3 obtains the upstream transmission rate corresponding to each ONU, that is, the transmission rate of the optical packet transmitted by each ONU, through discovery processing in the GE-PON, and holds the transmission rate for each ONU. Yes. Further, the control unit 3 assigns an upstream band to each ONU. In the PON system, the uplink bandwidth is assigned by time division multiplexing so that signals transmitted from each ONU do not overlap. The control unit 3 allocates an upstream band to each ONU, that is, a time zone permitting transmission from each ONU to the OLT 50 by time division multiplexing, and transmits the allocation result to each ONU via the optical transmitter 2. Each ONU transmits an optical signal to the OLT 50 according to the allocation result received from the OLT 50. As described above, since transmission from each ONU to the OLT 50 is performed by time division multiplexing in the PON system, the OLT 50 receives optical signals transmitted from each ONU in a burst manner, that is, intermittently. Hereinafter, a group of signals transmitted in bursts is called an optical packet. An optical packet is composed of a predetermined bit string called a preample and data.

As described above, since the control unit 3 allocates an upstream band to each ONU, it knows the time for receiving an optical signal from each ONU. For this reason, the control part 3 can obtain | require the time when the optical receiver 1 starts reception of the optical packet transmitted from ONU. Therefore, the control unit 3 can generate a reset signal that is input to the optical receiver 1 described above. In addition, since the control unit 3 knows the upstream transmission rate of each ONU, the optical packet to be received next can generate a rate select signal based on the optical signal of any transmission rate. As described above, the rate select signal is used for switching frequency response characteristics in the receiver 12 of the optical receiver 1. Therefore, the rate select signal has a value indicating the transmission rate corresponding to the optical packet for each optical packet. In the preamble portion of the optical packet, synchronization processing or the like is performed, so the frequency response characteristics may not be suitable for the transmission rate, and before the optical receiver 1 receives the data portion of the optical packet, The value of the rate select signal only needs to be a value indicating the corresponding transmission rate.

The control unit 3 can generate a rate select signal and a reset signal used in the optical receiver 1, but when the rate select signal and the reset signal are input to the optical receiver 1, the optical receiver 1 An optical module to be mounted requires two signal input pins. In recent years, downsizing of hardware is desired, and fewer input pins are desirable. Therefore, in the present embodiment, a control signal is input from the control unit 3 to the optical receiver 1 via one input pin, and the separation circuit 13 of the optical receiver 1 receives a rate select signal from the control signal. And the reset signal are separated. The control signal may be a signal in which the reset signal and the rate select signal are multiplexed by shifting the timing at which the reset is instructed by the reset signal and the timing at which the value of the rate select signal changes. It may be multiplexed by a method. Specific control signals will be described in the second and subsequent embodiments.

Next, the hardware configuration of the control unit 3 will be described. The control unit 3 is realized by a processing circuit. Even if this processing circuit is dedicated hardware, a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP that executes a program stored in the memory (Also referred to as “Digital Signal Processor”). Here, the memory is, for example, non-volatile or RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), etc. Volatile semiconductor memory, magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disk), etc. are applicable.

When the control unit 3 is realized by dedicated hardware, it is realized by the processing circuit 100 shown in FIG. The processing circuit 100 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof.

When the control unit 3 is realized by a control circuit including a CPU, the control circuit is, for example, a control circuit 200 having a configuration shown in FIG. As shown in FIG. 6, the control circuit 200 includes a processor 201 that is a CPU and a memory 202. When the control unit 3 is realized by the control circuit 200, the processor 201 reads out and executes a program stored in the memory 202 and corresponding to the process of the control unit 3. The memory 202 is also used as a temporary memory in each process executed by the processor 201.

Next, the operation of the optical receiver 1 according to the present embodiment will be described. FIG. 7 is a timing chart illustrating an example of each signal in the optical receiver 1 according to the first embodiment. The horizontal axis in FIG. 7 indicates time. The first stage of FIG. 7 shows an example of an optical signal received by the optical receiver 1, the second stage of FIG. 7 shows an example of a rate select signal, and the third stage of FIG. An example is shown. As shown in the first stage of FIG. 7, the optical receiver 1 receives optical packets in bursts. Each optical packet is composed of a preamble and data as described above. That is, the optical signal of the optical receiver 1 is an optical signal that is intermittently received as an optical packet. In the example of FIG. 7, the optical packet shown on the left side is transmitted at the transmission rate of the bit rate # 1, and the optical packet shown on the left side is transmitted at the transmission rate of the bit rate # 2.

The optical receiver 1 receives a control signal synchronized with the optical packet from the outside. The control signal is an arbitrary signal that can be separated into a rate select signal and a reset signal. The separation circuit 13 separates the control signal into a rate select signal and a reset signal. The rate select signal and the reset signal are input to the receiver 12. The operation of the receiver 12 when the rate select signal and the reset signal are input is as described above. The receiver 12 operates with a frequency response characteristic corresponding to the rate select signal, and the operation of the receiver 12 by the reset signal. To reset. In other words, the optical receiver 1 according to the present embodiment separates the first step of converting an optical signal into a current signal and the control signal input from the outside into a reset signal and a rate select signal. And a second step of outputting a rate select signal and a third step of converting a current signal into a voltage signal, switching a time constant according to a reset signal, and switching a frequency response characteristic according to a rate select signal To do.

In the example of FIG. 7, the rate select signal is a binary signal of high and low, where high indicates the bit rate # 1 and low indicates the bit rate # 2. Therefore, when the rate select signal is high, the receiver 12 operates with a frequency response characteristic suitable for the bit rate # 1, and when the rate select signal is low, the receiver 12 has a frequency suitable for the bit rate # 2. Operates with response characteristics. The correspondence between the value of the rate select signal and the bit rate is not limited to this example, and low may indicate the bit rate # 1 and high may indicate the bit rate # 2.

Further, in the example of FIG. 7, the reset signal is a binary signal of high and low, and high indicates that the reset is significant, that is, reset is instructed, and low indicates that the reset is not significant, that is, reset is instructed. Indicates not. As shown in the example of FIG. 7, the reset signal is generally a pulse signal indicating the reset timing. When the reset signal becomes a value indicating reset, that is, a value indicating that the reset is significant, the receiver 12 switches the time constant to the first time constant, that is, the fast response time constant as described above. Further, other initialization operations may be performed in response to the reset signal. The correspondence between the value of the reset signal and whether or not the reset is significant is not limited to this example. Low indicates that the reset is significant, and high indicates that the reset is not significant. Good.

As described above, in the optical receiver 1 according to the present embodiment, the control signal input from one signal input pin is separated into the reset signal and the rate select signal by the separation circuit 13. Thereby, using one signal input pin, the frequency response characteristic can be switched according to the transmission rate, and a high-speed response to an optical packet received in bursts can be realized. As a result, the frequency response characteristics can be switched according to the transmission rate, and the hardware can be reduced in size while realizing a high-speed response to optical packets received in bursts.

Embodiment 2. FIG.
FIG. 8 is a diagram illustrating a configuration example of the separation circuit of the optical receiver 1 according to the second embodiment of the present invention. In the second embodiment, a configuration example of the separation circuit 13 and an example of a control signal in the optical receiver 1 described in the first embodiment will be described.

The separation circuit 13 according to the second embodiment includes an edge detection circuit 14 as shown in FIG. The edge detection circuit 14 uses a rising edge detection circuit that detects a rising edge, a falling edge detection circuit that detects a falling edge, or a both-edge detection circuit that detects both rising and falling edges.

FIG. 9 is a timing chart illustrating an example of a control signal, a rate select signal, and a reset signal according to the second embodiment. FIG. 9 shows an example in which a rising edge detection circuit is used as the edge detection circuit 14. In the example shown in FIG. 9, the control signal changes from low to high at the timing when the reset signal changes from low to high, that is, when the reset signal changes from a value indicating that the reset is not significant to a value indicating that the reset is significant. Change. Thereafter, the control signal becomes a value corresponding to the transmission rate of the optical packet received by the optical receiver 1 after a predetermined time has elapsed. As described above, the control signal according to the present embodiment is a value corresponding to the transmission rate of the optical packet received by the optical receiver 1 during the rate indication period including the time point after the beginning of the optical packet and before receiving the data portion. Indicates. In the example of FIG. 9, the rate instruction period is a period from when the reset signal changes from low to high and after a certain time elapses until reception of the optical packet ends. In the example of FIG. 9, the bit rate # 1 is shown when the control signal is high, and the bit rate # 2 is shown when the control signal is low.

FIG. 10 is a flowchart illustrating an example of a control signal generation procedure according to the second embodiment. The control signal shown in FIG. 9 is generated by the control unit 3 of the OLT 50 on which the optical receiver 1 is mounted as described in the first embodiment. Here, it is assumed that the control signal is generated by the control unit 3.

The control unit 3 retains information on the uplink bandwidth allocated to each ONU, and determines whether or not the reception start timing of the optical packet is reached based on the information on the uplink bandwidth for each ONU that is retained ( Step S1). When the control unit 3 determines that the optical packet reception start timing is reached (Yes in step S1), the control unit 3 sets the control signal value to high (step S2). If the control unit 3 determines that it is not the optical packet reception start timing (No in step S1), it repeats step S1.

After step S2, the control unit 3 determines whether or not the transmission rate of the optical packet, that is, the received optical packet is the bit rate # 1 (step S3). When the transmission rate of the optical packet is the bit rate # 1 (step S3, Yes), the control unit 3 determines whether it is the reception end timing of the optical packet (step S4). When it is the reception end timing of the optical packet (step S4, Yes), the control unit 3 sets the value of the control signal output to the optical receiver 1 to low (step S5).

In step S3, when the transmission rate of the optical packet is not the bit rate # 1 (No in step S3), the control unit 3 determines whether or not a certain time has passed since the value of the control signal was set high (step S6). When the fixed time has passed (Yes at Step S6), the process proceeds to Step S5. When the fixed time has not passed (No at Step S6), Step S6 is repeated. If it is not the optical packet reception end timing in step S4 (No in step S4), step S4 is repeated. Through the above processing, the control unit 3 can generate the control signal shown in FIG. The processing procedure shown in FIG. 10 is an example, and the specific processing procedure for generating the control signal is not limited to the example of FIG.

Returning to the description of FIG. 9, when the edge detection circuit 14 detects the rising edge of the control signal, as shown in the second stage of FIG. 9, the edge detection circuit 14 generates a pulsed reset signal, and the generated reset signal is received by the receiver 12. Output to. Further, the separation circuit 13 of the optical receiver 1 outputs the input control signal as it is to the receiver 12 as a rate select signal. The receiver 12 only needs to have a frequency response characteristic corresponding to the transmission rate of the optical packet before receiving the data portion of the optical packet. For this reason, the fixed time in the process of FIG. 9 described above may be within the time zone corresponding to the preamble.

FIG. 11 is a diagram showing a circuit configuration example of the edge detection circuit 14 when the edge detection circuit 14 is a rising edge detection circuit. The edge detection circuit 14 shown in FIG. 11 includes a resistor 15, a capacitor 20, and an operational amplifier (operational amplifier) 24. The control signal is branched into two, one of the branched signals is input to the positive phase of the operational amplifier 24, and the other is input to the negative phase of the operational amplifier 24 through the low-pass filter 151 including the resistor 15 and the capacitor 20. Is done. Here, the operational amplifier 24 is used as a circuit that outputs a high value signal when the positive phase input voltage becomes higher than the negative phase input voltage. A signal input to the operational amplifier 24 through the low-pass filter 151 is a signal with a dull edge. Therefore, in the vicinity of the rising edge of the control signal, the signal input in the positive phase is larger than the signal input in the negative phase. The difference between the signal input in the positive phase and the signal input in the reverse phase is amplified by the operational amplifier 24, and becomes a pulse in the vicinity of the rising edge.

FIG. 12 is a diagram showing a circuit configuration example of the edge detection circuit 14 when the edge detection circuit 14 is a falling edge detection circuit. In this case, for example, a control signal obtained by inverting the control signal shown in FIG. 9 can be used. The edge detection circuit 14 shown in FIG. 12 includes a resistor 16, a capacitor 21, and an operational amplifier 25. In the edge detection circuit 14 shown in FIG. 12, the control signal is input to the negative phase of the operational amplifier 25, and the control signal via the low-pass filter 152 formed by the resistor 16 and the capacitor 21 is set to the positive phase of the operational amplifier 25. Entered. As a result, the signal output from the operational amplifier 25 is pulsed in the vicinity of the falling edge of the control signal.

FIG. 13 is a diagram showing a circuit configuration example of the edge detection circuit 14 when the edge detection circuit 14 is a both-edge detection circuit. The edge detection circuit 14 shown in FIG. 13 includes a falling detection circuit including a resistor 17, a capacitor 22, and an operational amplifier 26 that is a first operational amplifier, and a resistor 18, a capacitor 23, and an operational amplifier that is a second operational amplifier. 27, a rising edge detection circuit, and an OR circuit 28. The falling edge detection circuit is the same as the edge detection circuit 14 in FIG. 11, and the rising edge detection circuit is the same as the edge detection circuit 14 in FIG. The resistor 17 and the capacitor 22 constitute a first low-pass filter 153, and the resistor 18 and the capacitor 23 constitute a second low-pass filter 154. The OR circuit (logical sum circuit) 28 outputs an OR (logical sum) of the signal output from the falling detection circuit and the signal output from the rising detection circuit.

FIG. 14 is a diagram illustrating an example of an input signal to the operational amplifier in the edge detection circuit 14 according to the second embodiment and a signal output from the edge detection circuit 14. The first stage of FIG. 14 shows an input signal to the operational amplifier, and the solid line indicates the positive phase of the operational amplifier 24 shown in FIG. 11 and the operational amplifier 27 shown in FIG. 13, and the operational amplifier 25 shown in FIG. The input signal to the reverse phase of the operational amplifier 26 shown in FIG. 13 is shown. That is, the first solid line in FIG. 14 indicates a control signal input to the edge detection circuit 14. Also, the dotted line in the first stage of FIG. 14 indicates the reverse phase of the operational amplifier 24 shown in FIG. 11 and the operational amplifier 27 shown in FIG. 13, and the positive phase of the operational amplifier 25 shown in FIG. 12 and the operational amplifier 26 shown in FIG. The input signal to is shown.

The second stage of FIG. 14 shows the signal output from the edge detection circuit 14 shown in FIG. 11, and the third stage of FIG. 14 shows the signal output from the edge detection circuit 14 shown in FIG. 14 shows a signal output from the rising edge detection circuit 14 shown in FIG.

In FIG. 9, each signal in the case where the rising edge detection circuit is used as the edge detection circuit 14 is shown, but when the rising edge detection circuit or both edge detection circuits are used as the edge detection circuit 14, the timing chart is the example of FIG. 9. Is partly different.

When a falling detection circuit is used as the edge detection circuit 14, the logic of the control signal may be inverted and the correspondence between the value of the rate select signal and the bit rate may be inverted. Alternatively, a control signal as shown in FIG. 15 may be generated. FIG. 15 is a timing chart showing an example of each signal when a falling detection circuit is used as the edge detection circuit 14. When a falling detection circuit is used as the edge detection circuit 14, since the value of the reset signal becomes high when the control signal falls, the falling edge of the control signal is generated at the timing for instructing reset.

In the example of FIG. 15, the control signal is generated so that the value of the control signal changes from high to low at the reception start timing of the optical packet. When an optical packet with a bit rate # 1 of 1 is received, the control signal changes from low to high after a certain time from the optical packet reception start timing and goes high until the reception timing of the next optical packet. And is generated to change to low at the reception start timing of the next optical packet. Also, when an optical packet with a bit rate # 1 of 1 is received, the control signal remains low after becoming low at the reception start timing of the optical packet, and goes low for a certain time before the reception disclosure timing of the next packet. Is generated to change from high to low.

FIG. 16 is a timing chart showing an example of each signal when both edge detection circuits are used as the edge detection circuit 14. When both edge detection circuits are used as the edge detection circuit 14, the control signal is generated such that the falling edge and the falling edge become the timing for instructing the reset. Therefore, for example, when the control signal continuously receives optical packets having the same bit rate, the control signal is generated in the same manner as in the example of FIG. 9 and an optical packet having a bit rate different from that of the previous packet is received. In this case, as shown in FIG. 16, a value corresponding to the transmission rate of the previous optical packet may be maintained until the start timing of the next optical packet.

As described above, in the second embodiment, some configuration examples of the separation circuit 13 and examples of the control signal have been described. However, in the control signal according to the present embodiment, at least one of the rising edge and the falling edge is light. A rate indication period, which is a signal corresponding to the time at which the light receiving element 11, that is, the optical receiver 1 receives the beginning of the packet and includes the time after the time at which the beginning of the optical packet is received and before the start of data reception Then, what is necessary is just to be comprised so that it may have a value which shows the transmission rate of an optical packet. The separation circuit 13 includes an edge detection circuit 14 that detects an edge corresponding to the time at which the head of the optical packet of the control signal is received. The signal output from the edge detection circuit 14 is used as a reset signal, and the rate indication period The rate select signal may be generated based on the value of the control signal at.

As described above, in this embodiment, the example in which the edge detection circuit is used as the separation circuit 13 that can realize the effect of the first embodiment has been described. As described in the first embodiment, the separation circuit 13 is used to separate the control signal, the rate select signal, and the reset signal. Therefore, the frequency response characteristics can be switched according to the transmission rate, and the hardware can be reduced in size while realizing a high-speed response to optical packets received in bursts.

Embodiment 3 FIG.
FIG. 17 is a timing chart illustrating an example of each signal in the optical receiver 1 according to the third embodiment of the present invention. The configuration of the optical receiver 1 of the present embodiment is the same as that of the first embodiment, and the configuration of the separation circuit 13 can use the configuration shown in FIG. 8 of the second embodiment. The configuration shown in FIG. 13 can be used. Hereinafter, parts different from the first embodiment and the second embodiment will be described.

As described in the first embodiment, switching of the frequency response characteristics based on the rate select signal may be performed before receiving the data portion of the optical packet. However, if this switching is performed during reception of the optical packet, there is a problem. May occur. For this reason, it is more desirable to switch the frequency response characteristics before receiving the preamble portion. In the third embodiment, an operation is described in which frequency response characteristics are not switched during reception of an optical packet when a guard time is inserted between the optical packets.

As shown in FIG. 17, in this embodiment, it is assumed that a no-signal section called guard time is inserted between packets. The control signal is fixed to a value determined by the transmission rate during reception of the optical packet. During the guard time period, a signal obtained by inverting the signal level determined by the transmission rate of the optical packet immediately after the guard time is input. Here, it is assumed that the control signal is a binary signal, and the value obtained by inverting the value indicating the transmission rate is different from the value indicating the transmission rate and the value indicating the transmission rate which is not the value indicating the transmission rate. It shows that. As a result, the leading or trailing edge of the control signal occurs at the beginning of the optical packet, that is, at the start of reception. Therefore, the reset signal can be generated by the double edge detection circuit described in the second embodiment. Further, the rate select signal is not switched during reception of the optical packet.

FIG. 18 is a flowchart illustrating an example of a control signal generation procedure according to the third embodiment. The control signal is generated by the control unit 3 of the OLT 50 on which the optical receiver 1 is mounted as described in the first embodiment. As shown in FIG. 18, the control unit 3 determines whether or not it is the start time of the guard time (step S21). If it is not the start time of the guard time (No at Step S21), Step S21 is repeated. When it is the start timing of the guard time (step S21, Yes), the control unit 3 inverts the value of the control signal corresponding to the transmission rate of the next optical packet, that is, the value indicating the transmission rate. A value is set (step S22). And the control part 3 judges whether the guard time was complete | finished (step S23). If the guard time has not ended (No at Step S23), Step S23 is repeated.

When the guard time is over (step S23, Yes), the control unit 3 sets the value of the control signal as the value of the rate select signal corresponding to the transmission rate of the optical packet (step S24), and returns to step S21.

As described above, in this embodiment, in the guard time, the value of the control signal is set to a value obtained by inverting the value of the rate select signal corresponding to the transmission rate of the next optical packet. Let the value of the signal be the value of the rate select signal corresponding to the transmission rate of the optical packet. In the separation circuit 13 of the optical receiver 1, the reset signal is generated by using both edge detection circuits. Therefore, the effects described in the first embodiment can be obtained, and the rate select signal can be prevented from being switched during the reception of the optical packet, and problems caused by the rate select signal switching can be prevented.

Embodiment 4 FIG.
FIG. 19 is a timing chart illustrating an example of each signal in the optical receiver 1 according to the fourth embodiment of the present invention. In the fourth embodiment, an example different from the second and third embodiments will be described as a specific example of the control signal and the separation circuit 13 described in the first embodiment. The configuration of the optical receiver 1 is the same as that of the first embodiment. In this embodiment, the control signal is generated as a pulse signal.

As shown in FIG. 19, the control signal changes from low to high in the form of a pulse at the beginning, that is, at the start of reception for each optical packet. This pulse at the start of reception is called the first pulse or the first pulse. Thereafter, when the transmission rate of the optical packet is the bit rate # 1, the second pulse is input as the control signal. On the other hand, when the transmission rate of the optical packet is the bit rate # 2, the second pulse is not input and the control signal remains low. Thus, in the control signal of the fourth embodiment, the bit rate is indicated by the number of times the pulse is input. That is, the control signal of the fourth embodiment is a pulse signal, and has a number of pulses corresponding to the transmission rate of the optical packet before receiving the data portion of the optical packet for each optical packet. The leading pulse, which is one of the pulses, indicates the time at which the light receiving element receives the head of the optical packet.

In this embodiment, since a pulse is input at the head of the optical packet, the optical receiver 1 can use the control signal as a reset signal as it is. The optical receiver 1 can generate a rate select signal according to the number of pulses for each optical packet.

The control signal of the present embodiment is generated by the control unit 3 of the OLT 50, for example, as described in the first embodiment. When the first pulse is included in the head of each optical packet and the transmission rate of the optical packet is the bit rate # 1, the control unit 3 sends the second pulse after the first pulse. To be included.

FIG. 20 is a diagram illustrating a configuration example of the separation circuit 13 according to the present embodiment. As shown in FIG. 20, the separation circuit 13 of this embodiment includes a D-flip flop circuit 30 that is a first delay flip-flop circuit and a D-flip flop circuit that is a second delay flip-flop circuit. 31, a hysteresis circuit 32, a resistor 33, a capacitor 34, and an OR circuit 35. The resistor 33 and the capacitor 34 form a low pass filter 155.

As shown in FIG. 20, a control signal is input to one input section of the OR circuit 35, and a signal output from the OR circuit 35 is input to the clock input section of the D-flip flop circuit 30 to 30 output signals having opposite phases are input to the D input portion of the D flip-flop circuit 30. In addition, the positive phase output signal of the D-flip flop circuit 30 is input to the low-pass filter 155 including the resistor 33 and the capacitor 34, and the signal output from the low-pass filter 155 is input to the hysteresis circuit 32. A signal output from the hysteresis circuit 32 is input to the D input portion of the D-flip flop circuit 31, and a control signal is input to the clock input portion of the D-flip flop circuit 31. A signal output from the low-pass filter 155 is input to the other input portion of the OR circuit 35.

FIG. 21 is a timing chart illustrating an example of each signal in the separation circuit 13 according to the fourth embodiment. 21 shows the control signal, the second solid line in FIG. 21 shows the reset signal generated by the separation circuit 13 of the fourth embodiment, and the second dotted line in FIG. 4 shows a rate select signal generated by the separation circuit 13 of the fourth embodiment. The solid line at the third stage in FIG. 21 indicates the signal on the signal line A shown in FIG. 20, that is, the signal A, and the dotted line at the third stage in FIG. 21 indicates the signal at the signal line B shown in FIG. Show. The solid line at the fourth stage in FIG. 21 indicates the signal on the signal line C shown in FIG. 20, that is, the signal C, and the dotted line at the fourth stage in FIG. 21 indicates the signal at the signal line D shown in FIG. Show. The solid line at the fifth stage in FIG. 21 indicates the signal on the signal line E shown in FIG.

In the initial state, that is, before the control signal is input, the signal A and the signals C, D, E, and F are low, and the signal B is high. At this time, there is no problem whether the rate select signal is high or low. The control signal is input to the OR circuit 35 and the clock input unit of the D-flip flop circuit 31, and is output as it is as a reset signal. The signal E is low in the initial state, and when the first pulse is input as the control signal, the positive phase output of the D-flip flop circuit 31 becomes low in synchronization with the reset signal. The positive phase output signal of the D-flip flop circuit 31 is a rate select signal.

The control signal input to the OR circuit 35 is input to the clock input unit of the D-flip flop circuit 30 via the OR circuit 35. The D-flip flop circuit 30 forms a frequency divider, and the level of the output signal is switched in synchronization with the signal input to the clock input unit. Therefore, when the first pulse is input as the control signal, the signal B which is the output signal of the opposite phase of the D-flip flop circuit 30 is switched from high to low, and the positive phase of the D-flip flop circuit 30 is changed. The output signal, signal C, goes from low to high.

The signal C is input to the low-pass filter and hysteresis circuit 32 formed by the resistor 33 and the capacitor 34, and is output from the hysteresis circuit 32 as a signal D having a delay corresponding to the filter time constant. That is, the signal E, which is a signal output from the hysteresis circuit 32, rises with a delay from the rise of the first pulse of the control signal, as shown in FIG. The signal output from the hysteresis circuit 32 is input to the OR circuit 35 and then input to the clock input section of the D-flip flop circuit 30. As a result, the signal C that is the positive phase output signal of the D-flip flop circuit 30 becomes low, and the signal B that is the negative phase output signal of the D-flip flop circuit 30 becomes high. In synchronization with these operations, the signal A transitions from high to low, and the signal D transitions smoothly from high to low according to the time constant of the low-pass filter. Therefore, the signal E changes to low after maintaining the time high depending on the change of the signal D. While the signal E is high, the input to the D-flip flop circuit 30 is not changed by the OR circuit 35 even if the second pulse is input as the control signal. On the other hand, since the second pulse of the control signal is input to the D-flip flop circuit 31 as it is, a rate select signal that is a signal output from the D-flip flop circuit 31 when the second pulse is input. Changes to high.

With the above operation, when the pulse is input twice in succession to the separation circuit 13 of the fourth embodiment, the rate select signal becomes high, and when the pulse is input only once, the rate select signal is input. The signal goes low. Thereby, the separation circuit 13 according to the fourth embodiment can separate the reset signal and the rate select signal from the control signal.

Further, a circuit for masking the second pulse for the reset signal may be added to the configuration shown in FIG. FIG. 22 is a diagram illustrating a configuration example of the separation circuit 13 according to the fourth embodiment to which a circuit for masking the second pulse with respect to the reset signal is added. The separation circuit 13 shown in FIG. 22 has a mask circuit 42 configured by a buffer circuit 40 and an AND circuit (logical product circuit) 41 added to the separation circuit 13 shown in FIG. As a result, the second pulse can be masked with respect to the signal output as the reset signal, and one pulse per optical packet is output as the reset signal. As a result, it is possible to prevent problems caused by the reset signal being input to the receiver 12 twice in succession.

As described above, in this embodiment, the example in which the signal indicating the transmission rate by the number of pulses is used as the control signal capable of realizing the effect of the first embodiment. Therefore, the frequency response characteristics can be switched according to the transmission rate, and the hardware can be reduced in size while realizing a high-speed response to optical packets received in bursts.

The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

1 optical receiver, 2 optical transmitter, 3 control unit, 11 light receiving element, 12 receiver, 13 separation circuit, 14 edge detection circuit, 50 OLT, 51, 52, 53 ONU, 15, 16, 17, 18, 33 Resistor, 20, 21, 22, 23, 34 capacitor, 24, 25, 26, 27 operational amplifier, 28 OR circuit, 30, 31 D-flip flop circuit, 32 hysteresis circuit, 40 buffer circuit, 41 AND circuit, 42 mask circuit 151-155 Low-pass filter.

Claims

A light receiving element that converts an optical signal intermittently received as an optical packet into a current signal;
A control signal that is input from the outside and superimposes information indicating the time at which the light receiving element receives the head of the optical packet and information indicating the transmission rate of the optical packet, and the time at which the head of the optical packet is received. A separation circuit for separating the first signal and the second signal indicating the transmission rate of the optical packet, and outputting the first signal and the second signal;
A receiver that converts the current signal into a voltage signal, switches a time constant according to the first signal, and switches a frequency response characteristic according to the second signal;
An optical receiver comprising:
The optical packet is composed of a preamble and data,
The control signal is a signal corresponding to a time at which at least one of a rising edge and a falling edge receives the head of the optical packet by the light receiving element, and after the time of receiving the head of the optical packet and In the rate indication period, which is a period including the time before the start of data reception, has a value indicating the transmission rate of the optical packet,
The separation circuit is
An edge detection circuit for detecting the edge corresponding to the time of receiving the head of the optical packet of the control signal;
With
2. The light according to claim 1, wherein a signal output from the edge detection circuit is the first signal, and the second signal is generated based on a value of the control signal in the rate instruction period. Receiver.
The edge detection circuit includes:
A low-pass filter to which the control signal is input;
An operational amplifier in which the control signal is input to a positive phase input unit and the control signal is input to the negative phase input unit after passing through the low pass filter;
The optical receiver according to claim 2, further comprising:
The edge detection circuit includes:
A low-pass filter to which the control signal is input;
An operational amplifier in which the control signal is input to a negative phase input unit, and the control signal after passing through the low pass filter is input to a positive phase input unit;
The optical receiver according to claim 2, further comprising:
The edge detection circuit includes:
A first low-pass filter to which the control signal is input;
A first operational amplifier in which the control signal is input to a negative phase input unit, and the control signal after passing through the first low-pass filter is input to a positive phase input unit;
A second low-pass filter to which the control signal is input;
A second operational amplifier in which the control signal is input to a positive phase input unit, and the control signal after passing through the second low-pass filter is input to a negative phase input unit;
An OR circuit that calculates a logical sum of a signal output from the first operational amplifier and a signal output from the second operational amplifier;
The optical receiver according to claim 2, further comprising:
The optical packet is composed of a preamble and data,
Between the time when the light receiving element finishes receiving the optical packet and until the start of receiving the optical packet next to the optical packet, a guard time that is a period in which the optical packet is not received is provided,
The optical packet is an optical packet transmitted at a first transmission rate or a second transmission rate that is higher than the first transmission rate;
The control signal is a binary signal indicating the first transmission rate or the second transmission rate, and the guard time is a value indicating the transmission rate of the optical packet received immediately after the guard time. The optical receiver according to claim 5, wherein the optical receiver has different values and has a value indicating a transmission rate of the optical packet during reception of the optical packet.
The optical packet is composed of a preamble and data,
The control signal is a pulse signal, and has a number of pulses corresponding to a transmission rate of the optical packet before receiving the data of the optical packet for each optical packet, and The leading pulse, which is one of the pulses, indicates the time at which the light receiving element receives the head of the optical packet,
The separation circuit is
2. The optical receiver according to claim 1, wherein the first signal is generated based on the head pulse, and the second signal is generated based on the number of pulses for each optical packet.
The optical packet is an optical packet transmitted at a first transmission rate or a second transmission rate that is higher than the first transmission rate;
The separation circuit is
An OR circuit in which the control signal is input to one input unit;
A first delay flip-flop circuit in which a signal output from the logical sum circuit is input to a clock input unit, and an output signal of its own reverse phase is input to a D input unit;
A low-pass filter to which a positive phase output signal of the first delay flip-flop circuit is input;
A hysteresis circuit to which a signal output from the low-pass filter is input;
A second delay flip-flop circuit in which a signal output from the hysteresis circuit is input to a D input unit, and the control signal is input to a clock input unit;
With
A signal output from the low-pass filter is input to the other input portion of the OR circuit.
Outputting the control signal as the first signal;
8. The optical receiver according to claim 7, wherein a positive phase output signal of the second delay flip-flop circuit is output as the second signal.
The optical packet is an optical packet transmitted at a first transmission rate or a second transmission rate that is higher than the first transmission rate;
The separation circuit is
An OR circuit in which the control signal is input to one input unit;
A first delay flip-flop circuit in which a signal output from the logical sum circuit is input to a clock input unit, and an output signal of its own reverse phase is input to a D input unit;
A low-pass filter to which a positive phase output signal of the first delay flip-flop circuit is input;
A hysteresis circuit to which a signal output from the low-pass filter is input;
A second delay flip-flop circuit in which a signal output from the hysteresis circuit is input to a D input unit, and the control signal is input to a clock input unit;
A mask circuit that masks pulses other than the first pulse of the control signal and outputs the masked signal as the first signal;
With
A signal output from the low-pass filter is input to the other input portion of the OR circuit.
8. The optical receiver according to claim 7, wherein a positive phase output signal of the second delay flip-flop circuit is output as the second signal.
A control unit that generates a control signal in which information indicating a transmission rate of the optical packet and information indicating a time at which the head of the optical packet is received are superimposed;
An optical receiver that receives an optical signal intermittently received as an optical packet and receives the control signal;
With
The optical receiver is:
A light receiving element for converting the optical signal into a current signal;
The control signal is separated into a first signal indicating a time at which a head of the optical packet is received and a second signal indicating a transmission rate of the optical packet, and the first signal and the second signal are separated. A separation circuit that outputs
A receiver that converts the current signal into a voltage signal, switches a time constant according to the first signal, and switches a frequency response characteristic according to the second signal;
An optical communication device comprising:
A control method in an optical receiver that receives an optical signal intermittently received as an optical packet,
A first step of converting the optical signal into a current signal;
A first signal indicating the time at which the head of the optical packet is received, as a control signal on which information indicating the transmission rate of the optical packet and information indicating the time at which the head of the optical packet is received are superimposed. And a second step of separating the second signal indicating a transmission rate of the optical packet and outputting the first signal and the second signal;
A third step of converting the current signal into a voltage signal, switching a time constant according to the first signal, and switching a frequency response characteristic according to the second signal;
The control method characterized by including.