JP6524255B2 - Optical receiver, optical communication apparatus and control method - Google Patents

Description

  The present invention relates to an optical receiver in an optical communication system, an optical communication apparatus, and a control method in the optical receiver.

  In recent years, in optical communication systems, the transmission rate has been increased. On the other hand, it is desirable to continue to use an existing system that has not been speeded up, and it is necessary to coexist the new system that has been speeded up and the old system that is an existing system. At that time, the optical transceiver of the OLT (Optical Line Terminal), which is a base station in the optical access system, is required to be multi-rate to accommodate the new and old systems, and for any light reception level signal It is also required to have both fast response and high homo-code continuity tolerance.

  Patent Document 1 discloses an invention capable of realizing optimal frequency response characteristics for different transmission rates by switching the internal feedback resistance value of the preamplifier with a rate switching signal which is an external signal. There is.

  In the optical communication system, the OLT intermittently receives packets transmitted from each ONU (Optical Network Unit), that is, in a burst manner. For this reason, in the optical receiver 1 of the OLT, stable control is desired and a high-speed response at the start of packet reception is desired. In Patent Document 2, a high speed response is realized by switching to a high speed time constant when a reset signal is input from outside by using a low speed time constant to realize a high homo-code continuity resistance when the control converges. doing.

JP, 2010-166216, A International Publication No. 2012/137299

  In the case of realizing both multi-rate and high-speed response by using the above-described conventional technique, both a rate switching signal for switching the transmission rate and a reset signal for switching to the high-speed time constant are required. On the other hand, in recent years, in order to reduce the cost of the optical access system, it is required to increase the mounting density of the optical transmitter / receiver to miniaturize the optical transmitter / receiver. When the optical transmitter-receiver is mounted as an optical module mounted on a substrate, in order to miniaturize the optical transmitter-receiver, the substrate and the optical module are miniaturized, and a connector for connecting the optical module to an external interface substrate It is also a big challenge to reduce the number of input / output pins of each unit. Therefore, the optical receiver is required to realize both multi-rate and high-speed response while avoiding large-scale hardware.

  The present invention has been made in view of the above, and it is an object of the present invention to provide an optical receiver capable of realizing high-speed response to burst signals and correspondence to a plurality of transmission rates while avoiding upsizing of hardware. To aim.

In order to solve the problems described above and to achieve the object, an optical receiver according to the present invention includes a light receiving element that converts an optical signal intermittently received as an optical packet into a current signal, and control input from the outside And a separation circuit that separates a signal into a first signal indicating the time of receiving the beginning of the optical packet and a second signal indicating the transmission rate of the optical packet, and outputting the first signal and the second signal. And. The control signal is a signal in which information indicating the time when the light receiving element receives the head of the optical packet and information indicating the transmission rate of the optical packet are superimposed. Further, the optical receiver according to the present invention includes an inverting amplifier that converts a current signal into a voltage signal, switches a time constant in automatic gain control of the inverting amplifier according to a first signal, and responds to a second signal. And a receiver for switching frequency response characteristics. An optical packet is composed of a preamble and data. The control signal is a signal corresponding to the time when the light receiving element receives at least one of the rising edge and the falling edge of the light packet, and starts receiving data after the time when the light packet is received. In the rate indication period, which is a period including the time before, the value has a value indicating the transmission rate of the optical packet.

  The optical receiver according to the present invention has an effect that it is possible to realize high-speed response to a burst signal and correspondence to a plurality of transmission rates while avoiding an increase in hardware size.

FIG. 1 is a diagram showing an example of the configuration of an optical receiver according to a first embodiment. FIG. 2 shows a configuration example of a receiver according to Embodiment 1. A diagram showing an example of configuration of a gain control circuit according to a first embodiment A diagram showing a configuration example of the optical communication system according to the first embodiment The figure which shows the structural example of the processing circuit of Embodiment 1. FIG. 2 shows a configuration example of a control circuit of a first embodiment. Timing chart showing an example of each signal in the optical receiver according to the first embodiment FIG. 7 shows a configuration example of the separation circuit of the optical receiver according to Embodiment 2. Timing chart showing an example of a control signal, a rate select signal and a reset signal according to the second embodiment Flowchart showing an example of a control signal generation procedure according to the second embodiment The figure which shows the circuit structural example of the edge detection circuit at the time of making an edge detection circuit into a rising edge detection circuit. A diagram showing an example of the circuit configuration of an edge detection circuit when the edge detection circuit is a falling edge detection circuit The figure which shows the circuit structural example of the edge detection circuit at the time of using an edge detection circuit as a both-edge detection circuit FIG. 17 shows an example of an input signal to an operational amplifier in the edge detection circuit of the second embodiment and a signal output from the edge detection circuit. Timing chart showing an example of each signal in the case where a falling edge detection circuit is used as an edge detection circuit according to the second embodiment Timing chart showing an example of each signal in the case where both edge detection circuits are used as the edge detection circuit of the second embodiment Timing chart showing an example of each signal in the optical receiver according to the third embodiment Flowchart showing an example of a control signal generation procedure according to the third embodiment Timing chart showing an example of each signal in the optical receiver according to the fourth embodiment FIG. 16 shows a configuration example of the separation circuit of the fourth embodiment Timing chart showing an example of each signal in the separation circuit of the fourth embodiment The figure which shows the structural example of the isolation | separation circuit of Embodiment 4 which added the circuit which masks the 2nd pulse with respect to a reset signal.

  Hereinafter, an optical receiver 1, an optical communication apparatus, and a control method according to an embodiment of the present invention will be described in detail based on the drawings. The present invention is not limited by the embodiment.

Embodiment 1
FIG. 1 is a diagram showing an example of the configuration of an optical receiver 1 according to a first embodiment of the present invention. As shown in FIG. 1, the optical receiver 1 according to the first embodiment includes a light receiving element 11, a receiver 12 and a separation circuit 13. The optical receiver 1 according to the first embodiment is an optical receiver 1 that receives an optical packet in a burst manner. The optical receiver 1 according to the first embodiment is mounted, for example, on an OLT, which is an optical communication device, as described later.

  The light receiving element 11 is an element that converts the received light signal, that is, the light receiving signal into a current signal and outputs the current signal, and is, for example, an APD (Avalanche Photo Diode) or a PD (Photo Diode). The receiver 12 converts the current signal output from the light receiving element 11 into a voltage signal.

  The separation circuit 13 is a reset signal, which is a first signal used for switching the time constant in the receiver 12, and a second control signal, which is input from the outside, used for switching the frequency response characteristic in the receiver 12. And a reset signal and a rate select signal are input to the receiver 12. The control signal is a signal in which information indicating the time when the optical receiver 1 receives the beginning of the optical packet, that is, the time when the light receiving element 11 receives the beginning of the optical packet, and information indicating the transmission rate of the optical packet are superimposed. is there. The reset signal is a signal indicating a time when the optical receiver 1 receives the head of the optical packet received.

  The rate select signal is a signal indicating the transmission rate of the optical signal received by the optical receiver 1, that is, the transmission rate of the signal input to the receiver 12. In the first embodiment, the transmission rate of the optical signal received by the optical receiver 1 is a bit rate # 1 which is a first transmission rate, and a bit rate # which is a second transmission rate higher than the first transmission rate. We shall include 2 types with 2. Therefore, the rate select signal is, for example, a binary signal indicating either a value indicating that the bit rate is # 1 or a value indicating the bit rate # 2.

  The reset signal is a signal input from the separation circuit 13 and is a signal instructing initialization or reset of the optical receiver 1. The reset signal is, for example, a value instructing reset each time reception of an optical packet is started.

  The control signal may be generated from the control signal so as to be able to separate the reset signal and the rate select signal, and the specific form of the control signal is not particularly limited. Specific examples of the control signal will be described in Embodiment 2 and later. For example, when the optical receiver 1 is mounted on an OLT, the control signal is input to the optical receiver 1 from a control unit that controls an ONU in the OLT.

  The receiver 12 includes an amplifier and a control circuit that controls the amplifier, and is configured to be able to change control parameters in the amplifier in the receiver 12 according to a reset signal and a rate select signal. The control parameters include a frequency characteristic parameter which is a parameter corresponding to the frequency response characteristic of the receiver 12 and a time constant of a control circuit in the receiver 12. The frequency characteristic parameters are, for example, the feedback resistance value and the open loop gain described in Patent Document 1, and are changed according to the rate select signal. Further, the control circuit of the receiver 12 can change the time constant in accordance with the reset signal, for example, by the method described in Patent Document 2.

  The optimal frequency response characteristic in the operation of the receiver 12 varies depending on the transmission rate of the signal input to the receiver 12. The receiver 12 can change the frequency response parameter as described above, and the first frequency response parameter, which is the frequency response parameter for realizing the optimum frequency response characteristic for the bit rate # 1, and the bit rate It is assumed that a second frequency response parameter, which is a frequency response parameter for achieving an optimum frequency response characteristic, for # 2 can be set.

  FIG. 2 is a diagram showing an example of a configuration of the receiver 12 according to the first embodiment. The receiver 12 shown in FIG. 2 includes an inverting amplifier 121 which is a variable gain type inverting amplifier, a resistor 122 which is a first resistor, a resistor 123 which is a second resistor, and a MOS (Metal Oxide Semiconductor) transistor 124. , A gain control circuit 125, and a convergence determination circuit 126. The gain control circuit 125 performs automatic gain control on the inverting amplifier 121. The convergence determination circuit 126 determines the convergence of control by the gain control circuit 125. The MOS transistor 124 of the receiver 12 shown in FIG. 2 turns on or off in response to a rate select signal which is a signal indicating the transmission rate of the signal input to the receiver 12.

  The resistor 122, the resistor 123, and the MOS transistor 124 constitute a feedback resistor. The resistance value of the feedback resistor portion, that is, the feedback resistance value changes in accordance with the on / off state of the MOS transistor 124 serving as a switch. The frequency response characteristic depends on the feedback resistance value. Further, as described above, the optimal frequency response characteristic in the operation of the receiver 12 differs depending on the transmission rate of the signal input to the receiver 12. Therefore, the optimal feedback resistance value differs depending on the transmission rate of the signal input to the receiver 12. In the receiver 12 shown in FIG. 2, the resistance values of the resistors 122 and 123 and the resistance value of the MOS transistor 124 are optimum for the bit rate # 2 of the resistance value of the feedback resistance section when the MOS transistor 124 is on. And the resistance value of the feedback resistor portion when the MOS transistor 124 is off is set to a value that is optimum for the bit rate # 1. The MOS transistor 124 is turned on when the value of the rate select signal is a value indicating bit rate # 2, and the MOS transistor 124 is turned off when the value of the rate select signal is a value indicating bit rate # 1. By doing this, it is possible to use an optimal feedback resistance value according to the transmission rate. Thereby, the optimum frequency response characteristic can be realized according to the transmission rate.

  FIG. 3 is a diagram showing a configuration example of the gain control circuit 125 of the first embodiment. The gain control circuit 125 shown in FIG. 3 includes a high speed time constant circuit 127, a low speed time constant circuit 128, a switch 129, an arithmetic circuit 130, and a logic circuit 131 which is a D-flip flop. The high speed time constant circuit 127 is a circuit that averages the signal output from the inverting amplifier 121 with a first time constant. The low speed time constant circuit 128 is a circuit that averages the signal output from the inverting amplifier 121 with a second time constant longer than the first time constant. The switch 129 outputs one of the signal output from the high speed time constant circuit 127 and the signal output from the low speed time constant circuit 128 to the arithmetic circuit 130 based on the reset signal and the convergence determination signal. The arithmetic circuit 130 generates a gain control signal according to a predetermined control logic for automatically controlling the gain of the inverting amplifier 121 based on the signal output from the switch 129, and generates the gain control signal as an inverting amplifier. Output to 121.

  The convergence determination circuit 126 detects the convergence of automatic gain control based on the signal output from the gain control circuit 125, generates a convergence determination signal which is a signal indicating whether or not the convergence is detected, and generates the convergence. The determination signal is input to the logic circuit 131. As the convergence determination circuit 126, for example, a circuit obtained by removing the logic circuit from the convergence determination circuit described in Patent Document 2 can be used.

  The logic circuit 131 generates a time constant switching signal for switching the time constant circuit selected by the switch 129 based on the reset signal and the convergence determination signal, and outputs the generated time constant switching signal to the switch 129. The logic circuit 131 sets the time constant switching signal to a value instructing selection of the high-speed time constant circuit 127 when the reset signal has a value instructing reset. The logic circuit 131 sets the time constant switching signal to a value instructing selection of the low speed time constant circuit 128 when the convergence determination signal becomes a value instructing the convergence detection. By the above operation, when the optical receiver 1 starts reception of the optical packet, the first time constant which is the high speed time constant is set, and when the control converges, the second time constant which is the low speed time constant is set. Ru. Thus, the receiver 12 can realize high homo-code continuity tolerance and high-speed response.

  The configuration examples of FIGS. 2 and 3 are an example, and the configuration of the receiver 12 is not limited to the example of FIG. The receiver 12 may be any receiver 12 that performs switching of the frequency response characteristic based on the rate select signal and an operation based on the reset signal. For example, the receiver 12 may have a function of performing automatic offset control of a preamplifier, and may switch the time constant in the automatic offset control based on a reset signal. Further, in the examples of FIGS. 2 and 3, an example is described in which the reset signal is used to set a time constant suitable for starting reception of an optical packet, that is, a high speed time constant, when the time constant can be switched. . The operation of setting a suitable time constant at the start of reception of an optical packet can be referred to as an initialization operation in the receiver 12. The reset signal is not limited to switching of the time constant, and may be an operation for initializing the operation in the receiver 12. Further, although the example in which the feedback resistance value and the open loop gain are changed by the rate select signal has been described in FIG. 2, the control parameters to be changed based on the rate select signal are not limited to these.

  The separation circuit 13 separates a control signal to be described later input from the outside into a reset signal and a rate select signal, and inputs the reset signal and the rate select signal to the receiver 12. The reset signal is a signal indicating the beginning of the optical packet received by the optical receiver 1. The rate select signal is a signal instructing the receiver 12 to set the first frequency response parameter or the second frequency response parameter as the frequency response parameter. The control signal is generated to be able to separate the reset signal and the rate select signal from the control signal.

  The optical receiver 1 according to the first embodiment is mounted on, for example, an OLT in an optical communication system. FIG. 4 is a diagram showing an example of the configuration of the optical communication system of the first embodiment. As shown in FIG. 4, the optical communication system 60 according to the first embodiment includes an OLT 50 and ONUs 51, 52, 53. The OLT 50 is connected to the ONUs 51, 52, 53 via an optical star coupler and an optical fiber as a transmission path. Although the number of ONUs is three in FIG. 4, the number of ONUs is not limited to this.

  The OLT 50 performs bandwidth allocation for upstream communication to the ONUs 51, 52, 53, and grasps the reception time of optical packets transmitted from each ONU. The OLT 50 and the ONUs 51, 52, 53 operate according to a protocol (hereinafter referred to as PON protocol) in a PON (Passive Optical Network) system. As the PON protocol, for example, a protocol conforming to the standard of GE-PON of IEEE (Institute of Electrical and Electronics Engineers) or the standard of G-PON of International Telecommunication Union Telecommunication Standardization Sector (ITU-T) can be used. .

  The OLT 50 includes the optical receiver 1 of the first embodiment, an optical transmitter 2, and a control unit 3. The optical receiver 1 converts an optical signal received from each ONU via an optical fiber, that is, a light reception signal, into a voltage signal and outputs the voltage signal to the control unit 3. The optical transmitter 2 converts the transmission signal to be transmitted to each ONU generated by the control unit 3 into an optical signal, and transmits the optical signal to each ONU via an optical fiber.

  The control unit 3 generates a transmission signal to be transmitted to each ONU in accordance with the PON protocol, and outputs the transmission signal to the optical transmitter 2. Further, according to the PON protocol, the signal received from each ONU via the optical receiver 1 Implement the process. In addition, the control unit 3 acquires the transmission rate in the upstream direction corresponding to each ONU, that is, the transmission rate of the optical packet transmitted by each ONU by discovery processing or the like in the GE-PON, and holds the transmission rate for each ONU. There is. Also, the control unit 3 allocates an upstream band to each ONU. In the PON system, uplink bandwidths are allocated by time division multiplexing so that the signals transmitted from the ONUs do not overlap. The control unit 3 assigns an upstream band to each ONU by time division multiplexing, that is, a time zone for allowing transmission from each ONU to the OLT 50, and transmits the assignment result to each ONU via the optical transmitter 2. Each ONU transmits an optical signal to the OLT 50 in accordance with the assignment result received from the OLT 50. As described above, in the PON system, transmission from each ONU to the OLT 50 is performed by time division multiplexing, so the OLT 50 receives the optical signal transmitted from each ONU in a burst manner, that is, intermittently. Hereinafter, a group of signals transmitted in bursts will be called an optical packet. An optical packet is composed of a predetermined bit string called a preamble and data.

  As described above, since the controller 3 assigns the upstream band to each ONU, it grasps the time to receive an optical signal from each ONU. Therefore, the control unit 3 can obtain the time when the optical receiver 1 starts to receive the optical packet transmitted from the ONU. Therefore, the control unit 3 can generate a reset signal to be input to the above-described optical receiver 1. In addition, since the control unit 3 knows the upstream transmission rate of each ONU, it can also generate a rate select signal based on the optical signal of which transmission rate the optical packet to be received next. The rate select signal is used to switch frequency response characteristics in the receiver 12 of the optical receiver 1 as described above. Therefore, the rate select signal has a value indicating the transmission rate corresponding to the optical packet for each optical packet. Since synchronization processing and the like are performed in the preamble portion of the optical packet, the frequency response characteristic does not have to be suitable for the transmission rate, and before the optical receiver 1 receives the data portion of the optical packet, The value of the rate select signal may be a value indicating the corresponding transmission rate.

  Although the control unit 3 can generate the rate select signal and the reset signal used in the optical receiver 1, if the rate select signal and the reset signal are respectively input to the optical receiver 1, the optical receiver 1 The optical module to be mounted requires two signal input pins. In recent years, hardware miniaturization has been desired, and it is desirable that the number of input pins be as small as possible. Therefore, in the present embodiment, the control signal is input from the control unit 3 to the optical receiver 1 through one input pin, and the separation circuit 13 of the optical receiver 1 receives the rate select signal from the control signal. And the reset signal. The control signal may be one in which the reset signal and the rate select signal are multiplexed by shifting the timing at which reset is instructed by the reset signal and the timing at which the value of the rate select signal changes. It may be multiplexed by a method. The specifics of the control signal will be described in the second and subsequent embodiments.

  Next, the hardware configuration of the control unit 3 will be described. The control unit 3 is realized by a processing circuit. This processing circuit is a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP, etc.) which executes the program stored in the memory and the memory even if it is dedicated hardware. (Also referred to as a digital signal processor) may be employed. Here, the memory is, for example, nonvolatile or random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), etc. Volatile semiconductor memory, magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disk), etc. correspond.

  When the control unit 3 is realized by dedicated hardware, it is realized by the processing circuit 100 shown in FIG. The processing circuit 100 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a combination thereof.

  When the control unit 3 is realized by a control circuit including a CPU, this control circuit is, for example, a control circuit 200 configured as shown in FIG. As shown in FIG. 6, the control circuit 200 includes a processor 201, which is a CPU, and a memory 202. When the control unit 3 is realized by the control circuit 200, it is realized by the processor 201 reading out and executing a program corresponding to the process of the control unit 3 stored in the memory 202. The memory 202 is also used as a temporary memory in each process performed by the processor 201.

  Next, the operation of the optical receiver 1 of this embodiment will be described. FIG. 7 is a timing chart diagram showing an example of each signal in the optical receiver 1 of the first embodiment. The horizontal axis of FIG. 7 shows time. The first stage of FIG. 7 shows an example of an optical signal received by the optical receiver 1, the second stage of FIG. 7 shows an example of a rate select signal, and the third stage of FIG. An example is shown. As shown in the first stage of FIG. 7, the optical receiver 1 receives an optical packet in a burst manner. Each optical packet is composed of a preamble and data as described above. That is, the optical signal of the optical receiver 1 is an optical signal intermittently received as an optical packet. In the example of FIG. 7, the optical packet shown on the left is transmitted at the transmission rate of bit rate # 1, and the optical packet shown on the left is transmitted at the transmission rate of bit rate # 2.

  A control signal synchronized with the optical packet is input to the optical receiver 1 from the outside. The control signal is any signal that can be separated into a rate select signal and a reset signal. The separation circuit 13 separates the control signal into a rate select signal and a reset signal. The rate select signal and the reset signal are input to the receiver 12. The operation of the receiver 12 when the rate select signal and the reset signal are input is as described above, and the receiver 12 operates with the frequency response characteristic according to the rate select signal, and the operation of the receiver 12 by the reset signal Reset That is, the optical receiver 1 according to the present embodiment separates the optical signal into the current signal and the control signal input from the outside into the reset signal and the rate select signal, and the reset signal And a second step of outputting the rate select signal, and a third step of converting the current signal into a voltage signal, switching the time constant according to the reset signal, and switching the frequency response characteristic according to the rate select signal. Do.

  In the example of FIG. 7, the rate select signal is a binary signal of high and low, high indicates bit rate # 1, and low indicates bit rate # 2. Thus, while the rate select signal is high, receiver 12 operates with a frequency response characteristic suitable for bit rate # 1, and while the rate select signal is low, receiver 12 has a frequency suitable for bit rate # 2. Operates with response characteristics. The correspondence between the value of the rate select signal and the bit rate is not limited to this example, and low may indicate bit rate # 1 and high may indicate bit rate # 2.

  Also, in the example of FIG. 7, the reset signal is a binary signal of high and low, where high indicates that reset is significant, ie, reset has been instructed, and low indicates that reset is not significant, ie, reset is indicated. Indicates that it is not The reset signal is generally a pulse-like signal indicating the timing of resetting, as shown in the example of FIG. The receiver 12 switches the time constant to the first time constant, that is, the fast response time constant, as described above, when the reset signal becomes the value indicating the reset, ie, the value indicating that the reset is significant. In addition, other initialization operations may be performed according to the reset signal. Note that the correspondence between the value of the reset signal and whether the reset is significant is not limited to this example, and a low indicates that the reset is significant, and a high indicates that the reset is not significant. Good.

  As described above, in the optical receiver 1 according to the present embodiment, the separation circuit 13 separates the control signal input by one signal input pin into the reset signal and the rate select signal. As a result, using one signal input pin, it is possible to switch frequency response characteristics according to the transmission rate and to realize high-speed response to an optical packet received in a burst manner. As a result, the frequency response characteristic can be switched according to the transmission rate, and the hardware can be miniaturized while realizing high-speed response to the burst-received optical packet.

Second Embodiment
FIG. 8 is a view showing a configuration example of the separation circuit of the optical receiver 1 according to the second embodiment of the present invention. In the second embodiment, a configuration example of the separation circuit 13 in the optical receiver 1 described in the first embodiment and an example of a control signal will be described.

  The separation circuit 13 of the second embodiment is configured of an edge detection circuit 14 as shown in FIG. The edge detection circuit 14 uses a rising edge detection circuit that detects rising, a falling edge detection circuit that detects falling, or a both edge detection circuit that detects both rising and falling edges.

  FIG. 9 is a timing chart diagram showing an example of a control signal, a rate select signal and a reset signal according to the second embodiment. FIG. 9 shows an example in which a rising edge detection circuit is used as the edge detection circuit 14. In the example shown in FIG. 9, the control signal goes from low to high at the timing when the reset signal goes from low to high, that is, from the value indicating that reset is not significant to the value indicating that reset is significant. Change. After that, the control signal has a value according to the transmission rate of the optical packet received by the optical receiver 1 after a predetermined time has elapsed. As described above, the control signal of the present embodiment has a value according to the transmission rate of the optical packet received by the optical receiver 1 during the rate designation period including the time point before the reception of the data portion after the head of the optical packet. Indicates In the example of FIG. 9, the rate indication period is from when the reset signal changes from low to high and after a predetermined time has elapsed until the reception of the optical packet is ended. In the example of FIG. 9, when the control signal is high, bit rate # 1 is indicated, and when the control signal is low, bit rate # 2 is indicated.

  FIG. 10 is a flowchart of an example of a control signal generation procedure according to the second embodiment. The control signal shown in FIG. 9 is generated by the control unit 3 of the OLT 50 on which the optical receiver 1 is mounted, as described in the first embodiment. Here, the control signal is described as being generated by the control unit 3.

  The control unit 3 holds information on the upstream band allocated to each ONU, and determines whether it is time to start receiving an optical packet based on the information on the upstream band for each ONU that is held ((1) Step S1). When the control unit 3 determines that the reception start timing of the optical packet has come (Yes in step S1), the value of the control signal is set high (step S2). When the controller 3 determines that it is not the reception start timing of the optical packet (No in step S1), the controller 3 repeats step S1.

  After step S2, the control unit 3 determines whether the transmission rate of the optical packet, that is, the optical packet to be received is the bit rate # 1 (step S3). When the transmission rate of the optical packet is the bit rate # 1 (Yes in step S3), the control unit 3 determines whether it is the reception end timing of the optical packet (step S4). When it is the reception end timing of the optical packet (Yes in step S4), the control unit 3 sets the value of the control signal to be output to the optical receiver 1 low (step S5).

  In step S3, when the transmission rate of the optical packet is not the bit rate # 1 (No in step S3), the control unit 3 determines whether a predetermined time has elapsed since the value of the control signal is high (step S6). If the predetermined time has elapsed (Yes at step S6), the process proceeds to step S5, and if the predetermined time has not elapsed (No at step S6), step S6 is repeated. When it is not the reception end timing of the optical packet in step S4 (No in step S4), step S4 is repeated. By the above processing, the control unit 3 can generate the control signal shown in FIG. Note that the processing procedure shown in FIG. 10 is an example, and the specific processing procedure for generating the control signal is not limited to the example of FIG.

  Returning to the description of FIG. 9, the edge detection circuit 14 generates a pulse-like reset signal when detecting the rising edge of the control signal as shown in the second stage of FIG. 9, and the generated reset signal is received by the receiver 12 Output to Further, the separation circuit 13 of the optical receiver 1 outputs the input control signal as it is to the receiver 12 as a rate select signal. Before the receiver 12 receives the data portion of the optical packet, the frequency response characteristic may be set according to the transmission rate of the optical packet. Therefore, the predetermined time in the process of FIG. 9 described above may be within the time zone corresponding to the preamble.

  FIG. 11 is a diagram showing a circuit configuration example of the edge detection circuit 14 when the edge detection circuit 14 is a rising edge detection circuit. The edge detection circuit 14 shown in FIG. 11 includes a resistor 15, a capacitor 20, and an operational amplifier (operational amplifier) 24. The control signal is branched into two, and one of the branched signals is input to the positive phase of the operational amplifier 24 and the other is input to the opposite phase of the operational amplifier 24 through the low pass filter 151 configured of the resistor 15 and the capacitor 20. Be done. Here, the operational amplifier 24 is used as a circuit that outputs a high value signal when the positive phase input voltage becomes higher than the negative phase input voltage. The signal input to the operational amplifier 24 through the low pass filter 151 is a signal with a blunt edge. Therefore, in the vicinity of the rising edge of the control signal, the signal input in the positive phase becomes larger than the signal input in the reverse phase. The difference between the signal input in the positive phase and the signal input in the opposite phase is amplified by the operational amplifier 24 to be pulsed near the rising edge.

  FIG. 12 is a diagram showing a circuit configuration example of the edge detection circuit 14 when the edge detection circuit 14 is a falling edge detection circuit. In this case, for example, an inverted version of the control signal shown in FIG. 9 can be used as the control signal. The edge detection circuit 14 shown in FIG. 12 is composed of a resistor 16, a capacitor 21 and an operational amplifier 25. In the edge detection circuit 14 shown in FIG. 12, the control signal is input to the opposite phase of the operational amplifier 25, and the control signal passing through the low pass filter 152 configured of the resistor 16 and the capacitor 21 is in the positive phase of the operational amplifier 25. It is input. As a result, the signal output from the operational amplifier 25 is pulsed near the falling edge of the control signal.

  FIG. 13 is a diagram showing a circuit configuration example of the edge detection circuit 14 when the edge detection circuit 14 is a both edge detection circuit. The edge detection circuit 14 shown in FIG. 13 includes a falling detection circuit comprising a resistor 17, a capacitor 22, and an operational amplifier 26 which is a first operational amplifier, and an operational amplifier which is a resistor 18, a capacitor 23 and a second operational amplifier. A rise detection circuit 27 and an OR circuit 28 are provided. The falling edge detection circuit is similar to the edge detection circuit 14 of FIG. 11, and the rising edge detection circuit is similar to the edge detection circuit 14 of FIG. The resistor 17 and the capacitor 22 constitute a first low pass filter 153, and the resistor 18 and the capacitor 23 constitute a second low pass filter 154. The OR circuit (OR circuit) 28 outputs an OR (logical sum) of the signal output from the falling edge detection circuit and the signal output from the rising edge detection circuit.

  FIG. 14 is a diagram showing an example of an input signal to the operational amplifier in the edge detection circuit 14 of the second embodiment and a signal output from the edge detection circuit 14. The first stage of FIG. 14 shows an input signal to the operational amplifier, and the solid line shows the positive phase of the operational amplifier 24 shown in FIG. 11 and the operational amplifier 27 shown in FIG. 13 and the operational amplifier 25 shown in FIG. The input signal to the reverse phase of the operational amplifier 26 shown in FIG. 13 is shown. That is, the solid line in the first stage of FIG. 14 indicates the control signal input to the edge detection circuit 14. Further, the dotted line in the first stage of FIG. 14 is the opposite phase of the operational amplifier 24 shown in FIG. 11 and the operational amplifier 27 shown in FIG. 13 and the positive phase of the operational amplifier 25 shown in FIG. 12 and the operational amplifier 26 shown in FIG. The input signal to is shown.

  The second stage of FIG. 14 shows the signal outputted from the edge detection circuit 14 shown in FIG. 11, and the third stage of FIG. 14 shows the signal outputted from the edge detection circuit 14 shown in FIG. FIG. 14 shows a signal output from the rising edge detection circuit 14 shown in FIG.

  FIG. 9 shows each signal in the case where the rising edge detection circuit is used as the edge detection circuit 14. However, when the rising edge detection circuit or both edge detection circuit is used as the edge detection circuit 14, the timing chart is the example of FIG. It is partly different from.

  When the falling edge detection circuit is used as the edge detection circuit 14, the logic of the control signal may be inverted to invert the correspondence between the value of the rate select signal and the bit rate. Alternatively, control signals as shown in FIG. 15 may be generated. FIG. 15 is a timing chart diagram showing an example of each signal in the case where a falling edge detection circuit is used as the edge detection circuit 14. When the falling edge detection circuit is used as the edge detection circuit 14, the value of the reset signal becomes high at the falling edge of the control signal, so that the falling edge of the control signal is generated to be the timing for instructing reset.

  In the example of FIG. 15, the control signal is generated so that the value of the control signal changes from high to low at the reception start timing of the optical packet. Also, when an optical packet having a bit rate # 1 of 1 is received, the control signal value changes from low to high after a certain time from the reception start timing of the optical packet, and high until the reception start timing of the next optical packet. It is generated to be maintained and change to low at the start of reception of the next optical packet. The control signal goes low at the reception start timing of the optical packet and then keeps low when the optical packet with bit rate # 1 is 1 and is low for a certain time before the reception disclosure timing of the next packet. Is generated to change from high to high.

  FIG. 16 is a timing chart diagram showing an example of each signal in the case where both edge detection circuits are used as the edge detection circuit 14. When both edge detection circuits are used as the edge detection circuit 14, the falling and falling times of the control signal are generated so as to be the timing for instructing reset. Therefore, for example, when the control signal continuously receives an optical packet having the same bit rate, it generates a control signal as in the example of FIG. 9 and receives an optical packet having a bit rate different from that of the previous packet. In this case, as shown in FIG. 16, the value corresponding to the transmission rate of the previous optical packet may be maintained until the start timing of the next optical packet.

  As described above, in the second embodiment, some configuration examples of the separation circuit 13 and examples of control signals have been described, but in the control signal of the present embodiment, at least one of rising edge and falling edge is light A rate indication period which is a signal corresponding to the time when the light receiving element 11, ie, the optical receiver 1, receives the head of the packet, and which includes the time after the time when the head of the optical packet is received and before the start of data reception. In the above, it may be configured to have a value indicating the transmission rate of the optical packet. The separation circuit 13 includes an edge detection circuit 14 that detects an edge corresponding to the time of receiving the beginning of the optical packet of the control signal, and the signal output from the edge detection circuit 14 is used as a reset signal. It may be configured to generate a rate select signal based on the value of the control signal at.

  As described above, in the present embodiment, the example using the edge detection circuit as the separation circuit 13 capable of realizing the effects of the first embodiment has been described. As described in the first embodiment, by using this separation circuit 13, the control signal, the rate select signal, and the reset signal are separated. Therefore, the frequency response characteristic can be switched according to the transmission rate, and the hardware can be miniaturized while realizing high-speed response to the optical packet received in a burst manner.

Third Embodiment
FIG. 17 is a timing chart diagram showing an example of each signal in the optical receiver 1 according to the third embodiment of the present invention. The configuration of the optical receiver 1 of the present embodiment is the same as that of the first embodiment, and the configuration of the separation circuit 13 can be the configuration shown in FIG. 8 of the second embodiment. The configuration shown in FIG. 13 can be used. Hereinafter, portions different from the first embodiment and the second embodiment will be described.

  As described in the first embodiment, switching of the frequency response characteristic based on the rate select signal may be performed before receiving the data portion of the optical packet, but there is a problem if this switching is performed during reception of the optical packet. Can occur. For this reason, it is more desirable to switch the frequency response characteristics before receiving the preamble portion. In the third embodiment, an operation for preventing switching of frequency response characteristics during reception of an optical packet when guard time is inserted between optical packets will be described.

  As shown in FIG. 17, in this embodiment, it is assumed that a no-signal section called guard time is inserted between packets. The control signal is fixed at a value determined by the transmission rate during reception of the optical packet. Then, during the guard time period, a signal obtained by inverting the signal level determined by the transmission rate of the optical packet immediately after the guard time is input. Here, the control signal is a binary signal, and a value obtained by inverting the value indicating the transmission rate is a value other than the value indicating the transmission rate among the two values, and a value different from the value indicating the transmission rate. Indicates that. This causes the rising or falling edge of the control signal at the beginning of the optical packet, ie, at the start of reception. Therefore, the reset signal can be generated by the double edge detection circuit described in the second embodiment. Also, switching of the rate select signal does not occur during reception of the optical packet.

  FIG. 18 is a flowchart of an example of a control signal generation procedure according to the third embodiment. The control signal is generated by the control unit 3 of the OLT 50 on which the optical receiver 1 is mounted as described in the first embodiment. As shown in FIG. 18, the control unit 3 determines whether it is the start time of the guard time (step S21). When it is not the start timing of the guard time (No in step S21), step S21 is repeated. When it is the start timing of the guard time (Yes in step S21), the control unit 3 inverts the value of the rate select signal corresponding to the transmission rate of the next optical packet, that is, the value indicating the transmission rate Let it be a value (step S22). Then, the control unit 3 determines whether the guard time has ended (step S23). If the guard time has not ended (step S23 No), step S23 is repeated.

  If the guard time is over (Yes at step S23), the control unit 3 sets the value of the control signal as the value of the rate select signal corresponding to the transmission rate of the optical packet (step S24), and returns to step S21.

  As described above, in the present embodiment, in the guard time, the value of the control signal is the value obtained by inverting the value of the rate select signal corresponding to the transmission rate of the next optical packet, and control is performed during reception of the optical packet. Let the value of the signal be the value of the rate select signal corresponding to the transmission rate of the optical packet. Then, the separation circuit 13 of the optical receiver 1 generates the reset signal using the both edge detection circuit. Therefore, the effects described in the first embodiment can be obtained, and it is possible to prevent switching of the rate select signal during reception of the optical packet, and to prevent problems caused by switching of the rate select signal.

Fourth Embodiment
FIG. 19 is a timing chart diagram showing an example of each signal in the optical receiver 1 according to the fourth embodiment of the present invention. In the fourth embodiment, as a specific example of the control signal and the separation circuit 13 described in the first embodiment, an example different from the second embodiment and the third embodiment will be described. The configuration of the optical receiver 1 is the same as that of the first embodiment. In the present embodiment, the control signal is generated as a pulse signal.

  As shown in FIG. 19, the control signal changes from low to high in a pulsed manner at the beginning, that is, at the start of reception, for each optical packet. The pulse at the start of this reception is called the leading pulse or the first pulse. Thereafter, when the transmission rate of the optical packet is the bit rate # 1, the second pulse is input as a control signal. On the other hand, when the transmission rate of the optical packet is the bit rate # 2, the second pulse is not input, and the control signal remains low. Thus, in the control signal of the fourth embodiment, the bit rate is indicated by the number of times the pulse is input. That is, the control signal of the fourth embodiment is a pulse signal, and has a number of pulses corresponding to the transmission rate of the optical packet between the reception of the data portion of the optical packet for each optical packet. The leading pulse, which is one of the pulses, indicates the time when the light receiving element receives the beginning of the optical packet.

  In the present embodiment, since the pulse is input at the head of the optical packet, the optical receiver 1 can use the control signal as it is as the reset signal. Also, the optical receiver 1 can generate a rate select signal according to the number of pulses for each optical packet.

  The control signal of the present embodiment is generated by, for example, the control unit 3 of the OLT 50 as described in the first embodiment. When the control signal contains a first pulse at the beginning of each optical packet and the transmission rate of the optical packet is bit rate # 1, the control unit 3 generates a second pulse after the first pulse. To be included.

  FIG. 20 is a diagram showing a configuration example of the separation circuit 13 of the present embodiment. As shown in FIG. 20, the separation circuit 13 of this embodiment includes a D-flip-flop circuit 30 which is a first delay-type flip-flop circuit and a D-flip-flop circuit which is a second delay-type flip-flop circuit. 31, a hysteresis circuit 32, a resistor 33, a capacitor 34, and an OR circuit 35. The resistor 33 and the capacitor 34 form a low pass filter 155.

  As shown in FIG. 20, a control signal is input to one input portion of the OR circuit 35, and a signal output from the OR circuit 35 is input to the clock input portion of the D-flip flop circuit 30, and the D-flip flop circuit An output signal of reverse phase of 30 is input to the D input portion of the D-flip flop circuit 30. Further, the positive phase output signal of the D-flip flop circuit 30 is input to the low pass filter 155 composed of the resistor 33 and the capacitor 34, and the signal output from the low pass filter 155 is input to the hysteresis circuit 32. A signal output from the hysteresis circuit 32 is input to the D input section of the D flip-flop circuit 31, and a control signal is input to the clock input section of the D flip-flop circuit 31. The signal output from the low pass filter 155 is input to the other input portion of the OR circuit 35.

  FIG. 21 is a timing chart diagram showing an example of each signal in the separation circuit 13 of the fourth embodiment. The first stage of FIG. 21 shows the control signal, the solid line of the second stage of FIG. 21 shows the reset signal generated by the separation circuit 13 of the fourth embodiment, and the dotted line of the second stage of FIG. 18 shows a rate select signal generated by the separation circuit 13 of the fourth embodiment. The solid line in the third stage in FIG. 21 indicates the signal on signal line A shown in FIG. 20, ie, signal A, and the dotted line in the third stage in FIG. 21 indicates the signal in signal line B shown in FIG. Show. The solid line at the fourth stage in FIG. 21 indicates the signal on the signal line C shown in FIG. 20, that is, the signal C. The dotted line in the fourth stage in FIG. 21 indicates the signal at the signal line D shown in FIG. Show. The solid line at the fifth stage in FIG. 21 indicates the signal on signal line E shown in FIG.

  In the initial state, that is, before the control signal is input, the signal A and the signals C, D, E, and F are low, and the signal B is high. At this time, there is no problem whether the rate select signal is high or low. The control signal is input to the OR circuit 35 and the clock input unit of the D-flip flop circuit 31, and is output as it is as a reset signal. The signal E is low in the initial state, and when the first pulse is input as a control signal, the positive phase output of the D flip-flop circuit 31 becomes low in synchronization with the reset signal. The positive phase output signal of the D-flip flop circuit 31 is a rate select signal.

  The control signal input to the OR circuit 35 is also input to the clock input unit of the D-flip flop circuit 30 via the OR circuit 35. The D-flip flop circuit 30 forms a divider circuit, and switches the level of the output signal in synchronization with the signal input to the clock input unit. Therefore, when the first pulse is input as the control signal, the signal B which is the output signal of the reverse phase of the D flip-flop circuit 30 switches from high to low, and the positive phase of the D flip-flop circuit 30 The signal C, which is an output signal, goes from low to high.

  The signal C is input to a low pass filter formed by the resistor 33 and the capacitor 34 and the hysteresis circuit 32, and is output from the hysteresis circuit 32 as a signal D having a delay according to the filter time constant. That is, as shown in FIG. 21, the signal E, which is a signal output from the hysteresis circuit 32, rises behind the rising edge of the first pulse of the control signal. The signal output from the hysteresis circuit 32 is input to the OR circuit 35 and then input to the clock input unit of the D-flip flop circuit 30. As a result, the signal C which is the positive phase output signal of the D flip-flop circuit 30 becomes low, and the signal B which is the reverse phase output signal of the D flip-flop circuit 30 becomes high. In synchronization with these operations, the signal A transitions from high to low, and the signal D transitions gently from high to low according to the time constant of the low pass filter. Thus, the signal E changes to low after maintaining high for a time dependent on the change of the signal D. While the signal E is high, the input to the D-flip flop circuit 30 is not changed by the OR circuit 35 even if the second pulse is input as a control signal. On the other hand, since the second pulse of the control signal is inputted as it is to the D flip-flop circuit 31, a rate select signal which is a signal outputted from the D flip-flop circuit 31 when the second pulse is inputted. Changes to high.

  By the above operation, the rate select signal becomes high when the pulse is inputted twice consecutively to the separation circuit 13 of the fourth embodiment, and the rate select signal is inputted when the pulse is inputted only once. The signal goes low. Thereby, the separation circuit 13 according to the fourth embodiment can separate the reset signal and the rate select signal from the control signal.

  In addition, a circuit for masking a second pulse for the reset signal may be added to the configuration shown in FIG. FIG. 22 is a diagram showing a configuration example of the separation circuit 13 of the fourth embodiment to which a circuit for masking the second pulse with respect to the reset signal is added. The separation circuit 13 shown in FIG. 22 is the same as the separation circuit 13 shown in FIG. 20 except that a mask circuit 42 formed of a buffer circuit 40 and an AND circuit (AND circuit) 41 is added. Thus, the second pulse can be masked with respect to the signal output as the reset signal, and one pulse per optical packet is output as the reset signal. As a result, it is possible to prevent a failure due to the reset signal being input to the receiver 12 twice consecutively.

  As described above, in the present embodiment, an example in which the signal indicating the transmission rate by the number of pulses is used as the control signal that can realize the effect of the first embodiment has been described. Therefore, the frequency response characteristic can be switched according to the transmission rate, and the hardware can be miniaturized while realizing high-speed response to the optical packet received in a burst manner.

  The configuration shown in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and one of the configurations is possible within the scope of the present invention. Parts can be omitted or changed.

  Reference Signs List 1 optical receiver, 2 optical transmitter, 3 control unit, 11 light receiving element, 12 receiver, 13 separation circuit, 14 edge detection circuit, 50 OLT, 51, 52, 53 ONU, 15, 16, 17, 18, 33 Resistor, 20, 21, 22, 23, 34 capacitor, 24, 25, 26, 27 operational amplifier, 28 OR circuit, 30, 31 D flip-flop circuit, 32 hysteresis circuit, 40 buffer circuit, 41 AND circuit, 42 mask circuit , 151-155 low pass filter.

Claims (9)

A light receiving element for converting an optical signal intermittently received as an optical packet into a current signal;
A control signal in which information indicating the time when the light receiving element receives the head of the optical packet and information indicating the transmission rate of the optical packet, which are input from the outside, is superimposed on the time when the head of the optical packet is received A separation circuit that separates a first signal to be shown and a second signal to indicate the transmission rate of the optical packet and outputs the first signal and the second signal;
A receiver comprising: an inverting amplifier that converts the current signal into a voltage signal; switching a time constant in automatic gain control of the inverting amplifier according to the first signal; and switching frequency response characteristics according to the second signal When,
Equipped with
The optical packet is composed of a preamble and data,
The control signal is a signal corresponding to the time when the light receiving element receives at least one of the rising edge and the falling edge of the light packet, and the time from the time when the light packet is received the rate instruction period is a period including the previous time to start the reception of data, the optical receiver according to claim Rukoto to have a value indicating the transmission rate of the optical packet. Before Symbol separation circuit,
An edge detection circuit for detecting the edge corresponding to a time when the head of the optical packet of the control signal is received;
Equipped with
The light according to claim 1, wherein the signal output from the edge detection circuit is the first signal, and the second signal is generated based on the value of the control signal in the rate indication period. Receiver. The edge detection circuit
A low pass filter to which the control signal is input;
An operational amplifier in which the control signal is input to the positive phase input unit, and the control signal after passing through the low pass filter is input to the negative phase input unit;
The light receiver according to claim 2, comprising: The edge detection circuit
A low pass filter to which the control signal is input;
An operational amplifier in which the control signal is input to the negative phase input portion, and the control signal after passing through the low pass filter is input to the positive phase input portion;
The light receiver according to claim 2, comprising: The edge detection circuit
A first low pass filter to which the control signal is input;
A first operational amplifier to which the control signal is input to an input portion of reverse phase, and to which the control signal after passing through the first low pass filter is input to a positive phase input portion;
A second low pass filter to which the control signal is input;
A second operational amplifier in which the control signal is input to the positive phase input unit, and the control signal after passing through the second low pass filter is input to the negative phase input unit;
A logical sum circuit that calculates the logical sum of the signal output from the first operational amplifier and the signal output from the second operational amplifier;
The light receiver according to claim 2, comprising: Between the front Symbol receiving element is completed the reception of the optical packet to the start of reception of the next of said optical packet of the optical packet, the guard time is provided a period of not receiving the optical packet,
The optical packet is an optical packet transmitted at a first transmission rate or a second transmission rate higher than the first transmission rate,
The control signal is a binary signal indicating the first transmission rate or the second transmission rate, and in the guard time, a value indicating the transmission rate of the optical packet received immediately after the guard time 6. The optical receiver according to claim 5, wherein the optical receiver has different values, and has a value indicating a transmission rate of the optical packet during reception of the optical packet. A light receiving element for converting an optical signal intermittently received as an optical packet into a current signal;
A control signal in which information indicating the time when the light receiving element receives the head of the optical packet and information indicating the transmission rate of the optical packet, which are input from the outside, is superimposed on the time when the head of the optical packet is received A separation circuit that separates a first signal to be shown and a second signal to indicate the transmission rate of the optical packet and outputs the first signal and the second signal;
A receiver comprising: an inverting amplifier that converts the current signal into a voltage signal; switching a time constant in automatic gain control of the inverting amplifier according to the first signal; and switching frequency response characteristics according to the second signal When,
Equipped with
The optical packet is composed of a preamble and data,
The control signal is a pulse signal, and the transmission of the optical packet is performed in a rate indication period which is a period including a time after receiving the head of the optical packet for each optical packet and before starting reception of the data. The rising edge of the leading pulse , which has a number of pulses corresponding to the rate, and which is one of the pulses for each of the optical packets, indicates the time at which the light receiving element receives the beginning of the optical packet;
The separation circuit is
It said head pulse to generate a first signal based on the optical receiver you and generates the second signal based on the number of the pulses of each of the optical packets. A control unit that generates a control signal in which information indicating a transmission rate of an optical packet and information indicating a time at which the head of the optical packet is received are superimposed;
An optical receiver that receives an optical signal intermittently received as an optical packet and receives the control signal;
Equipped with
The optical receiver is
A light receiving element that converts the light signal into a current signal;
The control signal is separated into a first signal indicating a time to receive the head of the optical packet and a second signal indicating a transmission rate of the optical packet, and the first signal and the second signal are separated. A separation circuit that outputs
A receiver comprising: an inverting amplifier that converts the current signal into a voltage signal; switching a time constant in automatic gain control of the inverting amplifier according to the first signal; and switching frequency response characteristics according to the second signal When,
Equipped with
The optical packet is composed of a preamble and data,
The control signal is a signal corresponding to the time when the light receiving element receives at least one of the rising edge and the falling edge of the light packet, and the time from the time when the light packet is received the rate instruction period is a period including the previous time to start the reception of data, the optical communication apparatus according to claim Rukoto to have a value indicating the transmission rate of the optical packet. A control method in an optical receiver for receiving an optical signal intermittently received as an optical packet, comprising:
Converting the light signal to a current signal;
A control signal input from the outside, in which information indicating the transmission rate of the optical packet and information indicating the time to receive the head of the optical packet are superimposed, is a first signal indicating the time to receive the head of the optical packet And a second step of separating into a second signal indicating the transmission rate of the optical packet, and outputting the first signal and the second signal;
The current signal is converted to a voltage signal by an inverting amplifier, the time constant in automatic gain control of the inverting amplifier is switched according to the first signal, and the frequency response characteristic is switched according to the second signal. Step and
Only including,
The optical packet is composed of a preamble and data,
The control signal is a signal corresponding to a time when at least one edge of the rising edge and the falling edge receives the head of the optical packet, and receives the head of the optical packet. A control method characterized by having a value indicating a transmission rate of the optical packet in a rate indication period which is a period including a time after the time and before the start of reception of the data .

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