WO2017088264A1 - 具有低切换频率的数据线驱动极性的阵列基板 - Google Patents

具有低切换频率的数据线驱动极性的阵列基板 Download PDF

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Publication number
WO2017088264A1
WO2017088264A1 PCT/CN2015/099662 CN2015099662W WO2017088264A1 WO 2017088264 A1 WO2017088264 A1 WO 2017088264A1 CN 2015099662 W CN2015099662 W CN 2015099662W WO 2017088264 A1 WO2017088264 A1 WO 2017088264A1
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sub
polarity
pixels
pixel
data line
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English (en)
French (fr)
Inventor
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/906,560 priority Critical patent/US10629145B2/en
Publication of WO2017088264A1 publication Critical patent/WO2017088264A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present patent application relates to a substrate, and more particularly to an array substrate having a data line driving polarity with a low switching frequency.
  • the data line is lowered (Data Line)
  • the switching frequency of the positive and negative polarity of the signal to reduce the power consumption of the entire display panel, meet the requirements of green environmental protection, and improve the display quality of the display panel.
  • liquid crystal display liquid crystal display, LCD
  • LCD liquid crystal display
  • cathode ray tube, CRT cathode ray tube
  • Data line sharing Data Line The Sharing, DLS
  • DLS Data Line The Sharing
  • Dot Inversion is a better way to reverse the display.
  • the display panel adopts the data line sharing (DLS) architecture, using the traditional driving method, with high-definition (HD) resolution (1366 ⁇ 768) and 60Hz operating frequency, when the display panel is working, the signal of the data line is every two. Pixel needs to switch the polarity once, that is, every 21.7 ⁇ s (equal to 1/(60*768)) needs to switch once polarity, and the corresponding data line signal frequency is on the order of 20kHz.
  • the disadvantage is that the power consumption of the data line is increased.
  • the charging time of the data line sharing (DLS) architecture pixel (Pixel) is very short, and the resistance/capacitance delay of the signal switching on the data line sharing (RC) Delay) will further affect the charging of the pixel, which is not conducive to the improvement of display quality.
  • This problem will be more serious when the resolution of the display panel is increased. Therefore, it is necessary to develop a new type of array substrate to solve the above problems.
  • an object of the present patent application is to provide an array substrate having a data line driving polarity with a low switching frequency, and when the condition of dot inversion inside the display panel is realized, by reducing the data line (Data Line)
  • the switching frequency of the positive and negative polarity of the signal to reduce the power consumption of the entire display panel, meet the requirements of green environmental protection, and improve the display quality of the display panel.
  • the first embodiment of the present application provides a data line driving polarity array substrate having a low switching frequency for a liquid crystal panel, wherein the array substrate includes: a gate driver, a plurality of gate contacts for generating a plurality of scan signals; a source driver for generating a data signal; and a plurality of scan lines electrically connecting the plurality of gate contacts of the gate driver for correspondingly receiving the a plurality of scan signals, the plurality of gate contacts being the same as the number of the plurality of scan lines and corresponding to each other; and a plurality of data lines electrically connected to the source driver for receiving the data signal correspondingly;
  • the plurality of scan lines are interleaved with the plurality of data lines to form a matrix arrangement of rows and columns to form a plurality of pixel regions, each pixel region comprising one data line and two scan lines, and each pixel region is of a different color type Two sub-pixels each having a first polarity and a second polarity of different driving
  • the first sub-pixel group having the first polarity is charged, and the source driver is switchable to charge a second sub-pixel group having the second polarity among consecutive pixels.
  • the number of sub-pixels of the first sub-pixel group and the second sub-pixel group is greater than the number of sub-pixels of each pixel region, respectively, so that the first sub-pixel group is driven or the second time.
  • the frequency of the pixel group is lower than the frequency of the two sub-pixels corresponding to one pixel area.
  • the driving polarity of each pixel is different from the driving polarity of several sub-pixels around it.
  • the first polarity and the second polarity are positive polarity and negative polarity, respectively, or the first polarity and the second polarity are negative polarity and positive polarity, respectively.
  • the sub-pixels of the two different color types are composed of sub-pixels of any two of the blue sub-pixel, the green sub-pixel, and the red sub-pixel.
  • the sub-pixels of the two different color types are composed of sub-pixels of any two of the white sub-pixel, the blue sub-pixel, the green sub-pixel, and the red sub-pixel.
  • the gate contacts of the gate driver are numbered G(0), G(1), G(2), ..., G(n), respectively, and the number of the plurality of scan lines are respectively GL(0), GL(1), GL(2)...GL(n), where n is a positive integer, wherein the plurality of gate contacts G(8k+2), G(8k+3), G( 8k+4) and G(8k+5) respectively correspond to the plurality of scan lines GL(8k+4), GL(8k+5), GL(8k+2), and GL(8k+3) Cross-electrical connection, k is an integer.
  • the plurality of gate contact portions G(8k), G(8k+1), G(8k+6), and G(8k+7) are respectively associated with the plurality of scan lines GL(8k), GL (8k+1), GL (8k+6), and GL (8k+7) form the corresponding direct electrical connection.
  • 1A is a circuit diagram of an array substrate that drives polarity in accordance with a data line having a low switching frequency in the first embodiment of the present patent application.
  • FIG. 1B is a driving timing waveform diagram of scan lines and data lines of the array substrate in the first embodiment according to the present patent application.
  • FIG. 1B is a driving timing waveform diagram of scan lines and data lines of the array substrate in the first embodiment according to the present patent application.
  • FIG. 2A is a circuit diagram of an array substrate that drives polarity in accordance with a data line having a low switching frequency in a second embodiment of the present patent application.
  • 2B is a driving timing waveform diagram of scan lines and data lines of the array substrate in the second embodiment according to the present patent application.
  • FIG. 1A is a circuit diagram of an array substrate having a data line driving polarity with a low switching frequency according to a first embodiment of the present patent application
  • FIG. 1B is an array substrate according to a first embodiment of the present patent application.
  • Driving timing waveform diagram of scan lines and data lines The array substrate is a data line sharing structure, and is used for a liquid crystal panel.
  • the array substrate is provided with a gate driver 100, a source driver 102, a plurality of scan lines GL0 GL GL13, a plurality of data lines DL1 DL DL5, and a plurality of sub-pixels 104B. , 104G, 104R.
  • there are 14 scanning lines and 5 data lines but the number is not limited thereto, for example, more scanning lines and data lines.
  • the gate driver 100 is provided with a plurality of gate contact portions G0 to G13 for generating a plurality of scan signals.
  • the source driver 102 is used to generate a data signal.
  • the plurality of gate contact portions G0 G G13 are electrically connected to the plurality of gate contact portions G0 G G13 of the gate driver 100 for receiving the plurality of scan signals corresponding to the plurality of gate contact portions G0 G G13
  • the number of scanning lines GL0 to GL13 is the same and corresponds to each other.
  • a plurality of data lines DL1 DL DL5 are electrically connected to the source driver 102 for correspondingly receiving the data signals.
  • the plurality of scan lines GL0 GL GL13 are interleaved with the plurality of data lines DL1 DL DL5 to form a matrix arrangement of rows and columns to form a plurality of pixel regions 106, each of which includes a data line DL1.
  • each pixel area 106 is composed of two sub-pixels 104B, 104G, 104R of different color types, the two sub-pixels 104B, 104G, 104R have different driving respectively
  • the first polarity 108P of the polarity and the second polarity 108N wherein a part of the gate contact portions G0 G G13 are directly electrically connected to a part of the scan lines GL0 GL GL13, and the other part of the gate contact portions G0 G G13 are correspondingly cross-connected.
  • Another portion of the scan lines GL0 GL GL13 are connected in a manner such that, on each of the data lines DL1 DL DL5, the source driver 102 has the first sub-pixel group having the first polarity 108P among consecutive pixel regions 106 For example, the positive polarity sub-pixels on the data line DL2 and the scan lines GL2, GL3, GL6, GL7 are alternately charged, and the source driver 102 can switch to the second plurality of consecutive pixel regions 106.
  • the sub-pixel group for example, the negative polarity sub-pixels on the data line DL2 and the interlaced positions of the scan lines GL1, GL4, GL5, GL8 are charged, wherein the first sub-pixel group and the second sub-pixel group are The number of pixels is greater than the number of sub-pixels 104B, 104G, and 104R of each pixel region 106, respectively, so that the frequency of driving the first sub-pixel group or the second sub-pixel group is lower than two corresponding to one pixel region 106. The frequency of the sub-pixels.
  • the driving polarity of each of the pixels 104B, 104G, 104R is different from the driving polarities of the plurality of sub-pixels 104B, 104G, 104R around it.
  • the driving polarity of each of the pixels 104B, 104G, 104R is opposite to the driving polarity of the plurality of sub-pixels 104B, 104G, 104R around it to form a data line sharing (Data Line Sharing, DLS) display panel architecture.
  • DLS Data Line Sharing
  • the first polarity and the second polarity are positive polarity (+) and negative polarity (-), respectively, or the first polarity and the second polarity are negative polarity (-), respectively Positive polarity (+).
  • the two different color type sub-pixels 104B, 104G, 104R are composed of sub-pixels of any two colors of the blue sub-pixel 104B, the green sub-pixel 104G, and the red sub-pixel 104R.
  • the number of the gate contact portions of the gate driver 100 is G0, G1, G2, ..., Gn, respectively, and the number of the plurality of scan lines. Respectively GL0, GL1, GL2...GLn, where n is a positive integer, wherein the plurality of gate contacts G(8k+2), G(8k+3), G(8k+4), and G(8k+5) And forming the corresponding cross-electrical connection with the plurality of scan lines GL(8k+4), GL(8k+5), GL(8k+2), and GL(8k+3), respectively, k being an integer.
  • four of the eight sets of eight gate contact portions G0, G1, G2, ... G7 are cross-connected together with the gate lines of the gate driver 100 and the different numbered display lines inside the display panel, such as shown in FIG. 1A.
  • a plurality of gate contact portions G(8k), G(8k+1), G(8k+6), and G(8k+7) and the plurality of scan lines GL(8k), GL(8k+1), GL, respectively (8k+6) and GL(8k+7) form the corresponding direct electrical connection.
  • the other four of the set of eight gate contact portions G0, G1, G2, ... G7 are directly connected together in the gate driver 100 and the same numbered scan lines inside the display panel.
  • the G gate driver 100 when the display panel is in normal operation, the G gate driver 100 is sequentially turned on in the order of G1, G2, G3, . . . Gn (for example, a 10 ⁇ s pulse width corresponds to a data signal to a pixel charging pulse width. ), but the data line switches polarity once after every 4 sub-pixels are charged (ie, 4 charge pulse widths).
  • the data line DL2 is taken as an example, and the gate contact portion is used.
  • the sub-pixels corresponding to G(8k), G(8k+1), G(8k+2), and G(8k+3) are negative polarity (-), and gate contact portions G(8k+4), G( The sub-pixels corresponding to 8k+5), G(8k+6) and G(8k+7) are positive polarity (+), and the polarity switching is performed every 43.4 ⁇ s after the data line, which is different from the prior art.
  • the frequency of data line polarity switching is reduced by 1/2.
  • a high-definition (HD) resolution (1366 ⁇ 768) display panel is taken as an example, 60 Hz.
  • the operating frequency only need to switch 384 (equal to 1 / (60 * 768 * 2)) sub-polarity, because the power consumption of the data line is proportional to the square of the frequency, therefore, after the data line signal frequency is reduced, the entire display panel Power consumption will Significant decline, in line with the current green environmental needs.
  • the sub-pixels 104B, 104G, and 104R are electrically connected to the scan lines GL and the data lines DL.
  • Each of the pixels 104B, 104G, and 104R has a transistor 108 and a liquid crystal capacitor (liquid-crystal).
  • Capacitor, CLC) and storage capacitor (storage capacitor, CS) wherein each transistor 108 has a gate G, a source S and a drain D, and the gate G is connected to the scan line GL, and the source S is connected to the data line DL.
  • the drain D is connected to the liquid crystal capacitor (CLC) and the storage capacitor (CS), and the liquid crystal capacitor (CLC) and the storage capacitor (CS) are grounded (as shown in FIG.
  • the thin film transistor 108 connected to the scan line is turned on (switch On, the pixel electrodes of the liquid crystal capacitors are electrically connected to the vertical data lines DL, and the corresponding video signals are fed through the vertical data lines to charge the liquid crystal capacitors to an appropriate voltage level; in other words, to these
  • the liquid crystal capacitor corresponding to the sub-pixel is charged to drive the liquid crystal molecules in the liquid crystal layer to cause the liquid crystal display to display an image; and at the same time, the storage capacitors (CS) connected to the data line are charged, and the storage capacitor (CS)
  • the voltage across the liquid crystal capacitor (CLC) is maintained at a constant value, that is, the voltage across the liquid crystal capacitor (CLC) is maintained by the storage capacitor (CS) before the data is updated.
  • FIG. 2A is a circuit diagram of an array substrate having a data line driving polarity with a low switching frequency according to a second embodiment of the present patent application
  • FIG. 2B is an array substrate according to a second embodiment of the present patent application.
  • Driving timing waveform diagram of scan lines and data lines The array substrate having the data line driving polarity with the low switching frequency in the second embodiment of the second embodiment is similar to the first embodiment, except that the sub-pixels of the two different color types are white sub-pixels 104W, The sub-pixels of any two colors of the blue sub-pixel 104B, the green sub-pixel 104G, and the red sub-pixel 104R are composed.
  • the driving polarity of each of the pixels 104W, 104B, 104G, 104R is different from the driving polarities of the plurality of sub-pixels 104W, 104B, 104G, 104R around it.
  • the driving polarity of each of the pixels 104W, 104B, 104G, 104R is opposite to the driving polarity of the plurality of sub-pixels 104W, 104B, 104G, 104R around it to form a data line sharing (Data Line Sharing, DLS) display panel architecture.
  • DLS Data Line Sharing
  • the first polarity and the second polarity are positive polarity (+) and negative polarity (-), respectively, or the first polarity and the second polarity are negative polarity (-), respectively Positive polarity (+).
  • the two different color type sub-pixels 104W, 104B, 104G, 104R are any two colors of the white sub-pixel 104W, the blue sub-pixel 104B, the green sub-pixel 104G, and the red sub-pixel 104R.
  • the sub-pixels are composed.
  • the number of the gate contact portions of the gate driver 100 is G0, G1, G2, ..., Gn, respectively, and the number of the plurality of scan lines. Respectively GL0, GL1, GL2...GLn, where n is a positive integer, wherein the plurality of gate contacts G(8k+2), G(8k+3), G(8k+4), and G(8k+5) And forming the corresponding cross-electrical connection with the plurality of scan lines GL(8k+4), GL(8k+5), GL(8k+2), and GL(8k+3), respectively, k being an integer.
  • four of the eight sets of gate contact portions G0, G1, G2, ... G7 are cross-connected together with the gate lines of the gate driver 100 and the different numbers inside the display panel, such as shown in FIG. 2A.
  • a plurality of gate contact portions G(8k), G(8k+1), G(8k+6), and G(8k+7) and the plurality of scan lines GL(8k), GL(8k+1), GL, respectively (8k+6) and GL(8k+7) form the corresponding direct electrical connection.
  • the other four of the set of eight gate contact portions G0, G1, G2, ... G7 are directly connected together in the gate driver 100 and the same numbered scan lines inside the display panel.
  • the G gate driver 100 when the display panel is in normal operation, the G gate driver 100 is sequentially turned on in the order of G1, G2, G3, . . . Gn (for example, a 10 ⁇ s pulse width corresponds to a data signal to charge the pulse width of the primary pixel). ), but the data line is switched once every 4 sub-pixels charged (ie, 4 charge pulse widths).
  • G1, G2, G3, . . . Gn for example, a 10 ⁇ s pulse width corresponds to a data signal to charge the pulse width of the primary pixel.
  • the data line DL2 is taken as an example, the gate contact portion
  • the frequency of data line polarity switching is reduced by 1/2.
  • a high-definition (HD) resolution (1366 ⁇ 768) display panel is taken as an example, 60 Hz.
  • the operating frequency only need to switch 384 (equal to 1 / (60 * 768 * 2)) sub-polarity, because the power consumption of the data line is proportional to the square of the frequency, therefore, after the data line signal frequency is reduced, the entire display panel Power consumption will Significant decline, in line with the current green environmental needs.
  • the data line driving polar array substrate with low switching frequency of the patent application redesigns the driving mode of the liquid crystal panel of the DLS architecture, and on the basis of realizing the dot inversion, the frequency of the data online signal is significantly reduced and the frequency is reduced.
  • the power consumption of the panel can also improve the charging of the pixel.
  • this new wiring design can reduce the frequency of positive and negative polarity switching of the data line signal to at least 1/2 of the original, for example.
  • the polarity of the signal is switched every 4 sub-pixels, and the corresponding data line power consumption is also significantly reduced.

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Abstract

一种具有低切换频率的数据线驱动极性的阵列基板，通过两个次像素（104B、104G、104R）分别具有不同驱动极性的第一极性以及第二极性，其中一部分栅极接触部（G0~G13）相对应直接电性连接一部分扫描线（GL0~GL13），另一部分栅极接触部（G0~G13）相对应交叉电性连接另一部分扫描线（GL0~GL13），使得源极驱动器对连续的若干像素区域中具有第一极性的第一次像素群组充电，并且源极驱动器可切换对连续的若干像素区域中具有第二极性的第二次像素群组充电，其中第一次像素群组以及第二次像素群组的次像素之数量分别大于每一像素区域的次像素数量，使驱动第一次像素群组或是第二次像素群组之频率低于一像素区域对应的两个次像素之频率，以减少整个显示面板的功耗，提高显示面板的显示品质。

Description

具有低切换频率的数据线驱动极性的阵列基板 技术领域
本专利申请涉及一种基板，且特别是涉及一种具有低切换频率的数据线驱动极性的阵列基板，当实现显示面板内部的点反转的条件时，通过降低数据线(Data Line)上信号正、负极性的切换频率，以减少整个显示面板的功耗，符合绿色环保要求，提高显示面板的显示品质。
 背景技术
由于液晶显示器(liquid crystal display, LCD)具有低辐射、体积小及低耗能等优点，因此逐渐取代传统的阴极射线管(cathode ray tube, CRT)显示器，广泛地应用在笔记型计算机、个人数字助理(personal digital assistant, PDA)、平面电视，或行动电话等信息产品上。
现有技术中，在液晶面板生产中降低制作成本是一项非常重要的课题。数据线共享(Data Line Sharing, DLS）架构是一种常用的方法，它是将扫描线（Gate Line）的数量加倍，而数据线（Data Line）的数量减半，从而减少源极(Source)驱动器的数量，达到降低成本的目的。
现有的液晶面板驱动方式中，点反转（Dot Inversion）是显示效果较佳的一种反转方式。采用数据线共享(DLS)架构的显示面板如果使用传统的驱动方式，以高清(HD)的分辨率(1366×768)，60Hz的工作频率，则当显示面板工作时，数据线的信号每两个像素(Pixel)就需要切换一次极性，即大约每21.7μs(等于1/(60*768))需要切换一次极性，对应的数据线信号频率为20kHz数量级左右。这样的缺点一方面是增加了数据在线的功率消耗，另一方面数据线共享(DLS)架构像素(Pixel)的充电时间很短，数据线共享上的信号切换的电阻/电容延迟(RC Delay)也会进一步影响像素的充电情况，不利于显示品质的提高，当显示面板的分辨率提高时，这个问题会更加严重。因此需要发展一种新式的阵列基板，以解决上述问题。
 技术问题
有监于此，本专利申请的目的在于提供一种具有低切换频率的数据线驱动极性的阵列基板，当实现显示面板内部的点反转的条件时，通过降低数据线(Data Line)上信号正、负极性的切换频率，以减少整个显示面板的功耗，符合绿色环保要求，提高显示面板的显示品质。
 技术解决方案
为达到上述发明目的，本专利申请第一实施例中提供一种具有低切换频率的数据线驱动极性的阵列基板，用于液晶面板，其中所述阵列基板包括：一栅极驱动器，设有若干栅极接触部，用以产生若干扫描信号；一源极驱动器，用以产生数据信号；若干扫描线，电性连接所述栅极驱动器的若干栅极接触部，用以相对应接收所述若干扫描信号，所述若干栅极接触部与所述若干扫描线的数量相同并且互相对应；以及若干数据线，电性连接所述源极驱动器，用以相对应接收所述数据信号；其中，所述若干扫描线与所述若干数据线交错形成矩阵方式的行列配置，以形成若干像素区域，每一像素区域包括一条数据线以及两条扫描线，并且每一像素区域是由不同颜色类型的两个次像素所组成，所述两个次像素分别具有不同驱动极性的第一极性以及第二极性，其中一部分栅极接触部相对应直接电性连接一部分扫描线，另一部分栅极接触部相对应交叉电性连接另一部分扫描线，使得在每一数据在线，所述源极驱动器对连续的若干像素区域中具有所述第一极性的第一次像素群组进行充电，并且所述源极驱动器可切换对连续的若干像素区域中具有所述第二极性的第二次像素群组进行充电，其中所述第一次像素群组以及所述第二次像素群组的次像素的数量分别大于每一像素区域的次像素的数量，使驱动所述第一次像素群组或是第二次像素群组的频率低于一像素区域对应的两个次像素的频率。
在一实施例中，在每一次像素的驱动极性与其周围的若干次像素的驱动极性不相同。
在一实施例中，所述第一极性以及所述第二极性分别为正极性以及负极性，或是所述第一极性以及所述第二极性分别为负极性以及正极性。
在一实施例中，所述两种不同颜色类型的次像素是由蓝色次像素、绿色次像素以及红色次像素中任意两种颜色的次像素所组成。
在一实施例中，所述两种不同颜色类型的次像素是由白色次像素、蓝色次像素、绿色次像素以及红色次像素中任意两种颜色的次像素所组成。
在一实施例中，所述栅极驱动器的若干栅极接触部的编号分别为G(0)、G(1)、G(2)…G(n)，所述若干扫描线的编号分别为GL(0)、GL(1)、GL(2)…GL(n)，其中n为正整数，其中所述若干栅极接触部G（8k+2）、G（8k+3）、G（8k+4）及G（8k+5）分别与所述若干扫描线GL(8k+4)、GL(8k+5)、GL(8k+2)及GL(8k+3)形成所述相对应交叉电性连接，k为整数。
在一实施例中，所述若干栅极接触部G（8k）、G（8k+1）、G（8k+6）及G（8k+7）分别与所述若干扫描线GL(8k)、GL(8k+1)、GL(8k+6)及GL(8k+7)形成所述相对应直接电性连接。
 有益效果
提供一种具有低切换频率的数据线驱动极性的阵列基板，当实现显示面板内部的点反转的条件时，通过降低数据线(Data Line)上信号正、负极性的切换频率，以减少整个显示面板的功耗，符合绿色环保要求，提高显示面板的显示品质。
附图说明
图1A:为根据本专利申请第一实施例中具有低切换频率的数据线驱动极性的阵列基板的电路示意图。
图1B:为根据本专利申请第一实施例中阵列基板的扫描线与数据线的驱动时序波形图。
图2A:为根据本专利申请第二实施例中具有低切换频率的数据线驱动极性的阵列基板的电路示意图。
图2B:为根据本专利申请第二实施例中阵列基板的扫描线与数据线的驱动时序波形图。
 本发明的最佳实施方式
本专利申请说明书提供不同的实施例来说明本专利申请不同实施方式的技术特征。实施例中的各组件的配置是为了清楚说明本专利申请揭示的内容，并非用以限制本专利申请。在不同的图式中，相同的组件符号表示相同或相似的组件。
参考图1A及1B，图1A为根据本专利申请第一实施例中具有低切换频率的数据线驱动极性的阵列基板的电路示意图，图1B为根据本专利申请第一实施例中阵列基板的扫描线与与数据线的驱动时序波形图。所述阵列基板为数据线共享的架构，用于液晶面板，所述阵列基板设有栅极驱动器100、源极驱动器102、若干扫描线GL0~GL13、若干数据线DL1~DL5以及若干次像素104B、104G、104R。此处为14条扫描线以及5条数据线，但其数量不限于此，例如是更多条的扫描线以及数据线。
如图1A及1B所示，栅极驱动器100设有若干栅极接触部G0~G13，用以产生若干扫描信号。源极驱动器102用以产生数据信号。若干扫描线GL0~GL13电性连接所述栅极驱动器100的若干栅极接触部G0~G13，用以相对应接收所述若干扫描信号，所述若干栅极接触部G0~G13与所述若干扫描线GL0~GL13的数量相同并且互相对应。若干数据线DL1~DL5电性连接所述源极驱动器102，用以相对应接收所述数据信号。
如图1A及1B所示，所述若干扫描线GL0~GL13与所述若干数据线DL1~DL5交错形成矩阵方式的行列配置，以形成若干像素区域106，每一像素区域106包括一条数据线DL1~DL5以及两条扫描线GL0~GL13，并且每一像素区域106是由不同颜色类型的两个次像素104B、104G、104R所组成，所述两个次像素104B、104G、104R分别具有不同驱动极性的第一极性108P以及第二极性108N，其中一部分栅极接触部G0~G13相对应直接电性连接一部分扫描线GL0~GL13，另一部分栅极接触部G0~G13相对应交叉电性连接另一部分扫描线GL0~GL13，使得在每一数据线DL1~DL5上，所述源极驱动器102对连续的若干像素区域106中具有所述第一极性108P的第一次像素群组例如数据线DL2上与扫描线GL2、GL3、GL6、GL7交错位置的正极性之次像素进行充电，并且所述源极驱动器102可切换对连续的若干像素区域106中具有所述第二极性108N的第二次像素群组例如数据线DL2上与扫描线GL1、GL4、GL5、GL8交错位置的负极性的次像素进行充电，其中所述第一次像素群组以及所述第二次像素群组的次像素的数量分别大于每一像素区域106的次像素104B、104G、104R的数量，使驱动所述第一次像素群组或是第二次像素群组的频率低于一像素区域106对应的两个次像素的频率。
如图1A及1B所示，在一实施例中，在每一次像素104B、104G、104R的驱动极性与其周围的若干次像素104B、104G、104R的驱动极性不相同。在一优选实施例中，每一次像素104B、104G、104R的驱动极性与其周围多个次像素104B、104G、104R的驱动极性相反，以形成数据线共享(Data Line Sharing, DLS)的显示面板架构。所述第一极性以及所述第二极性分别为正极性(+)以及负极性(-)，或是所述第一极性以及所述第二极性分别为负极性(-)以及正极性(+)。在一实施例中，所述两种不同颜色类型的次像素104B、104G、104R是由蓝色次像素104B、绿色次像素104G以及红色次像素104R中任意两种颜色的次像素所组成。
如图1A及1B所示，以高清(HD)的显示面板为例，所述栅极驱动器100的若干栅极接触部的编号分别为G0、G1、G2…Gn，所述若干扫描线的编号分别为GL0、GL1、GL2…GLn，其中n为正整数，其中所述若干栅极接触部G(8k+2)、G(8k+3)、G(8k+4)及G(8k+5)分别与所述若干扫描线GL(8k+4)、GL(8k+5)、GL(8k+2)及GL(8k+3)形成所述相对应交叉电性连接，k为整数。换言之，一组8个栅极接触部G0、G1、G2…G7中的4个在栅极驱动器100和显示面板内部不相同编号的扫描线交叉连接在一起，例如图1A所示。若干栅极接触部G(8k)、G(8k+1)、G(8k+6)及G(8k+7)分别与所述若干扫描线GL(8k)、GL(8k+1)、GL(8k+6)及GL(8k+7)形成所述相对应直接电性连接。换言之，一组8个栅极接触部G0、G1、G2…G7中的另外4个在栅极驱动器100和显示面板内部相同编号的扫描线直接连接在一起。
如图1A及1B所示，在显示面板正常工作时，G栅极驱动器100按照G1、G2、G3…Gn的顺序依次打开(例如是10μs脉波宽度对应一数据信号对一次像素充电脉波宽度)，但是数据线是每给4个次像素充电(即4个充电脉波宽度)之后才会切换一次极性，在图1A所示的电路中，以数据线DL2为例，栅极接触部G(8k)、G(8k+1)、G(8k+2)及G(8k+3)对应的次像素为负极性(-)，而栅极接触部G(8k+4)、G(8k+5)、G(8k+6)及G(8k+7)对应的次像素为正极性(+)，数据线每隔43.4μs之后才会进行一次极性切换，其与现有技术中DLS架构面板相比，数据线极性切换的频率降低了1/2，在一帧(Frame)的时间段内，例如以高清(HD)的分辨率(1366×768)显示面板为例，60Hz的工作频率，只需要切换384(等于1/(60*768*2))次极性，因为数据线的功率消耗和频率的平方成正比，因此，数据线信号频率降低之后，整个显示面板的功率消耗将会显着下降，符合现在绿色环保的需求。
这些次像素104B、104G、104R电性连接这些扫描线GL与数据线DL，每一次像素104B、104G、104R具有一晶体管108、液晶电容(liquid-crystal capacitor, CLC)以及储存电容(storage capacitor, CS)，其中每一晶体管108具有一栅极(gate)G、一源极(source)S以及一汲极(drain)D，而栅极G连接扫描线GL，源极S连接数据线DL，且汲极D共同连接液晶电容(CLC)以及储存电容(CS)，所述液晶电容(CLC)以及储存电容(CS)接地(如图1A所示)或是共同连接至共享线(common line)(未图示)。当扫描线上施加足够大的正电压时，连接所述扫描线上的薄膜晶体管108会被开启(switch on)，使这些液晶电容的像素电极与垂直方向的数据线DL电性导通，而经由垂直数据线送入对应的视频信号，以将这些液晶电容充电至适当的电压水平；换言之，对这些次像素所对应的液晶电容进行充电，以驱动液晶层内的液晶分子，使液晶显示器显示影像；同时，对连接所述数据线的这些储存电容(CS)进行充电，所述储存电容(CS)在于使液晶电容(CLC)两端的电压维持在一定值下，亦即在未进行数据更新之前，液晶电容(CLC)的两端电压藉由储存电容(CS)维持住。
参考图2A及2B，图2A为根据本专利申请第二实施例中具有低切换频率的数据线驱动极性的阵列基板的电路示意图，图2B为根据本专利申请第二实施例中阵列基板的扫描线与数据线的驱动时序波形图。第二实施例之第二实施例中具有低切换频率的数据线驱动极性的阵列基板与第一实施例类似，其差异在于所述两种不同颜色类型的次像素是由白色次像素104W、蓝色次像素104B、绿色次像素104G以及红色次像素104R中任意两种颜色的次像素所组成。
如图2A及2B所示，在一实施例中，在每一次像素104W、104B、104G、104R的驱动极性与其周围的若干次像素104W、104B、104G、104R的驱动极性不相同。在一优选实施例中，每一次像素104W、104B、104G、104R的驱动极性与其周围多个次像素104W、104B、104G、104R的驱动极性相反，以形成数据线共享(Data Line Sharing, DLS)的显示面板架构。所述第一极性以及所述第二极性分别为正极性(+)以及负极性(-)，或是所述第一极性以及所述第二极性分别为负极性(-)以及正极性(+)。在一实施例中，所述两种不同颜色类型的次像素104W、104B、104G、104R是由白色次像素104W、蓝色次像素104B、绿色次像素104G以及红色次像素104R中任意两种颜色的次像素所组成。
如图2A及2B所示，以高清(HD)的显示面板为例，所述栅极驱动器100的若干栅极接触部的编号分别为G0、G1、G2…Gn，所述若干扫描线的编号分别为GL0、GL1、GL2…GLn，其中n为正整数，其中所述若干栅极接触部G(8k+2)、G(8k+3)、G(8k+4)及G(8k+5)分别与所述若干扫描线GL(8k+4)、GL(8k+5)、GL(8k+2)及GL(8k+3)形成所述相对应交叉电性连接，k为整数。换言之，一组8个栅极接触部G0、G1、G2…G7中的4个在栅极驱动器100和显示面板内部不相同编号的扫描线交叉连接在一起，例如图2A所示。若干栅极接触部G(8k)、G(8k+1)、G(8k+6)及G(8k+7)分别与所述若干扫描线GL(8k)、GL(8k+1)、GL(8k+6)及GL(8k+7)形成所述相对应直接电性连接。换言之，一组8个栅极接触部G0、G1、G2…G7中的另外4个在栅极驱动器100和显示面板内部相同编号的扫描线直接连接在一起。
如图2A及2B所示，在显示面板正常工作时，G栅极驱动器100按照G1、G2、G3…Gn的顺序依次打开(例如是10μs脉波宽度对应一数据信号对一次像素充电脉波宽度)，但是数据线是每给4个次像素充电(即4个充电脉波宽度)之后才会切换一次极性，在图2A所示的电路中，以数据线DL2为例，栅极接触部G(8k)、G(8k+1)、G(8k+2)及G(8k+3)对应的次像素为负极性(-)，而栅极接触部G(8k+4)、G(8k+5)、G(8k+6)及G(8k+7)对应的次像素为正极性(+)，数据线每隔43.4μs之后才会进行一次极性切换，其与现有技术中DLS架构面板相比，数据线极性切换的频率降低了1/2，在一帧(Frame)的时间段内，例如以高清(HD)的分辨率(1366×768)显示面板为例，60Hz的工作频率，只需要切换384(等于1/(60*768*2))次极性，因为数据线的功率消耗和频率的平方成正比，因此，数据线信号频率降低之后，整个显示面板的功率消耗将会显着下降，符合现在绿色环保的需求。
本专利申请之具有低切换频率的数据线驱动极性的阵列基板重新设计了DLS架构的液晶面板的驱动方式，在实现点反转的基础上，显着的降低了数据在线信号的频率，降低面板的功耗，另外也可以改善像素的充电情况，其与现有DLS架构面板相比，这种新的布线设计可以使数据线信正负极性切换的频率降低为原来的至少1/2，例如每4个次像素切换一次信号的极性，相应的数据线功率消耗也会显着降低。
虽然本专利申请已用较佳实施例揭露如上，然其并非用以限定本专利申请，本专利申请所属技术领域中具有通常知识者，在不脱离本专利申请的精神和范围内，当可作各种的更动与润饰，因此本专利申请的保护范围当视后附的权利要求范围所界定者为准。

Claims (7)

  1. 一种具有低切换频率的数据线驱动极性的阵列基板，用于液晶面板，其中所述阵列基板包括：
    一栅极驱动器，设有若干栅极接触部，用以产生若干扫描信号；
    一源极驱动器，用以产生数据信号；
    若干扫描线，电性连接所述栅极驱动器的若干栅极接触部，用以相对应接收所述若干扫描信号，所述若干栅极接触部与所述若干扫描线的数量相同并且互相对应；以及
    若干数据线，电性连接所述源极驱动器，用以相对应接收所述数据信号；
    其中，所述若干扫描线与所述若干数据线交错形成矩阵方式的行列配置，以形成若干像素区域，每一像素区域包括一条数据线以及两条扫描线，并且每一像素区域是由不同颜色类型的两个次像素所组成，所述两个次像素分别具有不同驱动极性的第一极性以及第二极性，其中一部分栅极接触部相对应直接电性连接一部分扫描线，另一部分栅极接触部相对应交叉电性连接另一部分扫描线，使得在每一数据在线，所述源极驱动器对连续的若干像素区域中具有所述第一极性的第一次像素群组进行充电，并且所述源极驱动器可切换对连续的若干像素区域中具有所述第二极性的第二次像素群组进行充电，其中所述第一次像素群组以及所述第二次像素群组的次像素的数量分别大于每一像素区域的次像素的数量，使驱动所述第一次像素群组或是第二次像素群组的频率低于一像素区域对应的两个次像素的频率。
  2. 根据权利要求1所述的具有低切换频率的数据线驱动极性的阵列基板，其中在每一次像素的驱动极性与其周围的若干次像素的驱动极性不相同。
  3. 根据权利要求1所述的具有低切换频率的数据线驱动极性的阵列基板，其中所述第一极性以及所述第二极性分别为正极性以及负极性，或是所述第一极性以及所述第二极性分别为负极性以及正极性。
  4. 根据权利要求1所述的具有低切换频率的数据线驱动极性的阵列基板，其中所述两种不同颜色类型的次像素是由蓝色次像素、绿色次像素以及红色次像素中任意两种颜色的次像素所组成。
  5. 根据权利要求1所述的具有低切换频率的数据线驱动极性的阵列基板，其中所述两种不同颜色类型的次像素是由白色次像素、蓝色次像素、绿色次像素以及红色次像素中任意两种颜色的次像素所组成。
  6. 根据权利要求1所述的具有低切换频率的数据线驱动极性的阵列基板，其中所述栅极驱动器的若干栅极接触部的编号分别为G(0)、G(1)、G(2)…G(n)，所述若干扫描线的编号分别为GL(0)、GL(1)、GL(2)…GL(n)，其中n为正整数，其中所述若干栅极接触部G（8k+2）、G（8k+3）、G（8k+4）及G（8k+5）分别与所述若干扫描线GL(8k+4)、GL(8k+5)、GL(8k+2)及GL(8k+3)形成所述相对应交叉电性连接，k为整数。
  7. 根据权利要求6所述的具有低切换频率的数据线驱动极性的阵列基板，其中所述若干栅极接触部G（8k）、G（8k+1）、G（8k+6）及G（8k+7）分别与所述若干扫描线GL(8k)、GL(8k+1)、GL(8k+6)及GL(8k+7)形成所述相对应直接电性连接。
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