WO2017084565A1 - 存储数据访问方法及相关的控制器、设备、主机和系统 - Google Patents

存储数据访问方法及相关的控制器、设备、主机和系统 Download PDF

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Publication number
WO2017084565A1
WO2017084565A1 PCT/CN2016/106000 CN2016106000W WO2017084565A1 WO 2017084565 A1 WO2017084565 A1 WO 2017084565A1 CN 2016106000 W CN2016106000 W CN 2016106000W WO 2017084565 A1 WO2017084565 A1 WO 2017084565A1
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Prior art keywords
logical address
address
data
storage controller
host
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PCT/CN2016/106000
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English (en)
French (fr)
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周杰
刘光辉
张伟业
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华为技术有限公司
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Priority to EP16865742.7A priority Critical patent/EP3370155B1/en
Priority to KR1020187017018A priority patent/KR102104288B1/ko
Publication of WO2017084565A1 publication Critical patent/WO2017084565A1/zh
Priority to US15/983,592 priority patent/US10783086B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Definitions

  • Embodiments of the present invention relate to the field of data storage and, more particularly, to a method, a storage controller, a host, a storage device, and a storage system for accessing data stored in a storage device.
  • the smart terminal device includes a built-in storage device for storing data.
  • a smart phone generally uses an embedded multimedia card (eMMC) chip as a built-in memory chip.
  • the eMMC chip is packaged by the eMMC memory controller and the Nand flash memory chip, and integrates a central processing unit (CPU), a read only memory (ROM), and a random access memory (Random) in the eMMC memory controller. Access Memory, RAM).
  • eMMC embedded multimedia card
  • Firmware of the built-in storage device mainly solves the problem of bad blocks and read interference inherent in Flash particles to improve the reliability of the use of Flash particles, and at the same time, it can bring different manufacturers and processes to the host (such as the CPU in the smartphone).
  • the storage device's firmware usually manages Flash particles using the Flash Translation Layer (FTL) algorithm. After the FTL algorithm maps, the storage device presents a logical address to the host. When the host accesses the storage device, the actual physical address cannot be seen.
  • FTL Flash Translation Layer
  • the existing storage device has a small area, a correspondingly small resource, a weak computing power of the CPU, and a low processing performance of the storage device. Therefore, the host has a lower access speed to the storage device.
  • the embodiments of the present invention provide a method, a storage controller, a host, a storage device, and a system for accessing data stored in a storage device, which are used to improve the access speed of the host to the storage device.
  • an embodiment of the present invention discloses a method for accessing data stored in a storage device, which is executed by a storage controller located in a storage device, where the storage device further includes storage control At least one flash granule of communication, including:
  • the identifier information is the first identifier information or the second identifier information; the first address is located by the software located in the host.
  • the logical address processing module sends, after the logical address processing module receives the first logical address sent by the logical address sending module of the software upper layer located in the host, determines whether the first logical address belongs to the logical address corresponding to the operating system data or belongs to the user.
  • the logical address corresponding to the data when it is determined that the first logical address belongs to the logical address corresponding to the operating system data, the first logical address is sent to the storage controller, and the first identification information is sent to the storage controller, and the first address is
  • the first logical address belongs to the logical address corresponding to the user data
  • the first logical address is converted into the second physical address, and then sent to the storage controller, and sent to the storage controller for the second identifier.
  • Information, at this time, the first address is the second physical address;
  • the identification information is the first identification information
  • converting the first address to the first physical address and accessing the flash memory particles according to the first physical address
  • the flash memory particles are accessed according to the received first address.
  • an embodiment of the present invention discloses a method for data storage, which is executed by a logical address processing module of a software underlying layer in a host, including:
  • the logical address is sent to the storage controller, and the first identifier information is sent to the storage controller, where the first identifier information is configured to enable the storage controller to receive the first After identifying the information, converting the first logical address to the first physical address and accessing information of the data in the flash granule according to the first physical address;
  • the first logical address is converted into the second physical address, and then sent to the storage controller, and sent to the storage controller to send the second identifier information, where the second The identification information is information that enables the storage controller to access data in the flash granules using the second physical address based on the received second identification information.
  • an embodiment of the present invention discloses a storage controller, which is located in a storage device, where the storage device further includes at least one flash memory component that communicates with the storage controller, and the storage controller includes: receiving Unit, judgment unit, conversion unit, and access unit, where:
  • the receiving unit is configured to receive, by the host, a first address for accessing the flash granule and the identifier information for indicating the address type of the first address, where the identifier information is the first identifier information or the second identifier information; the first address is located at the host
  • the logical address processing module of the software underlying is sent, wherein the logical address processing module receives the first logical address sent by the logical address sending module of the upper layer of the software in the host, and determines that the first logical address belongs to the logic corresponding to the operating system data.
  • the address still belongs to the logical address corresponding to the user data; when it is determined that the first logical address belongs to the logical address corresponding to the operating system data, the first logical address is sent to the storage controller, and the first identification information is sent to the storage controller.
  • the first address is the first logical address; when it is determined that the first logical address belongs to the logical address corresponding to the user data, the first logical address is converted into the second physical address, and then sent to the storage controller, and sent to the storage controller.
  • the first address is the second physical address;
  • the determining unit is configured to determine whether the received identification information is the first identification information or the second identification information
  • the converting unit is configured to convert the first address received by the receiving unit into a first physical address
  • the access unit is configured to access the flash memory particle according to the first physical address converted by the converting unit.
  • the access unit is configured to access the flash memory particles according to the first address received by the receiving unit.
  • an embodiment of the present invention discloses a host, including a processor and a memory, where the memory stores instructions for being executed by the processor, and the processor executes the software program by reading the instruction, where the software program includes a logical address located at an upper layer of the software.
  • the sending module and the logical address processing module located at the bottom of the software wherein:
  • the logical address sending module is configured to send the first logical address to the logical address processing module
  • the logical address processing module is configured to receive the first logical address sent by the logical address sending module
  • the logical address processing module is further configured to determine whether the logical address belongs to a logical address corresponding to the operating system data or a logical address corresponding to the user data;
  • the logical address processing module is further configured to: when determining that the logical address belongs to a logical address corresponding to the operating system data, send the logical address to the storage controller, and send the first identifier information to the storage controller, where the first identifier information is After the storage controller receives the first identification information, it will be the first Converting the logical address to the first physical address and accessing information of the data in the flash granule according to the first physical address;
  • the logical address processing module is further configured to: when determining that the logical address belongs to the logical address corresponding to the user data, convert the first logical address into the second physical address, send the information to the storage controller, and send the second logical address to the storage controller to send the second Identification information, wherein the second identification information is information capable of causing the storage controller to access data in the flash memory using the second physical address according to the received second identification information.
  • an embodiment of the present invention discloses a storage device, including the storage controller mentioned in the third aspect and at least one flash memory particle.
  • an embodiment of the present invention discloses a communication system, including the storage device mentioned in the fifth aspect and the host mentioned in the fourth aspect.
  • the storage controller in the storage device can determine the type of the accessed address according to the identification information. If it is a logical address, the storage controller maps the logical address to a physical address and accesses it; if it is a physical address, directly accesses the physical address sent by the host. The physical address is obtained by the host converting the logical address from the upper layer of the software according to the preset address area information. Thus, if it is a physical address, the conversion process is performed by the host, and the storage controller of the storage device does not need to be converted again. Since the processing power of the host is higher than that of the storage controller, the speed at which the host accesses the storage device can be improved.
  • the operational data is data of the operating system software itself and some data generated by the operating system during operation;
  • the user data is the data written by the user to the storage device after the operating system is installed.
  • the address in the received access request is regarded as a logical address and converted into a third physical address according to the third physical address.
  • Access flash granules This is compatible with scenarios based on existing bootloader applications, because the bootloader is usually a hardened program and accessed using logical addresses, which are not received by the storage controller after the bootloader's access request.
  • the information is identified so that the logical address in the access request is converted to a physical address so that the flash granules can be accurately accessed.
  • FIG. 1 is a schematic structural view of an eMMC chip in the prior art
  • FIG. 2 is a schematic flow chart of a first embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a storage device according to Embodiment 4 of the present invention.
  • FIG. 4 is a schematic structural diagram of a host according to Embodiment 5 of the present invention.
  • 1 is a schematic block diagram of an applicable storage device.
  • the storage device 100 shown in FIG. 1 is an eMMC chip existing in the prior art.
  • the eMMC chip can be used as a built-in memory chip of the smart terminal.
  • the storage device (for example, an eMMC chip) includes an eMMC storage controller 110 and Nand flash memory particles 120 (hereinafter also referred to as flash memory particles).
  • the eMMC storage controller 110 includes a central processing unit (CPU) 111, a random access memory (RAM) 112, a read only memory (ROM) 113, an eMMC interface 114, and Nand. Interface 115.
  • the eMMC interface 114 is used to connect to the host Host, thereby implementing the connection between the storage device 100 and the host. Through the eMMC interface 114, the Host can send the command information specified by the eMMC protocol and the address and data corresponding to the command information.
  • the host Host in the embodiment of the present invention may be a processor in the terminal device, such as a CPU in a smart phone or the like.
  • the Nand interface 115 can be used to connect the eMMC storage controller 110 with the Nand flash granules 120.
  • the Nand flash granules 120 can have one or more, only one of which is identified for convenience of illustration.
  • the eMMC storage controller 110 can send command information to the Nand flash granule 120 through the Nand interface 115 to complete the access operation.
  • the access operation may be a read operation, a write operation, or an erase operation on the data of the Nand flash memory particle 120.
  • the eMMC memory controller 110 can manage the Nand flash memory particles 120 by an FTL algorithm. Through the mapping of the FTL algorithm, the storage device 100 presents logical addresses to the host. That is to say, the prior art does not see the actual physical address when the host is accessing.
  • GC Garbage Collection
  • WL Wear Leveling
  • SD Secure Digital
  • the first embodiment of the present invention provides a method for accessing data of a storage device, including the following steps:
  • the underlying logical address processing module of the software located in the host receives the logical address sent by the logical address sending module of the upper layer of the software located in the host;
  • the host can generally include the following parts at the software level: the top layer is the application, followed by the file system and the kernel.
  • the underlying software layer refers to the "kernel" layer.
  • the logical address processing module in this step can be located in the kernel, that is, at the host level, and the code of the kernel layer needs to be modified compared to the prior art.
  • the upper layer of the software generally refers to the two layers of "application” and "file system”, that is, the logical address sending module may refer to a software module located in an application or a file system for transmitting a logical address.
  • a relatively complete operating system will include a file system for organizing files in the management system.
  • the logical address processing module at this time, the software module for transmitting the logical address in the file system can be regarded as a "logical address sending module". If there is no file system, you can also apply the direct send logical address to the logical address processing module.
  • the module used to send the logical address in the application is called the “logical address sending module”.
  • the ultimate purpose of the upper layer of software to send logical addresses is to access the storage device.
  • some basic operation information such as operation type (such as read and write), operand, length, and some protocol definition information such as check digit, start bit, and end bit are required.
  • the logical address processing module determines that the received logical address belongs to the operating system data. The address is still the address corresponding to the user data;
  • the host needs to manage the physical address space and the logical address space of the storage device, that is, the host needs to know which physical address spaces the storage device has and need to perform mapping between the physical address and the logical address.
  • the host also needs to divide the physical address space of the storage device, one part is used to store operating system data, and the other part is to store user data.
  • the operation data includes the data of the operating system software itself and some data generated by the operating system during the running process (eg, a log file, a file system related file); the user data refers to the user writes after the operating system is installed.
  • the data to the storage device typically some application software installed by the user, and the data generated during the running of the application software.
  • the management storage device address space (including the logical address and the physical address) is all completed by the storage controller.
  • the host is also provided with the function of the part, and the host and the storage controller are respectively Complete a part of the address translation function.
  • the method for the host to complete this part of the function is similar to the method for the storage controller to complete the part of the function in the prior art.
  • the storage device includes a 16G physical address space, and the host and the storage controller communicate based on the eMMC protocol, which mainly includes the following steps. :
  • S301 The host sends a command (such as a CMD 6 command) to the storage controller to configure related registers, and the range of the defined logical address space is 0-2G (corresponding to operating system data);
  • a command such as a CMD 6 command
  • the storage controller maps a part of the physical address to the 0-2G logical address according to the register (since part of the management information is required, the part of the physical address is greater than 2G, such as 2.5G);
  • the storage controller configures a range of available physical address spaces (eg, 13.5G, corresponding to user data) to another related register.
  • the host reads another related register (such as read by a CMD 8 command) to know how many physical addresses are available, and maps the physical addresses to the logical addresses.
  • another related register such as read by a CMD 8 command
  • the storage controller completes the mapping between the logical address and the physical, and the host does not participate; that is, the host can only know the logical address of 0-2G, but I don't know which physical addresses 0-2G logical addresses are mapped to;
  • the host is finished
  • the mapping between the logical address and the physical address does not involve the storage controller; that is, the host knows which logical addresses are mapped to which physical addresses, but the storage controller does not know.
  • the logical address is sent to the storage controller, and the first identifier information is sent to the storage controller.
  • This step can be easily understood as “transparently transmitting" the logical address to the memory controller, that is, the logical address processing module "does not process the logical address” and directly passes it to the memory controller.
  • the "do not process the logical address” here is a relative (compared to the step of converting the logical address into a physical address involved in S14), and the concept of colloquialism, in practice, strictly speaking, due to the specific
  • the interface protocol needs to call the command in the corresponding protocol to deliver the "logical address", and does not forward it without any processing.
  • this process belongs to a process of standardizing operations based on the protocol, it does not involve the true transmission. The data is changed, so usually this process is considered to be a process of "transparent" without changing the data.
  • command may be information used by two parties for communication, and may not be called a command in some protocols, but is a term called “message” or “message”.
  • messages may be information used by two parties for communication, and may not be called a command in some protocols, but is a term called “message” or “message”.
  • the “first” in the “first identification information” in this step is only used to distinguish it from other identification information, and does not represent a special meaning.
  • other “first” appearing in this embodiment such as The first physical address
  • the second such as the second physical address
  • the two processes of sending the logical address and sending the first identification information are not strictly performed in sequential order, and one of the first transmissions, the other may be sent later, or one of the two may be simultaneously passed.
  • the protocol defines a message or a command or a message to be sent.
  • the logical address is converted into the second physical address, and then sent to the storage controller, and the second identifier information is sent to the storage controller.
  • This step is a branch parallel to S13.
  • it When it is judged that it belongs to the address corresponding to the user data, it cannot be "transparently transmitted” like S13, but the logical address is converted into the second physical address and then sent to the storage controller ( Of course, it will also involve some of the specific protocols introduced in step 13. Standardized command encapsulation, transmission, etc.).
  • the execution order of the step of transmitting the second physical address and transmitting the second identification information is not limited.
  • the storage controller converts the received logical address into the first physical address and accesses information of the data in the flash granule according to the first physical address; when the storage controller receives the second identification information, And accessing information of the data in the flash granules using the received second physical address.
  • the storage controller receives the information sent by the logical address processing module from the host through a standard protocol interface (such as the eMMC protocol).
  • a standard protocol interface such as the eMMC protocol.
  • the address cannot be known based only on the received "address”. Indicates whether "logical address” or "physical address” after conversion, and how to handle logical address or physical address. Therefore, a message is needed to tell the storage controller how to process.
  • This information is the first identification information and the second identification information.
  • the storage controller determines the identification information received to adopt the corresponding processing strategy, that is, receives the corresponding processing policy. After the first identification information, the address conversion is performed, and the data in the flash granule is accessed according to the converted first physical address; after the second identification information is received, the data in the flash granule is directly accessed according to the received second physical address.
  • the identification information (including the first identification information and the second identification information) may be implemented based on an existing protocol or using a proprietary protocol. Generally, for convenience of implementation, it may be extended based on an existing protocol, for example, based on some reserved fields of the protocol, or using a reserved command or the like.
  • the host and the storage controller use the eMMC protocol for communication, and the command reserved by the eMMC grave can be used to implement the delivery of the identification information.
  • the communication parties perform based on the command (Command, CMD), wherein the CMD 60-63 is a reserved command, and therefore, these commands can be used to deliver the identification information.
  • the logical address processing module when the logical address processing module needs to send a logical address, it may first send a CMD 60 command, and carry the parameter 0x754C4241, indicating that the first identification information is sent; similarly, in step 504, the logical address processing module needs to send the first When the physical address is two, a CMD 60 command may be sent first, and the CMD 60 carries the parameter 0x7550504E, indicating that the second identification information is sent.
  • These commands for passing identification information can be used before each access request. Sending can also be sent when the first type of request is accessed for the first time, and subsequent visits use the previous result. For example, a first identification information is sent through the CMD 60, and if the CMD 60 command is not sent, the access command is sent directly. By default, these subsequent access commands are the first identification information unless the CMD 60 command is sent again to indicate The second identification information is sent, so that the subsequent access command is changed to the second identification information by default.
  • the storage controller When the storage controller receives these commands, it knows how to process the "address" in the received command (such as directly depending on the address or address translation).
  • the transmission of the indication identifier is not necessarily strictly limited to the execution of the logical address, and various commands (or messages, or messages) are used according to different protocols. Different definitions can also be performed after sending a logical address, or at the same time (such as encapsulation to a command, or encapsulation into a message).
  • S12 at the code level, it may be judged only once, that is, whether the received logical address belongs to the range A, and if it belongs to the range A, an operation is performed, otherwise another operation is performed; literally, It does not seem to be exactly the same as S12, but combined with other conditions (for example, only define two addresses, define the A range as the logical address corresponding to the operating system data, then the rest is naturally the logical address corresponding to the user data), It can be found that the logical level is the same as the S12.
  • a part of the logical address to physical address conversion function implemented by the original storage controller is moved to the host, and the processing capability of the host is generally higher than that of the storage controller, thereby improving the host accessing the storage device. speed.
  • the host since the host implements the mapping management of the physical address and logical address of the flash memory, the host can directly manage the physical address of the flash granule and the running process of various algorithms (such as an address mapping algorithm), and can be based on the host itself.
  • the running state at the right time to initiate garbage collection and wear leveling operations, improve the management of storage devices, reduce the impact of Nand bad blocks and data fragmentation on storage performance. Moreover, when a fault occurs, the fault can be located more clearly.
  • the foregoing embodiment is described by using two specific examples.
  • the host and the storage controller are based on the eMMC protocol, and the total physical space of the flash memory particles is assumed to be 10000 Byte (only for For example, the actual physical space will be much larger than this number, where the first 2000 is used for operating system data (including management information), and the remaining 8000 physical space is allocated to user data; meanwhile, on the host (kernel) side, 2000 is The physical space is mapped to the logical address space 100-2099; on the storage controller side, the 8000 physical space is mapped to the logical address space 2100-10099; as shown in Table 1:
  • the application sends a first request for accessing the file to the file system.
  • the file system converts the first request into a second request that is accessed by using a logical address, and the logical address to be accessed carried in the second request is a logical address between 2201-2300, and sends the second request to the kernel. ;
  • the kernel determines that the logical address between 2201-2300 belongs to the address corresponding to the user data, converts the logical address 2201-2300 into the physical address 2101-2200, and encapsulates the second request according to the eMMC protocol requirement, and then sends the second request to the storage controller. And sending an identification information indicating that the type is a physical address (that is, indicating that the subsequent memory does not need to be converted again);
  • the storage controller After receiving the access request based on the physical address 2101-2200, the storage controller directly accesses the physical address 2101-2200 of the flash granule.
  • the application sends a first request for accessing the file to the file system.
  • the file system converts the first request into a second request accessed by using a logical address, and the logical address to be accessed carried in the second request is a logical address between 100-199, and sends the second request to the kernel. ;
  • the kernel determines that the logical address between 100-199 belongs to an address corresponding to the operating system data, and after the encapsulation according to the eMMC protocol, the third request including the logical address 100-199 is "transparently transmitted" to the storage controller, and sends an identifier.
  • Information indicating that the type is a logical address (that is, indicating subsequent memory conversion);
  • the memory storage controller After receiving the third request, the memory storage controller converts the logical address 100-199 to the physical address 0-99, and accesses the flash granule through the physical address 0-99.
  • the embodiment discloses a communication device (such as a mobile device, a tablet, and the like) that uses a boot loader, and a method for the communication device to access the storage device.
  • the communication device in this embodiment includes a host and a storage device in the foregoing embodiment, and the host and the storage device communicate through a protocol such as eMMC.
  • the host mainly includes a CPU.
  • CPU central processing unit
  • peripheral circuits such as power management related circuits, interface circuits for communicating with peripheral devices, etc.
  • the communication device in this embodiment uses a boot loader (usually represented by an English boot loader or a bootloader) during use, which is a program for booting the operating system.
  • This program is a solidified program that is adapted to the CPU and is generally provided by the CPU manufacturer. Other manufacturers using the CPU will not modify the program.
  • the existing boot loader uses the logical address to access the operating system data stored in the storage granule.
  • the storage controller can still convert the logical address to the physical address to the operating system data, The existing boot loader still works and is compatible.
  • the storage controller can be processed by the logical address by default after the power is turned on. That is, after the storage controller is powered on, if the identification information is not received, the default received address is a logical address, and then The logical address is converted and converted to a physical address to access the flash granules.
  • the specific implementation method may be different according to the manner of transmitting the identification information.
  • the identification information is carried by a predefined field of a message, then by reading the field, it is known whether there is identification information; if the identification information is transmitted The way is based on a single command (as passed in CMD 60 as exemplified above), then if you do not receive this command, you can think that you have not received the identification information.
  • the embodiment of the present invention discloses a storage controller, which is located in a storage device, and the storage device further includes at least one flash memory particle that communicates with the storage controller.
  • the storage controller includes a receiving unit 41 and determines The unit 42, the conversion unit 43, and the access unit 44; these units are used to perform the various steps in the first embodiment, specifically:
  • the receiving unit is configured to receive, by the host, a first address for accessing the flash granule and the identifier information for indicating the address type of the first address, where the identifier information is the first identifier information or the second identifier information; the first address is located at the host
  • the logical address processing module of the software underlying is sent, wherein the logical address processing module receives the first logical address sent by the logical address sending module of the upper layer of the software in the host, and determines that the first logical address belongs to the logic corresponding to the operating system data.
  • the address still belongs to the logical address corresponding to the user data; when it is determined that the first logical address belongs to the logical address corresponding to the operating system data, the first logical address is sent to the storage controller, and the first identification information is sent to the storage controller.
  • the first address is the first logical address; when it is determined that the first logical address belongs to the logical address corresponding to the user data, the first logical address is converted into the second physical address, and then sent to the storage controller, and sent to the storage controller.
  • the first address is the second physical address;
  • the determining unit is configured to determine whether the received identification information is the first identification information or the second identification information
  • the converting unit is configured to convert the first address received by the receiving unit into a first physical address
  • the access unit is configured to access the flash memory particle according to the first physical address converted by the converting unit.
  • the access unit is configured to access the flash memory particles according to the first address received by the receiving unit.
  • each of the above units is a logical division.
  • the hardware stored in the memory RAM+ROM
  • a processor such as a CPU
  • an embodiment of the present invention discloses a host 50.
  • the host in the embodiment of the present invention includes a processor (such as a CPU) 51 and a memory (such as a ROM may be included). And a RAM), wherein the memory stores instructions for execution by the processor, and the processor executes the related steps in the related embodiments (such as Embodiments 1 and 2) by reading instructions in the memory, implementing and storing Communication between devices.

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Abstract

一种用于访问存储在存储设备中数据的方法、存储控制器、主机、存储设备和系统，该方法包括：接收第一地址以及指示地址类型的标识信息；当标识信息指示为逻辑地址类型时，将第一地址转换为第一物理地址，访问存储设备中对应的至少一个闪存颗粒；当标识信息指示为物理地址类型时，直接访问存储设备中对应的至少一个闪存颗粒。在访问存储设备时，根据标识信息判断访问的地址类型。若为逻辑地址，存储控制器将逻辑地址映射为物理地址并进行访问；若为物理地址，直接访问主机发送的物理地址。这样，存储设备的存储控制器不需要进行额外的操作，提高主机访问存储设备的速度。

Description

存储数据访问方法及相关的控制器、设备、主机和系统
本申请要求于2015年11月19日提交中国专利局、申请号为201510800479.1、发明名称为“存储数据访问方法及相关的控制器、设备、主机和系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及数据存储领域，并且更具体地，涉及用于访问存储在存储设备中数据的方法、存储控制器、主机、存储设备和存储系统。
背景技术
智能终端设备包括内置存储设备用来存储数据。例如，智能手机一般采用内嵌式多媒体存储卡(Embedded Multi-Media Card，eMMC)芯片作为内置存储芯片。eMMC芯片由eMMC存储控制器和Nand闪存颗粒封装得到，并在eMMC存储控制器中集成中央处理器(Central Processing Unit，CPU)、只读存储器(Read Only Memory，ROM)和随机存取存储器(Random Access Memory，RAM)。
内置的存储设备的固件(Firmware)主要解决Flash颗粒固有的坏块、读干扰等问题来提高Flash颗粒使用的可靠性，同时能够对主机(例如智能手机中的CPU)屏蔽厂商及工艺不同带来的Flash的差异。为此，存储设备的Firmware通常采用闪存转换层(Flash Translation Layer，FTL)算法管理Flash颗粒。经过FTL算法的映射，存储设备对主机(Host)呈现的是逻辑地址，Host在访问存储设备时，看不到实际的物理地址。
但是，现有的存储设备的面积较小，资源相应也较小，CPU的运算能力不强，存储设备的处理性能较低。因此，主机对于存储设备的访问速度较低。
发明内容
本发明实施例提供一种用于访问存储在存储设备中数据的方法、存储控制器、主机、存储设备和系统，用于提升主机对于存储设备的访问速度。
第一方面，本发明实施例公开了一种用于访问存储在存储设备中数据的方法，由位于存储设备中的存储控制器来执行，存储设备还包括与存储控制 器通信的至少一个闪存颗粒，包括：
接收主机发送的用于访问闪存颗粒的第一地址以及用于指示第一地址的地址类型的标识信息，标识信息为第一标识信息或者第二标识信息；第一地址由位于主机中的软件底层的逻辑地址处理模块发送，其中，逻辑地址处理模块接收到位于主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址后，判断第一逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；当判断第一逻辑地址属于操作系统数据对应的逻辑地址时，将第一逻辑地址发送给存储控制器，并向存储控制器发送第一标识信息，此时，第一地址为第一逻辑地址；当判断第一逻辑地址属于用户数据对应的逻辑地址时，将第一逻辑地址转换成第二物理地址后发送给存储控制器，并向存储控制器发送用于第二标识信息，此时，第一地址为第二物理地址；
当判断标识信息为第一标识信息时，将第一地址转换为第一物理地址，并根据第一物理地址访问闪存颗粒；
当判断标识信息为第二标识信息时，根据接收到的第一地址访问闪存颗粒。
第二方面，本发明实施例公开了一种用于数据存储的方法，由位于主机中的软件底层的逻辑地址处理模块来执行，包括：
接收位于主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址；
判断逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；
当判断逻辑地址属于操作系统数据对应的逻辑地址时，将逻辑地址发送给存储控制器，并向存储控制器发送第一标识信息，其中，第一标识信息为能够使得存储控制器收到第一标识信息后将第一逻辑地址转换为第一物理地址并根据第一物理地址访问闪存颗粒中的数据的信息；
当判断逻辑地址属于用户数据对应的逻辑地址时，将第一逻辑地址转换成第二物理地址后发送给存储控制器，并向存储控制器发送用于指示发送第二标识信息，其中，第二标识信息为能够使得存储控制器根据收到的第二标识信息使用第二物理地址访问闪存颗粒中的数据的信息。
第三方面，本发明实施例公开了一种存储控制器，位于存储设备，存储设备还包括与存储控制器通信的至少一个闪存颗粒，存储控制器包括：接收 单元、判断单元、转换单元和访问单元，其中：
接收单元用于接收主机发送的用于访问闪存颗粒的第一地址以及用于指示第一地址的地址类型的标识信息，标识信息为第一标识信息或者第二标识信息；第一地址由位于主机中的软件底层的逻辑地址处理模块发送，其中，逻辑地址处理模块接收到位于主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址后，判断第一逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；当判断第一逻辑地址属于操作系统数据对应的逻辑地址时，将第一逻辑地址发送给存储控制器，并向存储控制器发送第一标识信息，此时，第一地址为第一逻辑地址；当判断第一逻辑地址属于用户数据对应的逻辑地址时，将第一逻辑地址转换成第二物理地址后发送给存储控制器，并向存储控制器发送用于第二标识信息，此时，第一地址为第二物理地址；
判断单元用于判断接收到的标识信息为第一标识信息还是第二标识信息；
当判断单元判断标识信息为第一标识信息时，转换单元用于将接收单元接收到的第一地址转换为第一物理地址，访问单元用于根据转换单元转换得到的第一物理地址访问闪存颗粒；
当判断单元判断标识信息为第二标识信息时，访问单元用于根据接收单元接收到的第一地址访问闪存颗粒。
第四方面，本发明实施例公开了一种主机，包括处理器、存储器，存储器存储有用于被处理器执行的指令，处理器通过读取指令执行软件程序，软件程序包括位于软件上层的逻辑地址发送模块以及位于软件底层的逻辑地址处理模块，其中：
逻辑地址发送模块用于向逻辑地址处理模块发送第一逻辑地址；
逻辑地址处理模块用于接收位于逻辑地址发送模块发送的第一逻辑地址；
逻辑地址处理模块还用于判断逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；
逻辑地址处理模块还用于当判断逻辑地址属于操作系统数据对应的逻辑地址时，将逻辑地址发送给存储控制器，并向存储控制器发送第一标识信息，其中，第一标识信息为能够使得存储控制器收到第一标识信息后将第一 逻辑地址转换为第一物理地址并根据第一物理地址访问闪存颗粒中的数据的信息；
逻辑地址处理模块还用于当判断逻辑地址属于用户数据对应的逻辑地址时，将第一逻辑地址转换成第二物理地址后发送给存储控制器，并向存储控制器发送用于指示发送第二标识信息，其中，第二标识信息为能够使得存储控制器根据收到的第二标识信息使用第二物理地址访问闪存颗粒中的数据的信息。
第五方面，本发明实施例公开了一种存储设备，包括第三方面提到的存储控制器以及至少一个闪存颗粒。
第六方面，本发明实施例公开了一种通信系统，包括第五方面提到的存储设备以及第四方面提到的主机。
在这些方面的实施例中，主机在访问存储设备时，存储设备中的存储控制器可以根据标识信息判断所访问的地址类型。若为逻辑地址，则该存储控制器将逻辑地址映射为物理地址并进行访问；若为物理地址，则直接访问主机发送的物理地址。该物理地址由主机根据预设的地址区域信息将来自软件上层的逻辑地址转换所得。这样，若为物理地址时，该转换过程由主机执行，存储设备的存储控制器不需要进行再次转换。由于主机的处理能力比存储控制器高，从而能够提高主机访问存储设备的速度。
在这些方面的实施例中，操作数据为操作系统软件本身的数据以及操作系统在运行过程中产出的一些数据；
用户数据为安装完操作系统后，由用户写到存储设备中的数据。
同时，这些方面的实施例中，存储控制器在上电后，如果没有收到标识信息，将收到的访问请求中的地址当作逻辑地址并转成第三物理地址后根据第三物理地址访问闪存颗粒。这样可以兼容基于现有的引导加载器应用的场景，这是因为引导加载器通常是固化的程序，且使用逻辑地址来访问，存储控制器在引导加载器的访问请求后，由于不会收到标识信息，因此，将访问请求中的逻辑地址转成物理地址，从而可以准确地访问闪存颗粒。
附图说明
图1是现有技术中eMMC芯片结构示意图；
图2为本发明实施例一流程示意图；
图3为本发明实施例四存储设备结构示意图；
图4为本发明实施例五主机结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
图1是可应用的存储设备的示意框图。
图1所示的存储设备100为现有技术中存在着的一种eMMC芯片。该eMMC芯片可以作为智能终端的内置存储芯片。如图1所示，该存储设备(例如eMMC芯片)包括eMMC存储控制器110和Nand闪存颗粒120(以下也简称闪存颗粒)。其中，eMMC存储控制器110包括中央处理器(Central Processing Unit，CPU)111、随机存取存储器(Random Access Memory，RAM)112、只读存储器(Read Only Memory，ROM)113、eMMC接口114和Nand接口115。
eMMC接口114用于与主机Host连接，从而实现存储设备100和主机的连接。通过eMMC接口114，Host可以发送eMMC协议规定的命令信息以及该命令信息对应的地址和数据。本发明实施例中的主机Host可以为终端设备中的处理器，例如智能手机中的CPU等。
Nand接口115可以用于连接eMMC存储控制器110与Nand闪存颗粒120，Nand闪存颗粒120可以有一个或者多个，为了说明方便图中只标识出了一个。具体地，eMMC存储控制器110可以通过Nand接口115向Nand闪存颗粒120发送命令信息来完成访问操作。该访问操作可以为对Nand闪存颗粒120的数据的读操作，写操作，也可以为擦除操作等。
eMMC存储控制器110可以通过FTL算法管理Nand闪存颗粒120。经过FTL算法的映射，存储设备100对于主机来说呈现的都是逻辑地址。也就是说，现有技术在主机在访问时，看不到实际的物理地址。
另外，在现有的eMMC芯片的固件中，还会提供垃圾回收(Garbage Collection，GC)和磨损均衡(Wear Leveling，WL)等功能，以提高Nand Flash颗粒的可靠性和寿命。然而，这些算法在eMMC芯片的使用过程中是自动运行的，主机感知不到。而且，为了降低功耗，主机在不需要读写存储空间时，会让eMMC芯片进行休眠。在休眠时，上述算法都不会运行。这样， eMMC芯片没有足够的时间进行GC和WL等操作，使用一段时间之后导致芯片的性能下降，用户体验变差。而且，主机对eMMC芯片的内部实现不可见，当出现故障时难以定位。这也是现有eMMC芯片的其他弊端。
此外，其他类似的架构也有基于SD(Secure Digital)卡应用，基于SD卡的应用场景与图1类似，只需要将图1中的eMMC接口换成SD接口，将图1中的eMMC控制器换成SD控制器即可。
实施例一
基于上述现有的硬件结构，参见图2，本发明实施例一提供了一种访问存储设备数据的方法，包括如下步骤：
S11、位于主机中的软件底层的逻辑地址处理模块接收位于主机中的软件上层的逻辑地址发送模块发送的逻辑地址；
主机在软件层面一般可以包括以下几个部分：最上层是应用，依次往下是文件系统以及内核。通常，软件底层是指“内核”层，本步骤中的逻辑地址处理模块可以位于内核，即在主机层面，相比于现有技术，需要修改内核层的代码。相应地，软件上层通常是指“应用”以及“文件系统”这两层，即逻辑地址发送模块可以指位于应用或者文件系统中用于发送逻辑地址的软件模块。一般来说，一个相对完善的操作系统都会包括文件系统，用来组织管理系统中的文件，来自应用层的、用于访问存储设备的请求会先发给文件系统，然后由文件系统再转发给逻辑地址处理模块，此时，文件系统中用于发送逻辑地址的软件模块就可以认为是“逻辑地址发送模块”。如果没有文件系统，也可以应用直接发送逻辑地址给逻辑地址处理模块，则应用中用于发送逻辑地址的模块称为“逻辑地址发送模块”。
同时，可以理解的是，软件上层发送逻辑地址的最终目的是为了访问存储设备，为了达到这个目的，结合不同的访问类型，以及采用的不同的访问协议，实际中，可能还需要增加其他一些额外的信息来达到最终的目的。例如，采用eMMC协议进行访问时，还需要操作类型(如读、写)、操作数、长度等一些基本操作信息以及校验位、起始位、结束位等一些协议定义的信息)。这些都属于本领域技术人员所公知的技术，这里不详细描述，本实施例中，重点针对逻辑地址相关的处理进行详细说明。
S12、逻辑地址处理模块判断收到的逻辑地址属于操作系统数据对应的 地址还是属于用户数据对应的地址；
本实施例中，主机需要管理存储设备的物理地址空间以及逻辑地址空间，即主机要知道存储设备有哪些物理地址空间并且需要进行物理地址与逻辑地址之间的映射。同时，主机还需要对存储设备的物理地址空间进行划分，将其中一部分用于存储操作系统数据，另一部分存储用户数据。其中，操作数据包括操作系统软件本身的数据以及操作系统在运行过程中产出的一些数据(如：日志文件、文件系统相关的文件)；用户数据是指在安装完操作系统后，由用户写到存储设备中的数据，典型的如用户安装的一些应用软件，以及这些应用软件在运行过程中产生的数据。
现有技术中，管理存储设备地址空间(包括逻辑地址以及物理地址)是全部由存储控制器来完成的，本实施例中，相当于让主机也具有这部分的功能，主机和存储控制器各完成一部分地址转换的功能。主机完成这部分功能的方法跟现有技术中存储控制器完成这部分功能的方法类似，以存储设备包括16G物理地址空间、主机与存储控制器基于eMMC协议通信为例，主要包括以下几个步骤：
S301、主机向存储控制器发送命令(如CMD 6命令)来配置相关的寄存器，定义逻辑地址空间的范围是0-2G(对应于操作系统数据)；
S302、存储控制器根据寄存器将一部分物理地址映射到0-2G逻辑地址(由于需要一部分管理信息，这部分物理地址会大于2G，如2.5G)；
S303、存储控制器将剩下可用的物理地址空间(如13.5G，对应于用户数据)的范围配置到另一相关的寄存器；
S304、主机读取另一相关的寄存器(如通过CMD 8命令来读取)来知道多少物理地址可用，并将这些物理地址与逻辑地址进行映射；
其中，这部分的配置的具体实现(如命令的具体格式，寄存器的选择等)都是本领域技术人员所公知的技术，这里不再赘述。同时，本领域技术人员也知道如果基于其他协议时，可以根据其他协议的特性进行适应性修改，来完成类似的功能。
通过上述步骤可以看到，对于逻辑地址为0-2G地址空间，由存储控制器来完成逻辑地址与物理之间的映射，主机并不参与；即主机只能知道0-2G的逻辑地址，但并不了解0-2G逻辑地址映射到了哪些物理地址；
反之，对于剩下部分的物理地址(如剩下的13.5G空间)，由主机来完 成逻辑地址到物理地址之间的映射，存储控制器并不参与；即主机知道这部分哪些逻辑地址被映射到了哪些物理地址，但存储控制器并不知道。
需要说明的是，本实施例中，并不需要对应用、文件系统等软件模块进行修改，因此，能够最大化地兼容现有的系统，便于实现。
S13、当判断逻辑地址属于操作系统数据对应的地址时，将逻辑地址发送给存储控制器，并向存储控制器发送第一标识信息；
这个步骤可简单理解成将逻辑地址“透传”给存储控制器，即逻辑地址处理模块“不对逻辑地址进行处理”，而直接传给了存储控制器。当然，这里的“不对逻辑地址进行处理”是一个相对的(相比S14中涉及的将逻辑地址转成物理地址的步骤)、并且口语化的概念，实际当中，严格来说，由于涉及到具体的接口协议，需要调用对应协议中的命令来传递“逻辑地址”，而并不是不进行任何处理后转发，不过由于这个过程是属于基于协议进行标准化操作的一个过程，并不涉及对真正要传输的数据进行更改，因此，通常这个过程都被认为是没有更改数据，而是“透传”的一个过程。
需要说明的是，上述“命令”可以是一种通信双方用于交互的信息，在有些协议中可能并不叫命令，而是被称为“报文”、“消息”之类的术语。本领域技术人员都了解这些东西本质上都是用于按照某些约定的格式进行信息传递，因此，后续涉及基于某种特定协议进行相互交互的过程(如传递命令或者传递报文，或者传递消息等)在本实施例中就不进行详述。
本步骤中的“第一标识信息”中的“第一”仅用于与其他标识信息进行区分，并不代表特殊的含义，同理，本实施例中出现的其他含“第一”(如第一物理地址)、“第二”(如第二物理地址)也都表示类似的含义。
此外，还需要说明的是，本步骤中，发送逻辑地址以及发送第一标识信息的两个过程并不严格按先后顺序执行，可以其中一个先发，另一个后发，或者也可以同时通过一个协议定义消息或者命令或者报文等形式进行发送。
S14、当判断逻辑地址属于用户数据对应的地址时，将逻辑地址转换成第二物理地址后发送给所述存储控制器，并向存储控制器发送第二标识信息；
本步骤为跟S13并列的一个分支，当判断属于用户数据对应的地址时，就不能像S13那样进行“透传”，而是将逻辑地址转成第二物理地址后再发送给存储控制器(当然，也会涉及到步骤13中介绍的基于具体协议的一些 标准化的命令的封装、发送等操作)。
具体如何转换的方法跟现有技术实现转换的方法类似，本实施例并不对此进行详细描述。
需要说明的是，与S13类似，本步骤中，发送第二物理地址以及发送第二标识信息的步骤的执行顺序也不限定。
S15、存储控制器收到第一标识信息时，将收到的逻辑地址转换为第一物理地址并根据第一物理地址访问闪存颗粒中的数据的信息；存储控制器收到第二标识信息时，使用收到的第二物理地址访问所述闪存颗粒中的数据的信息。
存储控制器通过标准的协议接口(如eMMC协议)接收来自主机的逻辑地址处理模块发送的信息，本实施例中，对于存储控制器，仅根据收到的“地址”，其并不能知道这个地址表示的是“逻辑地址”还是转换后的“物理地址”，也不知道如何对逻辑地址或者物理地址进行处理。因此，需要一个信息去告诉存储控制器如何进行处理，这个信息就是第一标识信息以及第二标识信息，存储控制器通过判断接收到的是哪个标识信息来采取对应的处理策略，即，收到第一标识信息后，进行地址转换，根据转换后的第一物理地址访问闪存颗粒中的数据；收到第二标识信息后，直接根据收到的第二物理地址访问闪存颗粒中的数据。
标识信息(包括第一标识信息以及第二标识信息)可以基于现有的协议或者使用私有协议来实现。通常为了方便实现，可以基于现有的协议，例如，基于协议的一些预留的字段进行扩展，或者使用预留的命令等。
以主机与存储控制器使用eMMC协议进行通信为例，可以利用eMMC坟预留的命令来实现标识信息的传递。在eMMC协议中，通信双方基于命令(Command，CMD)进行，其中，CMD 60-63为预留的命令，因此，可以使用这些命令来传递标识信息。
例如，S13中，逻辑地址处理模块需要发送逻辑地址时，可以首先发送一个CMD 60命令，同时携带参数0x754C4241，表示发送了第一标识信息；类似的，步骤504中，逻辑地址处理模块需要发送第二物理地址时，可以首先发送一个CMD 60命令，该CMD 60携带参数0x7550504E，表示发送了第二标识信息。
这些用于传递标识信息的命令(如CMD 60)可以在每个访问请求前都 发送，也可以在第一次访问不同类型的请求时发送，后续的访问访求使用前一次的结果。例如，刚开始通过CMD 60发了一个第一标识信息，后续如果不发送CMD 60命令，而直接发送访问命令，则默认这些后续访问命令都是第一标识信息，除非再次发送CMD 60命令来表示发送第二标识信息，这样后续的访问命令又默认变成了第二标识信息。
当存储控制器收到这些命令后，就知道接下来如何对收到的命令中的“地址”进行处理(如直接根据地址访问还是进行地址转换)。
需要再次说明的是，如上述S13、S14中最后提到的一样，这个指示标识的发送并不一定严格限定在发送逻辑地址前面执行，根据不同协议对各种命令(或报文、或消息)的不同定义，也可以选择在发送逻辑地址后再执行，或者同时执行(如封装到一个命令，或者封装到一个报文后发送)。
此外，还需要说明的是，上述步骤都是逻辑层面的步骤，在真正实现的代码层面，可能并没有跟步骤一一对应的，从代码字面意义看跟步骤完全符合的代码，但这些代码背后所表示的逻辑含义是符合上述步骤的。例如，对于S12，在代码层面，可以只进行一次判断，即判断收到的逻辑地址是否属于范围A，如果属于这个范围A，执行一种操作，否则执行另一种操作；从字面上看，似乎并不和S12完全一致，但结合其他条件(例如，只定义两种地址，将A范围定义为操作系统数据对应的逻辑地址，那么剩下的自然就是用户数据对应的逻辑地址了)，就能发现在逻辑层面是跟S12一样的。这些在软件层面具体的实现比较灵活，也属于本领域技术人员所公知的技术，本发明各实施例不对此进行详细描述。
本发明实施例中，将原来存储控制器实现的逻辑地址到物理地址转换功能中的一部分移到主机来做，由于主机的处理能力通常都会比存储控制器高，从而能够提高主机访问存储设备的速度。
此外，由于在主机实现了对对闪存颗粒物理地址以及逻辑地址的映射管理，主机能够更直接地管理闪存颗粒的物理地址和各类算法(如地址映射算法)的运行过程，并可以根据主机自身的运行状态，在合适的时机发起垃圾回收和磨损均衡等操作，提高对存储设备的管理，降低Nand坏块和数据碎片化对存储性能的影响。而且，当出现故障时，可以更清楚地对故障进行定位。
实施例二
基于实施例一，本实施例通过两个具体的示例来对上述实施例进行说明，本实施例中，假设主机与存储控制器基于eMMC协议，假设闪存颗粒总的物理空间为10000Byte(仅用于示例，实际物理空间会远大于这个数)，其中前2000用于操作系统数据(包含管理信息)，剩下的8000物理空间分配给用户数据；同时，假设在主机(内核)侧，将2000的物理空间映射到了逻辑地址空间100-2099；在存储控制器侧，将8000物理空间映射到逻辑地址空间2100-10099；具体如表一所示：
表一
位置 逻辑地址空间 物理地址空间
主机(内核) 100-2099 0-1999
存储控制器 2100-10099 2000-9999
示例一：
S21、应用向文件系统发送访问文件的第一请求；
S22、文件系统将第一请求转成通过逻辑地址来进行访问的第二请求，第二请求中携带的要访问的逻辑地址是2201-2300之间的逻辑地址，并将第二请求发送给内核；
S23、内核判断2201-2300之间的逻辑地址属于用户数据对应的地址，将逻辑地址2201-2300转成物理地址2101-2200，并将第二请求重新根据eMMC协议要求封装后发送给存储控制器，并发送一个标识信息，指示类型是物理地址(也即指示后续存储器不需要再进行转换)；
S24、存储控制器收到基于物理地址2101-2200的访问请求后，直接访问闪存颗粒的物理地址2101-2200。
示例二：
S31、应用向文件系统发送访问文件的第一请求；
S32、文件系统将第一请求转成通过逻辑地址来进行访问的第二请求，第二请求中携带的要访问的逻辑地址是100-199之间的逻辑地址，并将第二请求发送给内核；
S33、内核判断100-199之间的逻辑地址属于操作系统数据对应的地址，根据eMMC协议要求封装后将包括逻辑地址100-199的第三请求“透传”给存储控制器，并发送一个标识信息，指示类型是逻辑地址(也即指示后续存储器进行转换)；
S34、内存存储控制器收到第三请求后将逻辑地址100-199转成物理地址0-99，并通过物理地址0-99访问闪存颗粒。
实施例三
基于上述各实施例，本实施例公开了一种使用boot loader的通信设备(如手机、平板等终端设备)以及该通信设备访问存储设备的方法。本实施例中的通信设备包括主机以及前述实施例中的存储设备，主机与存储设备之间通过例如eMMC等协议进行通信。主机主要包括CPU，当然，为了CPU能够更好地运行，还可以包括用于数据存储的内存，同时，还需要一些外围电路(如电源管理相关的电路、与外围设备通信的接口电路等)。
本实施例中的通信设备在使用过程中会用到引导加载器(通常用英文boot loader或者bootloader表示)，这是一个用于引导操作系统的一个程序。这个程序是跟CPU适配的一个固化的程序，一般由CPU厂家提供，使用该CPU的其他厂家不会对该程序进行修改。
同时，现有的引导加载器都使用逻辑地址来访问存储颗粒中存储的操作系统数据，在上述各实施例中，由于存储控制器对操作系统数据仍然可以进行逻辑地址到物理地址的转换，这样，现有的引导加载器仍然能够工作，起到了兼容的作用。
在这过程当中，需要对存储控制器进行一些适配性的工作，具体的：
由于引导加载器本身不具有上述实施例提到的发送上述实施例中提到的标识信息的能力，也就无法让存储控制器知道在收到地址时进行何种处理。此时，可以让存储控制器上电后默认对收到的地址按逻辑地址进行处理，即存储控制器在上电后，如果没有收到标识信息，则默认收到的地址是逻辑地址，然后对逻辑地址进行转换，转成物理地址后访问闪存颗粒。具体实现方法可以根据传递标识信息方式的不同而不同，例如，如果是通过一个消息的一个预定义字段携带标识信息时，那么通过读取这个字段就可知道是否有标识信息；如果传递标识信息的方式是基于一个单独的命令(如在上文举例的通过CMD 60来传递)，那么如果没有收到这个命令，就可认为没有收到标识信息。
实施例四
基于上述各实施例，本发明实施例公开了一种存储控制器，位于存储设备，存储设备还包括与存储控制器通信的至少一个闪存颗粒，参见图3，存储控制器包括接收单元41、判断单元42、转换单元43以及访问单元44；这些单元用于执行实施例一中的各个步骤，具体的：
接收单元用于接收主机发送的用于访问闪存颗粒的第一地址以及用于指示第一地址的地址类型的标识信息，标识信息为第一标识信息或者第二标识信息；第一地址由位于主机中的软件底层的逻辑地址处理模块发送，其中，逻辑地址处理模块接收到位于主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址后，判断第一逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；当判断第一逻辑地址属于操作系统数据对应的逻辑地址时，将第一逻辑地址发送给存储控制器，并向存储控制器发送第一标识信息，此时，第一地址为第一逻辑地址；当判断第一逻辑地址属于用户数据对应的逻辑地址时，将第一逻辑地址转换成第二物理地址后发送给存储控制器，并向存储控制器发送用于第二标识信息，此时，第一地址为第二物理地址；
判断单元用于判断接收到的标识信息为第一标识信息还是第二标识信息；
当判断单元判断标识信息为第一标识信息时，转换单元用于将接收单元接收到的第一地址转换为第一物理地址，访问单元用于根据转换单元转换得到的第一物理地址访问闪存颗粒；
当判断单元判断标识信息为第二标识信息时，访问单元用于根据接收单元接收到的第一地址访问闪存颗粒。
各单元具体执行方法可参见上述各实施例(如实施例一、二、三)中的相关步骤，这里不再赘述。
需要说明的是，上述各单元是逻辑上的划分，在具体硬件结构上，可以基于图1的硬件结构，即通过处理器(如CPU)来读取存储在存储器(RAM+ROM)中的代码执行相应的软件程序。
实施例五
参见图4，基于上述各实施例，本发明实施例公开了一种主机50，本发明实施例中的主机包括处理器(如CPU)51以及存储器(如可以包括ROM 以及RAM)，其中，存储器中存储用于供处理器执行的指令，处理器通过读取存储器中的指令来执行上述各相关实施例(如实施例一、二)中的相关步骤，实现与存储设备之间的通信。
以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种用于访问存储设备中的数据的方法，其特征在于，由位于存储设备中的存储控制器来执行，所述存储设备还包括与所述存储控制器通信的至少一个闪存颗粒，包括：
    接收主机发送的用于访问闪存颗粒的第一地址以及用于指示所述第一地址的地址类型的标识信息，所述标识信息为第一标识信息或者第二标识信息；所述第一地址由位于所述主机中的软件底层的逻辑地址处理模块发送，其中，所述逻辑地址处理模块接收到位于所述主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址后，判断所述第一逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；当判断所述第一逻辑地址属于所述操作系统数据对应的逻辑地址时，将所述第一逻辑地址发送给存储控制器，并向所述存储控制器发送所述第一标识信息，此时，所述第一地址为所述第一逻辑地址；当判断所述第一逻辑地址属于所述用户数据对应的逻辑地址时，将所述第一逻辑地址转换成第二物理地址后发送给所述存储控制器，并向所述存储控制器发送用于所述第二标识信息，此时，所述第一地址为所述第二物理地址；
    当判断所述标识信息为所述第一标识信息时，将所述第一地址转换为第一物理地址，并根据所述第一物理地址访问所述闪存颗粒；
    当判断所述标识信息为所述第二标识信息时，根据接收到的所述第一地址访问所述闪存颗粒。
  2. 根据权利要求1所述的方法，其特征在于：
    所述操作数据为操作系统软件本身的数据以及操作系统在运行过程中产出的一些数据；
    所述用户数据为安装完操作系统后，由用户写到所述存储设备中的数据。
  3. 根据权利要求1或2所述的方法，其特征在于，所述方法还包括：
    上电后，如果没有收到标识信息，将收到的访问请求中的地址当作逻辑地址并转成第三物理地址后根据所述第三物理地址访问闪存颗粒。
  4. 一种用于数据存储的方法，其特征在于，由位于主机中的软件底层的逻辑地址处理模块来执行，包括：
    接收位于所述主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址；
    判断所述逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；
    当判断所述逻辑地址属于所述操作系统数据对应的逻辑地址时，将所述逻辑地址发送给存储控制器，并向所述存储控制器发送第一标识信息，其中，所述第一标识信息为能够使得所述存储控制器收到所述第一标识信息后将所述第一逻辑地址转换为第一物理地址并根据所述第一物理地址访问闪存颗粒中的数据的信息；
    当判断所述逻辑地址属于所述用户数据对应的逻辑地址时，将所述第一逻辑地址转换成第二物理地址后发送给所述存储控制器，并向所述存储控制器发送用于指示发送第二标识信息，其中，所述第二标识信息为能够使得所述存储控制器根据收到的所述第二标识信息使用所述第二物理地址访问所述闪存颗粒中的数据的信息。
  5. 根据权利要求4所述的方法，其特征在于：
    所述操作数据为操作系统软件本身的数据以及操作系统在运行过程中产出的一些数据；
    所述用户数据为安装完操作系统后，由用户写到所述存储设备中的数据。
  6. 一种存储控制器，位于存储设备，所述存储设备还包括与所述存储控制器通信的至少一个闪存颗粒，其特征在于，所述存储控制器包括：接收单元、判断单元、转换单元和访问单元，其中：
    所述接收单元用于接收主机发送的用于访问闪存颗粒的第一地址以及用于指示所述第一地址的地址类型的标识信息，所述标识信息为第一标识信息或者第二标识信息；所述第一地址由位于所述主机中的软件底层的逻辑地址处理模块发送，其中，所述逻辑地址处理模块接收到位于所述主机中的软件上层的逻辑地址发送模块发送的第一逻辑地址后，判断所述第一逻辑地址 属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；当判断所述第一逻辑地址属于所述操作系统数据对应的逻辑地址时，将所述第一逻辑地址发送给存储控制器，并向所述存储控制器发送所述第一标识信息，此时，所述第一地址为所述第一逻辑地址；当判断所述第一逻辑地址属于所述用户数据对应的逻辑地址时，将所述第一逻辑地址转换成第二物理地址后发送给所述存储控制器，并向所述存储控制器发送用于所述第二标识信息，此时，所述第一地址为所述第二物理地址；
    所述判断单元用于判断接收到的标识信息为第一标识信息还是第二标识信息；
    当所述判断单元判断所述标识信息为所述第一标识信息时，所述转换单元用于将所述接收单元接收到的所述第一地址转换为第一物理地址，所述访问单元用于根据所述转换单元转换得到的所述第一物理地址访问所述闪存颗粒；
    当所述判断单元判断所述标识信息为所述第二标识信息时，所述访问单元用于根据所述接收单元接收到的所述第一地址访问所述闪存颗粒。
  7. 根据权利要求6所述的方法，其特征在于：
    所述操作数据为操作系统软件本身的数据以及操作系统在运行过程中产出的一些数据；
    所述用户数据为安装完操作系统后，由用户写到所述存储设备中的数据。
  8. 根据权利要求6或7中任一项所述的方法，其特征在于：
    所述判断单元还用于在上电后判断有没有收到标识信息；
    所述转换单元还用于当所述判断单元判断没有收到标识信息时，将收到的访问请求中的地址当作逻辑地址并转成第三物理地址；
    所述访问单元还用于根据所述转换单元转换得到的所述第三物理地址访问闪存颗粒。
  9. 一种主机，其特征在于：包括处理器、存储器，所述存储器存储有用于被所述处理器执行的指令，所述处理器通过读取所述指令执行软件程 序，所述软件程序包括位于软件上层的逻辑地址发送模块以及位于软件底层的逻辑地址处理模块，其中：
    所述逻辑地址发送模块用于向所述逻辑地址处理模块发送第一逻辑地址；
    所述逻辑地址处理模块用于接收位于所述逻辑地址发送模块发送的所述第一逻辑地址；
    所述逻辑地址处理模块还用于判断所述逻辑地址属于操作系统数据对应的逻辑地址还是属于用户数据对应的逻辑地址；
    所述逻辑地址处理模块还用于当判断所述逻辑地址属于所述操作系统数据对应的逻辑地址时，将所述逻辑地址发送给存储控制器，并向所述存储控制器发送第一标识信息，其中，所述第一标识信息为能够使得所述存储控制器收到所述第一标识信息后将所述第一逻辑地址转换为第一物理地址并根据所述第一物理地址访问闪存颗粒中的数据的信息；
    所述逻辑地址处理模块还用于当判断所述逻辑地址属于所述用户数据对应的逻辑地址时，将所述第一逻辑地址转换成第二物理地址后发送给所述存储控制器，并向所述存储控制器发送用于指示发送第二标识信息，其中，所述第二标识信息为能够使得所述存储控制器根据收到的所述第二标识信息使用所述第二物理地址访问所述闪存颗粒中的数据的信息。
  10. 如权利要求9所述的主机，其特征在于：
    所述操作数据为操作系统软件本身的数据以及操作系统在运行过程中产出的一些数据；
    所述用户数据为安装完操作系统后，由用户写到所述存储设备中的数据。
  11. 一种存储设备，其特征在于，包括如权利要求6-8中任一项所述的存储控制器，包括至少一个闪存颗粒。
  12. 一种存储系统，其特征在于，包括如权利要求11存储设备，如权利要求9-10中任一项所述的主机。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110362509A (zh) * 2018-04-10 2019-10-22 北京忆恒创源科技有限公司 统一地址转换与统一地址空间

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105353989B (zh) * 2015-11-19 2018-12-28 华为技术有限公司 存储数据访问方法及相关的控制器、设备、主机和系统
CN106339182A (zh) * 2016-08-25 2017-01-18 曾美枝 存储器管理方法和装置
US10997066B2 (en) * 2018-02-20 2021-05-04 Samsung Electronics Co., Ltd. Storage devices that support cached physical address verification and methods of operating same
KR20200122685A (ko) * 2019-04-18 2020-10-28 에스케이하이닉스 주식회사 메모리 시스템 내에서 서로 다른 종류의 데이터를 처리하기 위한 장치 및 방법
CN111949557B (zh) * 2019-05-16 2024-01-23 兆易创新科技集团股份有限公司 一种数据读取方法、装置及存储设备
CN111949213B (zh) * 2020-07-28 2022-08-30 新华三半导体技术有限公司 内存颗粒访问控制芯片、内存颗粒的访问控制系统及方法
CN114116526A (zh) * 2020-08-28 2022-03-01 美光科技公司 用于用嵌入式存储器系统进行受管理nand转译的技术
CN113127402B (zh) * 2021-04-29 2024-05-14 广东湾区智能终端工业设计研究院有限公司 一种spi访问控制方法、系统、计算设备及存储介质
CN114124883B (zh) * 2021-10-12 2023-09-12 鸬鹚科技(深圳)有限公司 基于云存储地址的数据访问方法、装置、计算机设备及介质
CN114756488A (zh) * 2022-06-15 2022-07-15 珠海妙存科技有限公司 一种eMMC总线调度方法、系统、装置及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101324867A (zh) * 2007-06-16 2008-12-17 深圳市硅格半导体有限公司 基于半导体存储介质的数据管理装置及管理方法
US20120079171A1 (en) * 2010-09-29 2012-03-29 Samsung Electronics Co., Ltd. Non-volatile memory systems and methods of managing power of the same
CN105005536A (zh) * 2015-07-01 2015-10-28 忆正科技（武汉）有限公司 固态存储设备、主机的工作方法及固态存储设备、主机
CN105353989A (zh) * 2015-11-19 2016-02-24 华为技术有限公司 存储数据访问方法及相关的控制器、设备、主机和系统

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6907600B2 (en) * 2000-12-27 2005-06-14 Intel Corporation Virtual translation lookaside buffer
US8307194B1 (en) * 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7644239B2 (en) * 2004-05-03 2010-01-05 Microsoft Corporation Non-volatile memory cache performance improvement
JP2008510238A (ja) * 2004-08-18 2008-04-03 ジャルナ エスアー オペレーティングシステム
US7490214B2 (en) * 2006-06-12 2009-02-10 Sun Microsystems, Inc. Relocating data from a source page to a target page by marking transaction table entries valid or invalid based on mappings to virtual pages in kernel virtual memory address space
KR100823171B1 (ko) * 2007-02-01 2008-04-18 삼성전자주식회사 파티션된 플래시 변환 계층을 갖는 컴퓨터 시스템 및플래시 변환 계층의 파티션 방법
US20090271562A1 (en) * 2008-04-25 2009-10-29 Sinclair Alan W Method and system for storage address re-mapping for a multi-bank memory device
US8024620B2 (en) * 2008-07-25 2011-09-20 Freescale Semiconductor, Inc. Dynamic address-type selection control in a data processing system
US8327066B2 (en) * 2008-09-30 2012-12-04 Samsung Electronics Co., Ltd. Method of managing a solid state drive, associated systems and implementations
KR20100082185A (ko) * 2009-01-08 2010-07-16 삼성전자주식회사 플래시 메모리, 캐시 메모리, 그리고 제어기를 포함하는 사용자 장치
JP5323030B2 (ja) * 2010-12-01 2013-10-23 株式会社東芝 メモリ装置及びメモリ制御方法
CN102023817A (zh) * 2010-12-03 2011-04-20 深圳市江波龙电子有限公司 一种存储设备数据的读写控制方法及系统
KR20130051564A (ko) * 2011-11-10 2013-05-21 삼성전자주식회사 메모리 모듈, 이를 포함하는 보드 어셈블리, 이를 포함하는 메모리 시스템, 및 상기 메모리 시스템의 동작 방법
KR20140057454A (ko) * 2012-11-02 2014-05-13 삼성전자주식회사 비휘발성 메모리 장치 및 이와 통신하는 호스트 장치
CN103914395B (zh) * 2013-01-06 2017-02-08 北京忆恒创源科技有限公司 用于存储设备的地址映射方法
US9575884B2 (en) * 2013-05-13 2017-02-21 Qualcomm Incorporated System and method for high performance and low cost flash translation layer
CN103946828B (zh) 2013-10-29 2017-02-22 华为技术有限公司 数据处理系统和数据处理的方法
JP6307962B2 (ja) * 2014-03-19 2018-04-11 日本電気株式会社 情報処理システム、情報処理方法、及び、情報処理プログラム
CN104252429B (zh) * 2014-09-03 2017-05-17 英业达科技有限公司 存储控制装置与供其调用其地址的方法
US10331364B2 (en) * 2015-10-16 2019-06-25 Cnex Labs, Inc. Method and apparatus for providing hybrid mode to access SSD drive

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101324867A (zh) * 2007-06-16 2008-12-17 深圳市硅格半导体有限公司 基于半导体存储介质的数据管理装置及管理方法
US20120079171A1 (en) * 2010-09-29 2012-03-29 Samsung Electronics Co., Ltd. Non-volatile memory systems and methods of managing power of the same
CN105005536A (zh) * 2015-07-01 2015-10-28 忆正科技（武汉）有限公司 固态存储设备、主机的工作方法及固态存储设备、主机
CN105353989A (zh) * 2015-11-19 2016-02-24 华为技术有限公司 存储数据访问方法及相关的控制器、设备、主机和系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3370155A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110362509A (zh) * 2018-04-10 2019-10-22 北京忆恒创源科技有限公司 统一地址转换与统一地址空间
CN110362509B (zh) * 2018-04-10 2024-04-12 北京忆恒创源科技股份有限公司 统一地址转换方法与统一地址空间

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