WO2017084067A1 - X-0级联式噪声整形结构的连续时间δ-∑调制器 - Google Patents

X-0级联式噪声整形结构的连续时间δ-∑调制器 Download PDF

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WO2017084067A1
WO2017084067A1 PCT/CN2015/095023 CN2015095023W WO2017084067A1 WO 2017084067 A1 WO2017084067 A1 WO 2017084067A1 CN 2015095023 W CN2015095023 W CN 2015095023W WO 2017084067 A1 WO2017084067 A1 WO 2017084067A1
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digital
analog
digital filter
quantizer
output
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PCT/CN2015/095023
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French (fr)
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朱凯
陈迟晓
易伟
任璞
冯泽民
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上海萌芯电子科技有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing

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  • the invention belongs to the field of integrated circuit technology, and in particular relates to a novel continuous-time delta-sigma modulator of X-0 cascaded noise shaping structure.
  • the ⁇ modulator is a common type of Analog-to-Digital Converter (ADC) and is characterized by high precision.
  • ADC Analog-to-Digital Converter
  • the filter and feedback DAC of continuous-time modulators are mainly implemented in the form of active RC filters and Digital-to-Analog Converters (DACs).
  • DACs Digital-to-Analog Converters
  • a high-order ⁇ modulation loop is often used.
  • the high-order ⁇ modulator implementation is implemented in two ways, one is to directly integrate a high-order loop transfer function, and the other is to be cascaded by a similar “pipelined” analog-to-digital converter.
  • the margin of the stage is quantized by giving it to the second analog to digital converter.
  • MASH Multi-stAge Noise Shaping
  • 1 is a schematic diagram of a discrete time cascaded multi-stage noise integer ⁇ modulator architecture.
  • the loop filter function is H Loop Filte, 1 (z), which implements the noise shaping of the p 1 order;
  • 102 is a ⁇ modulator,
  • the loop filter function is H Loop Filter, 2 (z), which implements p 2 order noise shaping.
  • ⁇ 1 and ⁇ 2 are quantization noises of two noise integers.
  • the analog subtractor 104 can obtain ⁇ 1 .
  • the quantized result of the two-stage noise is multiplied by the transfer function STF 2 or NTF 1 , then the final result Y will only include the high-order quantization integer of the quantization noise of the second-stage modulator. Therefore, the noise shaping effect can be greatly improved, and the oversampling rate is also significantly reduced.
  • FIG. 1 is a schematic diagram of a continuous time ⁇ modulator of a typical X-0MASH structure.
  • the analog circuit portion 201 of the conventional continuous-time delta-sigma modulator is composed of an integrator, a resonant amplifier and a current steering type digital-to-analog converter; a path 212 for loop delay compensation is implemented by a subtractor and digital-to-analog conversion.
  • the composition consists of a back end quantizer 211, a residual generation circuit 204, a residual quantizer 214, and a digital filter implementation 203 of the noise transfer function.
  • the modulator output will only include the quantized noise shaped result of the second stage quantizer. Since ⁇ 2 is the quantization noise of ⁇ 1 , the noise energy of ⁇ 2 is much smaller than the ⁇ 1 energy. At the same oversampling rate, the accuracy of the structure is higher than that of the non-cascaded structure.
  • the present invention proposes a continuous time ⁇ modulator structure of a novel X-0MASH structure that takes into account the accuracy and power consumption of the subtraction circuit.
  • the present invention provides a continuous time delta-sigma modulator of an X-0 cascaded noise shaping structure, comprising:
  • a two-step N-bit analog-to-digital converter providing quantized results of the main loop and the next-order loop of the X-0 cascaded noise shaping structure, wherein the simulation of the two-step N-bit analog-to-digital converter
  • the signal input end is connected to the analog output end of the analog circuit portion;
  • a first digital filter that cancels a quantization noise effect of the first stage loop of the X-0 cascode noise shaping structure, wherein an input of the first digital filter is coupled to the two-step N-bit analog-to-digital converter ;as well as
  • a second digital filter is used to implement loop delay compensation, wherein an input of the second digital filter is coupled to the analog circuit portion.
  • the two-step N-bit analog-to-digital converter comprises a coarse quantizer and a fine quantizer.
  • the input terminals of the coarse quantizer and the thin quantizer are respectively connected to the analog circuit portion, and the digital signal output end of the coarse quantizer is connected to the digital input end of the second digital filter, and the fine A digital signal output of the sub-quantizer is coupled to the digital input of the first digital filter.
  • the two-step N-bit analog-to-digital converter is implemented by a flash-assisted successive comparison analog-to-digital converter, which includes: a rough based on a Flash architecture. a quantizer and a fine quantizer based on a successive comparison architecture,
  • the P-bit precision coarse sub-quantizer is composed of 2 P -1 comparators, and the output of the comparator is encoded and output to the continuous time modulator and the fine quantizer;
  • the fine quantizer obtains the margin by flipping the capacitance, and then compares and further quantizes the Q bits by the comparator.
  • the first digital filter is a digital filter estimated by a noise transfer function of a filter implemented by a digital circuit.
  • the second digital filter is a loop delay compensated digital filter composed of a subtractor implemented by a digital circuit.
  • the output of the first digital filter and the output of the second digital filter are connected to an adder to make the continuous time delta-sigma modulation
  • the output signal of the device structure is a signal obtained by adding digital output signals of both the first digital filter and the second digital filter.
  • the analog input of the analog circuit portion is coupled to the signal input of the modulator.
  • the analog output of the analog circuit portion is further coupled to the digital output of the second digital filter.
  • the main feature of the above-mentioned X-0MASH structure continuous time ⁇ modulator is that it comprehensively considers the implementation of the margin generation and delay compensation path, using a two-part analog-to-digital converter and digitized The compensation of the residual amount, the low-power, energy-efficient realization of the continuous-time ⁇ modulator of the X-0MASH structure.
  • 1 is a schematic diagram of a discrete time cascaded multi-stage noise integer ⁇ modulator architecture.
  • FIG. 2 is a schematic diagram of a continuous time ⁇ modulator of a typical X-0 MASH structure.
  • FIG. 3 is a schematic diagram of a novel X-0MASH architecture applied to a continuous time ⁇ modulator according to the present invention.
  • FIG. 4 is a schematic diagram of a Flash SAR structure for implementing an analog-to-digital converter in the architecture of FIG. 3 according to the present invention.
  • Figure 5 is an embodiment of the operational timing of a two-step N-bit analog to digital converter.
  • a continuous-time ⁇ modulator structure of an X-0MASH structure mainly includes an analog circuit portion 310 of a conventional continuous-time delta-sigma modulator, and a two-step N (
  • N is a natural number) bit analog to digital converter 311, a first digital filter 312 (such as a digital filter for noise transfer function estimation), and a second digital filter 313 (such as a digital filter for loop delay compensation).
  • the analog circuit portion 310 implements a transfer function of the delta-sigma modulation loop. As shown, the analog input of the analog circuit section is connected to the signal input of the modulator.
  • the analog circuit portion 310 can be an analog portion of a conventional continuous time delta sigma modulator as shown in FIG. 2, which can be comprised of an integrator, a resonator circuit, and a feedback digital to analog converter.
  • a two-step N-bit analog-to-digital converter 311 provides quantized results for the main loop and the next-order loop of the X-0 cascaded noise shaping structure.
  • the analog signal input end of the two-step N-bit analog-to-digital converter 311 is connected to the analog output end of the analog circuit portion 310.
  • the first digital filter 312 eliminates the quantization noise effect of the first stage loop of the X-0 cascoded noise shaping structure.
  • the input of the first digital filter 312 is coupled to the two-step N-bit analog-to-digital converter 311.
  • the first digital filter 312 is a digital filter estimated by a noise transfer function of a filter implemented by a digital circuit.
  • the second digital filter 313 is used to implement loop delay compensation.
  • An input of the second digital filter 313 is coupled to the analog circuit portion 310.
  • the second digital filter 313 is a loop delay compensated digital filter composed of a subtractor implemented by a digital circuit.
  • the analog circuit portion 310 The analog output can be further coupled to the digital output of the second digital filter 313.
  • the analog circuit portion 310 of the conventional continuous time delta-sigma modulator, the two-step N-bit analog-to-digital converter 311, and the second digital filter 313 of the loop delay compensation form a delta-sigma modulator.
  • Loop The analog input of the analog circuit portion 310 of the continuous-time delta-sigma modulator is connected to the signal input of the modulator, the analog output is connected to the two-step N-bit analog-to-digital converter 311, and the digital input signal is connected to the loop delay compensation.
  • the output of the first digital filter 312 and the output of the second digital filter 313 are coupled to an adder to cause the continuous time delta-sigma modulator
  • the output signal of the structure is a signal obtained by adding digital output signals of both the first digital filter and the second digital filter.
  • the two-step N-bit analog-to-digital converter 311 can include a coarse sub-quantizer and a thin quantizer.
  • the coarse sub-quantizer and the input of the thin quantizer are connected to the analog circuit portion 310, respectively.
  • the digital signal output of the coarse quantizer is coupled to the digital input of the second digital filter 313, and the digital signal output of the fine quantizer is coupled to the digital input of the first digital filter 312.
  • the two-step N-bit analog-to-digital converter 311 can be implemented with a flash-assisted, successive-precision analog-to-digital converter (Flash-Assisted SAR ADC), as shown in FIG.
  • Flash-Assisted SAR ADC flash-Assisted SAR ADC
  • the continuous-time ⁇ modulator of the X-0MASH structure provided by the present invention can be implemented in many different ways.
  • the preferred embodiment is based on a blinking-assisted successive comparison analog-to-digital converter, only this
  • the invention provides a typical implementation circuit that is only used to illustrate the formation and use of the present invention and is not intended to limit the invention.
  • the blinking-assisted successive comparison analog-to-digital converter may further include a coarse sub-quantizer based on a Flash architecture and a fine quantizer based on a successive comparison architecture.
  • the coarse sub-quantizer and the input of the thin quantizer are connected to the analog circuit portion 310, respectively.
  • the digital signal output of the coarse quantizer is coupled to the digital input of the second digital filter 313, and the digital signal output of the fine quantizer is coupled to the digital input of the first digital filter 312.
  • a coarse sub-quantizer of P e.g., P is a natural number
  • bit precision consists of 2 P -1 comparators whose output is encoded and output to a continuous time modulator and a fine quantizer.
  • the thin quantizer obtains the margin by flipping the capacitance, and then performs a successive comparison and further quantization of Q (e.g., Q is a natural number) by the comparator.
  • the analog circuit portion 310 of the conventional continuous-time delta-sigma modulator is always kept in operation, and the working sequence of the two-step N-bit analog-to-digital converter 311 in this embodiment is as shown in FIG.
  • the timing diagram illustrates the working process as follows:
  • the Least Significant Bit (LSB) comparator 402 performs a successive comparison.
  • ⁇ 2 is the successive comparison trigger edge generated by the asynchronous circuit.
  • the updated clock edge of the analog-to-digital converter in a conventional continuous-time delta-sigma modulator is the edge produced after the delay ⁇ of the sample clock edge.
  • ⁇ is the loop delay when designing the loop.
  • the X-0MASH structure of the conventional continuous-time delta-sigma modulator shown in Fig. 2 is equivalent to the X-0MASH architecture of the novel continuous-time delta-sigma modulator described in the present invention.
  • the architecture proposed by the present invention has a higher digital implementation ratio, and has lower implementation cost and higher efficiency in advanced integrated circuit process implementation.

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Abstract

一种X-0级联式噪声整形结构的连续时间Δ-∑调制器，包括：模拟电路部分（310），该模拟电路部分（310）实现Δ-∑调制环路的传递函数；两步式的N位模数转换器（311），提供该X-0级联式噪声整形结构的主环路与下一级环路的量化结果，其中该两步式的N位模数转换器（311）的模拟信号输入端连接该模拟电路部分（310）的模拟输出端；第一数字滤波器（312），消除该X-0级联式噪声整形结构的第一级环路的量化噪声效应，其中该第一数字滤波器（312）的输入端连接该两步式的N位模数转换器（311）；以及第二数字滤波器（313），用于实现环路延时补偿，其中该第二数字滤波器（313）的输入端连接该模拟电路部分（310）。相对于传统的级联式噪声整形连续时间Δ-∑调制器具有低过采样、低功耗的特点，降低了宽带连续时间Δ-∑调制器对超高速时钟和宽带运放的设计难度，从而大幅提高了连续时间Δ-∑调制器的功耗。

Description

X-0级联式噪声整形结构的连续时间Δ-∑调制器 技术领域
本发明属于集成电路技术领域，具体涉及一种新型的X-0级联式噪声整形结构的连续时间Δ-∑调制器。
背景技术
Δ∑调制器是一种常见的模数转换器(Analog-to-Digital Converter，ADC)类型，特点在于高精度。近年来，Δ∑调制器的研究热点逐渐从传统离散时间、1MHz以下带宽，16位精度以上精度应用转变为连续时间、10MHz以上带宽，12至14位的应用场景。不同于离散时间，连续时间调制器的滤波器和反馈DAC主要以有源RC滤波器和电流舵型数模转换器(Digital-to-Analog Converters，DAC)为方式实现。其主要优势在于连续时间滤波器中使用的放大器的带宽基本和采样率相近上，而离散时间滤波器中的放大器带宽一般要高于采样率数倍，因此连续时间Δ∑调制器的能效更高。
为了更进一步Δ∑调制器提高能效，往往采用高阶的Δ∑调制环路。高阶的Δ∑调制器方式实现方式由两种，其一是直接综合处一个高阶的环路传递函数，其二是通过类似“流水线型”模数转换器级联的方式，将第一级的余量通过给到第二个模数转换器进行量化。我们将第二种级联式的架构称为多级噪声整型(Multi-stAge noise Shaping，MASH)。但是，不同于流水线模数转换器间的输出间仅存在延时关系，级联的Δ∑调制器输出中包含了被整型的量化误差，因此消除误差时需考虑噪声整型函数的效应。
图1是一个离散时间的级联的多级噪声整型Δ∑调制器架构的示意图。其中101为级联的Δ∑调制器的第一级，其环路滤波器函数为HLoop Filte，1(z)，实现了p1阶的噪声整型；102为一个Δ∑调制器，其环路滤波器函数为HLoop Filter，2(z)，实现了p2阶的噪声整型。那么，
Y1＝X·STF1+∈1·NTF1
Y2＝∈1·STF2+∈2·NTF2
Figure PCTCN2015095023-appb-000001
上式中，∈1，∈2是两次噪声整型的量化噪声。模拟减法器104可以得到∈1。通过后端信号的处理模块103，分别将两级噪声的量化结果乘以传递函数STF2或者NTF1，那么最后的结果Y中将仅仅包括第二级调制器的量化噪声的高阶量化整型，因此噪声整形效果可以大大提高，而过采样率也显著下降。
在面向连续时间的Δ∑调制器设计中，若完整地实现一个典型的MASH结构，设计者需要同时知道正确的传递函数STF2或者NTF1。目前而言，这样的估算还存在较大的难度。于是，因此简化的特殊情况成为了一个可以选择的实现。实际上，存在最简单的两个特殊情况STF2＝1或者NTF1＝1。此时，后续的数字信号处理模块就可以简化为寻找两个传递函数中不为单位增益的另一个传递函数。在这里，本发明仅对STF2＝1时，估算NTF1的情况进行讨论。
简单起见，假设第二级滤波的信号传递函数、噪声传递函数在此时均为1，即第二级时一个没有噪声整形的奈奎斯特模数转换器。此时，连续时间Δ-∑调制器架构称为X-0级联噪声整形结构，或者也被称为Leslie Singh结构。图2是一个典型的X-0MASH结构的连续时间Δ∑调制器示意图。其中包括传统连续时间Δ-∑调制器的模拟电路部分201，由积分器、谐振放大器和电流舵型数模转换器组成；用于环路延时补偿的路径212，由减法器和数模转换器组成；后端量化器211、余量产生电路204，余量量化器214，和噪声传递函数的数字滤波器实现203。
此时，Δ-∑环路传递函数的输出可以表示为：
Y＝X·STF1+∈1[NTF(s)-NTF′(z)]+∈2·NTF′(z)
若实际传递函数NTF(s)与数字化的估算噪声传递函数NTF(z)完全相同，那么调制器输出将仅包括第二级量化器的量化噪声整形后的结果。因为∈2是∈1的量化噪声，所以∈2的噪声能量远小于的∈1能量，在同样的过采样率下，该结构的精度要高于非级联的结构。
在实际设计过程中，减法器212与余量产生器204很难同时采用低功耗的无源器件实现减法。甚至，在保守的设计中，两者均会采用有源电路高精度地实现两个减法，以确保整个Δ-∑环路稳定性和Δ-∑调制器精度。因此，在典型的X-0MASH结构的连续时间Δ∑调制器结构，兼顾高精度的减法电路与功耗需求成为了电路设计的难点。
发明概述
针对现有技术的上述问题，本发明提出了一种兼顾减法电路精度与功耗的新型X-0MASH结构的连续时间Δ∑调制器结构。
具体的，本发明提供了一种X-0级联式噪声整形结构的连续时间Δ-∑调制器，包括：
模拟电路部分，该模拟电路部分实现Δ-∑调制环路的传递函数；
两步式的N位模数转换器，提供该X-0级联式噪声整形结构的主环路与下一级环路的量化结果，其中该两步式的N位模数转换器的模拟信号输入端连接该模拟电路部分的模拟输出端；
第一数字滤波器，消除该X-0级联式噪声整形结构的第一级环路的量化噪声效应，其中该第一数字滤波器的输入端连接该两步式的N位模数转换器；以及
第二数字滤波器，用于实现环路延时补偿，其中该第二数字滤波器的输入端连接该模拟电路部分。
较佳地，在上述的连续时间Δ-∑调制器中，该两步式的N位模数转换器包括粗子量化器和细子量化器，
其中，该粗子量化器和该细子量化器的输入端分别连接至该模拟电路部分，该粗子量化器的数字信号输出端连接至该第二数字滤波器的数字输入端，且该细子量化器的数字信号输出端连接至该第一数字滤波器的数字输入端。
较佳地，在上述的连续时间Δ-∑调制器中，该两步式的N位模数转换器采用闪烁型辅助的逐次比较型模数转换器实现，其包括：基于Flash架构的粗子量化器和基于逐次比较架构的细子量化器，
其中，P位精度的粗子量化器由2P-1个比较器组成，该比较器的输出经编码后输出至连续时间调制器和细子量化器；且
其中，该细子量化器通过翻转电容方式得到余量，再通过比较器进行Q位的逐次比较和进一步量化。
较佳地，在上述的连续时间Δ-∑调制器中，该第一数字滤波器是由数字电路实现的滤波器构成的噪声传递函数估算的数字滤波器。
较佳地，在上述的连续时间Δ-∑调制器中，该第二数字滤波器是由数字电路实现的减法器构成的环路延时补偿的数字滤波器。
较佳地，在上述的连续时间Δ-∑调制器中，该第一数字滤波器的输出端和该第二数字滤波器的输出端连接至一加法器，以使该连续时间Δ-∑调制器结构的输出信号是第一数字滤波器和第二数字滤波器两者的数字输出信号相加得到的信号。
较佳地，在上述的连续时间Δ-∑调制器中，该模拟电路部分的模拟输入端连接调制器的信号输入。
较佳地，在上述的连续时间Δ-∑调制器中，该模拟电路部分的模拟输出端进一步连接至该第二数字滤波器的数字输出端。
综上，本发明的上述X-0MASH结构的连续时间Δ∑调制器的主要特点是在于其综合考量了余量产生和延时补偿路径的实现方式，采用两部式模数转换器和数字化的余量补偿，低功耗、高能效地实现了X-0MASH结构的连续时间Δ∑调制器。
应当理解，本发明以上的一般性描述和以下的详细描述都是示例性和说明性的，并且旨在为如权利要求所述的本发明提供进一步的解释。
附图说明
包括附图是为提供对本发明进一步的理解，它们被收录并构成本申请的一部分，附图示出了本发明的实施例，并与本说明书一起起到解释本发明原理的作用。附图中：
图1是一个离散时间的级联的多级噪声整型Δ∑调制器架构的示意图。
图2是一个典型的X-0MASH结构的连续时间Δ∑调制器的示意图。
图3为本发明提出的新型应用于连续时间Δ∑调制器的X-0MASH架构的示意图。
图4为本发明提出的一种实现图3架构中模数转换器的Flash SAR结构的示意图。
图5为两步式的N位模数转换器的工作时序的一个实施例。
具体实施方式
现在将详细参考附图描述本发明的实施例。
根据本发明的一个实施例的X-0MASH结构的连续时间Δ∑调制器结构，如图3所示，其主要包括传统连续时间Δ-∑调制器的模拟电路部分310、两步式的N(例如N为自然数)位模数转换器311、第一数字滤波器312(例如噪声传递函数估算的数字滤波器)和第二数字滤波器313(例如环路延时补偿的数字滤波器)。
该模拟电路部分310实现Δ-∑调制环路的传递函数。如图所示，该模拟电路部分的模拟输入端连接调制器的信号输入。
该模拟电路部分310可以是如图2所示的传统连续时间Δ-∑调制器的模拟部分，其可以由积分器，谐振器电路和反馈数模转换器组成。
两步式的N位模数转换器311提供该X-0级联式噪声整形结构的主环路与下一级环路的量化结果。该两步式的N位模数转换器311的模拟信号输入端连接该模拟电路部分310的模拟输出端
第一数字滤波器312消除该X-0级联式噪声整形结构的第一级环路的量化噪声效应。该第一数字滤波器312的输入端连接该两步式的N位模数转换器311。较佳地，该第一数字滤波器312是由数字电路实现的滤波器构成的噪声传递函数估算的数字滤波器。
第二数字滤波器313用于实现环路延时补偿。该第二数字滤波器313的输入端连接该模拟电路部分310。较佳地，该第二数字滤波器313是由数字电路实现的减法器构成的环路延时补偿的数字滤波器。此外，该模拟电路部分310 的模拟输出端可以进一步连接至该第二数字滤波器313的数字输出端。
本发明中，该传统连续时间Δ-∑调制器的模拟电路部分310、两步式的N位模数转换器311以及环路延时补偿的第二数字滤波器313形成一个Δ-∑调制器环路。连续时间Δ-∑调制器的模拟电路部分310的模拟输入端连接调制器的信号输入，模拟输出端连接两步式的N位模数转换器311，数字输入信号连接环路延时补偿的第二数字滤波器313的数字输出。
此外，在图3所示的优选实施例中，该第一数字滤波器312的输出端和该第二数字滤波器313的输出端连接至一加法器，以使该连续时间Δ-∑调制器结构的输出信号是第一数字滤波器和第二数字滤波器两者的数字输出信号相加得到的信号。
较佳地，该两步式的N位模数转换器311可以包括粗子量化器和细子量化器。该粗子量化器和该细子量化器的输入端分别连接至该模拟电路部分310。该粗子量化器的数字信号输出端连接至该第二数字滤波器313的数字输入端，且该细子量化器的数字信号输出端连接至该第一数字滤波器312的数字输入端。
作为一个更优选的实施例，该两步式的N位模数转换器311可以采用闪烁型辅助的逐次比较型模数转换器(Flash-Assisted SAR ADC)实现，如图4所示。得注意的是，本发明提供的X-0MASH结构的连续时间Δ∑调制器可以以许多不同的方式实施，该优选实施例是基于一个闪烁型辅助的逐次比较型模数转换器，仅为本发明提供一个典型实现电路，仅用以说明本发明的形成与使用，并非用以限定本发明。
该闪烁型辅助的逐次比较型模数转换器可以进一步包括基于Flash架构的粗子量化器和基于逐次比较架构的细子量化器。该粗子量化器和该细子量化器的输入端分别连接至该模拟电路部分310。该粗子量化器的数字信号输出端连接至该第二数字滤波器313的数字输入端，且该细子量化器的数字信号输出端连接至该第一数字滤波器312的数字输入端。特别是，P(例如P为自然数)位精度的粗子量化器由2P-1个比较器组成，该比较器的输出经编码后输出至连续时间调制器和细子量化器。该细子量化器通过翻转电容方式得到余量，再通 过比较器进行Q(例如Q为自然数)位的逐次比较和进一步量化。
本发明在实际工作中传统连续时间Δ-∑调制器的模拟电路部分310始终保持工作状态，两步式的N位模数转换器311在该实施例的工作时序如图5所示，以下结合该时序图对其工作过程作如下说明：
(1)φ1为高电平时，两步式模数转换电路处于采样阶段，其他有源电路处于重置状态，
(2)φ1从高电平向低电平转换时，粗子(Most Significant Bit，MSB)的比较器410的下降沿进行比较，短时间后量化结果产生后，同时传递至连接环路延时补偿的数字滤波器313和细子量化器420，
(3)φ1为低电平、且粗子比较结束后，细子(Least Significant Bit，LSB)比较器402进行逐次比较。φ2是通过异步电路产生的逐次比较触发沿。
除了两步式模数转换器/量化器外，传统连续时间Δ-∑调制器中的模数转换器的更新时钟沿为采样时钟沿的延时τ后产生的沿。τ为环路设计时的环路延时。
通过数学模型可以证明：图2所示的传统的连续时间Δ-∑调制器的X-0MASH结构与本发明所述的新型连续时间Δ-∑调制器的X-0MASH架构是等价的。但是，相较于图2所示的传统架构，本发明提出的架构具有更高的数字化实现比例，在先进的集成电路工艺实现中具有更低的实现成本和更高的效率。
本领域技术人员可显见，可对本发明的上述示例性实施例进行各种修改和变型而不偏离本发明的精神和范围。因此，旨在使本发明覆盖落在所附权利要求书及其等效技术方案范围内的对本发明的修改和变型。

Claims (8)

  1. 一种X-0级联式噪声整形结构的连续时间Δ-∑调制器，其特征在于，包括：
    模拟电路部分，所述模拟电路部分实现Δ-∑调制环路的传递函数；
    两步式的N位模数转换器，提供所述X-0级联式噪声整形结构的主环路与下一级环路的量化结果，其中所述两步式的N位模数转换器的模拟信号输入端连接所述模拟电路部分的模拟输出端；
    第一数字滤波器，消除所述X-0级联式噪声整形结构的第一级环路的量化噪声效应，其中所述第一数字滤波器的输入端连接所述两步式的N位模数转换器；以及
    第二数字滤波器，用于实现环路延时补偿，其中所述第二数字滤波器的输入端连接所述模拟电路部分。
  2. 如权利要求1所述的连续时间Δ-∑调制器，其特征在于，所述两步式的N位模数转换器包括粗子量化器和细子量化器，
    其中，所述粗子量化器和所述细子量化器的输入端分别连接至所述模拟电路部分，所述粗子量化器的数字信号输出端连接至所述第二数字滤波器的数字输入端，且所述细子量化器的数字信号输出端连接至所述第一数字滤波器的数字输入端。
  3. 如权利要求1所述的连续时间Δ-∑调制器结构，其特征在于，所述两步式的N位模数转换器采用闪烁型辅助的逐次比较型模数转换器实现，其包括：基于Flash架构的粗子量化器和基于逐次比较架构的细子量化器，
    其中，P位精度的粗子量化器由2P-1个比较器组成，所述比较器的输出经编码后输出至连续时间调制器和细子量化器；且
    其中，所述细子量化器通过翻转电容方式得到余量，再通过比较器进行Q位的逐次比较和进一步量化。
  4. 如权利要求1所述的连续时间Δ-∑调制器，其特征在于，所述第一数字滤波器是由数字电路实现的滤波器构成的噪声传递函数估算的数字滤波器。
  5. 如权利要求1所述的连续时间Δ-∑调制器，其特征在于，所述第二数字滤波器是由数字电路实现的减法器构成的环路延时补偿的数字滤波器。
  6. 如权利要求1所述的连续时间Δ-∑调制器结构，其特征在于，所述第一数字滤波器的输出端和所述第二数字滤波器的输出端连接至一加法器，以使所述连续时间Δ-∑调制器结构的输出信号是第一数字滤波器和第二数字滤波器两者的数字输出信号相加得到的信号。
  7. 如权利要求1所述的连续时间Δ-∑调制器结构，其特征在于，所述模拟电路部分的模拟输入端连接调制器的信号输入。
  8. 如权利要求1所述的连续时间Δ-∑调制器结构，其特征在于，所述模拟电路部分的模拟输出端进一步连接至所述第二数字滤波器的数字输出端。
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