WO2017077778A1 - Élément de capture d'image et dispositif de capture d'image - Google Patents
Élément de capture d'image et dispositif de capture d'image Download PDFInfo
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- WO2017077778A1 WO2017077778A1 PCT/JP2016/077735 JP2016077735W WO2017077778A1 WO 2017077778 A1 WO2017077778 A1 WO 2017077778A1 JP 2016077735 W JP2016077735 W JP 2016077735W WO 2017077778 A1 WO2017077778 A1 WO 2017077778A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/65—Control of camera operation in relation to power supply
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
- A61B1/04—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Definitions
- the present invention relates to an imaging element and an imaging apparatus.
- an endoscope in which an image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) is disposed at the distal end of an insertion portion that is inserted into a body cavity is known (see, for example, Patent Document 1).
- an image signal captured by an image sensor is transmitted to an image processing apparatus using a transmission cable connected to a connection terminal of the image sensor.
- a signal for controlling the operation timing of the image sensor such as a power supply voltage, a ground, a voltage used for controlling the image sensor and a reference clock signal is transmitted from the image processing apparatus to the image sensor via a transmission cable. Is done.
- the imaging element for the endoscope has a smaller chip area.
- the endoscope described above requires connection terminals that require an area depending on the number of various signals transmitted between the image sensor and the image processing apparatus, and it is difficult to reduce the chip area. .
- the present invention has been made in view of the above, and an object of the present invention is to provide an imaging device and an imaging apparatus that can easily reduce the chip area.
- an imaging element includes a light receiving unit that generates and outputs an imaging signal corresponding to the amount of received light, and the imaging signal from the light receiving unit.
- a reading unit for reading a first input / output switching unit that selectively switches between an output of the imaging signal output from the reading unit and an input of a synchronization signal from the outside, and an input from the first input / output switching unit
- a readout timing control signal for controlling the timing at which the readout unit reads out the imaging signal based on the synchronization signal and a reference clock signal input from the outside, and the first input / output switching unit outputs the imaging signal.
- a timing control signal generation unit that generates and outputs a switching timing control signal that controls timing for selectively switching between the input and the input of the synchronization signal.
- the timing control signal generation unit includes a synchronization signal determination unit that determines a pattern of the synchronization signal, and a pattern of the synchronization signal that is determined by the synchronization signal determination unit.
- a counter unit that starts counting up a count value when it is determined to be a predetermined pattern, and outputs the read timing control signal to the read unit based on the count value of the counter unit, and the first And a decoder unit that outputs the switching timing control signal to the input / output switching unit, and an initialization unit that initializes the counter unit.
- the initialization unit includes a power-on reset circuit connected to the counter unit.
- the initialization unit includes a pull-up resistor and a pull-down resistor that are connected to the counter unit, respectively.
- An imaging device includes a light receiving unit that generates and outputs an imaging signal corresponding to the amount of received light, reads the imaging signal from the light receiving unit, and outputs a first imaging signal and a second imaging
- a reading unit that outputs a signal
- a first input / output switching unit that selectively switches between an output of the first imaging signal output from the reading unit and an input of a synchronization signal from the outside
- the first Read timing control for controlling the timing at which the reading unit reads the first imaging signal and the second imaging signal based on the synchronization signal input from the input / output switching unit and the reference clock signal input from the outside
- a timing control for generating and outputting a signal and a switching timing control signal for controlling a timing at which the first input / output switching unit selectively switches the output of the first imaging signal and the input of the synchronization signal.
- An image sensor comprising: a signal generation unit; a first transmission cable that transmits the first imaging signal output from the first input / output switching unit; and the first transmission cable that is transmitted by the first transmission cable.
- a second input / output switching unit that selectively switches between input of one imaging signal and output of the synchronization signal input from the outside to the first transmission cable; and the second input from the reading unit.
- the first impedance correction unit having the same impedance as that of the first input / output switching unit, and between the reading unit and the second transmission cable, or the imaging of the second transmission cable
- the element is connected And is disposed on one of opposite, characterized in that it comprises, and the second output switching section and the impedance is equal to the second impedance correction unit.
- the first impedance correction unit and the second impedance correction unit may be in an input / output switching state in which the second imaging signal is always output. It is a part.
- the first impedance correction unit is a first switch
- the second impedance correction unit is a second switch
- the first switch is disposed on a side opposite to the side to which the imaging element is connected of the second transmission cable
- the second switch is The second transmission cable is disposed on a side opposite to the side to which the image sensor is connected.
- a differential signal is input to the first input / output switching unit and the first impedance correction unit, and the second input / output switching unit and the first input / output switching unit.
- a differential amplifying circuit that amplifies and outputs the differential signal, connected to a side opposite to the side to which the first transmission cable or the second transmission cable of the impedance correction unit is connected. It is characterized by.
- FIG. 1 is a schematic diagram illustrating a configuration of an entire endoscope system including an image sensor according to an embodiment.
- FIG. 2 is a block diagram illustrating functions of a main part of the endoscope system including the image sensor according to the embodiment.
- FIG. 3 is a block diagram illustrating functions of main parts of the image sensor.
- FIG. 4 is a circuit diagram showing a configuration of the input / output switching unit.
- FIG. 5 is a diagram illustrating the relationship between the signal input to the input / output switching unit and the operation of the input / output switching unit.
- FIG. 6 is a block diagram illustrating functions of a main part of the input / output switching unit on the connector side.
- FIG. 7 is a flowchart showing an outline of the operation of the image sensor.
- FIG. 1 is a schematic diagram illustrating a configuration of an entire endoscope system including an image sensor according to an embodiment.
- FIG. 2 is a block diagram illustrating functions of a main part of the endoscope system including the image
- FIG. 8 is a block diagram illustrating functions of main parts of the image sensor according to the first modification of the embodiment.
- FIG. 9 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 2 of the embodiment.
- FIG. 10 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 3 of the embodiment.
- FIG. 11 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 4 of the embodiment.
- FIG. 12 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 5 of the embodiment.
- FIG. 13 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 6 of the embodiment.
- FIG. 14 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 7 of the embodiment.
- an imaging element and an imaging apparatus used in an endoscope system including an endoscope in which a tip is inserted into a subject explain. Further, the present invention is not limited by this embodiment. Further, in the description of the drawings, the same portions will be described with the same reference numerals. Furthermore, the drawings are schematic, and it should be noted that the relationship between the thickness and width of each member, the ratio of each member, and the like are different from the actual ones. Moreover, the part from which a mutual dimension and ratio differ also in between drawings.
- FIG. 1 is a schematic diagram illustrating a configuration of an entire endoscope system including an image sensor according to an embodiment.
- An endoscope system 1 shown in FIG. 1 includes an endoscope 2 (imaging device), a transmission cable 3, an operation unit 4, a connector unit 5, a processor 6 (processing device), a display device 7, and a light source. And a device 8.
- the endoscope 2 includes an insertion unit 100 that can be inserted into a subject. By inserting the insertion unit 100 into a body cavity of the subject, the endoscope 2 captures an image of the inside of the subject, and an imaging signal (VOUT) that is image data. Is output to the processor 6.
- the endoscope 2 is provided on one end side of the transmission cable 3 and on the distal end 101 side of the insertion unit 100 inserted into the body cavity of the subject, and an imaging unit 20 that captures an in-vivo image is provided.
- An operation unit 4 that receives various operations on the endoscope 2 is provided at the proximal end 102 of the insertion unit 100.
- An imaging signal (VOUT) of an image captured by the imaging unit 20 is output to the connector unit 5 through the transmission cable 3 having a length of several meters, for example.
- the transmission cable 3 connects the imaging unit 20 and the connector unit 5, and connects the imaging unit 20 and the light source device 8. Further, the transmission cable 3 propagates the imaging signal (VOUT) generated by the imaging unit 20 to the connector unit 5.
- the transmission cable 3 is configured using a cable, an optical fiber, or the like.
- the connector unit 5 is connected to the processor 6 and the light source device 8 and transmits an imaging signal (VOUT) output from the imaging unit 20 to the processor 6.
- the processor 6 performs predetermined image processing on the imaging signal (VOUT) input from the connector unit 5 and outputs the processed image signal to the display device 7. Further, the processor 6 controls the entire endoscope system 1 in an integrated manner. For example, the processor 6 performs control to switch the illumination light emitted from the light source device 8 or switch the imaging mode of the endoscope 2.
- the display device 7 displays an image corresponding to the imaging signal (VOUT) subjected to image processing by the processor 6.
- the display device 7 displays various information related to the endoscope system 1.
- the display device 7 is configured using a display panel such as a liquid crystal or an organic EL (Electro Luminescence).
- the light source device 8 irradiates illumination light from the distal end 101 side of the insertion portion 100 of the endoscope 2 toward the subject via the connector portion 5 and the transmission cable 3.
- the light source device 8 includes a white LED (Light Emitting Diode) that emits white light, an LED that emits NBI (Narrow Band Imaging) illumination light of narrowband light having a wavelength band narrower than the wavelength band of white light, and the like. Constructed using.
- the light source device 8 irradiates the subject with white light or NBI illumination light via the endoscope 2 under the control of the processor 6. In the present embodiment, the light source device 8 employs a simultaneous illumination method.
- FIG. 2 is a block diagram illustrating functions of a main part of the endoscope system including the image sensor according to the embodiment. With reference to FIG. 2, the detail of each part structure of the endoscope system 1 and the path
- the endoscope 2 illustrated in FIG. 2 includes an imaging unit 20 (imaging element), a transmission cable 3, and a connector unit 5.
- the imaging unit 20 includes a first chip 21 and a second chip 22. Further, the imaging unit 20 receives a power supply voltage (VDD), a negative power supply (VLO), and a ground (VSS) input from the processor 6 via the connector unit 5 and the transmission cable 3.
- VDD power supply voltage
- VLO negative power supply
- VSS ground
- a power supply stabilizing capacitor C1 is provided between the power supply voltage (VDD) supplied to the imaging unit 20 and the ground (VSS).
- a capacitor C2 for stabilizing the power supply is provided between the negative power supply (VLO) supplied to the imaging unit 20 and the ground (VSS).
- the first chip 21 includes a light receiving unit 23, a reading unit 24, and a timing control signal generation unit 25.
- the second chip 22 includes a buffer 26 and input / output switching as a first input / output switching unit. Part 27.
- the combination of the circuits arranged on the first chip 21 and the second chip 22 can be changed as appropriate.
- the timing control signal generation unit 25 disposed on the first chip 21 may be disposed on the second chip 22.
- the buffer 26 and the input / output switching unit 27 arranged on the second chip 22 may be arranged on the first chip 21.
- the light receiving unit 23 is arranged in a two-dimensional matrix, and a plurality of unit pixels 230 that receive light from the outside and generate and output an imaging signal (VOUT) corresponding to the amount of received light are arranged.
- the reading unit 24 reads the imaging signal (VOUT) photoelectrically converted from each of the plurality of unit pixels 230 of the light receiving unit 23 according to the read timing control signal output from the timing control signal generation unit 25.
- the timing control signal generation unit 25 captures an image by the reading unit 24 based on the synchronization signal (SYNC) input from the input / output switching unit 27 and the reference clock signal (CLK) input from the connector unit 5 via the transmission cable 3.
- SYNC synchronization signal
- CLK reference clock signal
- the buffer 26 amplifies and outputs an imaging signal (VOUT) output from each of the plurality of unit pixels 230 in the first chip 21.
- the input / output switching unit 27 inputs a synchronization signal (SYNC) input from the connector unit 5 via the transmission cable 3 and the buffer 26 in response to the switching timing control signal output from the timing control signal generation unit 25.
- the image pickup signal (VOUT) input from the reading unit 24 is selectively switched. A more detailed configuration of the image sensor will be described later.
- the connector unit 5 includes an input / output switching unit 51, a terminating resistor 52, an analog front end unit 53 (hereinafter referred to as “AFE unit 53”), an A / D conversion unit 54, and an imaging signal processing unit 55. , A synchronization signal generation unit 56, a reference clock signal generation unit 57, and a power supply voltage generation unit 58.
- the input / output switching unit 51 switches between the output of the synchronization signal (SYNC) and the input of the imaging signal (VOUT) in accordance with the synchronization signal (SYNC) output from the synchronization signal generation unit 56. More detailed configurations of the input / output switching unit 51 and the termination resistor 52 will be described later.
- the AFE unit 53 corrects the imaging signal (VOUT) that is an analog signal and outputs the corrected image signal to the A / D conversion unit 54.
- the A / D conversion unit 54 converts the analog imaging signal (VOUT) input from the AFE unit 53 into a digital imaging signal (VOUT) and outputs the digital imaging signal (VOUT) to the imaging signal processing unit 55.
- the imaging signal processing unit 55 is configured by, for example, an FPGA (Field Programmable Gate Array), and performs processing such as noise removal and format conversion processing on the digital imaging signal (VOUT) input from the A / D conversion unit 54. And output to the processor 6.
- FPGA Field Programmable Gate Array
- the synchronization signal generation unit 56 is supplied from the processor 6 and is a synchronization signal representing the start position of each frame based on a clock signal (for example, a 27 MHz clock signal) that serves as a reference for the operation of each component of the endoscope 2. (SYNC) is generated and output to the input / output switching unit 51.
- the synchronization signal (SYNC) generated by the synchronization signal generator 56 includes a horizontal synchronization signal and a vertical synchronization signal.
- the reference clock signal generation unit 57 generates a reference clock signal (CLK) based on a clock signal supplied from the processor 6 and serving as a reference for the operation of each component of the endoscope 2, and passes through the transmission cable 3. Output to the timing control signal generation unit 25 of the imaging unit 20.
- CLK reference clock signal
- the power supply voltage generator 58 generates a power supply voltage (VDD) necessary for driving the first chip 21 and the second chip 22 from the power supplied from the processor 6 to generate the first chip 21 and the second chip. 22 to output. Further, the power supply voltage generator 58 generates a negative power supply (VLO) necessary for driving the first chip 21 from the power supplied from the processor 6 and outputs the negative power supply (VLO) to the first chip 21. The power supply voltage generator 58 generates a power supply voltage (VDD) necessary for driving the first chip 21 and the second chip 22 using a regulator or the like.
- the processor 6 is a control device that comprehensively controls the entire endoscope system 1.
- the processor 6 includes a power supply unit 61, an image signal processing unit 62, a clock generation unit 63, a recording unit 64, an input unit 65, and a processor control unit 66.
- the power supply unit 61 supplies power to the power supply voltage generation unit 58 and supplies the ground (VSS) to the imaging unit 20 via the connector unit 5 and the transmission cable 3.
- the image signal processing unit 62 performs synchronization processing, white balance (WB) adjustment processing, gain adjustment processing, gamma correction processing on the digital imaging signal (VOUT) subjected to signal processing by the imaging signal processing unit 55.
- Image processing such as digital / analog (D / A) conversion processing and format conversion processing is performed to convert it into an image signal, and this image signal is output to the display device 7.
- the clock generator 63 generates a clock signal that is a reference for the operation of each component of the endoscope system 1, and outputs this clock signal to the synchronization signal generator 56 and the reference clock signal generator 57.
- the recording unit 64 records various information related to the endoscope system 1, data being processed, and the like.
- the recording unit 64 is configured using a recording medium such as a flash memory or a RAM (Random Access Memory).
- the input unit 65 receives input of various operations related to the endoscope system 1. For example, the input unit 65 receives an input of an instruction signal for switching the type of illumination light emitted from the light source device 8.
- the input unit 65 is configured using, for example, a cross switch or a push button.
- the processor control unit 66 comprehensively controls each unit constituting the endoscope system 1.
- the processor control unit 66 is configured using a CPU (Central Processing Unit) or the like.
- the processor control unit 66 switches the illumination light emitted from the light source device 8 in accordance with the instruction signal input from the input unit 65.
- FIG. 3 is a block diagram illustrating functions of main parts of the image sensor.
- the timing control signal generation unit 25 includes a shift register 251 that temporarily stores the synchronization signal (SYNC) output from the input / output switching unit 27, and the synchronization signal (SYNC) stored in the shift register 251.
- a sync signal discriminating unit 252 that discriminates a pattern, and a counter unit that starts counting up a count value when the sync signal (SYNC) pattern discriminated by the sync signal discriminating unit 252 is discriminated as a predetermined pattern.
- the read timing control signal is output to the read unit 24, the decoder timing unit 254 that outputs the switching timing control signal to the input / output switching unit 27, and the column counter 253
- Initialization means connected and initializing the column counter 253 And POR (power-on reset circuit: Power On Reset) of a 255, a.
- the input / output switching unit 27 is, for example, a multiplexer (MUX), and selectively selects the input of the synchronization signal (SYNC) and the output of the imaging signal (VOUT) in accordance with the switching timing control signal output from the decoder unit 254.
- FIG. 4 is a circuit diagram showing a configuration of the input / output switching unit 27. As shown in FIG. 4, the input / output switching unit 27 includes a switch 271 and a switch 272. The decoder unit 254 outputs a predetermined control signal to the switch 271 and the switch 272 as a switching timing control signal.
- FIG. 5 is a diagram illustrating the relationship between the signal input to the input / output switching unit and the operation of the input / output switching unit.
- the signal is output from the synchronization signal generation unit 56 and input / output switching unit
- a synchronization signal (SYNC) input from OUT via 51 is output from IN_B.
- SYNC synchronization signal
- FIG. 6 is a block diagram illustrating functions of a main part of the input / output switching unit on the connector side.
- the input / output switching unit 51 is, for example, a multiplexer (MUX), and the output of the synchronization signal (SYNC) and the imaging signal according to the synchronization signal (SYNC) output from the synchronization signal generation unit 56. (VOUT) input is switched.
- the input / output switching unit 51 is configured by, for example, two switches shown in FIG.
- the termination resistor 52 includes an AC termination resistor 521 connected to the ground (VSS), a DC cut capacitor 522 that cuts a DC current output from the imaging unit 20, and a DC termination resistor 523 connected to the ground (VSS). Have.
- FIG. 7 is a flowchart showing an outline of the operation of the image sensor.
- a power supply voltage VDD
- VDD power supply voltage
- the POR 255 outputs a control signal for initializing the column counter 253.
- the column counter 253 is initialized by the control signal output from the POR 255, and the count value is not counted up (step S101).
- the decoder unit 254 outputs a control signal to the SEL 1 of the input / output switching unit 27. Then, the input / output switching unit 27 is switched to input, and outputs the synchronization signal (SYNC) input from OUT via the input / output switching unit 51 from IN_B (step S102).
- the synchronization signal (SYNC) output from the input / output switching unit 27 is stored in the shift register 251.
- the synchronization signal determination unit 252 determines the pattern of the synchronization signal (SYNC) stored in the shift register 251.
- the synchronization signal determination unit 252 includes the column counter 253 and the decoder unit 254. Output a control signal.
- SYNC synchronization signal
- the decoder unit 254 determines whether a predetermined control end signal is input. When the decoder unit 254 determines that the control end signal is input (step S114: Yes), the control ends. On the other hand, when the decoder unit 254 determines that the control end signal has not been input (step S114: No), the process returns to S103, and the synchronization signal determination unit 252 detects a synchronization signal (SYNC) having a predetermined pattern. It will be in a waiting state to wait for.
- SYNC synchronization signal
- the input / output switching of the input / output switching unit 27 is performed by the control described above.
- the decoder unit 254 appropriately outputs a reading timing control signal corresponding to the count value of the column counter 253 to the reading unit 24, and the reading unit 24
- the timing for reading the imaging signal (VOUT) from each unit pixel 230 is controlled.
- the input / output switching unit 27 performs input / output switching so that the synchronization signal (SYNC) and the imaging signal (VOUT) are transmitted by the single transmission cable 3. .
- the image pickup unit 20 is an image pickup device that can reduce the chip area easily by reducing one connection terminal, which is conventionally required for the synchronization signal (SYNC) and the image pickup signal (VOUT). is there.
- the number of transmission cables 3 that is conventionally required for the synchronization signal (SYNC) and the imaging signal (VOUT) is reduced by one, and the transmission cable 3 can be easily reduced in diameter.
- FIG. 8 is a block diagram illustrating functions of main parts of the image sensor according to the first modification of the embodiment. As illustrated in FIG. 8, the timing control signal generation unit 25 ⁇ / b> A of the imaging device according to the first modification is replaced with the POR 255 of the imaging unit 20 according to the embodiment, and the initialization unit connected to the column counter 253. A pull-up resistor 256A and a pull-down resistor 257A.
- the initialization means may be configured to initialize the count of the column counter 253 when the endoscope system 1 is powered on, and is not limited to the POR255.
- FIG. 9 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 2 of the embodiment.
- the imaging device according to the second modification includes an imaging unit 20B, a transmission cable 3B, and a connector unit 5B.
- the reading unit 24 (see FIG. 2) outputs an imaging signal (Vsig1) as a first imaging signal and an imaging signal (Vsig2) as a second imaging signal.
- the timing control signal generation unit 25 (see FIG. 2) is based on the synchronization signal (SYNC) input from the input / output switching unit 27a and the reference clock signal (CLK) input from the connector unit 5B via the transmission cable 3B.
- a reading timing control signal for controlling the timing at which the reading unit 24 reads the imaging signal (Vsig1) and the imaging signal (Vsig2), and the input / output switching unit 27a receives the output of the imaging signal (Vsig1) and the input of the synchronization signal (SYNC).
- a switching timing control signal for controlling the timing of selective switching is generated and output.
- the imaging signal (Vsig1) is transmitted through the channel ch1 as the first signal channel
- the imaging signal (Vsig2) is transmitted through the channel ch2 as the second signal channel.
- the channel ch1 has the same configuration as the buffer 26, the input / output switching unit 27, the transmission cable 3, the input / output switching unit 51, and the termination resistor 52 of the embodiment. Specifically, the channel ch1 has a connector 26a that amplifies and outputs the imaging signal (Vsig1) output from the reading unit 24, and a switching timing control signal output from the timing control signal generation unit 25.
- the input / output switching unit 27a as the switching unit, the transmission cable 3a as the first transmission cable that transmits the imaging signal (Vsig1) output from the input / output switching unit 27a, and the imaging signal (Vsig1) transmitted by the transmission cable 3a )
- the output of the synchronization signal (SYNC) input from the synchronization signal generator 56 to the transmission cable 3a.
- Switch having an input and output switching unit 51a serving as a second input-output switching unit, and the terminating resistor 52a, the.
- the termination resistor 52a includes an AC termination resistor 521a, a DC cut capacitor 522a, and a DC termination resistor 523a.
- the channel ch2 amplifies and outputs the imaging signal (Vsig2) output from the reading unit 24, an input / output switching unit 27b as a first impedance correction unit having the same impedance as the input / output switching unit 27a, A transmission cable 3b as a second transmission cable for transmitting the imaging signal (Vsig2) output from the input / output switching unit 27b, and an input / output switching unit as a second impedance correction unit having the same impedance as the input / output switching unit 51a 51b and a terminating resistor 52b.
- the input / output switching unit 27b is always in a state of outputting the imaging signal (Vsig2) output from the reading unit 24 (that is, a state in which IN_A is selected).
- the input / output switching unit 51b is always in a state of outputting the imaging signal (Vsig2) (that is, a state in which IN_A is selected).
- the termination resistor 52b includes an AC termination resistor 521b, a DC cut capacitor 522b, and a DC termination resistor 523b.
- the imaging signal (Vsig1) and the imaging signal (Vsig2) are signals obtained by the reading unit 24 sequentially reading different one-line imaging signals of the unit pixels 230 arranged in a two-dimensional manner in the light receiving unit 23.
- the reading unit 24 reads the two lines of the light receiving unit 23 simultaneously, whereby the frame rate can be improved.
- the input / output switching unit 27a performs input / output switching so that the synchronization signal (SYNC), the imaging signal (Vsig1), and the imaging signal (Vsig2) are transmitted to the two transmission cables 3a.
- the data is transmitted with the transmission cable 3b.
- the imaging unit 20B has one connection terminal, which is conventionally required for the synchronization signal (SYNC), the imaging signal (Vsig1), and the imaging signal (Vsig2), reduced by one, and the chip area can be easily reduced in size. It is an imaging device that can.
- the output V1out from the input / output switching unit 51a in the channel ch1 is the impedance of the input / output switching unit 27a as Zmuxc1, the impedance of the transmission cable 3a as Zca1, the impedance of the input / output switching unit 51a as Zmuxo1, and the resistance of the AC termination resistor 521a as R11.
- R11 // R12 of Formula (1) represents the combined resistance of R11 and R12.
- the output V2out from the input / output switching unit 51b in the channel ch2 includes the impedance of the input / output switching unit 27b as Zmuxc2, the impedance of the transmission cable 3b as Zca2, the impedance of the input / output switching unit 51b as Zmuxo2, and the AC termination resistor 521b.
- R21 // R22 represents a combined resistance of R21 and R22.
- the input / output switching unit 27a and the input / output switching unit 27b are multiplexers (MUX) having the same configuration, and Zmuxc1 and Zmuxc2 are equal.
- the input / output switching unit 51a and the input / output switching unit 51b are multiplexers (MUXs) having the same configuration, and Zmuxo1 and Zmuxo2 are equal.
- V1out and V2out are equal to each other from Equation (1) and Equation (2), and a gain shift occurs between channel ch1 and channel ch2. Is prevented.
- the input / output switching unit 27a, the input / output switching unit 27b, the input / output switching unit 51a, and the input / output switching unit 51b are arranged in the same chip or on the same substrate, the temperature change or manufacturing during use Similarly, it is possible to prevent the impedance from changing due to process variations and causing a gain shift between channels.
- the input / output switching unit 27a, the input / output switching unit 27b, the input / output switching unit 51a, and the input / output switching unit 51b may be arranged on different chips or substrates.
- the impedances of the channel ch1 and the channel ch2 may be equalized. Therefore, the input / output switching unit 27b and the input / output switching unit 51b are provided between the reading unit 24 and the transmission cable 3b, or The transmission cable 3b may be disposed on either the side to which the imaging unit 20B is connected or the opposite side.
- the circuits arranged on the imaging unit 20B side are reduced. As a result, the chip area can be further reduced.
- FIG. 10 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 3 of the embodiment.
- the imaging apparatus according to the modification 3 includes an imaging unit 20C, a transmission cable 3C, and a connector unit 5C, and is an input / output switching unit that is a first impedance correction unit of the modification 2.
- 27b is replaced with a switch 28 serving as a first switch
- an input / output switching unit 51b serving as a second impedance correction unit is replaced with a switch 59 serving as a second switch.
- the switch 28 is one switch having the same configuration as the switch 271 and the switch 272 constituting the input / output switching unit 27 shown in FIG. 4 and has the same impedance as the input / output switching unit 27 and is always output from the reading unit 24.
- the signal (Vsig2) is output (switch is ON).
- the switch 59 is one switch having the same configuration as that of the input / output switching unit 51, and has the same impedance as that of the input / output switching unit 51.
- the switch 59 always captures the imaging signal (Vsig2) output from the reading unit 24. It is in a state where output is performed (switch is ON). Therefore, as in the case of the modification 2, it is possible to prevent a gain shift between the channel ch1 and the channel ch2. Furthermore, by arranging switches with the same configuration in one chip or on the same substrate, the impedance changes in the same way with respect to temperature changes and process variations, resulting in a gain shift between channels. Can be prevented.
- the input / output switching unit 27b and the input / output switching unit 51b which are multiplexers (MUX) including the two switches of the second modification, are replaced with one switch 28 and one switch 59, respectively.
- MUX multiplexers
- FIG. 11 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 4 of the embodiment.
- the imaging device according to the modification 4 includes an imaging unit 20D, a transmission cable 3D, and a connector unit 5D, and the switch 59a corresponding to the two switches 28 and the switch 59 of the modification 3.
- the switch 59b is arranged on the connector part 5D side.
- the switch 59a is one switch having the same configuration as the switch 271 and the switch 272 constituting the input / output switching unit 27 shown in FIG. 4 and has the same impedance as the input / output switching unit 27 and is always output from the reading unit 24.
- the signal (Vsig2) is output (switch is ON).
- the switch 59b is one switch having the same configuration as that of the input / output switching unit 51, and has the same impedance as that of the input / output switching unit 51.
- the switch 59b always outputs the imaging signal (Vsig2) output from the reading unit 24. It is in a state where output is performed (switch is ON). Therefore, as in the case of the modification example 3, it is possible to prevent a gain shift between the channel ch1 and the channel ch2.
- the chip area can be further reduced as compared with the third modification.
- FIG. 12 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 5 of the embodiment.
- the imaging device according to the modification 5 includes an imaging unit 20E, a transmission cable 3E, and a connector unit 5E, and a differential amplifier circuit 514 is added to the imaging device according to the modification 2. It is a configuration.
- a differential signal is input to channel ch1 and channel ch2. Specifically, a positive signal (Vsig1 (+)) output from the light receiving unit 23 is input to the input / output switching unit 27a of the channel ch1 via the reading unit 24 and the buffer 26a. The negative signal (Vsig1 ( ⁇ )) output from the light receiving unit 23 via the reading unit 24 and the buffer 26b is input to the input / output switching unit 27b of the channel ch2.
- a differential amplifier circuit 514 is connected to the opposite side of the input / output switching unit 51a and the input / output switching unit 51b to which the transmission cable 3a or the transmission cable 3b is connected. The differential amplifier circuit 514 amplifies and outputs the input differential signal.
- the imaging device according to the fifth modification has a small chip area and prevents a gain shift between the channel ch1 and the channel ch2. Furthermore, by arranging switches with the same configuration in one chip or on the same substrate, the impedance changes in the same way with respect to temperature changes and process variations, resulting in a gain shift between channels. Can be prevented. Further, in this configuration, by using the differential amplifier circuit 514, even a minute signal can be detected with low noise.
- the input / output switching unit 27b and the input / output switching unit 51b are arranged on the side opposite to the side to which the imaging unit 20E of the transmission cable 3b is connected, and the imaging unit 20E side
- Vsig1 ( ⁇ ) negative signal
- Vsig1 (+) positive signal
- FIG. 13 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 6 of the embodiment.
- the imaging device according to the modification 6 includes an imaging unit 20F, a transmission cable 3F, and a connector unit 5F, and a differential amplifier circuit 514 is added to the imaging device according to the modification 3. It is a configuration.
- a differential signal is input to channel ch1 and channel ch2. Specifically, a positive signal (Vsig1 (+)) output from the light receiving unit 23 is input to the input / output switching unit 27 of the channel ch1 via the reading unit 24 and the buffer 26a. The negative signal (Vsig1 ( ⁇ )) output from the light receiving unit 23 via the reading unit 24 and the buffer 26b is input to the switch 28 of the channel ch2.
- a differential amplifier circuit 514 is connected to the side opposite to the side where the transmission cable 3a or the transmission cable 3b of the input / output switching unit 51 and the switch 59 is connected. The differential amplifier circuit 514 amplifies and outputs the input differential signal.
- the imaging apparatus according to the sixth modification has a small chip area and prevents a gain shift between the channel ch1 and the channel ch2. Furthermore, by arranging switches with the same configuration in one chip or on the same substrate, the impedance changes in the same way with respect to temperature changes and process variations, resulting in a gain shift between channels. Can be prevented.
- FIG. 14 is a block diagram illustrating functions of main parts of an imaging apparatus according to Modification 7 of the embodiment.
- the imaging device according to Modification 7 includes an imaging unit 20G, a transmission cable 3G, and a connector unit 5G, and a differential amplifier circuit 514 is added to the imaging device according to Modification 4. It is a configuration.
- a differential signal is input to channel ch1 and channel ch2. Specifically, a positive signal (Vsig1 (+)) output from the light receiving unit 23 is input to the input / output switching unit 27 of the channel ch1 via the reading unit 24 and the buffer 26a. The negative signal (Vsig1 ( ⁇ )) output from the light receiving unit 23 via the reading unit 24, the buffer 26b, and the transmission cable 3b is input to the switch 59a of the channel ch2.
- a differential amplifier circuit 514 is connected to the side opposite to the side where the transmission cable 3a or the transmission cable 3b is connected between the input / output switching unit 51 and the switch 59b. The differential amplifier circuit 514 amplifies and outputs the input differential signal.
- the imaging device according to the modification example 7 has a small chip area and prevents a gain shift between the channel ch1 and the channel ch2.
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Abstract
Un élément de capture d'image selon l'invention comprend : une unité de réception de lumière qui génère et émet un signal de capture d'image correspondant à une quantité de réception de lumière ; une unité de lecture qui lit le signal de capture d'image émis par l'unité de réception de lumière ; une première unité de commutation d'entrée/sortie qui exécute une commutation sélective entre la sortie du signal de capture d'image émis par l'unité de lecture et l'entrée d'un signal de synchronisation depuis l'extérieur ; et une unité de génération de signal de commande de synchronisation qui génère et émet, sur la base du signal de synchronisation entré depuis la première unité de commutation d'entrée/sortie et d'un signal d'horloge de référence entré depuis l'extérieur, un signal de commande de synchronisation de lecture pour commander la synchronisation lorsque l'unité de lecture lit le signal de capture d'image, et un signal de commande de synchronisation de commutation pour commander la synchronisation lorsque la première unité de commutation d'entrée/sortie exécute une commutation sélective entre la sortie du signal de capture d'image et l'entrée du signal de synchronisation. L'invention fournit ainsi un élément de capture d'image dont une surface de puce peut être facilement réduite.
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Citations (3)
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JP2006108887A (ja) * | 2004-10-01 | 2006-04-20 | Canon Inc | 固体撮像装置の駆動方法 |
JP2011217206A (ja) * | 2010-03-31 | 2011-10-27 | Honda Motor Co Ltd | 固体撮像装置 |
JP2015188262A (ja) * | 2013-04-18 | 2015-10-29 | オリンパス株式会社 | 撮像素子、撮像装置および内視鏡システム |
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JP2006108887A (ja) * | 2004-10-01 | 2006-04-20 | Canon Inc | 固体撮像装置の駆動方法 |
JP2011217206A (ja) * | 2010-03-31 | 2011-10-27 | Honda Motor Co Ltd | 固体撮像装置 |
JP2015188262A (ja) * | 2013-04-18 | 2015-10-29 | オリンパス株式会社 | 撮像素子、撮像装置および内視鏡システム |
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