WO2017069398A1 - Ceramic circuit board and manufacturing method therefor - Google Patents

Ceramic circuit board and manufacturing method therefor Download PDF

Info

Publication number
WO2017069398A1
WO2017069398A1 PCT/KR2016/009703 KR2016009703W WO2017069398A1 WO 2017069398 A1 WO2017069398 A1 WO 2017069398A1 KR 2016009703 W KR2016009703 W KR 2016009703W WO 2017069398 A1 WO2017069398 A1 WO 2017069398A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
ceramic circuit
bonding layer
base layer
ceramic
Prior art date
Application number
PCT/KR2016/009703
Other languages
French (fr)
Korean (ko)
Inventor
박미소
곽만석
이은복
김동래
Original Assignee
주식회사 케이씨씨
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 케이씨씨 filed Critical 주식회사 케이씨씨
Publication of WO2017069398A1 publication Critical patent/WO2017069398A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/16Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

Definitions

  • the present invention relates to a ceramic circuit board and a method of manufacturing the same.
  • Ceramic materials such as alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), zirconia (ZrO 2 ) are conventionally used. It is used.
  • Direct bonding copper (DBC) has been developed and commercialized in which copper oxide is directly bonded to a substrate by melting copper oxide by heating.
  • the present invention provides a ceramic circuit board for component parts of a semiconductor device such as a power module substrate, comprising: a ceramic substrate, a base layer disposed on the ceramic substrate, a bonding layer disposed on the base layer, and the bonding layer; It includes a metal foil disposed, thereby providing a ceramic circuit board and a method of manufacturing the ceramic circuit board with improved properties such as TCT (thermal cycle test) performance, bonding strength, substrate warpage and VOID.
  • TCT thermal cycle test
  • a base layer disposed on the ceramic substrate
  • It includes a metal foil disposed on the bonding layer.
  • each member of the ceramic circuit board according to an embodiment of the present invention is "arranged" as long as the member is disposed above the member below it, and other members ( E.g., including other functional layers) is not excluded.
  • the ceramic substrate is selected from the group consisting of alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC) and zirconia (ZrO 2 ).
  • the base layer includes at least one selected from the group consisting of Cu, Ni, Cr, Ti, W, Mn, and Mo.
  • the thickness of the base layer is in the range of 0.015 to 0.5 ⁇ m
  • the metal foil includes one or more selected from the group consisting of Cu, Au, Ni and Ag
  • the thickness of the metal foil is 100 to 600 ⁇ m In range
  • the surface roughness Rz of at least one surface of the metal foil may be 2.0 ⁇ m or less.
  • the bonding layer contains at least one member selected from the group consisting of Cu, Sn, Ni, P, Ag, Zn, Ti, In.
  • the bonding layer is a composition
  • organic vehicle residue wherein the organic vehicle comprises at least one organic solvent selected from methanol, ethanol, terpineol, texanol, toluene, and the like, and optionally at least one organic binder of cellulose and acrylic do.
  • organic solvent selected from methanol, ethanol, terpineol, texanol, toluene, and the like, and optionally at least one organic binder of cellulose and acrylic do.
  • the thickness of the bonding layer is in the range of 5 to 100 ⁇ m.
  • the electronic component may be mounted on the ceramic circuit board of the present invention, and may be used in industrial fields such as power modules.
  • a method of manufacturing a ceramic circuit board is provided as follows.
  • At least one of the base layer and the bonding layer is formed by a method selected from the group consisting of a sputtering method, a printing method and a chemical plating method, and among them, may be formed by a DC sputtering method.
  • the bonding layer comprises 60 to 80 parts by weight of Cu, 10 to 30 parts by weight, P 3 to 15 parts by weight, In 3 to 15 parts by weight, and the organic vehicle balance, wherein the organic vehicle is methanol , At least one organic solvent selected from the group consisting of ethanol, terpineol and toluene, and optionally at least one organic binder of cellulose and acrylic.
  • the heat treatment in the step may be performed at a temperature range of 300 °C to 900 °C.
  • the mechanical strength such as bonding strength, substrate warpage amount, TCT and VOID characteristics are improved, and thus the bonding strength is not exfoliated by shrinkage-expansion due to repeated heat release. And it can be applied to industrial fields such as power module that requires thermal reliability.
  • FIG. 1 is a cross-sectional view showing a cross-sectional shape of a ceramic circuit board according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a cross-sectional shape of a ceramic circuit board according to still another embodiment of the present invention.
  • a ceramic circuit board 100 includes a ceramic substrate 101, a base layer 102 disposed on the ceramic substrate 101, and the base layer 102.
  • positioned on the said bonding layer 103 is included.
  • the ceramic circuit board 200 may include a structure of a base layer / bonding layer / metal foil on both sides as well as one side of the ceramic substrate 201.
  • the bonding layer 203 disposed on the base layer 202 and the base layer 202 and the metal foil 204 disposed on the bonding layer 203, respectively, on both surfaces of the ceramic substrate 201. ) May be included.
  • the material of the ceramic substrate 101 used in the present invention is not particularly limited thereto, but may include alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), and zirconia. (ZrO 2 ), and the like, among these, an alumina substrate having excellent inexpensive and excellent mechanical strength or an aluminum nitride substrate having excellent thermal conductivity can be used.
  • the thickness of the ceramic substrate 101 is not specifically limited, The range of 0.2 mm-1.0 mm which is the thickness of the ceramic substrate normally used can be used.
  • the base layer 102 having excellent adhesion with the ceramic substrate 101, at least one of Cu, Ni, Cr, Ti, W, Mn, or Mo is used by sputtering, printing, or chemical plating.
  • the base layer 102 is formed.
  • the base layer 102 include NiCr-Cu, Ti-Cu, Cu, W, Mn, Mo, and the like.
  • the thickness of the base layer 102 is not particularly limited thereto, according to one embodiment of the present invention, the thickness of the base layer 102 may be in the range of 0.015 to 0.5 ⁇ m. If the thickness of the base layer 102 is less than 0.015 ⁇ m, the thickness thereof is too high.
  • the thinness may impair adhesion to the ceramic substrate, and if the thickness of the base layer 102 is greater than 0.5 ⁇ m, the thickness may be too large and may adversely affect the thickness of the substrate and increase unnecessary resistance.
  • the DC sputtering method may be used in the method of forming the base layer 102 in terms of high film growth rate and easy thickness control.
  • the power is 1.0-2.0 kW
  • the voltage is 400-550 V
  • the current is 2.0-4.0 A
  • the amount of Ar is 100-300 sccm
  • the pressure is 3.0-4.0 mTorr.
  • the bonding layer 103 is disposed on the base layer 102, and then the bonding layer 103 is formed. ), The metal foil 104 and the ceramic substrate are joined by arranging and bonding the metal foil 104 on the wafer).
  • the metal foil 104 is Cu, Au, Ni or Ag, the thickness of the metal foil is preferably in the range of 100 to 600 ⁇ m, if the thickness of the metal foil 104 is less than 100 ⁇ m its thickness is too thin metal foil 104
  • the thickness of the metal foil 104 may be greater than 600 ⁇ m, and the efficiency of the ceramic circuit board 100 may decrease due to an increase in resistance () due to an increase in the thickness of the metal foil 104.
  • Adhesion of the section 103 may be lowered.
  • the bonding layer 103 is a layer formed of a composition including Cu, Sn, P, In, and an organic vehicle, and directly prints the composition on the base layer 102 disposed on the ceramic substrate 101, or the base
  • the composition is preformed in a predetermined shape on the layer 102 and placed (interposed) in a preform, and then the metal foil 104 is integrally disposed thereon to perform brazing, wherein the temperature depends on the material of the bonding layer 103. Although different, it can be carried out at approximately 300 °C to 900 °C.
  • the metal foil 104 used in the present invention is substantially not subjected to roughening treatment by forming a lump-shaped electrodeposition layer, or by performing an oxidation treatment, a reduction treatment, or an etching in order to improve adhesion to the metal foil 104 surface.
  • the term "substantially” means that the metal foil subjected to the roughening treatment can be used to such an extent that sufficient adhesive strength cannot be obtained, and a metal foil without any roughening treatment may be used. Therefore, the surface roughness of the metal foil used in the present invention may be 3.0 ⁇ m or less, 2.0 ⁇ m or less, or 0.3 ⁇ m or less on both sides of the 10-point average roughness Rz shown in JIS B0601.
  • the bonding layer 103 according to the present invention is composed of 60 to 80 parts by weight of Cu, 10 to 30 parts by weight of Sn, 3 to 15 parts by weight, 3 to 15 parts by weight of In, and the remainder of the organic vehicle.
  • the organic vehicle can include, for example, an organic solvent, and optionally an organic binder.
  • the organic solvent is not limited thereto, but organic solvents such as methanol, ethanol, terpineol, toluene, and the like may be used.
  • As the organic binder cellulose or acrylic organic binders such as ethyl cellulose and methyl cellulose may be used for handling. .
  • the thickness of the bonding layer 103 may be in the range of 5 to 100 ⁇ m. If the thickness of the bonding layer 103 is less than 5 ⁇ m, there is a problem in the adhesion between the base layer 102 and the metal foil 104. If the thickness of the bonding layer 103 is more than 100 ⁇ m, the bonding layer 103 is thick. Due to the difficulty in heat transfer from the metal foil 104 to the ceramic substrate 101, the efficiency of the ceramic circuit board 100 is lowered.
  • the bonding layer 103 is disposed between the base layer 102 and the metal foil 104, and is formed by the energy ray irradiation and / or heat treatment of the bonding layer 103 or the bonding layer 103 and the metal foil 104.
  • the metal foil 104 may be bonded to the ceramic substrate 101 including the base layer 102, and in the case of using a heat treatment, the metal foil 104 may be performed in a temperature range of 300 ° C. to 900 ° C.
  • heat treatment at a temperature of 1100 ° C. or higher is required, whereas the ceramic circuit board 100 of the present invention exhibits excellent mechanical bonding properties even by heat treatment at low temperatures.
  • the metal foil may be disposed on the bonding layer, and at least one of energy ray irradiation and heat treatment may be performed on the base layer and the bonding layer on the ceramic substrate.
  • At least one of the base layer and the bonding layer may be formed by a sputtering method, a printing method, or a chemical plating method, among which DC sputtering is most suitable.
  • the base layer, the bonding layer and the metal foil may be formed on only one side on the ceramic substrate, but is not limited thereto, as shown in FIG. 2, the layer on both sides of the ceramic substrate Can be formed.
  • the base layer 202, the bonding layer 303, and the metal foil 204 may be formed on both surfaces of the ceramic substrate 201.
  • the base layer 202, the bonding layer 203, and the metal foil 204 are formed on one side of the ceramic substrate 201, and at the same time or after that, the base layer on the other side of the ceramic substrate 201. 202, the bonding layer 203, and the metal foil 204 can be formed.
  • the base layer 202, the bonding layer 203, and the metal foil 204 formed on both surfaces of the ceramic substrate 201 are denoted by the same reference numerals for convenience of description.
  • the constituent materials of each of the base layer 202, the bonding layer 203, and the metal foil 204 to be formed are sufficient as long as they satisfy the scope of the present invention, and are not limited to the exact same.
  • TCT thermal cycle test
  • the void incidence was divided into 30 equal parts on the large ceramic metal bonded substrate, and the void generated area was counted.
  • the bond strength test was performed with a universal testing machine (UTM). The amount of warpage was measured.
  • Example 1-3 and Comparative Example 1 Evaluation of Physical Properties of Metal Bonded Alumina (Al 2 O 3 ) Substrate
  • the ceramic circuit board was manufactured according to the above-described method of manufacturing the ceramic circuit board.
  • ) / Cu layer was formed by sputtering method, paste printing method and chemical plating method, respectively.
  • the bonding layer was composed of 70 parts by weight of Cu, 10 parts by weight of Sn, 5 parts by weight of P, 5 parts by weight of In and 10 parts by weight of terpineol.
  • the composition was used, and as metal foil, the copper metal foil whose average surface roughness (Rz) is 1.5 micrometers was used (Examples 1-3).
  • Comparative Example 1 a substrate in which a Cu layer was directly bonded to a ceramic substrate without a base layer by using a direct bonding method, which is a conventional method of manufacturing a metal bonded ceramic substrate, was used.
  • the thickness of the base layer was 0.15 ⁇ m
  • the thickness of the bonding layer was 50 ⁇ m
  • the thickness of the copper metal foil was 300 ⁇ m.
  • the number of TCTs, the incidence of voids, the bond strength, and the amount of warpage of the substrate were measured.
  • Void occurrence rate Void occurrence area / total area ⁇ 100%
  • the ceramic circuit board of the present invention in which the ceramic substrate was bonded to Cu foil (Examples 1 to 3) exhibited excellent overall physical properties such as TCT, void generation rate, bonding strength, and substrate warping amount.
  • the metal bonded ceramic circuit board of the present invention has excellent mechanical bonding properties and thermal reliability compared to the conventional metal bonded ceramic circuit board, and can be applied in harsh environments such as heat sinks for power semiconductors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Ceramic Products (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

The present invention relates to a ceramic circuit board and a manufacturing method therefor, the ceramic circuit board comprising: a ceramic substrate; a base layer disposed on the ceramic substrate; a bonding layer disposed on the base layer; and a metal foil disposed on the bonding layer.

Description

세라믹 회로기판 및 이의 제조방법Ceramic Circuit Board and Manufacturing Method Thereof
본 발명은 세라믹 회로기판 및 이의 제조방법에 관한 것이다.The present invention relates to a ceramic circuit board and a method of manufacturing the same.
근래, 로봇이나 모터 등의 산업 기기의 고성능화가 진행되고 고전력, 고능률 인버터 등 고 파워모듈(high power module)이 요구됨에 따라서 반도체 소자로부터 발생되는 열도 증가하고 있다. 이 열을 효율적으로 방출하기 위해 파워모듈 기판에서는 종래부터 다양한 방법이 취해지고 있다. 특히, 최근에 양호한 열전도율을 가지는 세라믹 기판이 개발됨에 따라서 이 세라믹 기판에 금속판을 접합하고 회로를 형성한 후 반도체 소자를 탑재하는 구조로 모듈의 개발이 진행되고 있기도 하다.In recent years, as the performance of industrial devices such as robots and motors is advanced, and high power modules such as high power and high efficiency inverters are required, heat generated from semiconductor devices is also increasing. In order to dissipate this heat efficiently, various methods have been conventionally taken for the power module substrate. In particular, with the recent development of ceramic substrates having a good thermal conductivity, the development of modules has been progressed to a structure in which a semiconductor device is mounted after bonding a metal plate to a ceramic substrate and forming a circuit.
이러한 반도체 장치에 사용되는 전기절연성 기판으로서는 종래부터 알루미나(Al2O3), 질화알루미늄(AlN), 질화규소(Si3N4), 탄화규소(SiC), 지르코니아(ZrO2) 등의 세라믹 소재가 사용되고 있다. 상기와 같은 세라믹 소재의 기판과 금속을 접합하는 방법에는 여러가지 방법이 있는데, 예컨대 표면이 산화된 구리 판재를 세라믹 기판에 접촉 배치한 후, 구리의 융점보다는 낮고 구리 및 산소의 공융점 보다는 높은 온도로 가열하여 산화구리를 용융시켜 구리 판재를 기판에 직접 접합시키는 직접 접합법(Direct bonding copper: DBC) 이 개발되어 상용화되고 있다. As an electrically insulating substrate used in such a semiconductor device, ceramic materials such as alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), zirconia (ZrO 2 ) are conventionally used. It is used. There are various methods for bonding the metal and the substrate of the ceramic material as described above. For example, after placing the surface-oxidized copper sheet in contact with the ceramic substrate, the temperature is lower than the melting point of copper and higher than the eutectic point of copper and oxygen. Direct bonding copper (DBC) has been developed and commercialized in which copper oxide is directly bonded to a substrate by melting copper oxide by heating.
한편, 최근에는 보다 많은 열방출 및 강한 기계적인 접합 물성을 유지하기 위해 금속 회로기판을 납재층을 통하여 접합하는 활성금속 접합법에 의해 제조된 세라믹 회로기판 역시 개발되어 고신뢰성을 요구하는 전력반도체에 적용되고 있다. 상기 활성금속 접합법의 경우에는 직접 접합법에 비하여 접합 처리 온도가 낮기 때문에 금속-세라믹이 갖는 잔류응력이 작고, 접합층이 연성 금속이기 때문에 열충격이나 열적변화에 대해서 신뢰성이 크며, 접합시 계면에서 발생하는 미세기공(micro void) 발생이 적어 전기적인 특성이 우수한 장점을 갖고 있다. 하지만, 활성금속 접합법으로 얻어진 세라믹 회로기판의 경우 활성금속의 접합시 세라믹과의 반응에 의한 반응층이 형성되는데 이 반응층의 구조가 취약하여 기계적 강도도 저하되며, 이는 보다 큰 기계적 강도를 요구하는 최근의 파워모듈에서는 큰 단점으로 작용한다.Recently, ceramic circuit boards manufactured by an active metal bonding method for joining metal circuit boards through a brazing filler metal layer have also been developed in order to maintain more heat dissipation and strong mechanical bonding properties, and have been applied to power semiconductors requiring high reliability. It is becoming. In the case of the active metal bonding method, since the bonding process temperature is lower than that of the direct bonding method, the residual stress of the metal-ceramic is small, and since the bonding layer is a soft metal, it is highly reliable against thermal shock and thermal changes, and is generated at the interface during bonding. Micro voids are less generated and have excellent electrical characteristics. However, in the case of the ceramic circuit board obtained by the active metal bonding method, a reaction layer is formed by the reaction with the ceramic when the active metal is bonded, and the structure of the reaction layer is weak, so that the mechanical strength is lowered. This is a major disadvantage in recent power modules.
상기 활성금속 접합법의 단점을 극복하기 위해 납재 페이스트를 개재하여 세라믹 기판과 금속판을 접합하는 방법이 연구되고 있는데, 아직까지는 접합강도 및 기타 기계적 물성이 충분히 확보되지 않고 있는 실정이다. In order to overcome the shortcomings of the active metal bonding method, a method of bonding a ceramic substrate and a metal plate through a solder paste is being studied, but bonding strength and other mechanical properties have not been sufficiently secured.
[선행기술문헌][Preceding technical literature]
[특허문헌][Patent Documents]
일본특허공개공보 제2001-168482호Japanese Patent Laid-Open No. 2001-168482
한국특허공개공보 제2013-0132684호Korean Patent Publication No. 2013-0132684
본 발명은 파워모듈 기판 등의 반도체 장치의 구성부품용 세라믹 회로기판을 제공하는데 있어서, 세라믹 기판, 상기 세라믹 기판 상에 배치된 베이스층, 상기 베이스층 상에 배치된 접합층 및 상기 접합층 상에 배치된 금속박을 포함하며, 이로써 TCT(thermal cycle test) 성능, 접합강도, 기판 휨량(warpage) 및 VOID 등의 물성이 개선된 세라믹 회로기판 및 상기 세라믹 회로기판의 제조방법을 제공한다.The present invention provides a ceramic circuit board for component parts of a semiconductor device such as a power module substrate, comprising: a ceramic substrate, a base layer disposed on the ceramic substrate, a bonding layer disposed on the base layer, and the bonding layer; It includes a metal foil disposed, thereby providing a ceramic circuit board and a method of manufacturing the ceramic circuit board with improved properties such as TCT (thermal cycle test) performance, bonding strength, substrate warpage and VOID.
본 발명의 일 실시형태에 따른 세라믹 회로기판은,Ceramic circuit board according to an embodiment of the present invention,
세라믹 기판;Ceramic substrates;
상기 세라믹 기판 상에 배치된 베이스층; A base layer disposed on the ceramic substrate;
상기 베이스층 상에 배치된 접합층; 및A bonding layer disposed on the base layer; And
상기 접합층 상에 배치된 금속박을 포함하는 것이다.It includes a metal foil disposed on the bonding layer.
본 발명의 일 실시형태에 따른 세라믹 회로기판의 각 부재가 "배치"된다는 것은, 당해 부재가 그 아래의 부재 위에 배치되는 것이면 족한 것이고, 본 발명의 기술 사상을 일탈하지 않는다면 그 사이에 다른 부재 (예컨대, 다른 기능성 층을 포함)가 개재되는 것을 배제하는 것은 아니다.It is sufficient that each member of the ceramic circuit board according to an embodiment of the present invention is "arranged" as long as the member is disposed above the member below it, and other members ( E.g., including other functional layers) is not excluded.
본 발명의 일 실시형태에서 상기 세라믹 기판은 알루미나(Al2O3), 질화알루미늄(AlN), 질화규소(Si3N4), 탄화규소(SiC) 및 지르코니아(ZrO2)로 이루어진 군에서 선택되는 1종 이상을 포함하며, 상기 베이스층은 Cu, Ni, Cr, Ti, W, Mn, 및 Mo로 이루어진 군에서 선택되는 1종 이상을 포함한다.In one embodiment of the present invention, the ceramic substrate is selected from the group consisting of alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC) and zirconia (ZrO 2 ). At least one, and the base layer includes at least one selected from the group consisting of Cu, Ni, Cr, Ti, W, Mn, and Mo.
한편, 상기 베이스층의 두께는 0.015 내지 0.5㎛의 범위 내이며, 상기 금속박은 Cu, Au, Ni 및 Ag로 이루어진 군에서 선택되는 1종 이상을 포함하고, 상기 금속박의 두께는 100 내지 600㎛의 범위 내이다.On the other hand, the thickness of the base layer is in the range of 0.015 to 0.5㎛, the metal foil includes one or more selected from the group consisting of Cu, Au, Ni and Ag, the thickness of the metal foil is 100 to 600㎛ In range
또한, 본 발명의 일 실시형태에 의하면, 특별히 이에 제한되지는 않지만, 상기 금속박의 적어도 어느 하나의 표면, 보다 구체적으로는 두 표면 모두의 표면 조도(Rz)가 2.0㎛ 이하일 수 있다.In addition, according to one embodiment of the present invention, although not particularly limited thereto, the surface roughness Rz of at least one surface of the metal foil, more specifically, both surfaces, may be 2.0 μm or less.
또한, 본 발명의 일 실시형태에 의하면, 상기 접합층은 Cu, Sn, Ni, P, Ag, Zn, Ti, In 로 이루어진 군에서 선택되는 1종 이상을 포함한다.Moreover, according to one embodiment of the present invention, the bonding layer contains at least one member selected from the group consisting of Cu, Sn, Ni, P, Ag, Zn, Ti, In.
상기 접합층은 조성물로서,The bonding layer is a composition,
Cu 60 내지 80 중량부,60 to 80 parts by weight of Cu,
Sn 10 내지 30 중량부,Sn 10 to 30 parts by weight,
P 3 내지 15 중량부,P 3 to 15 parts by weight,
In 3 내지 15 중량부, 및 In 3 to 15 parts by weight, and
유기 비히클(vehicle) 잔부를 포함하는데, 상기 유기 비히클은 메탄올, 에탄올, 터피네올, 텍산올, 톨루엔 등으로부터 선택되는 하나 이상의 유기 용매 및, 선택적으로 셀룰로오스계 및 아크릴계 중 적어도 하나의 유기 결합제를 포함한다.An organic vehicle residue, wherein the organic vehicle comprises at least one organic solvent selected from methanol, ethanol, terpineol, texanol, toluene, and the like, and optionally at least one organic binder of cellulose and acrylic do.
또한, 특별히 이에 제한되지는 않지만, 상기 접합층의 두께는 5 내지 100㎛ 범위 내이다.In addition, although not particularly limited thereto, the thickness of the bonding layer is in the range of 5 to 100 μm.
또한, 본 발명의 세라믹 회로기판 상에 전자부품이 실장될 수 있으며, 파워모듈 등의 산업분야에 이용될 수 있다.In addition, the electronic component may be mounted on the ceramic circuit board of the present invention, and may be used in industrial fields such as power modules.
본 발명의 다른 일 실시형태에 따라 하기와 같이, 세라믹 회로기판의 제조방법을 제공하는데, 이 제조방법은 According to another embodiment of the present invention, a method of manufacturing a ceramic circuit board is provided as follows.
세라믹 기판 상에 베이스층을 배치하고, Placing a base layer on a ceramic substrate,
상기 베이스층 상에 접합층을 배치하며,Disposing a bonding layer on the base layer,
상기 접합층 상에 금속박을 배치하는 것을 포함하고,Disposing a metal foil on the bonding layer;
상기 세라믹 기판 상의 상기 베이스층, 상기 접합층 및 상기 금속박에 에너지선 조사 및 열처리 중 적어도 하나를 실시하는 것을 포함하는 것이다.And performing at least one of energy ray irradiation and heat treatment on the base layer, the bonding layer, and the metal foil on the ceramic substrate.
상기에서, 베이스층 및 접합층 중 적어도 어느 하나는 스퍼터링법, 인쇄법 및 화학도금법으로 이루어진 군으로부터 선택되는 방법에 의해서 형성되며, 그 중에서도 DC 스퍼터링법으로 형성될 수 있다.In the above, at least one of the base layer and the bonding layer is formed by a method selected from the group consisting of a sputtering method, a printing method and a chemical plating method, and among them, may be formed by a DC sputtering method.
상기 접합층은 상술한 바와 같이, Cu 60 내지 80 중량부, Sn 10 내지 30 중량부, P 3 내지 15 중량부, In 3 내지 15 중량부, 및 유기 비히클 잔부를 포함하는데, 상기 유기 비히클은 메탄올, 에탄올, 터피네올 및 톨루엔으로 이루어진 군으로부터 선택되는 적어도 하나의 유기 용매, 및 선택적으로 셀룰로오스계 및 아크릴계 중 적어도 하나의 유기 결합제를 포함하는 물질일 수 있다.The bonding layer, as described above, comprises 60 to 80 parts by weight of Cu, 10 to 30 parts by weight, P 3 to 15 parts by weight, In 3 to 15 parts by weight, and the organic vehicle balance, wherein the organic vehicle is methanol , At least one organic solvent selected from the group consisting of ethanol, terpineol and toluene, and optionally at least one organic binder of cellulose and acrylic.
또한, 상기 단계에서 열처리는 300℃ 내지 900℃의 온도범위에서 수행될 수 있다.In addition, the heat treatment in the step may be performed at a temperature range of 300 ℃ to 900 ℃.
본 발명의 세라믹 회로기판을 사용할 경우에는 접합강도, 기판 휨량, TCT 및 VOID 특성 등 기계적 물성이 향상되어 있어 세라믹 기판에 접합된 금속판이 반복적인 열방출에 따른 수축-팽창에 의해서도 박리되지 않으므로 접합강도 및 열적신뢰성이 요구되는 파워모듈 등의 산업분야에 적용할 수 있다. In the case of using the ceramic circuit board of the present invention, the mechanical strength such as bonding strength, substrate warpage amount, TCT and VOID characteristics are improved, and thus the bonding strength is not exfoliated by shrinkage-expansion due to repeated heat release. And it can be applied to industrial fields such as power module that requires thermal reliability.
도 1은 본 발명의 일 실시형태에 의한 세라믹 회로기판의 단면 형상을 나타내는 단면도이다.1 is a cross-sectional view showing a cross-sectional shape of a ceramic circuit board according to an embodiment of the present invention.
도 2는 본 발명의 또 다른 실시형태에 의한 세라믹 회로기판의 단면 형상을 나타내는 단면도이다. 2 is a cross-sectional view showing a cross-sectional shape of a ceramic circuit board according to still another embodiment of the present invention.
도 1을 참조하여 본 발명의 일 실시형태에 의한 세라믹 회로기판(100)은 세라믹 기판(101)과, 상기 세라믹 기판(101) 상에 배치된 베이스층(102)과, 상기 베이스층(102) 상에 배치된 접합층(103)과, 상기 접합층 상에(103) 배치된 금속박(104)을 포함하는 것이다.Referring to FIG. 1, a ceramic circuit board 100 according to an exemplary embodiment of the present invention includes a ceramic substrate 101, a base layer 102 disposed on the ceramic substrate 101, and the base layer 102. The bonding layer 103 arrange | positioned on and the metal foil 104 arrange | positioned on the said bonding layer 103 is included.
또한, 도 2를 참조하면, 본 발명의 또 다른 실시형태에 의한 세라믹 회로기판(200)은 세라믹 기판(201)의 한쪽 면뿐만이 아니라 양쪽 면에 베이스층/접합층/금속박의 구조를 포함할 수 있는데, 구체적으로 세라믹 기판(201)을 중심으로 양면에 각각 베이스층(202)과 상기 베이스층(202) 상에 배치된 접합층(203)과 상기 접합층(203)상에 배치된 금속박(204)을 포함할 수도 있다.Also, referring to FIG. 2, the ceramic circuit board 200 according to another embodiment of the present invention may include a structure of a base layer / bonding layer / metal foil on both sides as well as one side of the ceramic substrate 201. Specifically, the bonding layer 203 disposed on the base layer 202 and the base layer 202 and the metal foil 204 disposed on the bonding layer 203, respectively, on both surfaces of the ceramic substrate 201. ) May be included.
이하에서는 본 발명의 세라믹 회로 기판 각 부재에 대하여, 편의를 위하여 도 1을 참조로 하여 설명한다.Hereinafter, each member of the ceramic circuit board of the present invention will be described with reference to FIG. 1 for convenience.
<세라믹 기판><Ceramic Substrate>
먼저 본 발명에 사용되는 세라믹 기판(101) 재료로는 특별히 이에 제한되지는 않지만, 알루미나(Al2O3), 질화알루미늄(AlN), 질화규소(Si3N4), 탄화규소(SiC), 지르코니아(ZrO2) 등을 들 수 있는데, 이 중에서도 저렴하고 기계적 강도가 우수한 알루미나 기판 또는 열전도도가 우수한 질화알루미늄 기판을 사용할 수 있다. 세라믹 기판(101)의 두께는 특별하게 한정되지는 않지만, 통상적으로 사용되는 세라믹 기판의 두께인 0.2mm 내지 1.0mm의 범위를 사용할 수 있다.First, the material of the ceramic substrate 101 used in the present invention is not particularly limited thereto, but may include alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), and zirconia. (ZrO 2 ), and the like, among these, an alumina substrate having excellent inexpensive and excellent mechanical strength or an aluminum nitride substrate having excellent thermal conductivity can be used. Although the thickness of the ceramic substrate 101 is not specifically limited, The range of 0.2 mm-1.0 mm which is the thickness of the ceramic substrate normally used can be used.
<베이스층><Base layer>
상기 세라믹 기판(101)과 밀착성이 우수한 베이스층(102)을 형성하는데 있어서, 스퍼터링법, 인쇄법 또는 화학도금법을 이용하여서 Cu, Ni, Cr, Ti, W, Mn 또는 Mo 중 1종 이상을 포함하는 베이스층(102)을 형성한다. 베이스층(102)의 예로는 NiCr-Cu, Ti-Cu, Cu, W, Mn, Mo 등을 들 수 있다. 베이스층(102)의 두께는 특별히 이에 제한되지는 않지만, 본 발명의 일 실시형태에 의하면 0.015 내지 0.5㎛ 범위 내일 수 있는데, 상기 베이스층(102)의 두께가 0.015㎛ 미만이면, 그 두께가 너무 얇아 세라믹 기판과의 밀착성이 저해될 수 있고, 상기 베이스층(102)의 두께가 0.5㎛ 초과이면, 그 두께가 너무 커서 기판의 박형화, 불필요한 저항의 증가 등 악영향을 미칠 수 있다. 또한, 상기 베이스층(102) 형성 방법 중에서 막 성장 속도가 높고 두께 조절이 용이하다는 점에서 DC 스퍼터링법을 사용할 수 있다.In forming the base layer 102 having excellent adhesion with the ceramic substrate 101, at least one of Cu, Ni, Cr, Ti, W, Mn, or Mo is used by sputtering, printing, or chemical plating. The base layer 102 is formed. Examples of the base layer 102 include NiCr-Cu, Ti-Cu, Cu, W, Mn, Mo, and the like. Although the thickness of the base layer 102 is not particularly limited thereto, according to one embodiment of the present invention, the thickness of the base layer 102 may be in the range of 0.015 to 0.5 μm. If the thickness of the base layer 102 is less than 0.015 μm, the thickness thereof is too high. The thinness may impair adhesion to the ceramic substrate, and if the thickness of the base layer 102 is greater than 0.5 μm, the thickness may be too large and may adversely affect the thickness of the substrate and increase unnecessary resistance. In addition, the DC sputtering method may be used in the method of forming the base layer 102 in terms of high film growth rate and easy thickness control.
상기 DC 스퍼터링 방법에서의 조건으로, 전력은 1.0-2.0kW, 전압은 400-550V, 전류는 2.0-4.0A이며, Ar량은 100-300sccm, 압력은 3.0-4.0mTorr이다.As a condition in the DC sputtering method, the power is 1.0-2.0 kW, the voltage is 400-550 V, the current is 2.0-4.0 A, the amount of Ar is 100-300 sccm, and the pressure is 3.0-4.0 mTorr.
<금속박 및 접합층><Metal foil and bonding layer>
상기 세라믹 기판(101)에 스퍼터링 방법 등으로 베이스층(102)(예컨대, NiCr/Cu)을 형성한 후, 상기 베이스층(102) 상에 접합층(103)을 배치 후, 상기 접합층(103) 상에 금속박(104)을 배치하여 접합함으로써 금속박과 세라믹 기판을 접합시킨다.After the base layer 102 (eg, NiCr / Cu) is formed on the ceramic substrate 101 by a sputtering method or the like, the bonding layer 103 is disposed on the base layer 102, and then the bonding layer 103 is formed. ), The metal foil 104 and the ceramic substrate are joined by arranging and bonding the metal foil 104 on the wafer).
상기 금속박(104)은 Cu, Au, Ni 또는 Ag이며, 금속박의 두께는 100 내지 600㎛ 범위 내인 것이 적합한데, 상기 금속박(104)의 두께가 100㎛ 미만이면 그 두께가 너무 얇아 금속박(104)의 내구성에 영향을 미칠 수 있으며, 금속박(104)의 두께가 600㎛ 초과이면 금속박(104)의 두께 증가로 인한 저항()의 증가로 세라믹 회로 기판(100)의 효율이 떨어질 수 있고, 접합층과(103)의 접착력이 저하될 수 있다. 본 발명의 일 실시형태에 따른 금속박(104)의 두께를 100 내지 600㎛ 이내로 함으로써 접합층(103)과의 접착력을 최대로 하여 생성되는 기판의 내구성을 향상시킬 수 있다. The metal foil 104 is Cu, Au, Ni or Ag, the thickness of the metal foil is preferably in the range of 100 to 600㎛, if the thickness of the metal foil 104 is less than 100㎛ its thickness is too thin metal foil 104 The thickness of the metal foil 104 may be greater than 600 μm, and the efficiency of the ceramic circuit board 100 may decrease due to an increase in resistance () due to an increase in the thickness of the metal foil 104. Adhesion of the section 103 may be lowered. By setting the thickness of the metal foil 104 according to one embodiment of the present invention to 100 to 600 µm or less, the durability of the substrate produced by maximizing the adhesive force with the bonding layer 103 can be improved.
상기 접합층(103)은 Cu, Sn, P, In 및 유기 비히클을 포함하는 조성물로 형성된 층으로서, 세라믹 기판(101) 상에 배치된 베이스층(102) 위에 상기 조성물을 직접 인쇄하거나, 상기 베이스층(102) 위에 상기 조성물을 일정 모양으로 미리 형성하여 프리폼으로 배치(개재)한 후에 그 위에 금속박(104)을 일체로 배치하여 브레이징을 실시하는데, 이때 온도는 접합층(103)의 재질에 따라 다르지만 대략 300℃ 내지 900℃에서 실시할 수 있다.The bonding layer 103 is a layer formed of a composition including Cu, Sn, P, In, and an organic vehicle, and directly prints the composition on the base layer 102 disposed on the ceramic substrate 101, or the base The composition is preformed in a predetermined shape on the layer 102 and placed (interposed) in a preform, and then the metal foil 104 is integrally disposed thereon to perform brazing, wherein the temperature depends on the material of the bonding layer 103. Although different, it can be carried out at approximately 300 ℃ to 900 ℃.
본 발명에서 사용되는 상기 금속박(104)은, 금속박(104) 표면에 접착성을 향상시키기 위하여 혹 모양의 전착물층의 형성이나 산화 처리, 환원 처리, 에칭 등에 의한 조화 처리가 실질적으로 실시되지 않는 것이다. 여기서 실질적으로라는 용어는, 충분한 접착 강도를 얻을 수 없는 정도로 조도화 처리된 금속박도 사용할 수 있다는 의미이고, 조도화 처리가 전혀 실시되어 있지 않은 금속박을 이용할 수도 있다. 따라서, 본 발명에서 사용되는 금속박의 표면 조도는 JIS B0601에 나타낸 10점 평균 조도(Rz)가 양면 모두 3.0㎛ 이하이거나, 2.0㎛ 이하, 0.3㎛ 이하일 수 있다. 이러한 매끄러운 표면을 지닌 금속박을, 하기의 접합층을 이용하여 배치함으로써, 본 발명에 따른 금속박은 세라믹 기판과의 충분한 접착력 등을 확보할 수 있다. The metal foil 104 used in the present invention is substantially not subjected to roughening treatment by forming a lump-shaped electrodeposition layer, or by performing an oxidation treatment, a reduction treatment, or an etching in order to improve adhesion to the metal foil 104 surface. will be. The term "substantially" means that the metal foil subjected to the roughening treatment can be used to such an extent that sufficient adhesive strength cannot be obtained, and a metal foil without any roughening treatment may be used. Therefore, the surface roughness of the metal foil used in the present invention may be 3.0 µm or less, 2.0 µm or less, or 0.3 µm or less on both sides of the 10-point average roughness Rz shown in JIS B0601. By arrange | positioning the metal foil which has such a smooth surface using the following bonding layer, the metal foil which concerns on this invention can ensure sufficient adhesive force etc. with a ceramic substrate.
본 발명에 따른 접합층(103)은 그 조성물로서, Cu 60 내지 80 중량부, Sn 10 내지 30중량부, P 3 내지 15중량부, In 3 내지 15중량부 및 유기 비히클 잔부로 이루어지는데, 상기 유기 비히클은 일례로 유기 용제, 및 선택적으로 유기 결합제를 포함할 수 있다. 유기 용제로는 이에 제한되지 않으나 메탄올, 에탄올, 터피네올, 톨루엔 등의 유기 용제를 사용할 수 있으며, 유기 결합제로는 취급성을 위해 에틸셀룰로오스, 메틸셀룰로오스 등의 셀룰로오스계나 아크릴계 유기 결합제를 사용할 수 있다. The bonding layer 103 according to the present invention is composed of 60 to 80 parts by weight of Cu, 10 to 30 parts by weight of Sn, 3 to 15 parts by weight, 3 to 15 parts by weight of In, and the remainder of the organic vehicle. The organic vehicle can include, for example, an organic solvent, and optionally an organic binder. The organic solvent is not limited thereto, but organic solvents such as methanol, ethanol, terpineol, toluene, and the like may be used. As the organic binder, cellulose or acrylic organic binders such as ethyl cellulose and methyl cellulose may be used for handling. .
본 발명의 일 실시형태에 의하면, 상기 접합층(103)의 두께는 5 내지 100㎛ 범위 내일 수 있다. 상기 접합층(103)의 두께가 5㎛ 미만이면, 베이스층(102)과 금속박(104)의 밀착력에 문제점이 있고, 상기 접합층(103)의 두께가 100㎛ 초과이면 접합층(103) 두께로 인해 금속박(104)에서 세라믹 기판(101)으로 열 전달이 어려움에 따라 세라믹 회로 기판(100)의 효율이 떨어지는 문제점이 있다.According to one embodiment of the invention, the thickness of the bonding layer 103 may be in the range of 5 to 100㎛. If the thickness of the bonding layer 103 is less than 5 μm, there is a problem in the adhesion between the base layer 102 and the metal foil 104. If the thickness of the bonding layer 103 is more than 100 μm, the bonding layer 103 is thick. Due to the difficulty in heat transfer from the metal foil 104 to the ceramic substrate 101, the efficiency of the ceramic circuit board 100 is lowered.
상기 접합층(103)은 베이스층(102)과 금속박(104) 사이에 배치되어, 접합층(103)또는 접합층(103) 및 금속박(104)에 대한 에너지선 조사 및/또는 열처리에 의해 상기 금속박(104)을 베이스층(102)을 포함하는 세라믹 기판(101)에 접합시킬 수 있으며, 열처리를 이용하는 경우에는 300 내지 900℃의 온도 범위에서 수행할 수 있는데, 종래 Ti, Ag 및 Cu를 납재 페이스트로 하여 금속층과 세라믹 기판을 열처리로 접합시키는 경우에는 1100℃ 이상 온도에서의 열처리가 필요하였던 반면, 본 발명의 세라믹 회로기판(100)은 저온에서의 열처리로도 우수한 기계적 접합 물성을 나타낸다. The bonding layer 103 is disposed between the base layer 102 and the metal foil 104, and is formed by the energy ray irradiation and / or heat treatment of the bonding layer 103 or the bonding layer 103 and the metal foil 104. The metal foil 104 may be bonded to the ceramic substrate 101 including the base layer 102, and in the case of using a heat treatment, the metal foil 104 may be performed in a temperature range of 300 ° C. to 900 ° C. When the metal layer and the ceramic substrate are bonded by heat treatment as a paste, heat treatment at a temperature of 1100 ° C. or higher is required, whereas the ceramic circuit board 100 of the present invention exhibits excellent mechanical bonding properties even by heat treatment at low temperatures.
본 발명의 세라믹 회로기판을 제조하는 방법은,The method of manufacturing the ceramic circuit board of the present invention,
세라믹 기판 상에 베이스층을 배치하고, Placing a base layer on a ceramic substrate,
상기 베이스층 상에 접합층을 배치하며,Disposing a bonding layer on the base layer,
상기 접합층 상에 금속박을 배치하고, 상기 세라믹 기판 상의 상기 베이스층, 상기 접합층에 에너지선 조사 및 열처리의 적어도 하나를 실시하는 것을 포함할 수 있다.The metal foil may be disposed on the bonding layer, and at least one of energy ray irradiation and heat treatment may be performed on the base layer and the bonding layer on the ceramic substrate.
상기 베이스층 및 접합층의 배치에 있어서 적어도 어느 하나는 스퍼터링법, 인쇄법 또는 화학도금법으로 형성될 수 있는데, 그 중에서도 DC 스퍼터링법이 가장 적합하다.At least one of the base layer and the bonding layer may be formed by a sputtering method, a printing method, or a chemical plating method, among which DC sputtering is most suitable.
본 발명의 일 실시형태에 의하면, 상기 베이스층, 접합층 및 금속박은 세라믹 기판 상의 한쪽 면에서만 형성될 수 있지만, 이에 제한되지 않으며, 도 2에서 보는 바와 같이, 세라믹 기판의 양쪽 면 모두에서 상기 층들이 형성될 수 있다. 예를 들어, 도 2에 도시한 바와 같이, 세라믹 기판(201)의 양 면에 베이스층 (202), 접합층(303) 및 금속박(204)이 각각 형성될 수 있다. 구체적으로, 세라믹 기판(201)의 한쪽 면에 베이스층(202), 접합층(203) 및 금속박(204)을 형성하고, 이와 동시에 또는 그 후에, 세라믹 기판(201)의 다른 쪽 면에 베이스층(202), 접합층(203) 및 금속박(204)을 형성할 수 있다. According to one embodiment of the invention, the base layer, the bonding layer and the metal foil may be formed on only one side on the ceramic substrate, but is not limited thereto, as shown in FIG. 2, the layer on both sides of the ceramic substrate Can be formed. For example, as shown in FIG. 2, the base layer 202, the bonding layer 303, and the metal foil 204 may be formed on both surfaces of the ceramic substrate 201. Specifically, the base layer 202, the bonding layer 203, and the metal foil 204 are formed on one side of the ceramic substrate 201, and at the same time or after that, the base layer on the other side of the ceramic substrate 201. 202, the bonding layer 203, and the metal foil 204 can be formed.
도 2에서는 세라믹 기판(201)을 중심으로 양쪽 면에 형성되는 베이스층(202), 접합층(203), 및 금속박(204)을 설명의 편의를 위하여 동일 부호로 기재한 것이며, 상기 양쪽 면에 형성되는 각각의 베이스층(202), 접합층(203), 및 금속박(204)의 구성 물질은 본 발명의 범위 내를 만족하는 것이라면 족하고, 상호 완전 동일한 것으로 한정하는 것은 아니다.In FIG. 2, the base layer 202, the bonding layer 203, and the metal foil 204 formed on both surfaces of the ceramic substrate 201 are denoted by the same reference numerals for convenience of description. The constituent materials of each of the base layer 202, the bonding layer 203, and the metal foil 204 to be formed are sufficient as long as they satisfy the scope of the present invention, and are not limited to the exact same.
상기 방법으로 제조한 세라믹 회로기판과 종래 방법으로 제조한 세라믹 회로기판의 TCT 특성, Void 발생률, 접합강도 및 기판 휨량(warpage) 등의 물성을 테스트해 보았다.Physical properties such as TCT characteristics, void incidence, bonding strength, and warpage of the ceramic circuit board manufactured by the above method and the ceramic circuit board manufactured by the conventional method were tested.
TCT(thermal cycle test: 열 싸이클 테스트)는 구체적으로 -55℃ 내지 150℃의 온도로 계속 싸이클을 돌려 박리현상(delamination)이 몇 싸이클째 나타나는지를 조사해 보는 방법에 의해 구하였고, 박리현상은 초음파 현미경(scanning acoustic microscopy)으로 확인하였다.The thermal cycle test (TCT) was obtained by examining the number of cycles of delamination by continuously rotating the cycle at a temperature of -55 ° C to 150 ° C. It was confirmed by (scanning acoustic microscopy).
또한, Void 발생률은 대형 세라믹 금속 접합 기판에 30등분을 하여 Void 발생 영역을 카운팅하였으며, 접합강도 테스트는 UTM(universal testing machine)으로 실시하였고, 기판 휨량 테스트는 3차원 측정기로 대형 세라믹 금속접합 기판의 휨량을 측정하였다. In addition, the void incidence was divided into 30 equal parts on the large ceramic metal bonded substrate, and the void generated area was counted. The bond strength test was performed with a universal testing machine (UTM). The amount of warpage was measured.
이하, 본 발명을 하기와 같은 실시예에 의거하여 더욱 상세하게 설명한다. 단, 하기 실시예들은 본 발명을 예시하기 위한 것일 뿐, 본 발명이 이들 실시예들에 의해 한정되는 것은 아니다.Hereinafter, the present invention will be described in more detail based on the following examples. However, the following examples are only for illustrating the present invention, and the present invention is not limited by these examples.
실시예 1-3 및 비교예 1: 금속접합 알루미나(Al2O3) 기판에 대한 물성 평가Example 1-3 and Comparative Example 1: Evaluation of Physical Properties of Metal Bonded Alumina (Al 2 O 3 ) Substrate
상술한 본 발명의 세라믹 회로기판 제조방법에 따라 제조하였는데, 세라믹 기판으로서는 테이스 캐스팅 방법에 의해 제조된 두께 약 0.38mm 의 알루미나 기판을 사용하였으며, 베이스층으로서는 NixCr1 -x(x=0.8)/Cu의 층을 스퍼터링법, 페이스트 인쇄법 및 화학도금법으로 각각 형성하였고, 접합층으로서 Cu 70중량부, Sn 10중량부, P 5중량부, In 5중량부 및 터피네올 10 중량부로 이루어진 조성물을 사용하였으며, 금속박으로는 평균 표면 조도(Rz)가 1.5㎛인 구리 금속박을 사용하였다(실시예 1 내지 3). 이와는 대조적으로, 비교예 1에서는 종래의 금속접합 세라믹 기판 제조방법인 직접 접합법을 사용하여 세라믹 기판에 베이스층 없이 Cu층을 직접 접합한 기판을 대상으로 하였다. 상기 실시예 1 내지 3에 사용된 세라믹 회로기판 중 베이스층의 두께는 각각 0.15㎛였고, 접합층의 두께는 50㎛였으며, 구리 금속박의 두께는 300㎛였다.The ceramic circuit board was manufactured according to the above-described method of manufacturing the ceramic circuit board. As the ceramic substrate, an alumina substrate having a thickness of about 0.38 mm manufactured by the die casting method was used, and Ni x Cr 1 -x (x = 0.8) was used as the base layer. ) / Cu layer was formed by sputtering method, paste printing method and chemical plating method, respectively. The bonding layer was composed of 70 parts by weight of Cu, 10 parts by weight of Sn, 5 parts by weight of P, 5 parts by weight of In and 10 parts by weight of terpineol. The composition was used, and as metal foil, the copper metal foil whose average surface roughness (Rz) is 1.5 micrometers was used (Examples 1-3). In contrast, in Comparative Example 1, a substrate in which a Cu layer was directly bonded to a ceramic substrate without a base layer by using a direct bonding method, which is a conventional method of manufacturing a metal bonded ceramic substrate, was used. In the ceramic circuit boards used in Examples 1 to 3, the thickness of the base layer was 0.15 μm, the thickness of the bonding layer was 50 μm, and the thickness of the copper metal foil was 300 μm.
각각의 경우에 따른 TCT 횟수, Void 발생률, 접합강도 및 기판 휨량을 측정하여 하기 표 1에 나타내었다.In each case, the number of TCTs, the incidence of voids, the bond strength, and the amount of warpage of the substrate were measured.
구분division 실시예 1Example 1 실시예 2Example 2 실시예 3Example 3 비교예 1Comparative Example 1
베이스층(NixCr1 -x(x=0.8)/Cu)형성방법Base layer (Ni x Cr 1 -x (x = 0.8) / Cu) formation method 스퍼터링Sputtering 페이스트 인쇄법Paste printing method 화학도금법Chemical plating 베이스층없음No base layer
접합층형성방법Bonding layer formation method Cu/Sn/P/In/terpineol 조성물을 이용한브레이징 솔더Brazing Solder Using Cu / Sn / P / In / terpineol Compositions Cu 직접 접합Cu direct bonding
TCT 횟수(회)TCT Count (times) 1,000회1,000 1,000회1,000 100회100 times 60회60 times
Void 발생률(%)Void Incidence (%) 0.10.1 0.50.5 0.10.1 1010
접합강도(N/mm)Bond strength (N / mm) 2020 2020 1010 66
기판 휨량(mm)Substrate Warpage (mm) 0.50.5 0.50.5 0.60.6 1One
*TCT 테스트: -55℃ 내지 150℃, 1,000Cycle* TCT test: -55 ℃ to 150 ℃, 1,000Cycle
*Void 발생률: Void 발생면적/전체면적 × 100%* Void occurrence rate: Void occurrence area / total area × 100%
*기판 휨량(warpage) 테스트: 최대 휨량 - 최소 휨량* Board warpage test: Maximum warpage-minimum warpage
상기 표 1에서 보는 바와 같이, 세라믹 기판과 Cu 금속을 직접 접합하는 종래의 방법에 의해 얻어진 세라믹 회로기판(비교예 1)에 비해, 세라믹 기판 상에 스퍼터링법, 페이스트 인쇄법, 화학도금법 등으로 베이스층을 형성한 후, 세라믹 기판과 Cu박을 접합시킨 본 발명의 세라믹 회로기판의 경우(실시예 1 내지 3)에 TCT, Void 발생률, 접합강도, 기판휨량 등 전반적인 물성이 우수하였다.As shown in Table 1, compared to the ceramic circuit board (Comparative Example 1) obtained by the conventional method of directly bonding the ceramic substrate and the Cu metal, the base is sputtered, paste printed, chemical plating, etc. on the ceramic substrate. After the layer was formed, the ceramic circuit board of the present invention in which the ceramic substrate was bonded to Cu foil (Examples 1 to 3) exhibited excellent overall physical properties such as TCT, void generation rate, bonding strength, and substrate warping amount.
따라서, 본 발명의 금속접합 세라믹 회로기판은 기계적 접합 물성 및 열적신뢰성이 종래의 금속접합 세라믹 회로기판에 비해 우수하여, 전력반도체용 방열기판과 같이 가혹 환경에서도 응용할 수 있다.Therefore, the metal bonded ceramic circuit board of the present invention has excellent mechanical bonding properties and thermal reliability compared to the conventional metal bonded ceramic circuit board, and can be applied in harsh environments such as heat sinks for power semiconductors.
[부호의 설명][Description of the code]
100, 200 세라믹 회로기판100, 200 ceramic circuit board
101, 201 세라믹 기판101, 201 ceramic substrate
102, 202 베이스층102, 202 Base Layer
103, 203 접합층103, 203 bonding layer
104, 204 금속박104, 204 metal foil

Claims (18)

  1. 세라믹 기판;Ceramic substrates;
    상기 세라믹 기판 상에 배치된 베이스층; A base layer disposed on the ceramic substrate;
    상기 베이스층 상에 배치된 접합층; 및A bonding layer disposed on the base layer; And
    상기 접합층 상에 배치된 금속박을 포함하는 세라믹 회로기판.Ceramic circuit board comprising a metal foil disposed on the bonding layer.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 세라믹 기판은 알루미나(Al2O3), 질화알루미늄(AlN), 질화규소(Si3N4) 또는 탄화규소(SiC), 및 지르코니아(ZrO2)로 이루어진 군에서 선택되는 1종 이상을 포함하는 것인 세라믹 회로기판.The ceramic substrate includes at least one selected from the group consisting of alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ) or silicon carbide (SiC), and zirconia (ZrO 2 ). Ceramic circuit board.
  3. 청구항 1에 있어서,The method according to claim 1,
    상기 베이스층은 Cu, Ni, Cr, Ti, W, Mn, 및 Mo로 이루어진 군에서 선택되는 1종 이상을 포함하는 것인 세라믹 회로기판.The base layer is a ceramic circuit board comprising at least one selected from the group consisting of Cu, Ni, Cr, Ti, W, Mn, and Mo.
  4. 청구항 1에 있어서,The method according to claim 1,
    상기 베이스층의 두께는 0.015 내지 0.5㎛ 범위인 것인 세라믹 회로기판.The thickness of the base layer is a ceramic circuit board in the range of 0.015 to 0.5㎛.
  5. 청구항 1에 있어서,The method according to claim 1,
    상기 금속박은 Cu, Au, Ni 및 Ag로 이루어진 군에서 선택되는 1종 이상을 포함하는 것인 세라믹 회로기판.The metal foil is a ceramic circuit board containing at least one selected from the group consisting of Cu, Au, Ni and Ag.
  6. 청구항 1에 있어서,The method according to claim 1,
    상기 금속박의 두께는 100 내지 600㎛ 범위인 것인 세라믹 회로기판.The thickness of the metal foil is a ceramic circuit board in the range of 100 to 600㎛.
  7. 청구항 1에 있어서,The method according to claim 1,
    상기 금속박의 적어도 어느 하나의 표면의 표면 조도(Rz)가 3.0㎛ 이하인 것인 세라믹 회로기판.The surface roughness (Rz) of at least one surface of the said metal foil is 3.0 micrometers or less.
  8. 청구항 1에 있어서,The method according to claim 1,
    상기 접합층은 Cu, Sn, Ni, P, Ag, Zn, Ti, 및 In 로 이루어진 군에서 선택되는 1종 이상을 포함하는 것인 세라믹 회로기판.The bonding layer is a ceramic circuit board comprising one or more selected from the group consisting of Cu, Sn, Ni, P, Ag, Zn, Ti, and In.
  9. 청구항 8에 있어서,The method according to claim 8,
    상기 접합층은 조성물로서,The bonding layer is a composition,
    Cu 60 내지 80 중량부,60 to 80 parts by weight of Cu,
    Sn 10 내지 30 중량부,Sn 10 to 30 parts by weight,
    P 3 내지 15 중량부,P 3 to 15 parts by weight,
    In 3 내지 15 중량부, 및 In 3 to 15 parts by weight, and
    유기 비히클 잔부를 포함하는 것인 세라믹 회로기판.Ceramic circuit board comprising the organic vehicle balance.
  10. 청구항 9에 있어서,The method according to claim 9,
    상기 유기 비히클은 메탄올, 에탄올, 터피네올 및 톨루엔으로 이루어진 군으로부터 선택되는 적어도 하나의 유기 용매, 및 선택적으로 셀룰로오스계 및 아크릴계 중 적어도 하나의 유기 결합제를 포함하는 것인 세라믹 회로기판.Wherein the organic vehicle comprises at least one organic solvent selected from the group consisting of methanol, ethanol, terpineol and toluene, and optionally an organic binder of at least one of cellulose and acrylic.
  11. 청구항 1에 있어서,The method according to claim 1,
    상기 접합층의 두께는 100 내지 600㎛ 범위인 것인 세라믹 회로기판.The thickness of the bonding layer is a ceramic circuit board in the range of 100 to 600㎛.
  12. 청구항 1 내지 청구항 11 중 어느 한 항의 세라믹 회로기판 상에 전자부품이 실장되어 있는 전자 소재.An electronic material in which an electronic component is mounted on a ceramic circuit board according to any one of claims 1 to 11.
  13. 세라믹 기판 상에 베이스층을 배치하고,Placing a base layer on a ceramic substrate,
    상기 베이스층 상에 접합층을 배치하며,Disposing a bonding layer on the base layer,
    상기 접합층 상에 금속박을 배치하는 것을 포함하며,It includes disposing a metal foil on the bonding layer,
    상기 접합층에 에너지선 조사 및 열처리 중 적어도 하나를 실시하는 것인, 세라믹 회로기판의 제조방법.At least one of energy ray irradiation and heat treatment to the bonding layer, manufacturing method of a ceramic circuit board.
  14. 청구항 13에 있어서,The method according to claim 13,
    상기 베이스층 및 접합층 중 적어도 어느 하나는 스퍼터링법, 인쇄법 및 화학도금법으로 이루어진 군으로부터 선택되는 방법에 의해서 형성되는 것인 세라믹 회로기판의 제조방법.At least one of the base layer and the bonding layer is formed by a method selected from the group consisting of a sputtering method, a printing method and a chemical plating method.
  15. 청구항 13에 있어서,The method according to claim 13,
    상기 베이스층 및 접합층 중 적어도 어느 하나는 DC 스퍼터링법으로 형성되는 것인 세라믹 회로기판의 제조방법.At least one of the base layer and the bonding layer is formed by a DC sputtering method.
  16. 청구항 13에 있어서,The method according to claim 13,
    상기 접합층은, The bonding layer,
    Cu 60 내지 80 중량부,60 to 80 parts by weight of Cu,
    Sn 10 내지 30 중량부,Sn 10 to 30 parts by weight,
    P 3 내지 15 중량부,P 3 to 15 parts by weight,
    In 3 내지 15 중량부, 및In 3 to 15 parts by weight, and
    유기 비히클 잔부를 포함하는 조성물인 것인 세라믹 회로기판의 제조방법.A method of manufacturing a ceramic circuit board, which is a composition comprising an organic vehicle balance.
  17. 청구항 16에 있어서,The method according to claim 16,
    상기 유기 비히클은 메탄올, 에탄올, 터피네올 및 톨루엔으로 이루어진 군으로부터 선택되는 적어도 하나의 유기 용매, 및 선택적으로 셀룰로오스계 및 아크릴계 중 적어도 하나의 유기 결합제를 포함하는 것인 세라믹 회로기판의 제조방법.Wherein said organic vehicle comprises at least one organic solvent selected from the group consisting of methanol, ethanol, terpineol and toluene, and optionally at least one organic binder of cellulose and acrylic.
  18. 청구항 13에 있어서,The method according to claim 13,
    상기 열처리는 300℃ 내지 900℃의 온도 범위에서 수행되는 것인 세라믹 회로기판의 제조방법.The heat treatment is a method of manufacturing a ceramic circuit board is carried out in a temperature range of 300 ℃ to 900 ℃.
PCT/KR2016/009703 2015-10-23 2016-08-31 Ceramic circuit board and manufacturing method therefor WO2017069398A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2015-0148152 2015-10-23
KR1020150148152A KR101929613B1 (en) 2015-10-23 2015-10-23 Ceramic circuit board and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2017069398A1 true WO2017069398A1 (en) 2017-04-27

Family

ID=58557648

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2016/009703 WO2017069398A1 (en) 2015-10-23 2016-08-31 Ceramic circuit board and manufacturing method therefor

Country Status (2)

Country Link
KR (1) KR101929613B1 (en)
WO (1) WO2017069398A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164991A (en) * 1998-11-27 2000-06-16 Kyocera Corp Ceramic circuit board
JP2010109068A (en) * 2008-10-29 2010-05-13 Kyocera Corp Wiring board, and method of manufacturing the same
JP2013098404A (en) * 2011-11-02 2013-05-20 Panasonic Corp Ceramic substrate and electronic component module using the same
KR20140127228A (en) * 2012-02-01 2014-11-03 미쓰비시 마테리알 가부시키가이샤 Substrate for power modules, substrate with heat sink for power modules, power module, method for producing substrate for power modules, and paste for bonding copper member
JP2015062953A (en) * 2013-08-26 2015-04-09 三菱マテリアル株式会社 Joined body, and substrate for power module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349098A (en) * 1999-06-04 2000-12-15 Sumitomo Electric Ind Ltd Bonded body of ceramic substrate and semiconductor device, and its manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164991A (en) * 1998-11-27 2000-06-16 Kyocera Corp Ceramic circuit board
JP2010109068A (en) * 2008-10-29 2010-05-13 Kyocera Corp Wiring board, and method of manufacturing the same
JP2013098404A (en) * 2011-11-02 2013-05-20 Panasonic Corp Ceramic substrate and electronic component module using the same
KR20140127228A (en) * 2012-02-01 2014-11-03 미쓰비시 마테리알 가부시키가이샤 Substrate for power modules, substrate with heat sink for power modules, power module, method for producing substrate for power modules, and paste for bonding copper member
JP2015062953A (en) * 2013-08-26 2015-04-09 三菱マテリアル株式会社 Joined body, and substrate for power module

Also Published As

Publication number Publication date
KR101929613B1 (en) 2018-12-14
KR20170047720A (en) 2017-05-08

Similar Documents

Publication Publication Date Title
CN101416570B (en) Multilayer ceramic substrate, method for producing the same and electronic component
WO2010011009A1 (en) Metal substrate for an electronic component module, module comprising same, and method for manufacturing a metal substrate for an electronic component module
WO2010114238A2 (en) Circuit board, and method for manufacturing same
WO2011111989A2 (en) Metal-bonded ceramic substrate
US20200185320A1 (en) Ceramic circuit substrate
WO2020159031A1 (en) Power semiconductor module package and manufacturing method of same
WO2021162369A1 (en) Power module and method for manufacturing same
WO2022045694A1 (en) Ceramic circuit board for dual-side cooling power module, method for preparing same, and dual-side cooling power module having same
WO2014073039A1 (en) Substrate for light emitting diodes
CN110843272A (en) Ceramic copper-clad plate and preparation process and application thereof
Wei et al. A comparison study for metalized ceramic substrate technologies: For high power module applications
JP2004119568A (en) Ceramic circuit board
WO2017069398A1 (en) Ceramic circuit board and manufacturing method therefor
JP6125527B2 (en) Light emitting diode substrate and method for manufacturing light emitting diode substrate
WO2022145869A1 (en) Method of manufacturing power semiconductor module, and power semiconductor module manufactured thereby
WO2020009338A1 (en) Metallized ceramic substrate and method for manufacturing same
WO2017155249A1 (en) Lamination system for manufacturing ceramic substrate, and method for manufacturing ceramic substrate using same
WO2021235721A1 (en) Method for manufacturing ceramic circuit board
WO2017122966A1 (en) Ceramic circuit board and method for manufacturing same
WO2009145461A2 (en) Substrate for ceramic printed circuit board and method for manufacturing the substrate
JP3794454B2 (en) Nitride ceramic substrate
WO2017065407A1 (en) Ceramic circuit board and manufacturing method therefor
WO2024144121A1 (en) Ceramic substrate for power module and power module comprising same
WO2023128687A1 (en) Nickel alloy composition for copper-bonding layer for copper-bonded nitride substrate
KR102621334B1 (en) Manufacturing method of ceramic heat dissipation substrate simplified masking process

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16857656

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16857656

Country of ref document: EP

Kind code of ref document: A1