WO2017051654A1

WO2017051654A1 - Ringing suppression circuit

Info

Publication number: WO2017051654A1
Application number: PCT/JP2016/074732
Authority: WO
Inventors: 卓矢本田; 磯村　博文; 岸上　友久; 寛之森; 森　康裕; 佑樹堀井
Original assignee: 株式会社デンソー; 株式会社日本自動車部品総合研究所
Priority date: 2015-09-24
Filing date: 2016-08-25
Publication date: 2017-03-30
Also published as: MY187665A

Abstract

A ringing suppression circuit that is connected to a transmission line for transmitting a differential signal changing between binary levels of High and Low by means of a pair of high and low potential side signal lines and that suppresses ringing incident to the transmission of the differential signal comprises: a line switching element (N4, P4) connected between the pair of signal lines; and a control unit (9) that, upon detection of a change in level of the differential signal from High to Low, turns on the line switching element, fixes the on-state and, after clocking a certain time, cancels the on-state.

Description

Ringing suppression circuit

Cross-reference of related applications

This application is based on Japanese Patent Application No. 2015-186796 filed on September 24, 2015 and Japanese Patent Application No. 2016-80325 filed on April 13, 2016, which is described herein. Incorporate content.

The present disclosure relates to a ringing suppression circuit connected to a transmission line that transmits a differential signal.

When a digital signal is transmitted through a transmission line, a part of the signal energy is reflected at the timing when the signal level changes on the receiving side, thereby causing waveform distortion such as overshoot or undershoot, that is, ringing. There are problems that arise. Conventionally, various proposals have been made on techniques for suppressing waveform distortion. For example, Patent Document 1 discloses a technology for suppressing ringing by matching impedance only for a certain period that does not affect communication when the voltage level of a transmission line transitions between low and high as shown in FIG. Yes.

In CAN (Controller Area Network, registered trademark), which is a kind of in-vehicle communication, low level and high level differential signals, that is, data bits are referred to as recessive and dominant, respectively. Here, as shown in FIG. 23, it is assumed that the ringing waveform changes with a large amplitude of (1) dominant → (2) recessive → (3) dominant → (4) recessive.

Then, in the configuration of Patent Document 1, the ringing suppression operation is started in response to the first change from (1) to (2), and when the predetermined time has elapsed, the suppression operation is stopped in the next (3). Then, the ringing suppression operation is restarted in response to the next change to (4). For this reason, the time from the start of the first suppression operation in (2) to the stop after (4) is prolonged. Therefore, if the next bit; dominant is transmitted during the suppression operation, the current is drawn and the signal waveform is distorted.

Japanese Patent No. 5498527

This disclosure is intended to provide a ringing suppression circuit that can always perform a ringing suppression operation according to a level change of a differential signal for a certain period of time.

In the first aspect of the present disclosure, a pair of high-potential side signal lines and low-potential side signal lines are connected to a transmission line that transmits a differential signal that changes to a binary level of high and low, A ringing suppression circuit that suppresses ringing that occurs during transmission detects an interline switching element connected between the pair of signal lines, and detects that the level of the differential signal has changed from high to low. A control unit that turns on the switching element to fix the on state and releases the on state after measuring a predetermined time.

According to the ringing suppression circuit described above, when the control unit detects that the level of the differential signal has changed from high to low, the line switching element is turned on to fix the state, and after measuring a certain time, The on state is released. With this configuration, once the line switching element is turned on according to the level change of the differential signal, the state is fixed. Therefore, even if the level change of the differential signal occurs again thereafter, it is affected. Without any problem, the line-to-line switching element reliably maintains the ON state for a certain period of time. Thereby, it is possible to prevent the ringing suppression period from being unnecessarily prolonged and to perform signal transmission stably.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram illustrating a configuration of a ringing suppression circuit according to the first embodiment. FIG. 2 is an operation state transition diagram (part 1). FIG. 3 is a transition diagram (part 2) of the operating state. FIG. 4 is an operation state transition diagram (part 3). FIG. 5 is an operation state transition diagram (Part 4). FIG. 6 is an operation timing chart (part 1). FIG. 7 is an operation timing chart (part 2). FIG. 8 is an operation timing chart (part 3). FIG. 9 is an operation timing chart corresponding to a part of FIG. 8 in the case of the configuration of Patent Document 1. FIG. 10 is a diagram illustrating a configuration of a ringing suppression circuit according to the second embodiment. FIG. 11 is an operation timing chart (part 1). FIG. 12 is an operation timing chart (part 2). FIG. 13 is an operation timing chart (part 3). FIG. 14 is a diagram showing a configuration of the ringing suppression circuit according to the third embodiment. FIG. 15 is a diagram showing the configuration of the ringing suppression circuit according to the fourth embodiment. FIG. 16 is a diagram illustrating a configuration of a ringing suppression circuit according to the fifth embodiment. FIG. 17 is a diagram illustrating a configuration of a ringing suppression circuit according to the sixth embodiment. FIG. 18 is a diagram (part 1) illustrating another configuration of the line-to-line switching element; FIG. 19 is a diagram (part 2) illustrating another configuration of the line switching element; FIG. 20 is a diagram (part 3) illustrating another configuration of the line switching element; FIG. 21 is a diagram (part 4) illustrating another configuration of the line switching element; FIG. 22 is an operation timing chart corresponding to a part of FIG. 11 in the case of the configuration of Patent Document 1. FIG. 23 is an operation timing chart corresponding to a part of FIG.

(First embodiment)
As shown in FIG. 1, a communication bus 1 corresponding to a transmission line includes a high-potential side signal line 1H and a low-potential side signal line 1L. The low-potential side signal line 1L includes five N-channel MOSFET_N0 to N4 sources. Is connected. The drain of FET_N4, which is a line switching element, is connected to the high potential side signal line 1H. The drain of the FET_N0 is connected to the high potential side signal line 1H via the resistance element R0, and is connected to the gates of the FET_N1 and N3. FET_N0 to N3 correspond to first to fourth switching elements. The source of the FET corresponds to a potential reference side conduction terminal, the drain corresponds to a non-reference side conduction terminal, and the gate corresponds to a conduction control terminal.

The source of the P-channel MOSFET_P1 and P2 is connected to the power supply line 2 to which the power supply VCC is supplied, and the drain of the FET_P1 is connected to the drain of the FET_N1 and the gate of the FET_N2 through the resistance element R1. FET_P1 and P2 correspond to the fifth and sixth switching elements. The drain of the FET_P2 is connected to the gate of the FET_N0, the drains of the FET_N2 and N3, and the gate of the FET_N4 through the resistance element R2.

A series circuit of a resistance element R3 and an N-channel MOSFET_N6 is connected between the power supply line 2 and the low potential side signal line 1L, and the gate of the FET_N6 is connected to the gate of the FET_N0. A series circuit of resistance elements R4 and R5 is connected between the power supply line 2 and the ground, and a common connection point thereof is connected to a non-inverting input terminal of the comparator COMP1. The inverting input terminal of the comparator COMP1 is connected to the drain of the FET_N6. FET_N6 corresponds to a detection switching element.

The output terminal of the comparator COMP1 is connected to the clock terminal C of the D flip-flop FF1 corresponding to the second flip-flop. The resistance elements R3 to R5, FET_N6, and the comparator COMP1 constitute an ON confirmation circuit 3 corresponding to the second set signal output unit.

A series circuit of resistance elements R6 to R8 is connected between the high potential side signal line 1H and the low potential side signal line 1L, and the common connection point of the resistance elements R6 and R7 is a non-inverting input terminal of the comparator COMP2. The common connection point of the resistance elements R7 and R8 is connected to the inverting input terminal. The output terminal of the comparator COMP2 is connected to the gate of the N-channel MOSFET_N7 via the inverter gate INV0. The resistance elements R6 to R7, the comparator COMP2, and the inverter gate INV0 constitute a comparison circuit 4 corresponding to the first set signal output unit. FET_N7 also corresponds to the first set signal output unit.

The source of FET_N7 is connected to the ground, and the drain is connected to the clock terminal C of the D flip-flop FF2 corresponding to the first flip-flop via the buffer BUF1. A series circuit of a resistor element R10 and a capacitor C1 is connected between the power supply line 2 and the ground, and a common connection point thereof is connected to the drain of the FET_N7. The resistor element R10 and the capacitor C1 constitute a delay circuit 5 corresponding to the detection mask unit. The input terminals D of the D flip-flops FF2 and FF1 are connected to the power supply line 2 via resistance elements R9 and R11, respectively.

The output terminal Q of the D flip-flop FF1 is connected to the gate of the N-channel MOSFET_N8 via the inverter gate INV2. The source of the FET_N8 is connected to the ground, and the drain is connected to one input terminal of the NOR gate NOR2 via the buffer BUF2. A series circuit of a resistor element R12 and a capacitor C2 is connected between the power supply line 2 and the ground, and a common connection point thereof is connected to the drain of the FET_N8. The resistor element R12 and the capacitor C2 constitute a delay circuit 6. A high-active reset signal RST is applied to the other input terminal of the NOR gate NOR2, and the output terminal of the NOR gate NOR2 is connected to the negative logic reset terminal RB of the D flip-flop FF2.

The output terminal Q of the D flip-flop FF2 is connected to the gate of the FET_P1, and is also connected to the gate of the FET_P2 through the inverter gate INV1. Further, the output terminal Q of the D flip-flop FF2 is connected to one of the input terminals of the NOR gate NOR1 via the inverter gate INV3. A reset signal RST is applied to the other input terminal of the NOR gate NOR1, and an output terminal of the NOR gate NOR1 is connected to a negative logic reset terminal RB of the D flip-flop FF1.

In the above, the

delay circuits

5 and 6, the D flip-flops FF1 and FF2, and their peripheral circuits constitute the ON state holding circuit 7. Further, the FET_N0 to N5, P1 and P2, the inverter gate INV1, and the resistance element R0 constitute an on setting unit 8. Further, the control unit 9 is configured by removing the FET_N4 in the above configuration, and the ringing suppression circuit 10 is configured by the FET_N4 and the control unit 9.

Next, the operation of this embodiment will be described. In the following, assuming that the present embodiment is applied to the above-mentioned CAN, the low level of the differential signal is referred to as “recessive” and the high level is referred to as “dominant”.

<Initial state; recessive>
As shown in FIG. 2, both the D flip-flops FF1 and FF2 are reset when the reset signal RST is once activated in the initial state when the power is turned on. Thereby, FET_P1 is turned on, FET_P2 is turned off, FET_N2 is turned on, and FET_N0, N1, N3, N4, and N6 are turned off. Then, the output signal of the ON confirmation circuit 3 becomes low level. In the figure, ◯ indicates an ON state element or an energized element, and X indicates an OFF state element or an unenergized element.

Further, since FET_N7 and N8 are turned ON, the reset of the D flip-flop FF2 is released, but the output signal of the inverter gate INV3 is at a high level, so the D flip-flop FF1 is maintained in the reset state. At this time, if the communication bus 1 is in a recessive state not driven by the transmission node, the output signal of the comparison circuit 4 becomes high level. Therefore, neither D flip-flop FF1 nor FF2 is triggered and the reset state is maintained.

<Recessive → Dominant>
Next, as shown in FIG. 3, when the communication bus 1 is driven by the transmission node and the differential signal becomes the dominant level, a current flows through the series circuit of the resistance elements R6 to R8, and the output signal of the comparison circuit 4 is low. Become a level. Then, since FET_N7 is turned off, charging of the capacitor C1 is started. Thereafter, when the time corresponding to the RC time constant elapses and the terminal voltage of the capacitor C1 rises to a high level, the D flip-flop FF2 is triggered and the output terminal Q becomes a high level. Thereby, FET_P1 is turned OFF and FET_P2 is turned ON, FET_N2 is turned OFF, and FET_N1 and N3 are turned ON. Further, the reset of the D flip-flop FF1 is released.

That is, when the communication bus 1 changes to a dominant level, the delay circuit 5 has an effect of masking detection of the change by the D flip-flop FF1 for a time corresponding to the RC time constant. The above time corresponds to the “dominant mask time” shown in FIG.

<Dominant → Recessive (Start of suppression operation)>
Next, as shown in FIG. 4, when the transmission node stops driving the communication bus 1 and the differential signal returns to the recessive level, the gates of the FET_N1 and N3 become the low level, and these turn off. At this time, since FET_P2 is ON, the gates of FET_N1, N4, and N6 are set to the high level via the resistance element R2, and these are turned ON. That is, when the FET_N4 is turned on, the impedance of the communication bus 1 is lowered, and the ringing suppression operation is started. At this time, the output signals of the ON confirmation circuit 3 and the comparison circuit 4 are both at a high level. As a result, the D flip-flop FF1 is triggered, the FET_N8 is turned off, and charging of the capacitor C2 is started.

<Recessive (Suppression operation completed)>
Thereafter, when a time corresponding to the RC time constant has elapsed and the terminal voltage of the capacitor C2 has risen to a high level, the D flip-flop FF2 is reset via the NOR gate NOR2. Then, as shown in FIG. 5, the output terminal Q turns to the low level, the FET_P1 is turned on, the FET_P2 is turned off, and the state returns to the same state as the initial state shown in FIG. Is done. That is, when the ringing suppression operation is started from the time when the differential signal changes from dominant to recessive as shown in FIG. 4, the delay time given according to the RC time constant of the delay circuit 6 elapses from that time. The process ends at the time (see FIG. 6).

As shown in FIG. 7, when a dominant level noise occurs during the ringing suppression operation, if the noise generation period is shorter than the dominant mask period, the level change of the communication bus 1 is not detected by the D flip-flop FF2. . Therefore, the ringing suppression operation is executed in the same manner as in the case shown in FIG.

Further, as shown in FIG. 8, the same is true when recessive level noise occurs in a dominant state. If the noise generation period is shorter than the dominant mask period, the level change of the communication bus 1 is D flip-flop FF2. Is not detected by. Therefore, as shown in FIG. 9 corresponding to the configuration of Patent Document 1, no extra ringing suppression operation is started.

As described above, according to the present embodiment, when the control unit 9 detects that the differential signal transmitted through the transmission line 1 has changed from dominant to recessive, the control unit 9 turns on the FET_N4 to fix the state, and delays the delay. After a certain time is counted by the circuit 6, the ON state is released. With this configuration, once the FET_N4 is turned on according to the level change of the differential signal, the state is fixed. Therefore, even if the level change of the differential signal occurs again, the FET_N4 is not affected. Reliably maintains the ON state for a certain period of time. Thereby, it is possible to prevent the ringing suppression period from being unnecessarily prolonged and to perform signal transmission stably.

Then, the control unit 9 includes a D flip-flop FF2, a D flip-flop FF1 that outputs a signal for resetting the D flip-flop FF2 in a set state, an output terminal Q of the D flip-flop FF1, and a D flip-flop FF2. The delay circuit 6 disposed between the reset terminal RB, the comparison circuit 4 that outputs a signal for setting the D flip-flop FF2 when detecting that the differential signal has changed from recessive to dominant, the FET_N7, and the FET_N4 are turned on. An ON confirmation circuit 3 that outputs a signal for setting the D flip-flop FF1 when it is detected to be ON, and an ON setting unit 8 that enables the gate of the FET_N4 to be turned ON when the D flip-flop FF2 is set. Consists of.

Thus, after the D flip-flop FF2 is set, when the differential signal changes from dominant to recessive, the FET_N4 is turned on and the ringing suppression operation is started. At this time, the ON state of the FET_N4 is fixed by setting the D flip-flop FF2. When the D flip-flop FF2 is reset, the ON state of the FET_N4 is released and the ringing suppression operation is stopped. Therefore, the period from when the differential signal changes from dominant to recessive until the D flip-flop FF2 is reset is a ringing suppression period.

Once the D flip-flop FF2 is set by the output signal of the comparison circuit 4, the D flip-flop FF2 is reset after the delay time in the delay time 5 has elapsed. Therefore, even if the differential signal level changes during the ringing suppression period, the D flip-flop FF2 is suppressed. Is not affected by this, and the suppression period can be maintained constant.

The ON confirmation circuit 3 includes a FET_N6 whose drain is connected to the power supply line 2 via the resistance element R3, and whose source and gate are respectively connected to the source and gate of the FET_N4. The ON setting unit 8 has FET_N0 to N3 whose sources are connected to the low potential side signal line 1L, its source connected to the power supply line 2, and its drain connected to the drain of FET_N1 and the gate of FET_N2 via the resistor element R1. FET_P1 having a source connected to the power supply line 2 and a drain connected to the drain of the FET_N3 and the gate of the FET_N1 via the resistance element R2.

Then, the gate of FET_N0 is connected to the gate of FET_N4, the gates of FET_N1 and N3 are connected to the drain of FET_N0 and connected to the high potential side signal line 1H via the resistance element R0, and the gate of FET_N2 is connected to the drain of FET_N1. When the D flip-flop FF2 is set, the FET_P1 is turned on and the FET_P2 is turned off. Thereby, the ON setting unit 8 can set the gate of the FET_N4 to the ON level when the D flip-flop FF2 is set, and can set the gate of the FET_N4 to the OFF level when the D flip-flop FF2 is reset.

In addition, when the delay circuit 5 detects that the level of the differential signal has changed from recessive to dominant, the delay circuit 5 delays the set signal of the D flip-flop FF2 output via the FET_N7, so that the control unit 8 The detection of the change due to is masked for a certain time. With this configuration, even if the recessive level noise is superimposed when the differential signal is at the dominant level and the ringing suppression operation is not started, the control unit 8 does not start the suppression operation at that time. . Thereby, it is possible to prevent the dominant signal waveform transmitted normally from being distorted by the influence of noise.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 10, the ringing suppression circuit 11 according to the second embodiment includes an ON state holding circuit 12 in which the FET_N 7 and the delay circuit 5 are deleted from the ON state holding circuit 7. In this case, as shown in FIG. 11, the normal ringing suppression operation is performed in the same manner as in the first embodiment. Also, as shown in FIG. 12, even when dominant level noise occurs in a recessive state, the ringing suppression operation is performed as in the first embodiment.

However, as shown in FIG. 13, when a recessive level noise is generated in a dominant state, the ringing suppression operation is started in accordance with the level change, so that the dominant signal waveform is distorted.

(Third and fourth embodiments)
As shown in FIG. 14, the ringing suppression circuit 13 of the third embodiment has a configuration in which FET_N0 to N4 are replaced with P-channel MOSFET_P0 to P4. The sources of the FET_P0 to P4 are connected to the high potential side signal line 1H, and the drain of the FET_P4 that is a line switching element is connected to the low potential side signal line 1L. The gates of the FET_P0 and P4 are connected to the drains of the FET_P2 and P3, and are also connected to the gate of the P-channel MOSFET_P6 that constitutes the comparison circuit 3P.

The drain of the FET_P0 is connected to the low-potential side signal line 1L via the resistance element R0 and to the gates of the FET_P1 and P3. The FET_P1 and P2 constituting the on setting unit 8 of the first embodiment are replaced with N-channel MOSFET_N1 and N2 to constitute the on setting unit 8P. The sources of FET_N1 and N2 are connected to the ground. The drain of the FET_N1 is connected to the drain of the FET_P1 and the gate of the FET_P2 through the resistance element R1, and the drain of the FET_N2 is connected to the gate of the FET_P4 through the resistance element R2.

Accordingly, the comparison circuit 3 becomes the comparison circuit 3P as described above, and the series circuit of the FET_P6 and the resistance element R3 is connected between the signal line 1H and the ground, and the common connection point between them is the comparator COMP1. It is connected to the inverting input terminal. The common connection point of the resistance elements R4 and R5 is connected to the non-inverting input terminal of the comparator COMP1. The output terminal of the comparator COMP1 is connected to the clock terminal C of the D flip-flop FF1 via the inverter gate INV4. In the case of the third embodiment configured as described above, the same effect as that of the first embodiment can be obtained.

In addition, the ringing suppression circuit 14 of the fourth embodiment shown in FIG. 15 is configured by replacing the ringing suppression circuit 11 of the second embodiment with FET_N0 to N4 by P-channel MOSFET_P0 to P4 as in the third embodiment. The ON state holding circuit 12P is provided by removing the FET_N7 and the delay circuit 5 from the ON state holding circuit 7. In this case, the inverter gate INV4 is inserted between the output terminal of the comparison circuit 4 and the clock terminal C of the D flip-flop FF2, but if the inverter gate INV0 of the comparison circuit 4 is deleted, the inverter gate INV4 is not necessary. Become. Note that the inverter gate INV4 of the third embodiment is an inverter gate INV5. According to 4th Embodiment comprised as mentioned above, the effect similar to 2nd Embodiment is acquired.

(Fifth embodiment)
A ringing suppression circuit 15 of the fifth embodiment shown in FIG. 16 is a combination of the first embodiment and the fourth embodiment, and the on setting unit 8P is used as the on setting unit 8N. Is added. In order to avoid duplication of symbols, FET_N1 and N2 in the fourth embodiment are FET_N11 and N12, and resistance elements R0 to R3 are R20 to R22 and R24.

In the ON confirmation circuit 3N configured around the comparator COMP1, a resistance element R23 is inserted between the resistance element R5 and the ground. The common connection point of the resistance elements R5 and R23 is connected to the non-inverting input terminal of the comparator COMP3 that constitutes the ON confirmation circuit 3P. The output terminal of the comparator COMP1 is connected to one of the input terminals of the OR gate OR1, and the output terminal of the comparator COMP3 is connected to the other input terminal of the OR gate OR1 via the inverter gate INV4. The output terminal of the OR gate OR1 is connected to the clock terminal C of the D flip-flop FF1. According to the fifth embodiment configured as described above, the same effects as those of the first and fourth embodiments can be obtained.

(Sixth embodiment)
A ringing suppression circuit 16 according to the sixth embodiment shown in FIG. 17 applies the configuration of the fifth embodiment to the configuration of the second embodiment, and includes ON setting

units

8N and 8P. According to the sixth embodiment configured as described above, the same effects as those of the second and fifth embodiments can be obtained.

(Other embodiments)
The FET_N4 or P4, which is a line-to-line switching element, may be configured with the elements shown in FIGS. 18 shows a configuration in which a resistance element R13 is inserted between the signal line 1H and the drain of the FET_N4, and a resistance element R14 is inserted between the source of the FET_N4 and the signal line 1L. FET_N4 is replaced with FET_P4.

FIG. 20 shows a configuration using so-called analog switches in which FET_N4 and P4 are connected in parallel. FIG. 21 shows resistance elements R13, R14 between the

signal lines

1H, 1L and the analog switches, as in FIG. Is inserted.

The present disclosure is not limited to the embodiment described above or illustrated in the drawings, and the following modifications or expansions are possible.

It may be implemented in combination with each embodiment disclosed in Patent Document 1.

The

delay circuits

5 and 6 are not limited to those composed of resistance elements and capacitors, but may be composed of, for example, a combination with a constant current source.

Resistance elements R1, R2, R21, and R22 may be replaced with constant current sources.

Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

A pair of high-potential side signal lines and low-potential side signal lines are connected to a transmission line that transmits a differential signal that changes to a binary level of high and low, and ringing that occurs due to transmission of the differential signal is suppressed. In the ringing suppression circuit,
A line switching element (N4, P4) connected between the pair of signal lines;
When it is detected that the level of the differential signal has changed from high to low, the control unit (9) turns on the line switching element to fix the on state, and releases the on state after measuring a certain time. A ringing suppression circuit.
The controller is
A first flip-flop (FF2) reset in an initial state;
A second flip-flop (FF1) that is reset in an initial state and outputs a reset signal for resetting the first flip-flop when in a set state;
A delay circuit (6) disposed between an output terminal of the second flip-flop and a reset terminal of the first flip-flop;
A first set signal output unit (4, FET_N7) for outputting a set signal for setting the first flip-flop upon detecting that the level of the differential signal has changed from low to high;
A second set signal output unit (3) for outputting a set signal for setting the second flip-flop upon detecting that the line switching element is turned on;
2. The ringing suppression circuit according to claim 1, further comprising: an ON setting unit that enables the conduction control terminal of the line switching element to be turned on when the first flip-flop is set. 3.
In the second set signal output unit, the non-potential reference side conduction terminal is connected to the power source via the resistance element (R3), and the potential reference side conduction terminal and the conduction control terminal are respectively connected to the potential reference side conduction of the line-to-line switching element. A switching element for detection (N6, P6) connected to the terminal and the conduction control terminal;
The on setting unit includes first to fourth switching elements (N0 to N3, P0 to P3) in which a potential reference side conduction terminal is connected to a potential reference side conduction terminal of the line-to-line switching element;
The potential reference side conduction terminal is connected to the power source, and the non-reference side conduction terminal is connected to the non-reference side conduction terminal of the second switching element and the conduction control terminal of the third switching element via the resistance element (R1). A fifth switching element (P1, N1),
The potential reference side conduction terminal is connected to the power source, and the non-reference side conduction terminal is connected to the non-reference side conduction terminal of the third switching element and the conduction control terminal of the line-to-line switching element via the resistance element (R2). A sixth switching element (P2, N2),
The conduction control terminal of the first switching element is connected to the conduction control terminal of the line switching element,
The conduction control terminals of the second and fourth switching elements are connected to the non-reference-side conduction terminal of the first switching element, and the non-reference-side conduction terminal of the line-to-line switching element via a resistance element (R0). Connected to
The conduction control terminal of the third switching element is connected to the non-reference side conduction terminal of the second switching element,
3. The ringing suppression circuit according to claim 2, wherein when the first flip-flop is set, the fifth switching element is turned on and the sixth switching element is turned off.
The ringing suppression circuit according to claim 1, further comprising a detection mask section (5) for masking detection of the change by the control section for a predetermined time when it is detected that the level of the differential signal has changed from low to high.
The ringing suppression circuit according to claim 2 or 3, further comprising a detection mask unit (5) for masking detection of the change by the control unit for a certain period of time when detecting that the level of the differential signal has changed from low to high. .
The ringing suppression circuit according to claim 5, wherein the detection mask unit includes a delay circuit that delays a set signal output from the first set signal output unit to the first flip-flop.