CN108055025B

CN108055025B - Analog electronic time-delay control circuit

Info

Publication number: CN108055025B
Application number: CN201711097049.3A
Authority: CN
Inventors: 施文斌; 赵晨阳; 周伟云; 刘艳荣
Original assignee: Wuhan Aviation Instrument Co Ltd
Current assignee: Wuhan Aviation Instrument Co Ltd
Priority date: 2017-11-08
Filing date: 2017-11-08
Publication date: 2021-11-05
Anticipated expiration: 2037-11-08
Also published as: CN108055025A

Abstract

The invention belongs to the technical field of airborne equipment, and particularly relates to an analog electronic delay control circuit. The invention is an analog electronic delay control circuit composed of two analog triggers, which starts a first analog trigger A1 to work by the falling edge of an external signal to control the delay time T1; and triggering and starting a second analog trigger A2 to work through a falling edge of T1 after the delay is finished, sending a control execution command and outputting delay time T2. This technical scheme realizes the world control through the charge-discharge of RC circuit: r1 and C1 of the first analog flip-flop a1 set a control delay time T1; r2 and C2 of the second analog flip-flop a2 set the control execution time T2. The technical scheme has the advantages of simple time control adjustment and high delay time precision.

Description

Analog electronic time-delay control circuit

The technical field is as follows: the invention belongs to the technical field of airborne equipment, and particularly relates to an analog electronic delay control circuit.

Background art: the existing time delay for an aircraft mainly adopts a mechanical clock gear mechanism as a time delay control unit, and the time delay is set by adjusting the position of a clock gear. The delay control mode has the advantages that time adjustment is complex on one hand, delay time is low in precision on the other hand, and great errors are prone to occur.

The invention content is as follows:

the purpose of the invention is as follows: provided is an analog electronic delay control circuit which is simple and can ensure delay accuracy.

The technical scheme is as follows: an analog electronic time delay control circuit is formed by connecting a first analog trigger A1 and a second analog trigger A2 in series, wherein a trigger input signal is input into an input end 2 of the first analog trigger A1, an output end 3 is connected with an input end 2 of the second analog trigger A2, and a control execution signal is output from an output end 3 of the second analog trigger A2.

The first analog flip-flop a1 and the second analog flip-flop a2 have the same working principle, and after triggering, a falling edge triggers and outputs a time delay T1-1.1 × R1 × C1 and a time delay T2-1.1 × R2 × C2, respectively, after receiving a trigger input signal, the input end 2 of the first analog flip-flop a1 triggers and starts the first analog flip-flop a1 to work through the falling edge triggering, and controls the delay time T1; and triggering and starting a second analog trigger A2 to work through a falling edge of T1 after the delay is finished, sending a control execution command and outputting delay time T2.

The reset end 4 of the first analog trigger A1 is connected with high level, the voltage-controlled end 5 is connected with a fixed capacitor C01, the discharge end 7 is connected with a threshold end 6, and the first analog trigger A1, the resistor R1 and the capacitor C1 form a charging and discharging circuit; the reset end 4 of the second analog trigger A2 is connected with high level, the voltage-controlled end 5 is connected with a fixed capacitor C02, the discharge end 7 is connected with the threshold end 6, and the second analog trigger A2 and the capacitor C2 form a charging and discharging circuit.

The fixed capacitances C01 and C02 take any value between 0.01 μ F and 0.02 μ F.

Has the advantages that: the invention is an analog electronic delay control circuit composed of two analog triggers, which starts a first analog trigger A1 to work by the falling edge of an external signal to control the delay time T1; and triggering and starting a second analog trigger A2 to work through a falling edge of T1 after the delay is finished, sending a control execution command and outputting delay time T2. This technical scheme realizes the world control through the charge-discharge of RC circuit: r1 and C1 of the first analog flip-flop a1 set a control delay time T1; r2 and C2 of the second analog flip-flop a2 set the control execution time T2. The technical scheme has the advantages of simple time control adjustment and high delay time precision.

Description of the drawings:

FIG. 1 is a circuit diagram of the present invention

FIG. 2 is a diagram of the input and output signals of a single flip-flop of the present invention

FIG. 3 is a schematic circuit diagram of the present invention

FIG. 4 is a diagram of input and output signals of the system of the present invention

The specific implementation mode is as follows:

the present invention will be described in further detail with reference to the accompanying drawings, which refer to fig. 1 to 4.

The invention is an analog electronic time delay control circuit formed by connecting two analog triggers in series, wherein the input end 2 of the first analog trigger A1 inputs a trigger input signal, the output end 3 is connected with the input end 2 of the second analog trigger A2, and the output end 3 of the second analog trigger A2 outputs a control execution signal. Triggering and starting a first analog trigger A1 to work through the falling edge of an external signal, and controlling the delay time T1; and triggering and starting a second analog trigger A2 to work through a falling edge of T1 after the delay is finished, sending a control execution command and outputting delay time T2. This technical scheme realizes the world control through the charge-discharge of RC circuit: r1 and C1 of the first analog flip-flop a1 set a control delay time T1; r2 and C2 of the second analog flip-flop a2 set the control execution time T2. The technical scheme has the advantages of simple time control adjustment and high delay time precision.

Example 1:

the electronic time-delay parachute opening device for the airborne troops is used for tasks such as airborne delivery, and the controller of the electronic time-delay parachute opening device can use the analog electronic time-delay control circuit. When the capacitor C1 is 10uF, the resistor R1 is 400K Ω, the capacitor C2 is 10uF, and the resistor R2 is 100K Ω, the electronic delay parachute opener starts to operate, outputs a parachute opening execution command to open the parachute after the delay time T1 is 4.4s, and delays the control execution time T2 to 1.1s to ensure reliable parachute opening.

Example 2:

the ejection seat program controller is used for the ejection lifesaving of the aircraft pilots and other tasks, and the analog electronic time delay control circuit can be used by the program controller. When the capacitor C1 is 10uF, the resistor R1 is 200K Ω, the capacitor C2 is 10uF, and the resistor R2 is 100K Ω, the program controller starts to operate, outputs a command for controlling the launching of the parachute and the separation of the human chair to execute after the delay time T1 is 2.2s, and delays the execution time T2 to 1.1s in order to ensure the reliable launching task.

Claims

1. An analog electronic time delay control circuit is characterized in that a first analog trigger A1 and a second analog trigger A2 are connected in series, a resistor R1, a resistor R2, a capacitor C01, a capacitor C02, a capacitor C1 and a capacitor C2 are arranged outside the first analog trigger A1 and the second analog trigger A2, a trigger input signal is input to an input end 2 of the first analog trigger A1, an output end 3 is connected with an input end 2 of the second analog trigger A2, an output end 3 of the second analog trigger A2 outputs a control execution signal, a reset end 4 of the first analog trigger A1 is connected with a high level, a voltage control end 5 is connected with a fixed capacitor C01, a discharge end 7 is connected with a threshold end 6, and a resistor R1 and a capacitor C1 form a charge-discharge circuit; the reset end 4 of the second analog trigger A2 is connected with high level, the voltage-controlled end 5 is connected with a fixed capacitor C02, the discharge end 7 is connected with the threshold end 6, and the second analog trigger A2, the resistor R2 and the capacitor C2 form a charging and discharging circuit;

triggering and starting a first analog trigger A1 to work through the falling edge of an external signal, and controlling the delay time T1; triggering and starting a second analog trigger A2 to work through a falling edge after T1 delay, sending a control execution instruction, and outputting delay time T2, wherein R1 and C1 of the first analog trigger A1 set control delay time T1; r2 and C2 of the second analog trigger A2 set control execution time T2, and world control is realized through charging and discharging of an RC circuit;

2. The analog electronic delay control circuit of claim 1, wherein the first analog flip-flop a1 and the second analog flip-flop a2 operate on the same principle, and the falling edge triggers and outputs a time delay T1-1.1-R1-C1 and a time delay T2-1.1-R2-C2, respectively, after receiving a trigger input signal at the input terminal 2 of the first analog flip-flop a1, the first analog flip-flop a1 is triggered to operate by the falling edge, and the delay time T1 is controlled; and triggering and starting a second analog trigger A2 to work through a falling edge of T1 after the delay is finished, sending a control execution command and outputting delay time T2.

3. An analog electronic delay control circuit according to claim 2, wherein the fixed capacitors C01 and C02 take any value between 0.01 μ F and 0.02 μ F.