WO2017049665A1 - 阵列基板、液晶显示面板及液晶显示装置 - Google Patents

阵列基板、液晶显示面板及液晶显示装置 Download PDF

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WO2017049665A1
WO2017049665A1 PCT/CN2015/091472 CN2015091472W WO2017049665A1 WO 2017049665 A1 WO2017049665 A1 WO 2017049665A1 CN 2015091472 W CN2015091472 W CN 2015091472W WO 2017049665 A1 WO2017049665 A1 WO 2017049665A1
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pixels
lines
row
line
array substrate
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PCT/CN2015/091472
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English (en)
French (fr)
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杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/897,664 priority Critical patent/US20170248828A1/en
Publication of WO2017049665A1 publication Critical patent/WO2017049665A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate, a liquid crystal display panel, and a liquid crystal display device.
  • DLS Data Line Sharing
  • the DLS architecture doubles the number of scan lines and halve the number of data lines, thereby reducing the number of source driver ICs and reducing costs.
  • dot inversion is the best inversion method for display effect.
  • the panel of the DLS architecture adopts the traditional driving method, when working with the resolution of HD and the operating frequency of 60 Hz, the data line signal on it needs to switch polarity once every two pixels. That is to say, the polarity of the data line signal should be switched every 21.7 ⁇ s, and the corresponding data line signal frequency is about 20 kHz.
  • the DLS architecture using the above driving method increases the power consumption of the data line on the one hand, and makes the charging time of the pixel short on the other hand.
  • the RC delay caused by signal switching on the data line will further affect the charging of the pixel, thereby affecting the display effect of the panel.
  • the present invention provides an array substrate, a liquid crystal display panel, and a liquid crystal display device for reducing power consumption of a data line and improving charging of a pixel.
  • an array substrate comprising:
  • a plurality of data lines and the scan lines cooperate to form a plurality of regions, each of which is provided with a pixel.
  • the data line is formed by branching lines of a plurality of data signal lines, and one of the data signal lines forms two branching lines to drive two pixels of the same row on the array substrate, and the two pixels are spaced apart from each other.
  • An odd number of pixels, and One of the adjacent two rows of pixels is coupled to the data line on the left side thereof, and the other row is coupled to the data line on the right side thereof to implement pixel dot inversion when the data line column is inverted.
  • the same row of pixels on the array substrate are controlled by two scan lines adjacent to the row of pixels.
  • pixels driven by branch lines of the same data signal line in the same row are controlled by different scan lines.
  • two pixels of the same row of the branch line driven by the same data signal line are separated by one pixel.
  • adjacent columns of pixels are treated as a group, wherein two pixels of each row within the same group are controlled by the same scan line.
  • adjacent two rows of pixels in two columns of pixels within the same group are controlled by odd row scan lines or even row scan lines.
  • adjacent two rows of pixels in two columns of pixels within the same group one row being controlled by odd row scan lines and the other row being controlled by even row scan lines.
  • the data line is branched by the data signal line before entering the display area.
  • liquid crystal display panel using the array substrate described above.
  • liquid crystal display device using the liquid crystal display panel described above.
  • the invention can realize the dot inversion of the pixel in the case where the data line column is reversed, thereby reducing the power consumption of the display panel, improving the charging condition of the pixel, and improving the display quality of the panel.
  • FIG. 1 is a schematic diagram of a liquid crystal display panel with dot inversion under a DLS architecture in the prior art
  • FIG. 2 is a schematic diagram of waveforms on a scan line and a data line when a conventional driving method is used;
  • FIG. 3 is a schematic diagram of wiring of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a driving waveform corresponding to FIG. 3;
  • FIG. 5 is a schematic diagram showing pixel display using the array substrate wiring of FIG. 3 and a conventional pixel arrangement
  • FIG. 6 is a schematic diagram showing pixel display using the array substrate wiring of FIG. 3 and the WRGB pixel arrangement.
  • the display panel of the DLS architecture can reduce the number of corresponding data lines by 1/2 by doubling the number of scan lines. Compared with the traditional architecture, the total number of data lines on the display panel of the DLS architecture is significantly reduced, thereby reducing the number of data line driver ICs and ultimately achieving manufacturing cost savings.
  • FIG. 1 is a schematic structural view of a TFT-LCD panel using a DLS architecture and dot inversion.
  • G1 to 8 indicate scan line numbers
  • D1 to 5 indicate data signal line numbers
  • a part of the dotted line is pixels
  • the sign indicates the polarity of the drive voltage on the data line.
  • the polarity of each pixel is opposite to the polarity of its neighboring pixels, that is, the pixel is in a dot inversion manner.
  • the second data line D2 in FIG. 1 is taken as an example to illustrate the working principle of dot inversion.
  • Figure 2 is a corresponding waveform of Figure 1 in a conventional driving mode.
  • the scanning line G is sequentially turned on in the order of 1, 2, 3, ..., n+1, and the data signal line D is switched once in polarity every time the two G lines are turned on.
  • the D2 line needs to switch polarity once every 21.7 ⁇ s.
  • a total of 768 polarity needs to be switched, and the corresponding signal frequency is about 20 kHz.
  • This makes the signal frequency of the data line too high, which increases the power consumption of the panel.
  • this will also make the RC delay of the data line have a greater impact on the pixel charging, which is not conducive to the improvement of the display quality of the panel. This problem will be more serious when the resolution of the panel is improved.
  • FIG. 3 is a schematic diagram of wiring of an array substrate according to an embodiment of the present invention. The present invention will be described in detail below with reference to FIG. 3.
  • the array substrate includes a plurality of scan lines and a plurality of data lines.
  • the scan lines and the data lines are interleaved to form a plurality of regions, each of which is provided with one pixel.
  • the data lines are branched by a plurality of data signal lines form.
  • the data signal line here refers to a signal line that is connected to the driving chip and directly extracts a signal generated by the driving chip.
  • Each data signal line is divided into two branch traces, and the same drive signal is transmitted in the two branch traces.
  • the two branch traces drive two pixels of the same row on the array substrate, and the pixels are separated by an odd number of pixels. This is because when the pixels are dot inversion, as shown in FIG. 3, the pixel polarities of the odd-numbered pixels are the same between the pixels in the same row. Since the signals transmitted in the two branch traces of the same data signal line are the same, the two branch traces of the same data signal line need to drive pixels of an odd number of pixels in the same row to realize pixel dot inversion.
  • the data signal line D3 in FIG. 3 drives the fifth pixel P 1,5 and the seventh pixel P 1,7 of the first row of pixels, and the data signal line D4 drives the sixth pixel P 1 of the first row of pixels. , 6 and the eighth pixel P 1,8 .
  • the data signal line D3 can also drive the first pixel P 1,1 and the fifth pixel P 1,5 of the first row of pixels, and the data signal line D4 can also drive the second pixel of the first row of pixels.
  • P 1, 2 and the sixth pixel P 1,6 as long as the pixels in the same row of the two branch traces of the same data signal line have the same polarity.
  • pixels adjacent to two pixels in the same row and pixels of even pixels are driven by branch lines of different data signal lines.
  • the pixels P 1,1 in the first row of pixels are driven by the data signal line D1
  • the pixels P 1,2 are driven by the data signal line D2
  • the pixels P 1,3 are driven by the data signal line D1
  • the pixel P 1,4 is driven by the data signal line D2.
  • pixels spaced apart from the pixel P 1,1 in the first row of pixels such as the pixel P 1,4 , the pixel P 1,6 and the like, are driven by data signal lines other than the data signal line D1.
  • these branch traces i.e., data lines
  • branch traces are branched from the data signal lines before entering the display area, as shown in FIG.
  • dividing the data signal line into two branch traces forms a data line for driving the pixels, so that the number of data signal lines is halved. In this way, the number of driving chips can be reduced, and the manufacturing cost can be saved.
  • one of the adjacent two rows of pixels is coupled to the data line on the left side thereof, and the other row is coupled to the data line on the right side thereof, that is, the pixels of two adjacent rows in the same column need different data lines.
  • Drive as shown in Figure 3. This setting is because when the display panel displays the picture in dot inversion mode, the polarity of the pixels in the same column alternates positively and negatively. One row of the adjacent two rows of pixels shows positive polarity, and the other row shows negative polarity.
  • the pixels in the same column are driven by data lines whose both sides are set to different polarities.
  • the pixel polarity display in FIG. 3 can be realized without changing the polarity of the data lines in the display screen.
  • each pixel can realize dot inversion at the same time. In this way, the frequency of signal conversion on the data driving signal line can be reduced, the power consumption of the panel can be reduced, and the influence of the RC extension on the data line on the pixel charging can be reduced, thereby improving the display quality of the display panel.
  • the same row of pixels on the array substrate are controlled by two scan lines adjacent to the row of pixels.
  • the number of data signal lines and scanning lines in the present invention is not increased, and the number of data signal driving chips can be reduced, and the cost can be saved.
  • the branch traces of the same data signal line control the pixels of the odd-numbered pixels in the same row of pixels, in order to achieve individual control of each pixel, in one embodiment of the present invention, the branch line driving of the same data signal line is driven.
  • the two pixels on the same line must be controlled by different scan lines. As shown in FIG. 3, the fifth column pixel P 1,5 and the seventh column pixel P 1,7 of the first row of pixels are all driven by the data signal line D3, but the pixel P 1,5 is controlled by the scanning line G2, the pixel P 1,7 is controlled by the scanning line G1.
  • the branch traces of the same data signal line drive pixels spaced one pixel apart, that is, one pixel between the same row of pixels driven by the branch traces of the same data signal line is branched by other data signal lines.
  • Line drive Under such setting conditions, two adjacent columns of pixels are treated as one group, wherein two pixels of each row in the same group are controlled by the same scanning line.
  • the pixels in the larger dashed box are regarded as a group, that is, the first column pixel and the second column pixel are regarded as one group, the third column pixel and the fourth column pixel are regarded as one group, and so on. .
  • adjacent two rows of pixels in two columns of pixels within the same group one row being controlled by odd row scan lines and the other row being controlled by even row scan lines. That is to say, two pixels of the upper row in the same group are controlled by odd row scan lines, and two pixels of the next row are controlled by even row scan lines. Alternatively, two pixels of the previous row in the same group are controlled by even row scan lines, and two pixels of the next row are controlled by odd row scan lines. As shown in FIG.
  • the first column of pixels and the second column of pixels are regarded as a group, wherein the first row of pixels P 1,1 and P 1,2 in the group are controlled by the even-line scanning line G2, and the second row
  • the pixel P 2,1 and the pixel P 2,2 are controlled by the odd-line scanning line G3, and the third-row pixels P 3,1 and P 3,2 are controlled by the even-line scanning line G6.
  • adjacent two rows of pixels in two columns of pixels within the same group are controlled by odd row scan lines or even row scan lines. That is to say, two pixels of the upper row in the same group are controlled by odd row scan lines, and two pixels of the next row are also controlled by odd row scan lines. Alternatively, two pixels of the previous row in the same group are controlled by even row scan lines, and the two pixels of the next row are also controlled by even row scan lines. That is, when the first column pixel and the second column pixel in FIG.
  • the first row pixels P 1,1 and P 1,2 in the group are controlled by the even row scanning line G2
  • the second row pixel P 2, 1 and P 2, 2 are controlled by even-line scan lines G4
  • third-row pixels P 3, 1 and P 3, 2 are controlled by even-line scan lines G6.
  • FIG. 4 is a schematic diagram of a driving waveform corresponding to FIG. 3.
  • the array substrate shown in FIG. 3 has HD resolution, it has 1080 G lines, and the G lines are sequentially opened in the order of 1, 2, 3, ... 1079, 1080.
  • the polarity of the data line remains unchanged.
  • the polarity of the data line is switched once, and the polarity after switching remains for the other frame. duration.
  • the first row and the second row of pixels driven by the data signal lines D3 and D4 are taken as an example.
  • the polarity of the current screen is displayed as shown in FIG. 3, and the polarity of the driving signal output by D3 is positive at this time, and the output of D4 is The drive signal polarity is negative.
  • the pixel P 1,5 , the pixel P 1,7 , the pixel P 2,4 and the pixel P 2,6 driven by the data signal line D3 are all shown as positive polarity
  • the pixel P 1,6 driven by the data signal line D4 and the pixel P 1,8 , pixel P 2,5 , and pixel P 2,7 are all shown as negative polarity.
  • the data signal lines Data1 and Data2 are kept in the same polarity, that is, the horizontal and vertical pixels on the display screen are alternately displayed with positive and negative polarities.
  • the data signal lines D3 and D4 are reversed in polarity, and the pixels P 1,5 , P 1,7 , and pixels driven by the data signal line D3.
  • P 2, 4 and pixels P 2, 6 are both shown as negative polarity, and pixels P 1,6 , pixels P 1,8 , pixels P 2,5 , and pixels P 2,7 driven by data signal line D4 are both shown as Positive polarity.
  • the data signal lines D3 and D4 maintain the polarity, and the horizontal and vertical pixels on the display screen are also alternately displayed with positive and negative polarities.
  • dot inversion of pixels in the display area can be achieved.
  • FIG. 5 is a schematic diagram of pixel display using the array substrate wiring of FIG. 3 and the conventional pixel arrangement manner, wherein red, green, and blue represent pixels of three colors, and each column in the panel is a pixel of the same color. The adjacent red, green, and blue columns are repeated in each row of pixels in the display panel. For each column of pixels of the same color, positive and negative polarity alternates. For each row of pixels, the pixels of the three colors of red, green, and blue are sequentially arranged, and the polarities of the adjacent two pixels are opposite, as shown in FIG. 5. Through the pixel arrangement of FIG. 5, a regular mixed arrangement of three color pixels can be realized, thereby facilitating the display effect of the screen.
  • FIG. 6 is a schematic diagram of pixel display using the array substrate wiring + WRGB pixel arrangement of FIG. 3, wherein R (red), G (green), B (blue), and W (white) pixels of four colors.
  • R red
  • G green
  • B blue
  • W white
  • pixels of four colors of red, green, blue, and white are sequentially arranged, and the polarities of adjacent two pixels are opposite.
  • Each column in the vertical direction appears by two pixel interleaving intervals of different colors, and the adjacent two pixels have opposite polarities, and the pixels of the same color of the adjacent two rows are opposite in polarity, as shown in FIG. 6.
  • FIG. 6 Through the pixel arrangement of FIG. 6, it is also possible to realize a regular mixed arrangement of four color pixels, thereby facilitating the display effect of the screen.
  • a liquid crystal display panel which can employ the above array substrate.
  • the array substrate in the case where the data line columns are inverted, dot inversion of pixels can be achieved. It is not necessary to change the polarity of the data line frequently during the display process of one frame, thereby reducing the power consumption of the display panel, improving the charging condition of the pixel, and improving the display quality of the panel.
  • a liquid crystal display device using the liquid crystal display panel described above, which can realize dot inversion of pixels in a case where data line columns are inverted, thereby reducing
  • the power consumption of the display panel improves the charging of the pixels and improves the display quality of the panel.

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Abstract

一种阵列基板、液晶显示面板及液晶显示装置。阵列基板包括：多条扫描线（G1、G2、G3、G4、G5、G6）；多条数据线（D1、D2、D3、D4），与扫描线（G1、G2、G3、G4、G5、G6）配合形成多个区域，每个区域内均设有一像素，其中，数据线（D1、D2、D3、D4）由多条数据信号线的分支走线形成，一条数据信号线形成两条分支走线以驱动阵列基板上同一行的两个像素，两个像素之间间隔奇数个像素，并且相邻两行像素中的一行与其左侧的数据线（D1、D2、D3、D4）耦接，另一行与其右侧的数据线（D1、D2、D3、D4）耦接，用以在数据线（D1、D2、D3、D4）列反转时实现像素点反转。降低了显示面板的功耗，改善了像素的充电情况，提高了面板的显示品质。

Description

阵列基板、液晶显示面板及液晶显示装置
相关技术的交叉引用
本申请要求享有2015年9月22日提交的名称为“阵列基板、液晶显示面板及液晶显示装置”的中国专利申请201510605530.3的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，具体地说，涉及一种阵列基板、液晶显示面板及液晶显示装置。
背景技术
在液晶显示面板生产中，降低制作成本是一项非常重要的内容。目前，通常采用DLS(Data Line Sharing，数据线共享)架构来降低制作成本。DLS架构将扫描线的数量加倍，而数据线的数量减半，从而减少源极驱动IC的数量，达到降低成本的目的。
目前的液晶显示面板驱动方式中，点反转是显示效果最好的一种反转方式。如果DLS架构的面板采用传统的驱动方式，以HD的解析度、60Hz的工作频率工作时，其上的数据线信号每两个像素就需要切换一次极性。也就是大约每21.7μs数据线信号就要切换一次极性，对应的数据线信号频率为20kHz左右。采用以上驱动方式的DLS架构一方面增加了数据线的功率消耗，另一方面使得像素的充电时间很短。同时，数据线上信号切换导致的RC延迟会进一步影响像素的充电情况，进而影响面板的显示效果。
发明内容
为解决以上问题，本发明提供了一种阵列基板、液晶显示面板及液晶显示装置，用以降低数据线的功率消耗，改善像素的充电情况。
根据本发明的一个方面，提供了一种阵列基板，包括：
多条扫描线；
多条数据线，与所述扫描线配合形成多个区域，每个所述区域内均设有一像素，
其中，所述数据线由多条数据信号线的分支走线形成，一条所述数据信号线形成两条分支走线以驱动阵列基板上同一行的两个像素，所述两个像素之间间隔奇数个像素，并且 相邻两行像素中的一行与其左侧的数据线耦接，另一行与其右侧的数据线耦接，用以在所述数据线列反转时实现像素点反转。
根据本发明的一个实施例，所述阵列基板上的同一行像素由与该行像素相邻的两条扫描线控制。
根据本发明的一个实施例，同一行中由同一条所述数据信号线的分支走线驱动的像素由不同的扫描线控制。
根据本发明的一个实施例，同一条所述数据信号线形成的分支走线驱动的同一行的两个像素之间间隔一个像素。
根据本发明的一个实施例，将相邻的两列像素视为一组，其中，同一组内的每行的两个像素由同一条扫描线控制。
根据本发明的一个实施例，同一组内的两列像素中的相邻两行像素均由奇数行扫描线或偶数行扫描线控制。
根据本发明的一个实施例，同一组内的两列像素中的相邻两行像素，其中一行由奇数行扫描线控制，另一行由偶数行扫描线控制。
根据本发明的一个实施例，所述数据线由所述数据信号线在进入显示区之前分支形成。
根据本发明的一个方面，还提供了一种采用以上所述的阵列基板的液晶显示面板。
根据本发明的一个方面，还提供了一种采用以上所述的液晶显示面板的液晶显示装置。
本发明可以在数据线列反转的情况下，实现像素的点反转，从而降低了显示面板的功耗，改善了像素的充电情况，提高了面板的显示品质。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有技术中一种DLS架构下点反转的液晶显示面板示意图；
图2是采用传统驱动方式时的扫描线及数据线上的波形示意图；
图3是根据本发明的一个实施例的阵列基板布线示意图；
图4是对应图3的驱动波形示意图；
图5是采用图3的阵列基板布线+传统像素排列方式的像素显示示意图；以及
图6是采用图3的阵列基板布线+WRGB像素排列方式的像素显示示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
DLS架构的显示面板通过将扫描线的数量加倍的方法，使得相应的数据线的数量可以减少1/2。与传统的架构相比，DLS架构的显示面板上数据线的总数量会有明显的减少，从而减少数据线驱动IC的数量，最终达到节省制造成本的目的。
为了避免直流残留，现在的显示面板都采用正负极性反转的交流驱动方式，点反转是其中显示效果最好的一种。如图1所示为采用DLS架构和点反转的TFT-LCD面板的结构示意图。
如图1所示，G1～8表示扫描线编号，D1～5表示数据信号线编号，虚线框中部分为像素，其中的正负号表示数据线上驱动电压的极性。每一个像素的极性与其上下左右相邻像素的极性是相反的，即像素为点反转方式。
以图1中的第二条数据线D2为例来说明点反转的工作原理。当G1打开时，D2输出负极性信号；G2，G3打开时，D2切换为正极性信号；G4，G5打开时，D2又切换为负极性信号。即当扫描线G编号为4n+2和4n+3(n＝0，1，2…)时，D2输出正极性信号，而G编号为4n和4n+1(n＝0，1，2…)时，D2输出负极性信号。每给列方向的两个像素充电，D2就需要切换一次极性。
图2是图1采用传统驱动方式时的相应波形。扫描线G按照1，2，3……n，n+1的顺序依次打开，数据信号线D在每两条G线打开的时间就要切换一次极性。以HD解析度的面板为例，D2线在每21.7μs就需要切换一次极性。在整个一帧的时间内，总共需要切换768次极性，对应的信号频率为20kHz左右。这样使得数据线的信号频率太高，会增加面板的功耗。另外，这样还会使得数据线的RC延迟对像素充电的影响比较大，不利于面板显示品质的提高，当面板的分辨率提高时，这个问题会更加严重。
如图3所示为根据本发明的一个实施例的阵列基板布线示意图。以下参考图3来对本发明进行详细说明。
该阵列基板包括多条扫描线和多条数据线。这些扫描线和数据线相互交错配合形成多个区域，每个区域内均设置有一个像素。其中，这些数据线由多条数据信号线的分支走线 形成。此处的数据信号线指的是与驱动芯片连接、直接将驱动芯片产生的信号引出的信号线。
每一条数据信号线分为两条分支走线，这两条分支走线中传输相同的驱动信号。这两条分支走线驱动阵列基板上同一行的两个像素，这两个像素之间间隔奇数个像素。这是因为当像素为点反转时，如图3所示，同一行像素之间间隔奇数个像素的像素极性均相同。由于同一条数据信号线的两条分支走线中传输的信号相同，所以同一条数据信号线的两条分支走线需驱动同一行中间隔奇数个像素的像素，才能实现像素点反转。
如图3中数据信号线D3驱动第一行像素中的第五个像素P1,5和第七个像素P1,7，数据信号线D4驱动第一行像素中的第六个像素P1,6和第八个像素P1,8。当然，数据信号线D3也可以驱动第一行像素中的第一个像素P1,1和第五个像素P1,5，数据信号线D4也可以驱动第一行像素中的第二个像素P1,2和第六个像素P1,6，只要同一条数据信号线的两条分支走线控制的同一行中的像素极性相同即可。
另外，由于同一条数据信号线的两条分支走线驱动同一行间隔奇数个像素的像素，则同一行相邻两个像素及间隔偶数个像素的像素由不同的数据信号线的分支走线驱动。如图3所示，第一行像素中的像素P1,1由数据信号线D1驱动，像素P1,2由数据信号线D2驱动，像素P1,3由数据信号线D1驱动，像素P1,4由数据信号线D2驱动。同理，与第一行像素中的像素P1,1间隔偶数个像素的像素如像素P1,4、像素P1,6等由数据信号线D1之外的数据信号线驱动。
为避免数据信号线在显示区内分支造成显示区内布线复杂，在本发明中，将这些分支走线(即数据线)由数据信号线在进入显示区之前分支形成，如图3所示。另外，将数据信号线分为两条分支走线形成用于驱动像素的数据线，使得数据信号线的数量减半。这样，就可以减少驱动芯片的数量，达到节省制造成本的目的。
在该阵列基板中，相邻两行像素中的一行与其左侧的数据线耦接，另一行与其右侧的数据线耦接，即同一列中相邻两行的像素需由不同的数据线驱动，如图3所示。这样设置是因为显示面板以点反转方式显示画面时，同一列中像素的极性正负交替出现，相邻两行像素中一行显示正极性，另一行显示为负极性。
这样，在一帧的画面显示中，同一列中的像素由其两侧设置为不同极性的数据线驱动。通过图3的布线方式，在该显示画面内，数据线不需要改变极性就可以实现图3中的像素极性显示。在下一帧画面显示时，只需要数据线列反转，各像素就可以同时实现点反转。这样，就可以降低数据驱动信号线上信号转换的频率，降低面板功耗，还可以降低数据线上RC延长对像素充电的影响，从而提高显示面板的显示品质。
在本发明的一个实施例中，阵列基板上的同一行像素由与该行像素相邻的两条扫描线控制。与现有的DLS面板相比，本发明中数据信号线和扫描线的数量没有增加，可以减少数据信号驱动芯片的数量，仍然可以起到节省成本的作用。由于同一条数据信号线的分支走线控制同一行像素中间隔奇数个像素的像素，为实现对各像素的单独控制，在本发明的一个实施例中，同一条数据信号线的分支走线驱动的同一行上的两个像素必须由不同的扫描线控制。如图3所示，第一行像素中的第五列像素P1,5和第七列像素P1,7都由数据信号线D3驱动，但是像素P1,5由扫描线G2控制，像素P1,7由扫描线G1控制。
如图3所示，同一条数据信号线的分支走线驱动间隔一个像素的像素，即同一条数据信号线的分支走线驱动的同一行像素之间有一个像素被其他数据信号线的分支走线驱动。在这样的设置条件下，将相邻的两列像素视为一组，其中，同一组内的每行的两个像素由同一条扫描线控制。如图3所示，较大虚线框内的像素视为一组，即第一列像素和第二列像素视为一组，第三列像素和第四列像素视为一组，以此类推。
在本发明的一个实施例中，同一组内的两列像素中的相邻两行像素，其中一行由奇数行扫描线控制，另一行由偶数行扫描线控制。也就是说，同一组内上一行的两个像素由奇数行扫描线控制，则下一行的两个像素由偶数行扫描线控制。或者，同一组内上一行的两个像素由偶数行扫描线控制，则下一行的两个像素由奇数行扫描线控制。如图3所示，第一列像素和第二列像素视为一组，其中，该组中的第一行像素P1,1和P1,2由偶数行扫描线G2控制，第二行像素P2,1和像素P2,2由奇数行扫描线G3控制，第三行像素P3,1和P3,2由偶数行扫描线G6控制。
在本发明的一个实施例中，同一组内的两列像素中的相邻两行像素均由奇数行扫描线或偶数行扫描线控制。也就是说，同一组内上一行的两个像素由奇数行扫描线控制，则下一行的两个像素也由奇数行扫描线控制。或者，同一组内上一行的两个像素由偶数行扫描线控制，则下一行的两个像素也由偶数行扫描线控制。即图3中的第一列像素和第二列像素视为一组时，该组中的第一行像素P1,1和P1,2由偶数行扫描线G2控制，第二行像素P2,1和像素P2,2由偶数行扫描线G4控制，第三行像素P3,1和P3,2由偶数行扫描线G6控制。
如图4所示为对应图3的一种驱动波形示意图。由图4可知，当图3所示阵列基板为HD解析度，具有1080条G线，G线按照1，2，3……1079，1080的顺序依次打开。在显示面板显示一帧画面的过程中，数据线的极性保持不变，在显示下一帧画面时，数据线极性切换一次极性，并且切换后的极性保持该另一帧画面的持续时间。
以数据信号线D3和D4驱动的第一行和第二行像素为例进行说明，当前画面的极性显示如图3所示，则此时D3输出的驱动信号极性为正，D4输出的驱动信号极性为负。 由数据信号线D3驱动的像素P1,5、像素P1,7、像素P2,4和像素P2,6均显示为正极性，由数据信号线D4驱动的像素P1,6、像素P1,8、像素P2,5、和像素P2,7均显示为负极性。则在一帧画面内，数据信号线Data1和Data2保持极性不变，即可以实现显示画面上横向和纵向像素均正负极性交替显示。
按如图3所示的布线方式，在显示下一帧画面时，数据信号线D3和D4进行极性反转，由数据信号线D3驱动的像素P1,5、像素P1,7、像素P2,4和像素P2,6均显示为负极性，由数据信号线D4驱动的像素P1,6、像素P1,8、像素P2,5、和像素P2,7均显示为正极性。并且在该帧画面内，数据信号线D3和D4保持极性不变，显示画面上横向和纵向像素也正负极性交替显示。这样，在数据线列反转的方式下，可以实现显示区内像素的点反转。
如图5所示为采用图3的阵列基板布线+传统像素排列方式的像素显示示意图，其中，红、绿和蓝表示三种颜色的像素，面板中的每一列均为同一颜色的像素。以相邻的红、绿、蓝三列为一组，在显示面板中的每一行像素中重复出现。对于每一列相同颜色的像素，正负极性交替出现。对于每一行像素，红、绿、蓝三种颜色的像素依次排列显示，并且相邻两个像素的极性相反，具体如图5所示。通过图5的像素排布，可以实现三种颜色像素有规则的混合排列，从而有利于提高画面的显示效果。
如图6为采用图3的阵列基板布线+WRGB像素排列方式的像素显示示意图，其中，R(红)、G(绿)、B(蓝)和W(白)四种颜色的像素。对于每一行像素，红、绿、蓝和白四种颜色的像素依次排列显示，并且相邻两个像素的极性相反。纵向上每一列由不同颜色的两种像素交错间隔出现，相邻两个像素的极性相反，并且使得相邻两行相同颜色的像素极性相反，具体如图6所示。通过图6的像素排布，也可以实现四种颜色像素有规则的混合排列，从而有利于提高画面的显示效果。
根据本发明的另一个方面，还提供了一种液晶显示面板，该液晶显示面板可以采用以上所述的阵列基板。在采用该阵列基板时，在数据线列反转的情况下，可以实现像素的点反转。而不必使数据线在一帧画面的显示过程中频繁变换极性，从而降低了显示面板的功耗，改善了像素的充电情况，提高了面板的显示品质。
根据本发明的另一个方面，还提供了一种液晶显示装置，该液晶显示装置采用以上所述的液晶显示面板，可以在数据线列反转的情况下，实现像素的点反转，从而降低了显示面板的功耗，改善了像素的充电情况，提高了面板的显示品质。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发 明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种阵列基板，包括：
    多条扫描线；
    多条数据线，与所述扫描线配合形成多个区域，每个所述区域内均设有一像素，
    其中，所述数据线由多条数据信号线的分支走线形成，一条所述数据信号线形成两条分支走线以驱动阵列基板上同一行的两个像素，所述两个像素之间间隔奇数个像素，并且相邻两行像素中的一行与其左侧的数据线耦接，另一行与其右侧的数据线耦接，用以在所述数据线列反转时实现像素点反转。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板上的同一行像素由与该行像素相邻的两条扫描线控制。
  3. 根据权利要求2所述的阵列基板，其中，同一行中由同一条所述数据信号线的分支走线驱动的像素由不同的扫描线控制。
  4. 根据权利要求3所述的阵列基板，其中，同一条所述数据信号线形成的分支走线驱动的同一行的两个像素之间间隔一个像素。
  5. 根据权利要求4所述的阵列基板，其中，将相邻的两列像素视为一组，其中，同一组内的每行的两个像素由同一条扫描线控制。
  6. 根据权利要求5所述的阵列基板，其中，同一组内的两列像素中的相邻两行像素均由奇数行扫描线或偶数行扫描线控制。
  7. 根据权利要求5所述的阵列基板，其中，同一组内的两列像素中的相邻两行像素，其中一行由奇数行扫描线控制，另一行由偶数行扫描线控制。
  8. 根据权利要求1所述的阵列基板，其中，所述数据线由所述数据信号线在进入显示区之前分支形成。
  9. 一种液晶显示面板，包括阵列基板，其中，所述阵列基板包括：
    多条扫描线；
    多条数据线，与所述扫描线配合形成多个区域，每个所述区域内均设有一像素，
    其中，所述数据线由多条数据信号线的分支走线形成，一条所述数据信号线形成两条分支走线以驱动阵列基板上同一行的两个像素，所述两个像素之间间隔奇数个像素，并且相邻两行像素中的一行与其左侧的数据线耦接，另一行与其右侧的数据线耦接，用以在所述数据线列反转时实现像素点反转。
  10. 根据权利要求9所述的液晶显示面板，其中，所述阵列基板上的同一行像素由与该行像素相邻的两条扫描线控制。
  11. 根据权利要求10所述的液晶显示面板，其中，同一行中由同一条所述数据信号线的分支走线驱动的像素由不同的扫描线控制。
  12. 根据权利要求11所述的液晶显示面板，其中，同一条所述数据信号线形成的分支走线驱动的同一行的两个像素之间间隔一个像素。
  13. 根据权利要求12所述的液晶显示面板，其中，将相邻的两列像素视为一组，其中，同一组内的每行的两个像素由同一条扫描线控制。
  14. 根据权利要求13所述的液晶显示面板，其中，同一组内的两列像素中的相邻两行像素均由奇数行扫描线或偶数行扫描线控制。
  15. 根据权利要求13所述的液晶显示面板，其中，同一组内的两列像素中的相邻两行像素，其中一行由奇数行扫描线控制，另一行由偶数行扫描线控制。
  16. 根据权利要求9所述的液晶显示面板，其中，所述数据线由所述数据信号线在进入显示区之前分支形成。
  17. 一种液晶显示装置，包括液晶显示面板，所述液晶显示面板包括阵列基板，其中，所述阵列基板包括：
    多条扫描线；
    多条数据线，与所述扫描线配合形成多个区域，每个所述区域内均设有一像素，
    其中，所述数据线由多条数据信号线的分支走线形成，一条所述数据信号线形成两条分支走线以驱动阵列基板上同一行的两个像素，所述两个像素之间间隔奇数个像素，并且相邻两行像素中的一行与其左侧的数据线耦接，另一行与其右侧的数据线耦接，用以在所述数据线列反转时实现像素点反转。
PCT/CN2015/091472 2015-09-22 2015-10-08 阵列基板、液晶显示面板及液晶显示装置 WO2017049665A1 (zh)

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